Multi-chip synchronization method and device

Abstract

The present invention provides a multi-chip synchronization method, which is applied to a master chip and includes: performing secret key negotiation with each slave chip to determine a shared secret key; deriving multiple synchronization check codes in sequence based on the shared secret key and storing them in the master chip cache according to the derivation order; when entering a synchronization task point, obtaining a first synchronization check code corresponding to the current synchronization task point from the master chip cache and writing it into the synchronization register of the slave chip; so that the slave chip verifies the first synchronization check code and sends a second synchronization check code to the corresponding synchronization register in the master chip based on the verification result; obtaining each second synchronization check code in the synchronization register in the master chip in sequence and verifying it based on the corresponding third synchronization check code in the master chip cache, wherein each second synchronization check code corresponds one-to-one to each slave chip. The multi-chip synchronization method and device provided by the present invention can verify the security of the synchronization process by verifying the pre-negotiated and derived secret keys.

Description

Technical Field

[0001] The present invention relates to the field of encryption security technology, and in particular to a multi-chip synchronization method. Background Art

[0002] Multi-chip interconnection refers to the coordinated work of multiple chips through bus interconnection, which appears to be a complete system to the outside world. The multi-chip structure in the chip field can be the interconnection of multiple single-chip packages (SCMs), the interconnection of one or more homogeneous multi-chip packages (MCMs), or the interconnection of one or more heterogeneous multi-chip packages (SIPs). Common multi-chip interconnection topologies include wired, ring, star, and other topologies. In a multi-chip interconnection structure, it is usually involved that multiple chips perform the same task at the same time at a certain point in time. This time point is generally determined by the time when the master chip synchronizes other chips. When the tasks executed by multiple chips at the same time are sensitive tasks, in order to ensure data security and the correct execution of the tasks, secure synchronization is usually required when the multiple chips are synchronized. The secure synchronization in the existing technology often only focuses on data transmission and ensures the security of the synchronized data, but cannot guarantee the security of the synchronization process itself. Summary of the Invention

[0003] The multi-chip synchronization method and device provided by the present invention can be verified through pre-negotiated and derived secret keys, ensuring that the security of the synchronization process can be verified without consuming additional computing resources.

[0004] An embodiment of the present invention provides a multi-chip synchronization method, which is applied to a master chip and includes:

[0005] Perform key negotiation with each slave chip to determine the shared key;

[0006] Based on the shared secret key, multiple synchronization check codes are derived in sequence and stored in the main chip cache according to the derivation order;

[0007] When entering a synchronization task point, a first synchronization check code corresponding to the current synchronization task point is obtained from the master chip cache and written into the synchronization register of the slave chip; so that the slave chip verifies the first synchronization check code and sends a second synchronization check code to the corresponding synchronization register in the master chip according to the verification result;

[0008] The second synchronization check codes in the synchronization register of the master chip are sequentially obtained and verified according to the corresponding third synchronization check codes in the master chip cache, wherein the second synchronization check codes correspond one-to-one to the slave chips.

[0009] Optionally, deriving multiple synchronization check codes in sequence based on the shared secret key and storing them in the main chip cache in the derivation order includes:

[0010] Splitting the shared key to obtain a first sub-key and a second sub-key;

[0011] Based on the first sub-key and the second sub-key, a synchronization check code is first derived;

[0012] Starting from the second derivation of the synchronization check code, the synchronization check code formed by the previous derivation and the second sub-key are used to derive the synchronization check code.

[0013] Optionally, when entering the synchronization task point, obtaining the first synchronization check code corresponding to the current synchronization task point from the master chip cache and writing it into the synchronization register of the slave chip includes: obtaining the first synchronization check code from the corresponding synchronization check code sequence in the master chip cache according to the order of the current synchronization task point.

[0014] Optionally, obtaining the first synchronization check code from a corresponding synchronization check code sequence in the master chip cache according to the sequence of the current synchronization task points includes:

[0015] The synchronization check code sequence is determined according to the following formula: A = (x-1)*i+1; where A is the synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

[0016] Optionally, sequentially acquiring the second synchronization check codes in the synchronization register in the master chip and performing verification according to the corresponding third synchronization check codes in the cache of the master chip includes:

[0017] Reading the second synchronization check code in the synchronization register in the main chip in sequence;

[0018] Each time the synchronization register in the master chip is read, the target synchronization check code sequence in the master chip cache is determined based on the synchronization register sequence currently read;

[0019] The third synchronization check code is read from the target synchronization check code sequence in the main chip buffer, and the second synchronization check code is checked according to the third synchronization check code.

[0020] Optionally, each time the synchronization register in the master chip is read, determining the target synchronization check code sequence in the master chip cache according to the currently read synchronization register sequence includes:

[0021] The target synchronization check code sequence is determined according to the following formula: B = (x-1)*i+1+y; where B is the target synchronization check code sequence, y is the sequence of the synchronization registers currently read, x is the sequence of the current synchronization task points, and i is the total number of master chips and slave chips.

[0022] In a second aspect, the present invention provides a multi-chip synchronization method, applied to a slave chip, comprising:

[0023] Perform key negotiation with the main chip to determine the shared key;

[0024] Based on the shared secret key, multiple synchronization check codes are derived in sequence and stored in the slave chip cache according to the derivation order;

[0025] The first synchronization check code written by the master chip is read from the synchronization register of the slave chip, and is verified according to the corresponding fourth synchronization check code in the slave chip buffer;

[0026] According to the verification result of the first synchronization check code, a second synchronization check code is written into the corresponding synchronization register in the master chip.

[0027] Optionally, deriving multiple synchronization check codes in sequence based on the shared secret key and storing them in the slave chip cache in the derivation order includes:

[0028] Splitting the shared key to obtain a first sub-key and a second sub-key;

[0029] Based on the first sub-key and the second sub-key, a synchronization check code is first derived;

[0030] Starting from the second derivation of the synchronization check code, the synchronization check code formed by the previous derivation and the second sub-key are used to derive the synchronization check code.

[0031] Optionally, performing verification according to the corresponding fourth synchronization check code in the chip cache includes: extracting the fourth synchronization check code from the corresponding synchronization check code sequence in the chip cache according to the sequence of the current synchronization task points.

[0032] Optionally, according to the order of the current synchronization task points, extracting the fourth synchronization check code from the corresponding synchronization check code sequence in the chip cache includes:

[0033] The corresponding synchronization check code sequence is determined according to the following formula: C = (x-1)*i+1, where C is the corresponding synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

[0034] Optionally, writing a second synchronization check code into a corresponding synchronization register in the master chip according to a check result of the first synchronization check code includes:

[0035] Determine the target synchronization check code sequence in the slave chip cache according to the slave chip sequence;

[0036] Read the synchronization check code to be processed from the target synchronization check code sequence;

[0037] When the first synchronization check code passes the check, the synchronization check code to be processed is used as the second synchronization check code;

[0038] When the first synchronization check code fails to be checked, the synchronization check code to be processed is inverted and used as the second synchronization check code.

[0039] Optionally, determining the target synchronization check code sequence in the slave chip cache according to the slave chip sequence includes:

[0040] The target synchronization check code sequence is determined according to the following formula: D = (x-1)*i+1+z; where D is the target synchronization check code sequence, z is the sequence of the current slave chip among all slave chips, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

[0041] In a third aspect, the present invention provides a multi-chip synchronization device, applied to a master chip, comprising:

[0042] A negotiation module, used to perform key negotiation with each slave chip to determine a shared key;

[0043] A derivation module is used to derive multiple synchronization check codes in sequence based on the shared secret key and store them in the main chip cache according to the derivation order;

[0044] The sending module is configured to, when entering a synchronization task point, obtain a first synchronization check code corresponding to the current synchronization task point from the master chip cache and write the code into the synchronization register of the slave chip; so that the slave chip verifies the first synchronization check code and sends a second synchronization check code to the corresponding synchronization register in the master chip based on the verification result;

[0045] The verification module is used to sequentially obtain each second synchronization check code in the synchronization register of the master chip and perform verification according to the corresponding third synchronization check code in the master chip cache, wherein each second synchronization check code corresponds one-to-one to each slave chip.

[0046] Optionally, the derived module includes:

[0047] A splitting submodule, configured to split the shared key to obtain a first sub-key and a second sub-key;

[0048] A first derivation submodule, configured to derive a synchronization check code for the first time based on the first sub-key and the second sub-key;

[0049] The second derivation submodule is used to derive the synchronization check code from the second derivation, and to derive the synchronization check code based on the synchronization check code formed in the previous derivation and the second sub-key.

[0050] Optionally, the sending module includes: a reading submodule, configured to obtain the first synchronization check code from a corresponding synchronization check code sequence in the main chip cache according to the sequence of the current synchronization task points.

[0051] Optionally, the reading submodule includes:

[0052] The sequence unit is used to determine the synchronization check code sequence according to the following formula: A = (x-1)*i+1; where A is the synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

[0053] Optionally, the verification module includes:

[0054] A reading unit, configured to sequentially read the second synchronization check code in the synchronization register in the master chip;

[0055] The sequence unit is used to determine the target synchronization check code sequence in the master chip cache according to the synchronization register sequence currently read each time the synchronization register in the master chip is read;

[0056] The verification unit is configured to read a third synchronization check code from the target synchronization check code sequence in the main chip cache, and verify the second synchronization check code according to the third synchronization check code.

[0057] Optionally, the sequential unit includes:

[0058] The sequence subunit is used to determine the target synchronization check code sequence according to the following formula: B = (x-1)*i+1+y; where B is the target synchronization check code sequence, y is the sequence of the synchronization registers currently read, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

[0059] In a fourth aspect, the present invention provides a multi-chip synchronization device, applied to a slave chip, comprising:

[0060] Negotiation module, used to negotiate the key with the main chip to determine the shared key;

[0061] A derivation module is used to derive multiple synchronization check codes in sequence based on the shared secret key and store them in the slave chip cache according to the derivation order;

[0062] a verification module, configured to read the first synchronization check code written by the master chip from the synchronization register of the slave chip, and perform verification based on the corresponding fourth synchronization check code in the slave chip cache;

[0063] A writing module is used to write a second synchronization check code into a corresponding synchronization register in the main chip according to a check result of the first synchronization check code.

[0064] Optionally, the derived module includes:

[0065] A splitting submodule, configured to split the shared key to obtain a first sub-key and a second sub-key;

[0066] A first derivation submodule, configured to derive a synchronization check code for the first time based on the first sub-key and the second sub-key;

[0067] The second derivation submodule is used to derive the synchronization check code from the second derivation, and to derive the synchronization check code based on the synchronization check code formed in the previous derivation and the second sub-key.

[0068] Optionally, the verification module includes: an extraction submodule, configured to extract the fourth synchronization check code from a corresponding synchronization check code sequence in the chip cache according to the sequence of the current synchronization task points.

[0069] Optionally, removing the submodule includes:

[0070] The extraction unit is used to determine the corresponding synchronization check code sequence according to the following formula: C = (x-1)*i+1, where C is the corresponding synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

[0071] Optionally, the writing module includes:

[0072] The target unit is used to determine the target synchronization check code sequence in the slave chip cache according to the slave chip sequence;

[0073] The fetching unit is used to read the synchronization check code to be processed from the target synchronization check code sequence;

[0074] A first writing unit is configured to use the synchronization check code to be processed as a second synchronization check code when the first synchronization check code passes the check;

[0075] The second writing unit is configured to, when the first synchronization check code fails to be checked, invert the synchronization check code to be processed as a second synchronization check code.

[0076] Optionally, the target unit includes:

[0077] The target subunit is used to determine the target synchronization check code sequence according to the following formula: D = (x-1)*i+1+z; where D is the target synchronization check code sequence, z is the sequence of the current slave chip among all slave chips, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

[0078] In the technical solution provided by the present invention, a shared key is derived in advance to ensure that the master chip and the slave chip use the same random key. Subsequently, the master chip and the slave chip respectively derive the synchronization check code based on the shared key. Since the synchronization check code of each chip is completed by itself and does not interact with any chip, it is ensured that it is not leaked during the derivation process of the synchronization check code. In the technical solution provided by the present invention, space is exchanged for time, and the data used for synchronization is derived in advance, and when the synchronization point arrives, it is directly used. The data used for each notification is derived, and an order preservation function is implicit to ensure that the data transmission is orderly. In a multi-chip environment, the master chip and the slave chip can be synchronized securely, and the synchronization process is efficient. There is no need for a handshake protocol and no need to consider order preservation issues. At the same time, each synchronization does not require large-scale encryption and decryption calculations and cannot be cracked. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 This is a flow chart of a multi-chip synchronization method according to an embodiment of the present invention;

[0080] Figure 2 This is a flowchart of a key derivation method for multi-chip synchronization according to an embodiment of the present invention;

[0081] Figure 3 This is a flow chart of the second synchronization check code verification of the multi-chip synchronization method according to an embodiment of the present invention;

[0082] Figure 4 This is a flow chart of a multi-chip synchronization method according to an embodiment of the present invention;

[0083] Figure 5 This is a flowchart of a key derivation method for multi-chip synchronization according to an embodiment of the present invention;

[0084] Figure 6 A flow chart showing the formation of a second synchronization check code for a multi-chip synchronization method according to an embodiment of the present invention;

[0085] Figure 7 This is a schematic diagram illustrating a specific example of the interactive process of key negotiation and derivation in a multi-chip synchronization method according to an embodiment of the present invention;

[0086] Figure 8 This is a schematic diagram illustrating a specific example of the interaction process of synchronization tasks in a multi-chip synchronization method according to an embodiment of the present invention;

[0087] Figure 9 A schematic diagram of a multi-chip synchronization device according to an embodiment of the present invention;

[0088] Figure 10 A schematic diagram of a derived module of a multi-chip synchronization device according to an embodiment of the present invention;

[0089] Figure 11A schematic diagram of a verification module of a multi-chip synchronization device according to an embodiment of the present invention;

[0090] Figure 12 A schematic diagram of a multi-chip synchronization device according to an embodiment of the present invention;

[0091] Figure 13 A schematic diagram of a derived module of a multi-chip synchronization device according to an embodiment of the present invention;

[0092] Figure 14 FIG. 1 is a schematic diagram of a writing module of a multi-chip synchronization device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0093] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0094] The embodiment of the present invention provides a multi-chip synchronization method, which is applied to a master chip, such as Figure 1 Shown, including:

[0095] Step 100: Key negotiation is performed with each slave chip to determine a shared key. In some embodiments, the master chip and slave chips perform key negotiation to form a random shared key, and both chips use the same random key. Since the subsequent synchronization check code is derived from the shared key, the shared key ensures that multiple chips derive the same synchronization check code. The randomness of the key ensures that the shared key cannot be cracked.

[0096] In step 200, multiple synchronization check codes are sequentially derived based on the shared secret key and stored in the master chip cache according to the derivation order. In some embodiments, the master chip and the slave chip derive synchronization check codes based on the shared secret key. During the derivation process, since the master chip and the slave chip use the same derivation method, the synchronization check codes derived by the master chip and the slave chip are identical, and different synchronization check codes are derived in the same order in different chips. During the storage process, the multiple synchronization check codes are stored according to the derivation order, so that different synchronization check codes are stored in the same order in the caches of multiple chips. Because the key derivation task is completed by this chip itself, the master chip and other chips do not interact at this stage, and attackers cannot initiate the key derivation task of the slave chip, thus ensuring the security of the key derivation stage.

[0097] Step 300, when entering the synchronization task point, obtain the first synchronization check code corresponding to the current synchronization task point from the master chip cache and write it into the synchronization register of the slave chip; so that the slave chip verifies the first synchronization check code and sends the second synchronization check code to the corresponding synchronization register in the master chip based on the verification result; in some embodiments, each time the synchronization task point is entered, the master chip cache is searched in sequence to determine which synchronization check code stored in the cache corresponds to the current synchronization task point. For example, when entering the synchronization task point for the first time, the synchronization check code with a sequence of 1 in the cache is selected as the first synchronization check code, and when entering the synchronization task point for the second time, the synchronization check code with a sequence of i+1 in the cache is selected as the first synchronization check code, where i is the total number of master chips and slave chips. After determining the first synchronization check code, the first synchronization check code is written into the synchronization register of the slave chip for verification by the slave chip.

[0098] Step 400 sequentially obtains each second synchronization check code in the synchronization register of the master chip and verifies it based on the corresponding third synchronization check code in the master chip's cache, wherein each second synchronization check code corresponds one-to-one with each slave chip. In some embodiments, the number of synchronization registers in the master chip is at least the same as the number of slave chips, thereby enabling a one-to-one correspondence between each slave chip and the synchronization register in the master chip. That is, one synchronization register in the master chip is used to write the second synchronization check code of one slave chip. When reading, reading the first synchronization register indicates that the second synchronization check code currently being read is the synchronization register sent by the first slave chip. Among the multiple synchronization check codes stored in the cache, the multiple consecutive synchronization check codes after the first synchronization check code are multiple third synchronization check codes, and the multiple third synchronization check codes correspond one-to-one with the second synchronization check codes sent by the multiple slave chips. For example, the second synchronization check code sent by the slave chip with sequence 1 will be written to the synchronization register with sequence 1 in the master chip, and the third synchronization check code stored in the master chip's cache with sequence 2 corresponds to the second synchronization check code stored in the synchronization register with sequence 1.

[0099] In the technical solution provided by the embodiment of the present invention, the shared key is derived in advance to ensure that the master chip and the slave chip use the same random key. Subsequently, the master chip and the slave chip respectively derive the synchronization check code based on the co-occurrence key. Since the synchronization check code of each chip is completed by itself and does not interact with any chip, it is ensured that it is not leaked during the derivation process of the synchronization check code. In the technical solution provided by the present invention, space is exchanged for time, and the data used for synchronization is derived in advance, and when the synchronization point arrives, it is directly used. The data used for each notification is derived, and an order preservation function is implied to ensure that the data transmission is orderly. In a multi-chip environment, the master chip and the slave chip can be synchronized securely, and the synchronization process is efficient. There is no need for a handshake protocol and no need to consider order preservation issues. At the same time, each synchronization does not require large-scale encryption and decryption calculations and cannot be cracked.

[0100] As an optional implementation, Figure 2 As shown, in step 200, based on the shared secret key, multiple synchronization check codes are sequentially derived and stored in the main chip cache according to the derivation order, including:

[0101] Step 210: Split the shared key to obtain a first sub-key and a second sub-key. In some embodiments, the shared key is a random key negotiated between the master chip and the slave chip. During the splitting process, the master chip and the slave chip split the shared key in the same manner. Thus, after the splitting, the master chip and the slave chip obtain the same first sub-key and the same second sub-key.

[0102] In step 220, a synchronization check code is derived for the first time based on the first sub-key and the second sub-key. In some embodiments, when the first derivation is performed, since there are only the first sub-key and the second sub-key, the first sub-key and the second sub-key are operated to obtain the synchronization check code derived for the first time.

[0103] Step 230 , starting with the second derivation of the synchronization check code, a synchronization check code is derived based on the previously derived synchronization check code and the second sub-key. In some embodiments, starting with the second derivation of the synchronization check code, the later derived synchronization check code is associated with the previously derived synchronization check code, thereby implicitly implementing an order preservation function, ensuring that subsequent data transmission processes are transmitted in order.

[0104] As a specific implementation, for example, the synchronization check code can be derived based on a hash algorithm, and the derivation process is as follows:

[0105] Split the shared key into R', R";

[0106] Perform the first key derivation K(1)=HASH(R|(R″+1));

[0107] Perform the second key derivation K(2)=HASH(K(1)|(R”+2));

[0108] Perform the nth key derivation K(n)=HASH(K(n-1)|(R″+n));

[0109] As another specific implementation, for example, an encryption algorithm may be used to implement the derivation of the synchronization check code, and the derivation process is as follows:

[0110] Split the shared key into R', R";

[0111] Perform the first key derivation K(1)=Enc(R',R');

[0112] Perform the second key derivation K(2)=Enc(K(1),R”);

[0113] Perform the nth key derivation K(n)=Enc(K(n-1),R”).

[0114] As an optional implementation, in step 300, when entering the synchronization task point, obtaining the first synchronization check code corresponding to the current synchronization task point from the master chip cache and writing it into the synchronization register of the slave chip includes: obtaining the first synchronization check code from the corresponding synchronization check code sequence in the master chip cache according to the order of the current synchronization task point. In some embodiments, the order of the current synchronization task point refers to the number of times the synchronization task point is entered. Since a certain number of synchronization check codes are used each time a synchronization task point is entered, the next time entry is made, a synchronization check code after the last synchronization check code when the synchronization task point was last entered is used as the first synchronization check code. Therefore, the selection of the first synchronization check code is directly related to the order of the current synchronization task point.

[0115] As an optional implementation manner, obtaining the first synchronization check code from the corresponding synchronization check code sequence in the master chip cache according to the sequence of the current synchronization task points includes:

[0116] The corresponding synchronization check code sequence in the cache is determined according to the following formula: A = (x-1)*i+1; where A is the corresponding synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code uses 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are all different. Therefore, there will be i-1 second synchronization check codes, that is, i synchronization check codes will be used each time a synchronization task point is entered. The next time a synchronization check code is entered, the i+1th synchronization check code can be used as the first synchronization check code.

[0117] As an optional implementation, Figure 3 As shown, in step 400, sequentially obtaining the second synchronization check code in the synchronization register of the master chip and performing verification according to the corresponding third synchronization check code in the master chip cache includes:

[0118] Step 410: Read the second synchronization check codes from the synchronization registers of the master chip in sequence. In some embodiments, the master chip has at least the same number of synchronization registers as the slave chips, so that the second synchronization check codes sent by the slave chips can be written into the synchronization registers of the master chip in a one-to-one correspondence. During the reading process, the order of the synchronization registers in the master chip represents the order of the corresponding slave chips.

[0119] In step 420, each time the synchronization register in the master chip is read, the target synchronization check code sequence in the master chip cache is determined based on the sequence of the synchronization registers currently read. In some embodiments, among the multiple synchronization check codes stored in the master chip, since the synchronization check code with sequence 1 was used as the first synchronization check code in step 300, in the subsequent verification process, multiple consecutive check codes following the first synchronization check code are used as third synchronization check codes to verify the second synchronization check codes sent by different slave chips. The selection process of the multiple third synchronization check codes corresponds to the sequence of the multiple slave chips. For example, when entering the first synchronization task point, the second synchronization check code sent by the slave chip with sequence 1 needs to be verified using the third synchronization check code with sequence 2 in the master chip cache.

[0120] Step 430: Read a third synchronization check code from the target synchronization check code sequence in the master chip cache, and verify the second synchronization check code based on the third synchronization check code. In some embodiments, during the verification process, the second synchronization check code and the third synchronization check code can be compared to see if they are identical. If the two are identical, the verification passes; if they are different, the verification fails.

[0121] As an optional implementation, in step 420, each time the synchronization register in the master chip is read, determining the target synchronization check code sequence in the master chip cache according to the currently read synchronization register sequence includes:

[0122] The target synchronization check code sequence is determined according to the following formula: B = (x-1) * i + 1 + y; wherein B is the target synchronization check code sequence, y is the sequence of the synchronization registers currently read, x is the sequence of the current synchronization task point, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code will use 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are all different, therefore, there will be i-1 second synchronization check codes, that is, each time the synchronization task point is entered, i synchronization check codes will be used. The next time it is entered, the i+1th synchronization check code can be used as the first synchronization check code. Each time a synchronization task point is entered, the first synchronization check code and the second synchronization check code are selected in ascending order.

[0123] In each of the above embodiments, multiple synchronization check codes arranged in sequence in the main chip cache can be used cyclically. For example, when there are n synchronization check codes in the main chip, when the synchronization check code sequence to be selected is n+1, the synchronization check code with sequence 1 can be selected.

[0124] In the above-mentioned embodiments, the cache of the master chip may be located in a secure area within the chip, so that only secure processes can access it, thereby enhancing the storage security of the synchronization check code.

[0125] The embodiment of the present invention provides a multi-chip synchronization method, which is applied to a slave chip, such as Figure 4 As shown, including:

[0126] Step 500: Key negotiation is performed with the master chip to determine a shared key. In some embodiments, the master chip and the slave chip perform key negotiation to form a random shared key, and both the master and slave chips use the same random key. Since the subsequent synchronization check code is derived based on the shared key, the shared key here ensures that multiple chips derive the same synchronization check code. The randomness of the key ensures that the shared key cannot be cracked.

[0127] In step 600, multiple synchronization check codes are sequentially derived based on the shared secret key and stored in the slave chip cache according to the derivation order. In some embodiments, the master chip and the slave chip derive synchronization check codes based on the shared secret key. During the derivation process, since the master chip and the slave chip use the same derivation method, the synchronization check codes derived by the master chip and the slave chip are identical, and different synchronization check codes are derived in the same order in different chips. During the storage process, the multiple synchronization check codes are stored according to the derivation order, so that different synchronization check codes are stored in the same order in the caches of multiple chips. Because the key derivation task is completed by this chip itself, the master chip and other chips do not interact at this stage, and attackers cannot initiate the key derivation task of the slave chip, thus ensuring the security of the key derivation stage.

[0128] In step 700, the first synchronization check code written by the master chip is read from the synchronization register of the slave chip, and is verified based on the corresponding fourth synchronization check code in the slave chip cache. In some embodiments, the master chip cache and the slave chip cache store synchronization check codes with the same content and order. When the first synchronization check code is received, in order to verify whether the first synchronization check code is correct, the synchronization check code of the same order can be read from the slave chip cache as the fourth synchronization check code, and the two can be compared to see if they are the same.

[0129] Step 800, based on the verification result of the first synchronization check code, write the second synchronization check code to the corresponding synchronization register in the master chip. In some embodiments, the master chip cache and the slave chip cache store synchronization check codes with the same content and order. In order to make the second synchronization check code of each slave chip different, it is necessary to read a synchronization check code with a corresponding synchronization check code sequence in the cache as its own second synchronization check code after the first synchronization check code. For example, a slave chip with a sequence of 1 can read a synchronization check code with a corresponding synchronization check code sequence of 2 in the cache as the second synchronization check code. In some embodiments, the number of synchronization registers in the master chip is at least the same as the number of slave chips, so that the slave chip can correspond one-to-one with the synchronization register in the master chip, that is, one synchronization register in the master chip is used to write the second synchronization check code of a slave chip. When reading, reading the first synchronization register indicates that the second synchronization check code currently read is the synchronization register sent by the first slave chip.

[0130] In the technical solution provided by the embodiment of the present invention, the shared key is derived in advance to ensure that the master chip and the slave chip use the same random key. Subsequently, the master chip and the slave chip respectively derive the synchronization check code based on the co-occurrence key. Since the synchronization check code of each chip is completed by itself and does not interact with any chip, it is ensured that it is not leaked during the derivation process of the synchronization check code. In the technical solution provided by the present invention, space is exchanged for time, and the data used for synchronization is derived in advance, and when the synchronization point arrives, it is directly used. The data used for each notification is derived, and an order preservation function is implied to ensure that the data transmission is orderly. In a multi-chip environment, the master chip and the slave chip can be synchronized securely, and the synchronization process is efficient. There is no need for a handshake protocol and no need to consider order preservation issues. At the same time, each synchronization does not require large-scale encryption and decryption calculations and cannot be cracked.

[0131] As an optional implementation, Figure 5 As shown, in step 600, based on the shared secret key, multiple synchronization check codes are sequentially derived and stored in the slave chip cache according to the derivation order, including:

[0132] Step 610: Split the shared key to obtain a first sub-key and a second sub-key. In some embodiments, the shared key is a random key negotiated between the master chip and the slave chip. During the splitting process, the master chip and the slave chip split the shared key in the same manner. Thus, after the splitting, the master chip and the slave chip obtain the same first sub-key and the same second sub-key.

[0133] In step 620, a synchronization check code is derived for the first time based on the first sub-key and the second sub-key. In some embodiments, when the first derivation is performed, since there are only the first sub-key and the second sub-key, the first sub-key and the second sub-key are operated to obtain the synchronization check code derived for the first time.

[0134] Step 630: Starting from the second derivation of the synchronization check code, a synchronization check code is derived based on the synchronization check code derived from the previous derivation and the second sub-key. In some embodiments, starting from the second derivation of the synchronization check code, the subsequent derived synchronization check code is associated with the previous derived synchronization check code, thereby implicitly maintaining order and ensuring that subsequent data transmission is in order.

[0135] As a specific implementation, for example, the synchronization check code can be derived based on a hash algorithm, and the derivation process is as follows:

[0136] Split the shared key into R', R";

[0137] Perform the first key derivation K(1)=HASH(R|(R″+1));

[0138] Perform the second key derivation K(2)=HASH(K(1)|(R”+2));

[0139] Perform the nth key derivation K(n)=HASH(K(n-1)|(R″+n));

[0140] As another specific implementation, for example, an encryption algorithm may be used to implement the derivation of the synchronization check code, and the derivation process is as follows:

[0141] Split the shared key into R', R";

[0142] Perform the first key derivation K(1)=Enc(R',R');

[0143] Perform the second key derivation K(2)=Enc(K(1),R”);

[0144] Perform the nth key derivation K(n)=Enc(K(n-1),R”).

[0145] As an optional implementation, in step 800, verification based on the corresponding fourth synchronization check code from the chip cache includes: according to the order of the current synchronization task point, taking out the fourth synchronization check code from the corresponding synchronization check code order from the chip cache. In some embodiments, the order of the current synchronization task point refers to the number of times the synchronization task point is currently entered. Since a certain number of synchronization check codes are used each time a synchronization task point is entered, the next time the synchronization task point is entered, a synchronization check code after the last synchronization check code when the synchronization task point was last entered is used as the first synchronization check code. Therefore, the selection of the first synchronization check code is directly related to the order of the current synchronization task point. The fourth synchronization check code used to verify the first synchronization check code should be a synchronization check code with the same order as the first synchronization check code. Therefore, the same method can be used to determine the corresponding synchronization check code order in its cache.

[0146] As an optional implementation manner, according to the order of the current synchronization task points, extracting the fourth synchronization check code from the corresponding synchronization check code sequence in the chip cache includes:

[0147] The corresponding synchronization check code sequence is determined according to the following formula: C = (x-1) * i + 1, where C is the corresponding synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code will use 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are all different. Therefore, there will be i-1 second synchronization check codes, that is, each time the synchronization task point is entered, i synchronization check codes will be used. The next time it is entered, the i+1th synchronization check code can be used as the first synchronization check code. The fourth synchronization check code used to verify the first synchronization check code should be a synchronization check code with the same sequence as the first synchronization check code. Therefore, the same method can be used to determine the corresponding synchronization check code sequence in its cache.

[0148] As an optional implementation, Figure 6 As shown, in step 800, writing a second synchronization check code into a corresponding synchronization register in the master chip according to a check result of the first synchronization check code includes:

[0149] Step 810 determines the target synchronization check code sequence in the slave chip cache based on the slave chip sequence. In some embodiments, among the multiple synchronization check codes stored in the master chip, since the synchronization check code with sequence 1 was used as the fourth synchronization check code in step 700, multiple consecutive check codes following the fourth synchronization check code are used as the second synchronization check codes in the subsequent verification process, so that different slave chips have synchronization check codes with corresponding synchronization check code sequences in different caches. The selection process of multiple second synchronization check codes corresponds to the sequence of the multiple slave chips. For example, when entering the first synchronization task point, the slave chip with sequence 1 needs to use the target synchronization check code sequence with sequence 2 in the slave chip cache.

[0150] Step 820, read the synchronization check code to be processed from the target synchronization check code sequence; in some embodiments, since the second synchronization check code needs to represent the result of the first synchronization check code, the synchronization check codes in the target synchronization check code sequence need to be processed according to different check results.

[0151] Step 830, when the first synchronization check code is checked and passed, the synchronization check code to be processed is used as the second synchronization check code; in some embodiments, when the first synchronization check code is checked and passed, the synchronization check code to be processed is not processed, so that when the main chip uses the third synchronization check code for verification, it can pass the verification and enable the synchronization task to be carried out.

[0152] Step 840: When the first synchronization check code fails to be verified, the synchronization check code to be processed is inverted as the second synchronization check code. In some embodiments, when the first synchronization check code fails to be verified, the synchronization check code to be processed is inverted, so that when the master chip uses the third synchronization check code for verification, it cannot pass the verification, causing the synchronization task to fail.

[0153] As an optional implementation, in step 810, determining the target synchronization check code sequence in the slave chip cache according to the slave chip sequence includes:

[0154] The target synchronization check code sequence is determined according to the following formula: D = (x-1) * i + 1 + z; wherein D is the target synchronization check code sequence, z is the sequence of the current slave chip among all slave chips, x is the sequence of the current synchronization task point, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code will use 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are all different, therefore, there will be i-1 second synchronization check codes, that is, each time the synchronization task point is entered, i synchronization check codes will be used. The next time it is entered, the i+1th synchronization check code can be used as the first synchronization check code. Each time a synchronization task point is entered, the first synchronization check code and the second synchronization check code are selected in ascending order.

[0155] In each of the above embodiments, multiple synchronization check codes arranged in sequence in the main chip cache can be used cyclically. For example, when there are n synchronization check codes in the main chip, when the synchronization check code sequence to be selected is n+1, the synchronization check code with sequence 1 can be selected.

[0156] In the above-mentioned embodiments, the cache of the master chip may be located in a secure area within the chip, so that only secure processes can access it, thereby enhancing the storage security of the synchronization check code.

[0157] like Figure 7-Figure 8 As shown, the above implementation modes are described below by taking the synchronization process of a task point with order 1 as an example:

[0158] During the initialization phase:

[0159] The master chip negotiates keys with all slave chips to obtain the shared key R

[0160] The master chip and the slave chip derive keys based on the shared key R and store them in their respective internal caches; the cache should be in a secure area inside the chip and only accessible to secure processes.

[0161] During the safe synchronization phase:

[0162] The main chip enters the task synchronization point.

[0163] The master chip obtains the current synchronization check code M(1) from the cache as the first synchronization check code, that is, obtains the synchronization check code with the corresponding synchronization check code sequence of 1 in the cache of the master chip as the first synchronization check code.

[0164] Write the synchronization check code M(1) into the synchronization register of slave chips 1 to (i-1) and notify all slave chips 1 to (i-1).

[0165] Slave chips 1 to (i-1) receive notification from the master chip.

[0166] The slave chip obtains the sent synchronization check code M(1) from the synchronization register.

[0167] The slave chip synchronization information S(1) is obtained from the cache as the fourth synchronization check code, that is, the synchronization check code with the corresponding synchronization check code sequence of 1 in the cache of the slave chip is obtained as the fourth synchronization check code.

[0168] Compare M(1) and S(1).

[0169] If the comparison is successful, it indicates that the synchronization is successful, and the synchronization check code is taken out from the cache area. The synchronization check code is S (1 + slave chip order) as the second synchronization check code, that is, each slave chip determines the target synchronization check code order in its own cache based on its own order among all slave chips. The synchronization check code stored in the target synchronization check code order is the second synchronization check code.

[0170] If the comparison fails, it indicates that the synchronization has failed. The synchronization check code S (1 + slave chip order) is taken out from the cache area and inverted as the second synchronization check code. That is, each slave chip determines the target synchronization check code order in its own cache based on its own order among all slave chips. The inverted synchronization check code stored in the target synchronization check code order is the second synchronization check code.

[0171] Write the synchronization check code into the master chip synchronization register (1-i) and notify the master chip.

[0172] The master chip receives the notification and performs a loop process. The number of loops is i-1. Each loop reads the second synchronization check code in a synchronization register of the master chip. The next loop reads the second synchronization check code in the synchronization register that was incremented by 1 in the previous loop. The single loop process is as follows:

[0173] The second synchronization check code S (1+slave chip order) is read from the synchronization register. Since the synchronization register order in the master chip corresponds to the slave chip order one-to-one, the slave chip corresponding to the second synchronization check code can be directly determined based on the order of the currently read synchronization registers.

[0174] The synchronization check code M (1+slave chip sequence) currently used to check the slave chip is taken out from the master chip cache as the third synchronization check code, that is, the synchronization check code corresponding to the synchronization check code sequence of 1+slave chip sequence in the cache is read from the master chip cache as the third synchronization check code;

[0175] Compare M(1+order from chip) and S(1+order from chip):

[0176] If the comparison is successful, the master chip obtains the current synchronization result of the corresponding slave chip and proceeds to the next task;

[0177] If the comparison fails, the main chip reports an error.

[0178] Those skilled in the art will appreciate that the above example is based on a task point sequence of 1. When the task point sequence is other than 1, the calculation can be performed using the aforementioned formula. For example, when the current task point sequence is 2, the first synchronization check code is M(i+1), i.e., the synchronization check code corresponding to the synchronization check code sequence i+1 in the master chip cache.

[0179] The embodiment of the present invention provides a multi-chip synchronization device, which is applied to a master chip, such as Figure 9 As shown, including:

[0180] The negotiation module is configured to perform key negotiation with each slave chip to determine a shared key. In some embodiments, the master chip and slave chip perform key negotiation to form a random shared key, and both the master and slave chips use the same random key. Since the subsequent synchronization check code is derived based on the shared key, the shared key ensures that multiple chips derive the same synchronization check code. The randomness of the key ensures that the shared key cannot be cracked.

[0181] A derivation module is used to derive multiple synchronization check codes in sequence based on a shared secret key and store them in the master chip cache according to the derivation order. In some embodiments, the master chip and the slave chip derive synchronization check codes based on the shared secret key. During the derivation process, since the master chip and the slave chip use the same derivation method, the synchronization check codes derived by the master chip and the slave chip are the same, and the order in which different synchronization check codes are derived in different chips is the same. During the storage process, the multiple synchronization check codes are stored according to the derivation order, so that different synchronization check codes are stored in the same order in the caches of multiple chips. Since the key derivation task is completed by this chip itself, the master chip and other chips do not interact at this stage, and attackers cannot initiate the key derivation task of the slave chip, thereby ensuring the security of the key derivation stage.

[0182] The sending module is used to obtain the first synchronization check code corresponding to the current synchronization task point from the master chip cache and write it into the synchronization register of the slave chip when entering the synchronization task point; so that the slave chip verifies the first synchronization check code and sends the second synchronization check code to the corresponding synchronization register in the master chip based on the verification result; in some embodiments, each time the synchronization task point is entered, the master chip cache is searched in sequence to determine which synchronization check code stored in the cache corresponds to the current synchronization task point. For example, when entering the synchronization task point for the first time, the synchronization check code with a sequence of 1 in the cache is selected as the first synchronization check code, and when entering the synchronization task point for the second time, the synchronization check code with a sequence of i+1 in the cache is selected as the first synchronization check code, where i is the total number of master chips and slave chips. After determining the first synchronization check code, the first synchronization check code is written into the synchronization register of the slave chip for verification by the slave chip.

[0183] A verification module is configured to sequentially obtain each second synchronization check code from the synchronization registers of the master chip and verify it based on the corresponding third synchronization check code in the master chip's cache, wherein each second synchronization check code corresponds one-to-one to each slave chip. In some embodiments, the number of synchronization registers in the master chip is at least the same as the number of slave chips, thereby enabling a one-to-one correspondence between the slave chips and the synchronization registers in the master chip. That is, one synchronization register in the master chip is used to write the second synchronization check code of one slave chip. When reading, reading the first synchronization register indicates that the second synchronization check code currently being read is the synchronization register sent by the first slave chip. Among the multiple synchronization check codes stored in the cache, the multiple consecutive synchronization check codes following the first synchronization check code are multiple third synchronization check codes, and the multiple third synchronization check codes correspond one-to-one to the second synchronization check codes sent by the multiple slave chips. For example, the second synchronization check code sent by the slave chip with sequence 1 will be written to the synchronization register with sequence 1 in the master chip, and the third synchronization check code stored in the master chip's cache with sequence 2 corresponds to the second synchronization check code stored in the synchronization register with sequence 1.

[0184] In the technical solution provided by the embodiment of the present invention, a shared key is derived in advance to ensure that the master chip and the slave chip use the same random key. Subsequently, the master chip and the slave chip respectively derive the synchronization check code based on the shared key. Since the synchronization check code of each chip is completed by itself and does not interact with any chip, it is ensured that it is not leaked during the derivation process of the synchronization check code. In the technical solution provided by the present invention, space is exchanged for time, and the data used for synchronization is derived in advance, and when the synchronization point arrives, it is directly used. The data used for each notification is derived, and an order preservation function is implied to ensure that the data transmission is orderly. In a multi-chip environment, the master chip and the slave chip can be synchronized securely, and the synchronization process is efficient. There is no need for a handshake protocol and no need to consider order preservation issues. At the same time, each synchronization does not require large-scale encryption and decryption calculations and cannot be cracked.

[0185] As an optional implementation, Figure 10 As shown, the derived module includes:

[0186] The splitting submodule is configured to split the shared key to obtain a first sub-key and a second sub-key. In some embodiments, the shared key is a random key negotiated between the master chip and the slave chip. During the splitting process, the master chip and the slave chip split the shared key in the same manner. Thus, after the splitting, the master chip and the slave chip obtain the same first sub-key and the same second sub-key.

[0187] The first derivation submodule is used to derive a synchronization check code for the first time based on the first sub-key and the second sub-key. In some embodiments, when the derivation is performed for the first time, since there are only the first sub-key and the second sub-key, the first sub-key and the second sub-key are operated to obtain the synchronization check code derived for the first time.

[0188] The second derivation submodule is configured to, starting from the second derivation of the synchronization check code, derive a synchronization check code based on the synchronization check code generated in the previous derivation and the second sub-key. In some embodiments, starting from the second derivation of the synchronization check code, the synchronization check code generated in the subsequent derivation is associated with the synchronization check code generated in the previous derivation, thereby implicitly implementing an order preservation function and ensuring that subsequent data transmission processes are transmitted in an orderly manner.

[0189] As a specific implementation, for example, the synchronization check code can be derived based on a hash algorithm, and the derivation process is as follows:

[0190] Split the shared key into R', R";

[0191] Perform the first key derivation K(1)=HASH(R|(R″+1));

[0192] Perform the second key derivation K(2)=HASH(K(1)|(R”+2));

[0193] Perform the nth key derivation K(n)=HASH(K(n-1)|(R″+n));

[0194] As another specific implementation, for example, an encryption algorithm may be used to implement the derivation of the synchronization check code, and the derivation process is as follows:

[0195] Split the shared key into R', R";

[0196] Perform the first key derivation K(1)=Enc(R',R');

[0197] Perform the second key derivation K(2)=Enc(K(1),R”);

[0198] Perform the nth key derivation K(n)=Enc(K(n-1),R”).

[0199] As an optional embodiment, the sending module includes: a reading submodule, which is used to obtain a first synchronization check code from the corresponding synchronization check code sequence in the main chip cache according to the order of the current synchronization task point. In some embodiments, the order of the current synchronization task point refers to the number of times the synchronization task point is currently entered. Since a certain number of synchronization check codes are used each time a synchronization task point is entered, the next time the synchronization task point is entered, a synchronization check code after the last synchronization check code when the synchronization task point was last entered is used as the first synchronization check code. Therefore, the selection of the first synchronization check code is directly related to the order of the current synchronization task point.

[0200] As an optional implementation, the reading submodule includes:

[0201] The sequence unit is used to determine the corresponding synchronization check code sequence in the cache according to the following formula: A = (x-1) * i + 1; where A corresponds to the synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code will use 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are different. Therefore, there will be i-1 second synchronization check codes, that is, i synchronization check codes will be used each time a synchronization task point is entered. The next time it is entered, the i+1th synchronization check code can be used as the first synchronization check code.

[0202] As an optional implementation, Figure 11 As shown, the verification module includes:

[0203] The reading unit is configured to sequentially read the second synchronization check codes from the synchronization registers in the master chip. In some embodiments, the master chip has at least the same number of synchronization registers as the slave chips, so that the second synchronization check codes sent by the slave chips can be written into the synchronization registers of the master chip in a one-to-one correspondence. During the reading process, the order of the synchronization registers in the master chip represents the order of the corresponding slave chips.

[0204] The sequence unit is used to read the synchronization registers in the master chip each time and determine the target synchronization check code sequence in the master chip cache based on the currently read synchronization register sequence. In some embodiments, among the multiple synchronization check codes stored in the master chip, since the synchronization check code with sequence 1 is used as the first synchronization check code in the sending module, in the subsequent verification process, multiple consecutive check codes after the first synchronization check code are used as third synchronization check codes to verify the second synchronization check codes sent by different slave chips. The selection process of the multiple third synchronization check codes corresponds to the sequence of the multiple slave chips. For example, when entering the first synchronization task point, the second synchronization check code sent by the slave chip with sequence 1 needs to be verified using the third synchronization check code with sequence 2 in the master chip cache.

[0205] The verification unit is configured to read a third synchronization check code from the target synchronization check code sequence in the master chip cache and verify the second synchronization check code based on the third synchronization check code. In some embodiments, during the verification process, the second synchronization check code and the third synchronization check code may be compared to determine whether they are identical. If the second synchronization check code and the third synchronization check code are identical, the verification passes; if the second synchronization check code and the third synchronization check code are different, the verification fails.

[0206] As an optional implementation, the sequence unit includes:

[0207] The sequence subunit is used to determine the target synchronization check code sequence according to the following formula: B = (x-1) * i + 1 + y; wherein B is the target synchronization check code sequence, y is the sequence of the synchronization registers currently read, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code will use 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are all different, and therefore, there will be i-1 second synchronization check codes, that is, each time the synchronization task point is entered, i synchronization check codes will be used. The next time it is entered, the i+1th synchronization check code can be used as the first synchronization check code. Each time a synchronization task point is entered, the first synchronization check code and the second synchronization check code are selected in ascending order.

[0208] In each of the above embodiments, multiple synchronization check codes arranged in sequence in the main chip cache can be used cyclically. For example, when there are n synchronization check codes in the main chip, when the synchronization check code sequence to be selected is n+1, the synchronization check code with sequence 1 can be selected.

[0209] In the above-mentioned embodiments, the cache of the master chip may be located in a secure area within the chip, so that only secure processes can access it, thereby enhancing the storage security of the synchronization check code.

[0210] The embodiment of the present invention provides a multi-chip synchronization device, which is applied to a slave chip, such as Figure 12 As shown, including:

[0211] The negotiation module is configured to perform key negotiation with the master chip to determine a shared key. In some embodiments, the master chip and the slave chip perform key negotiation to form a random shared key, and both the master and slave chips use the same random key. Since the subsequent synchronization check code is derived based on the shared key, the shared key ensures that multiple chips derive the same synchronization check code. The randomness of the key ensures that the shared key cannot be cracked.

[0212] A derivation module is used to derive multiple synchronization check codes in sequence based on a shared secret key and store them in the slave chip cache according to the derivation order. In some embodiments, the master chip and the slave chip derive synchronization check codes based on the shared secret key. During the derivation process, since the master chip and the slave chip use the same derivation method, the synchronization check codes derived by the master chip and the slave chip are the same, and the order in which different synchronization check codes are derived in different chips is the same. During the storage process, the multiple synchronization check codes are stored according to the derivation order, so that different synchronization check codes are stored in the same order in the caches of multiple chips. Since the key derivation task is completed by this chip itself, the master chip and other chips do not interact at this stage, and attackers cannot initiate the key derivation task of the slave chip, thereby ensuring the security of the key derivation stage.

[0213] A verification module is used to read the first synchronization check code written by the master chip from the synchronization register of the slave chip, and verify it based on the corresponding fourth synchronization check code in the slave chip cache; in some embodiments, the master chip cache and the slave chip cache store synchronization check codes with the same content and order. When the first synchronization check code is received, in order to verify whether the first synchronization check code is correct, the synchronization check code of the same order can be read from the slave chip cache as the fourth synchronization check code, and the two can be compared to see if they are the same.

[0214] A writing module is used to write a second synchronization check code into the corresponding synchronization register in the master chip based on the verification result of the first synchronization check code. In some embodiments, the master chip cache and the slave chip cache store synchronization check codes with the same content and order. In order to make the second synchronization check code of each slave chip different, it is necessary to read a synchronization check code with a corresponding synchronization check code sequence in the cache as its own second synchronization check code after the first synchronization check code. For example, a slave chip with a sequence of 1 can read a synchronization check code with a corresponding synchronization check code sequence of 2 in the cache as the second synchronization check code. In some embodiments, the number of synchronization registers in the master chip is at least the same as the number of slave chips, so that the slave chip can correspond one-to-one with the synchronization register in the master chip, that is, one synchronization register in the master chip is used to write the second synchronization check code of a slave chip. When reading, reading the first synchronization register indicates that the second synchronization check code currently read is the synchronization register sent by the first slave chip.

[0215] In the technical solution provided by the embodiment of the present invention, a shared key is derived in advance to ensure that the master chip and the slave chip use the same random key. Subsequently, the master chip and the slave chip respectively derive the synchronization check code based on the shared key. Since the synchronization check code of each chip is completed by itself and does not interact with any chip, it is ensured that it is not leaked during the derivation process of the synchronization check code. In the technical solution provided by the present invention, space is exchanged for time, and the data used for synchronization is derived in advance, and when the synchronization point arrives, it is directly used. The data used for each notification is derived, and an order preservation function is implied to ensure that the data transmission is orderly. In a multi-chip environment, the master chip and the slave chip can be synchronized securely, and the synchronization process is efficient. There is no need for a handshake protocol and no need to consider order preservation issues. At the same time, each synchronization does not require large-scale encryption and decryption calculations and cannot be cracked.

[0216] As an optional implementation, Figure 13 As shown, the derived module includes:

[0217] The splitting submodule is configured to split the shared key to obtain a first sub-key and a second sub-key. In some embodiments, the shared key is a random key negotiated between the master chip and the slave chip. During the splitting process, the master chip and the slave chip split the shared key in the same manner. Thus, after the splitting, the master chip and the slave chip obtain the same first sub-key and the same second sub-key.

[0218] The first derivation submodule is used to derive a synchronization check code for the first time based on the first sub-key and the second sub-key. In some embodiments, when the derivation is performed for the first time, since there are only the first sub-key and the second sub-key, the first sub-key and the second sub-key are operated to obtain the synchronization check code derived for the first time.

[0219] The second derivation submodule is configured to, starting from the second derivation of the synchronization check code, derive a synchronization check code based on the synchronization check code generated in the previous derivation and the second sub-key. In some embodiments, starting from the second derivation of the synchronization check code, the synchronization check code generated in the subsequent derivation is associated with the synchronization check code generated in the previous derivation, thereby implicitly implementing an order preservation function and ensuring that subsequent data transmission processes are transmitted in an orderly manner.

[0220] As a specific implementation, for example, the synchronization check code can be derived based on a hash algorithm, and the derivation process is as follows:

[0221] Split the shared key into R', R";

[0222] Perform the first key derivation K(1)=HASH(R|(R″+1));

[0223] Perform the second key derivation K(2)=HASH(K(1)|(R”+2));

[0224] Perform the nth key derivation K(n)=HASH(K(n-1)|(R″+n));

[0225] As another specific implementation, for example, an encryption algorithm may be used to implement the derivation of the synchronization check code, and the derivation process is as follows:

[0226] Split the shared key into R', R";

[0227] Perform the first key derivation K(1)=Enc(R',R');

[0228] Perform the second key derivation K(2)=Enc(K(1),R”);

[0229] Perform the nth key derivation K(n)=Enc(K(n-1),R”).

[0230] As an optional implementation, the verification module includes: a fetching submodule, which is used to fetch the fourth synchronization check code from the corresponding synchronization check code sequence in the chip cache according to the order of the current synchronization task point. In some embodiments, the order of the current synchronization task point refers to the number of times the synchronization task point is currently entered. Since a certain number of synchronization check codes are used each time a synchronization task point is entered, the next time the synchronization check code is entered, a synchronization check code after the last synchronization check code when the synchronization task point was last entered is used as the first synchronization check code. Therefore, the selection of the first synchronization check code is directly related to the order of the current synchronization task point. The fourth synchronization check code used when verifying the first synchronization check code should be a synchronization check code with the same order as the first synchronization check code. Therefore, the same method can be used to determine the corresponding synchronization check code order in its cache.

[0231] As an optional implementation, removing the submodule includes:

[0232] The fetching unit is used to determine the corresponding synchronization check code sequence according to the following formula: C = (x-1) * i + 1, where C is the corresponding synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code will use 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are all different, so there will be i-1 second synchronization check codes, that is, each time the synchronization task point is entered, i synchronization check codes will be used. The next time it enters, the i+1th synchronization check code can be used as the first synchronization check code. The fourth synchronization check code used to verify the first synchronization check code should be a synchronization check code with the same sequence as the first synchronization check code. Therefore, the same method can be used to determine the corresponding synchronization check code sequence in its cache.

[0233] As an optional implementation, the writing module includes:

[0234] The target unit is used to determine the target synchronization check code sequence in the slave chip cache based on the slave chip sequence. In some embodiments, among the multiple synchronization check codes stored in the master chip, since the verification module uses the synchronization check code with sequence 1 as the fourth synchronization check code, in the subsequent verification process, multiple consecutive check codes after the fourth synchronization check code are used as the second synchronization check code, so that different slave chips have synchronization check codes with corresponding synchronization check code sequences in different caches. The selection process of multiple second synchronization check codes corresponds to the sequence of multiple slave chips. For example, when entering the first synchronization task point, the slave chip with sequence 1 needs to use the target synchronization check code sequence with sequence 2 in the slave chip cache.

[0235] The fetching unit is used to read the synchronization check code to be processed from the target synchronization check code sequence; in some embodiments, since the second synchronization check code needs to represent the result of the first synchronization check code, it is necessary to process the synchronization check code in the target synchronization check code sequence according to different verification results.

[0236] The first writing unit is used to use the synchronization check code to be processed as the second synchronization check code when the first synchronization check code is checked and passed; in some embodiments, when the first synchronization check code is checked and passed, the synchronization check code to be processed is not processed, so that when the main chip uses the third synchronization check code for verification, it can pass the verification and enable the synchronization task to be carried out.

[0237] The second writing unit is configured to, when the first synchronization check code fails to be verified, invert the synchronization check code to be processed as a second synchronization check code. In some embodiments, when the first synchronization check code fails to be verified, the synchronization check code to be processed is inverted, so that when the master chip uses the third synchronization check code for verification, the verification fails, causing the synchronization task to fail.

[0238] As an optional implementation, the target unit includes:

[0239] The target subunit is used to determine the target synchronization check code sequence according to the following formula: D = (x-1) * i + 1 + z; wherein D is the target synchronization check code sequence, z is the sequence of the current slave chip among all slave chips, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips. In some embodiments, when there is 1 master chip and i-1 slave chips, since the first synchronization check code will use 1 synchronization check code, the second synchronization check codes sent by the i-1 slave chips are all different, and therefore, there will be i-1 second synchronization check codes, that is, each time the synchronization task point is entered, i synchronization check codes will be used. The next time it is entered, the i+1th synchronization check code can be used as the first synchronization check code. Each time a synchronization task point is entered, the first synchronization check code and the second synchronization check code are selected in ascending order.

[0240] In each of the above embodiments, multiple synchronization check codes arranged in sequence in the main chip cache can be used cyclically. For example, when there are n synchronization check codes in the main chip, when the synchronization check code sequence to be selected is n+1, the synchronization check code with sequence 1 can be selected.

[0241] In the above-mentioned embodiments, the cache of the master chip may be located in a secure area within the chip, so that only secure processes can access it, thereby enhancing the storage security of the synchronization check code.

[0242] Those skilled in the art will appreciate that all or part of the processes in the above method embodiments can be implemented by instructing related hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0243] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A multi-chip synchronization method, characterized in that: Applied to the main chip, including: Perform key negotiation with each slave chip to determine the shared key; Based on the shared secret key, multiple synchronization check codes are derived in sequence and stored in the main chip cache according to the derivation order; When entering a synchronization task point, a first synchronization check code corresponding to the current synchronization task point is obtained from the master chip cache and written into the synchronization register of the slave chip; so that the slave chip verifies the first synchronization check code and sends a second synchronization check code to the corresponding synchronization register in the master chip according to the verification result; The second synchronization check codes in the synchronization register of the master chip are sequentially obtained and verified according to the corresponding third synchronization check codes in the master chip cache, wherein the second synchronization check codes correspond one-to-one to the slave chips.

2. The method according to claim 1, characterized in that Based on the shared secret key, multiple synchronization check codes are derived in sequence and stored in the main chip cache according to the derivation order, including: Splitting the shared key to obtain a first sub-key and a second sub-key; Based on the first sub-key and the second sub-key, a synchronization check code is first derived; Starting from the second derivation of the synchronization check code, the synchronization check code formed by the previous derivation and the second sub-key are used to derive the synchronization check code.

3. The method according to claim 1, characterized in that When entering the synchronization task point, obtaining the first synchronization check code corresponding to the current synchronization task point from the master chip cache and writing it into the synchronization register of the slave chip includes: obtaining the first synchronization check code from the corresponding synchronization check code sequence in the master chip cache according to the order of the current synchronization task point.

4. The method according to claim 3, characterized in that Obtaining a first synchronization check code from a corresponding synchronization check code sequence in a master chip cache according to a current synchronization task point sequence includes: The synchronization check code sequence is determined according to the following formula: A = (x-1)*i+1; where A is the synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

5. The method according to claim 1, wherein Sequentially acquiring the second synchronization check code in the synchronization register in the master chip and performing verification based on the corresponding third synchronization check code in the cache of the master chip includes: Reading the second synchronization check code in the synchronization register in the main chip in sequence; Each time the synchronization register in the master chip is read, the target synchronization check code sequence in the master chip cache is determined based on the synchronization register sequence currently read; The third synchronization check code is read from the target synchronization check code sequence in the main chip buffer, and the second synchronization check code is checked according to the third synchronization check code.

6. The method according to claim 5, characterized in that Each time the synchronization register in the master chip is read, the target synchronization check code sequence in the master chip cache is determined based on the currently read synchronization register sequence, including: The target synchronization check code sequence is determined according to the following formula: B = (x-1)*i+1+y; where B is the target synchronization check code sequence, y is the sequence of the synchronization registers currently read, x is the sequence of the current synchronization task points, and i is the total number of master chips and slave chips.

7. A multi-chip synchronization method, characterized in that: Applicable to slave chips, including: Perform key negotiation with the main chip to determine the shared key; Based on the shared secret key, multiple synchronization check codes are derived in sequence and stored in the slave chip cache according to the derivation order; The first synchronization check code written by the master chip is read from the synchronization register of the slave chip, and is verified according to the corresponding fourth synchronization check code in the slave chip buffer; According to the verification result of the first synchronization check code, a second synchronization check code is written into the corresponding synchronization register in the master chip.

8. The method according to claim 7, characterized in that Based on the shared secret key, multiple synchronization check codes are derived in sequence and stored in the slave chip cache in the order of derivation, including: Splitting the shared key to obtain a first sub-key and a second sub-key; Based on the first sub-key and the second sub-key, a synchronization check code is first derived; Starting from the second derivation of the synchronization check code, the synchronization check code formed by the previous derivation and the second sub-key are used to derive the synchronization check code.

9. The method according to claim 7, characterized in that The checking according to the corresponding fourth synchronization check code in the chip cache includes: taking out the fourth synchronization check code from the corresponding synchronization check code sequence in the chip cache according to the sequence of the current synchronization task points.

10. The method according to claim 9, characterized in that According to the sequence of the current synchronization task points, extracting the fourth synchronization check code from the corresponding synchronization check code sequence in the chip cache includes: The corresponding synchronization check code sequence is determined according to the following formula: C = (x-1)*i+1, where C is the corresponding synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

11. The method according to claim 7, characterized in that Writing a second synchronization check code into a corresponding synchronization register in the master chip according to a check result of the first synchronization check code includes: Determine the target synchronization check code sequence in the slave chip cache according to the slave chip sequence; Read the synchronization check code to be processed from the target synchronization check code sequence; When the first synchronization check code passes the check, the synchronization check code to be processed is used as the second synchronization check code; When the first synchronization check code fails to be checked, the synchronization check code to be processed is inverted and used as the second synchronization check code.

12. The method according to claim 11, characterized in that Determining the target synchronization check code sequence in the slave chip cache based on the slave chip sequence includes: The target synchronization check code sequence is determined according to the following formula: D = (x-1)*i+1+z; where D is the target synchronization check code sequence, z is the sequence of the current slave chip among all slave chips, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

13. A multi-chip synchronization device, characterized in that: Applied to the main chip, including: A negotiation module, used to perform key negotiation with each slave chip to determine a shared key; A derivation module is used to derive multiple synchronization check codes in sequence based on the shared secret key and store them in the main chip cache according to the derivation order; The sending module is configured to, when entering a synchronization task point, obtain a first synchronization check code corresponding to the current synchronization task point from the master chip cache and write the code into the synchronization register of the slave chip; so that the slave chip verifies the first synchronization check code and sends a second synchronization check code to the corresponding synchronization register in the master chip based on the verification result; The verification module is used to sequentially obtain each second synchronization check code in the synchronization register of the master chip and perform verification according to the corresponding third synchronization check code in the master chip cache, wherein each second synchronization check code corresponds one-to-one to each slave chip.

14. The device according to claim 13, characterized in that The derived module includes: A splitting submodule, configured to split the shared key to obtain a first sub-key and a second sub-key; A first derivation submodule, configured to derive a synchronization check code for the first time based on the first sub-key and the second sub-key; The second derivation submodule is used to derive the synchronization check code from the second derivation, and to derive the synchronization check code based on the synchronization check code formed in the previous derivation and the second sub-key.

15. The device according to claim 13, characterized in that The sending module includes: a reading submodule, which is used to obtain the first synchronization check code from the corresponding synchronization check code sequence in the main chip cache according to the sequence of the current synchronization task points.

16. The device according to claim 15, characterized in that The reading submodule includes: The sequence unit is used to determine the synchronization check code sequence according to the following formula: A = (x-1)*i+1; where A is the synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

17. The device according to claim 13, characterized in that The verification module includes: A reading unit, configured to sequentially read the second synchronization check code in the synchronization register in the master chip; The sequence unit is used to determine the target synchronization check code sequence in the master chip cache according to the currently read synchronization register sequence each time the synchronization register in the master chip is read; The verification unit is configured to read a third synchronization check code from the target synchronization check code sequence in the main chip cache, and verify the second synchronization check code according to the third synchronization check code.

18. The device according to claim 17, characterized in that The sequential unit includes: The sequence subunit is used to determine the target synchronization check code sequence according to the following formula: B = (x-1)*i+1+y; where B is the target synchronization check code sequence, y is the sequence of the synchronization registers currently read, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

19. A multi-chip synchronization device, characterized in that: Applicable to slave chips, including: Negotiation module, used to negotiate the key with the main chip to determine the shared key; A derivation module is used to derive multiple synchronization check codes in sequence based on the shared secret key and store them in the slave chip cache according to the derivation order; a verification module, configured to read the first synchronization check code written by the master chip from the synchronization register of the slave chip, and perform verification based on the corresponding fourth synchronization check code in the slave chip cache; A writing module is used to write a second synchronization check code into a corresponding synchronization register in the main chip according to a check result of the first synchronization check code.

20. The device according to claim 19, characterized in that The derived module includes: A splitting submodule, configured to split the shared key to obtain a first sub-key and a second sub-key; A first derivation submodule, configured to derive a synchronization check code for the first time based on the first sub-key and the second sub-key; The second derivation submodule is used to derive the synchronization check code from the second derivation, and to derive the synchronization check code based on the synchronization check code formed in the previous derivation and the second sub-key.

21. The device according to claim 19, characterized in that The verification module includes: an extraction submodule, which is used to extract the fourth synchronization check code from the corresponding synchronization check code sequence in the chip cache according to the sequence of the current synchronization task points.

22. The device according to claim 21, characterized in that The submodules to be removed include: The extraction unit is used to determine the corresponding synchronization check code sequence according to the following formula: C = (x-1)*i+1, where C is the corresponding synchronization check code sequence, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

23. The device according to claim 19, characterized in that The writing module includes: The target unit is used to determine the target synchronization check code sequence in the slave chip cache according to the slave chip sequence; The fetching unit is used to read the synchronization check code to be processed from the target synchronization check code sequence; A first writing unit is configured to use the synchronization check code to be processed as a second synchronization check code when the first synchronization check code passes the check; The second writing unit is configured to, when the first synchronization check code fails to be checked, invert the synchronization check code to be processed as a second synchronization check code.

24. The device according to claim 23, characterized in that Target units include: The target subunit is used to determine the target synchronization check code sequence according to the following formula: D = (x-1)*i+1+z; where D is the target synchronization check code sequence, z is the sequence of the current slave chip among all slave chips, x is the current synchronization task point sequence, and i is the total number of master chips and slave chips.

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