Memory controller based on compact workload representation and method thereof

Abstract

The present disclosure relates to a memory controller based on compact workload representation and method thereof. A compact representation of an input workload is generated in a memory system. A memory controller includes firmware (FW) and an encoder comprising a plurality of recurrent encoding blocks. Each recurrent encoding block receives one of input commands in the input workload and generates a hidden state vector corresponding to the received input command by applying a set of activation functions to the received input command. An Nth encoding block generates a final hidden state vector as a compact representation vector corresponding to the input command. The firmware determines a distance function between the compact representation vector and each of a plurality of compact workload vectors, and adjusts at least one of firmware parameters based on the determined distance function.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a scheme for analyzing workloads in a memory system. BACKGROUND

[0002] The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having a memory device(s) (i.e., data storage device(s)). The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic device.

[0003] Since memory systems using memory devices have no moving parts, they provide excellent stability, durability, high information access speed, and low power consumption. Examples of memory systems having these advantages include universal serial bus (USB) memory devices, memory cards having various interfaces (e.g., universal flash storage (UFS)), and solid state drives (SSDs). The memory system can perform operations associated with one or more workloads from a host. Workload analysis is important for performance and reliability improvement of the memory system. In this case, embodiments of the present invention are generated. SUMMARY

[0004] Aspects of the present invention include a system having a memory controller capable of understanding a compact representation of an input workload and a method thereof.

[0005] In an aspect, a system includes a memory device; and a controller including an encoder and a firmware (FW) coupled to the encoder, the encoder including a plurality of recurrent encoding blocks including a first encoding block to an Nth encoding block. Each recurrent encoding block is configured to: receive one of a plurality of input commands in an input workload associated with the memory device; and generate a hidden state vector corresponding to the received input command by applying a set of activation functions to the received input command. The Nth encoding block generates a final hidden state vector as a compact representation vector corresponding to the plurality of input commands. The FW is configured to: determine a distance function between the compact representation vector and each of a plurality of compact workload vectors; and adjust at least one of FW parameters based on the determined distance function.

[0006] In another aspect, a method for operating a controller of a memory system includes providing an encoder and firmware (FW) coupled to the encoder, the encoder including a plurality of recurrent encoding blocks including a first encoding block to an Nth encoding block; receiving, by each recurrent encoding block, one of a plurality of input commands in an input workload associated with a memory device; generating, by each recurrent encoding block, a hidden state vector corresponding to the received input command by applying a set of activation functions to the received input command; determining, by the firmware, a distance function between a compact representation vector corresponding to the plurality of input commands and each of a plurality of compact workload vectors; and adjusting, by the firmware, at least one of the firmware parameters based on the determined distance function. The Nth encoding block generates a final hidden state vector as the compact representation vector.

[0007] Other aspects of the application will become apparent by consideration of the following description. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram illustrating a data processing system according to an embodiment of the application.

[0009] Figure 2 is a block diagram illustrating a memory system according to an embodiment of the application.

[0010] Figure 3 is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the application.

[0011] Figure 4 is a diagram illustrating a data processing system according to an embodiment of the application.

[0012] Figure 5 is a diagram illustrating a recurrent neural network compiler according to an embodiment of the application.

[0013] Figure 6A is a diagram illustrating a plurality of recurrent blocks according to an embodiment of the application.

[0014] Figure 6B is a diagram illustrating a recurrent block according to an embodiment of the application.

[0015] Figure 7 is a diagram illustrating Figure 5 details of the recurrent neural network compiler of

[0016] Figure 8 is a diagram illustrating a recurrent neural network compiler according to an embodiment of the application.

[0017] Figure 9 is a diagram illustrating Figure 8 details of the recurrent neural network compiler of

[0018] Figure 10 FIG. 14 is a diagram illustrating a data set of a workload compressed and visualized by a recurrent neural network compiler according to an embodiment of the present application.

[0019] Figure 11 FIG. 15 is a diagram illustrating a data processing system including a memory system according to an embodiment of the present application.

[0020] Figure 12 FIG. 16 is a diagram illustrating an encoder according to an embodiment of the present application.

[0021] Figure 13 FIG. 17 is a diagram illustrating a decoder according to an embodiment of the present application.

[0022] Figure 14 FIG. 18 is a diagram illustrating a compact vector generator according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] Various embodiments are described in more detail below. The present application may, however, be embodied in different forms, not just the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. Moreover, the use of "embodiment," "another embodiment," etc., does not necessarily refer to the same (multiple) embodiment, and the different uses of "embodiment" and "another embodiment" are intended to note that a specific set of features is used in some embodiments but not in others. In the drawings, the same reference numbers in different drawings can identify the same components.

[0024] The present application can be realized in various other manners, including being implemented as a process, an apparatus, a system, a computer program product implemented on a computer readable storage medium; and / or a processor, such as a processor adapted to execute instructions stored on and / or provided by a memory coupled to the processor. In this specification, any of these implementations or any other form that the present application can take can be referred to as technology. Generally, the order of the steps of disclosed processes can be altered within the scope of the present application. Unless otherwise specified, components, such as a processor or a memory, described as being adapted to perform a task can be implemented as a general component temporarily configured to perform the task or a specific component manufactured to perform the task. As used herein, the term "processor" or the like refers to one or more devices, circuits, and / or processing cores adapted to process data (e.g., computer program instructions).

[0025] A detailed description of embodiments of the application is provided below along with accompanying figures that illustrate the aspects of the application. The application is described in connection with these embodiments, but the application is not limited to any embodiment. The scope of the application is limited only by the claims. Numerous alternatives, modifications and equivalents of the application are encompassed by the scope of the claims. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the application. These details are provided for the purpose of example; the application can be practiced without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the application has not been described in detail so that the application is not unnecessarily obscured.

[0026] Figure 1 is a block diagram illustrating a data processing system 2 according to an embodiment of the present application.

[0027] Referring to Figure 1 The data processing system 2 can include a host device 5 and a memory system 10. The memory system 10 can receive a request from the host device 5 and operate in response to the received request. For example, the memory system 10 can store data to be accessed by the host device 5.

[0028] The host device 5 can be implemented with any one of various types of electronic devices. In various embodiments, the host device 5 can include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder, and a digital video player. In various embodiments, the host device 5 can include a portable electronic device such as a mobile phone, a smart phone, an electronic book, an MP3 player, a portable multimedia player (PMP), and / or a portable game console.

[0029] The memory system 10 can be implemented with any one of various types of storage devices such as a solid state drive (SSD) and a memory card. In various embodiments, the memory system 10 can be provided as one of various components in an electronic device such as a computer, an ultra mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, and various electronic devices of a home network, one of various electronic devices of a computer network, one of various electronic devices of a telematics network, or one of various components of a computing system.

[0030] The memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control overall operations of the semiconductor memory device 200.

[0031] The semiconductor memory device 200 can perform one or more erase operations, program operations, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive a command CMD, an address ADDR, and data DATA through input / output lines. The semiconductor memory device 200 can receive power PWR through a power line and a control signal CTRL through a control line. The control signal CTRL can include a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals, according to the design and configuration of the memory system 10.

[0032] The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a solid state drive (SSD). The SSD can include a storage device for storing data. When the memory system 10 is used for the SSD, the operating speed of a host device (e.g., the host device 5 of FIG. 1) coupled to the memory system 10 can be significantly improved. Figure 1

[0033] ​The memory controller 100 and the semiconductor memory device 200 can be integrated into a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated as to configure a Personal Computer (PC) card of Personal Computer Memory Card International Association (PCMCIA), a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a MultiMediaCard (MMC), a Reduced Size MultiMediaCard (RS-MMC), a micro version of MMC (micro- MMC), a Secure Digital (SD) card, a mini Secure Digital (miniSD) card, a micro Secure Digital (microSD) card, a Secure Digital High Capacity (SDHC), and / or a Universal Flash Storage (UFS).

[0034] Figure 2 is a block diagram illustrating a memory system according to an embodiment of the present application. For example, Figure 2 The memory system of Figure 1 the memory system 10 illustrated.

[0035] Referring to Figure 2 , the memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can operate in response to a request from a host device (for example, the host device 5 of Figure 1 ), and particularly store data to be accessed by the host device.

[0036] The memory device 200 can store data to be accessed by the host device.

[0037] The memory device 200 can be implemented with a volatile memory device such as Dynamic Random Access Memory (DRAM) and / or Static Random Access Memory (SRAM), or a non-volatile memory device such as Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Ferroelectric Random Access Memory (FRAM), Phase-Change RAM (PRAM), Magnetoresistive RAM (MRAM), and / or Resistive RAM (RRAM).

[0038] The controller 100 can control storage of data in the memory device 200. For example, the controller 100 can control the memory device 200 in response to a request from the host device. The controller 100 can provide data read from the memory device 200 to the host device, and can store data provided from the host device into the memory device 200.

[0039] The controller 100 can include a storage 110, a control component 120 (which can be implemented as a processor such as a central processing unit (CPU)), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150, which are coupled through a bus 160.

[0040] The storage 110 can serve as a working memory of the memory system 10 and the controller 100, and store data for driving the memory system 10 and the controller 100. When the controller 100 controls the operation of the memory device 200, the storage 110 can store data of the controller 100 and the memory device 200 for operations such as a read operation, a write operation, a program operation, and an erase operation.

[0041] The storage 110 can be implemented with a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage 110 can store data of a host device for a read operation and a write operation in the memory device 200. To store the data, the storage 110 can include a program memory, a data memory, a write buffer, a read buffer, a mapping buffer, etc.

[0042] The control component 120 can control general operations of the memory system 10, and particularly control corresponding operations of the memory device 200 in response to a write request or a read request from a host device. The control component 120 can drive firmware called a flash translation layer (FTL) to control general operations of the memory system 10. For example, the FTL can perform operations such as logical-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. The L2P mapping is referred to as logical block addressing (LBA).

[0043] The ECC component 130 can detect and correct errors in data read from the memory device 200 during a read operation. When the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 can not correct the error bits, but can output an error correction failure signal indicating a failure in correcting the error bits.

[0044] In various embodiments, ECC component 130 may perform error correction operations based on coding modulations such as low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, turbo product codes (TPC), Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), or block-coded modulation (BCM). However, error correction is not limited to these techniques. Therefore, ECC component 130 may include any and all circuitry, systems, or means for appropriate error correction operations.

[0045] The host interface 140 can communicate with the host device through one or more of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and / or Electronic Integrated Drive (IDE).

[0046] Memory interface 150 provides an interface between controller 100 and memory device 200, allowing controller 100 to control memory device 200 in response to requests from host device. Memory interface 150 can generate control signals for memory device 200 and process data under the control of control component 120. When memory device 200 is flash memory such as NAND flash memory, memory interface 150 can generate memory control signals and process data under the control of control component 120.

[0047] Memory device 200 may include memory cell array 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer array 250 (which may be in the form of a page buffer array), column decoder 260, and input / output (I / O) circuitry 270. Memory cell array 210 may include multiple memory blocks 211 capable of storing data. Voltage generation circuitry 230, row decoder 240, page buffer array 250, column decoder 260, and I / O circuitry 270 may form peripheral circuitry for memory cell array 210. Peripheral circuitry may perform programming, reading, or erasing operations on memory cell array 210. Control circuitry 220 may control peripheral circuitry.

[0048] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as erase voltage and pass voltage.

[0049] The row decoder 240 can be in electrical communication with the voltage generation circuit 230 and the plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a row address generated by the control circuit 220, and transmit an operating voltage supplied from the voltage generation circuit 230 to the selected memory block.

[0050] The page buffer array 250 can be coupled with the memory cell array 210 through bit lines BL (not shown). The page buffer array 250 can pre-charge the bit lines BL with a positive voltage, transmit data to and receive data from the selected memory block in a program operation and a read operation, or temporarily store the transmitted data in response to a page buffer control signal(s) generated by the control circuit 220. Figure 3 The column decoder 260 can transmit and receive data to and from the page buffer array 250, or transmit and receive data to and from the input / output circuit 270.

[0051] The input / output circuit 270 can transmit a command and an address received from an external device (e.g., a memory controller 100) to the control circuit 220, transmit data from the external device to the column decoder 260, or output data from the column decoder 260 to the external device through the input / output circuit 270.

[0052] Figure 1 The control circuit 220 can control the peripheral circuit in response to the command and the address.

[0053] The control circuit 220 can control the peripheral circuit in response to the command and the address.

[0054] Figure 3 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present application. For example, Figure 3 The memory block can be any one of the memory blocks 211 of the memory cell array 210 illustrated in Figure 2

[0055] Referring to Figure 3 , the memory block 211 can include a plurality of word lines WL0 to WLn-1 coupled to the row decoder 240, a drain select line DSL, and a source select line SSL. These lines can be arranged in parallel, with the plurality of word lines located between the DSL and the SSL.

[0056] ​​The memory block 211 can further include a plurality of cell strings 221 coupled to the bit lines BL0 to BLm-1, respectively. The cell strings of each column can include one or more drain select transistors DST and one or more source select transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, a plurality of memory cells or memory cell transistors MC0 to MCn-1 can be coupled in series between the select transistors DST and SST. Each of the memory cells can be formed as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, or a quad-level cell (QLC) storing four bits of data.

[0057] The sources of the SSTs in each cell string can be coupled to a common source line CSL, and the drains of each DST can be coupled to a respective bit line. The gates of the SSTs in a cell string can be coupled to the SSL, and the gates of the DSTs in a cell string can be coupled to the DSL. The gates of the memory cells across a cell string can be coupled to respective word lines. That is, the gate of the memory cell MC0 is coupled to a respective word line WL0, the gate of the memory cell MC1 is coupled to a respective word line WL1, and so on. A group of memory cells coupled to a particular word line can be referred to as a physical page. Thus, the number of physical pages in the memory block 211 can correspond to the number of word lines.

[0058] The page buffer array 250 can include a plurality of page buffers 251 coupled to the bit lines BL0 to BLm-1. The page buffers 251 can operate in response to page buffer control signals. For example, the page buffers 251 can temporarily store data received through the bit lines BL0 to BLm-1 or sense voltages or currents of the bit lines during a read operation or a verify operation.

[0059] In some embodiments, the memory block 211 can include NAND-type flash memory cells. However, the memory block 211 is not limited to this type of cell, but can include NOR-type flash memory cells. The memory cell array 210 can be implemented as a hybrid flash memory of two or more types of memory cells combined, or as a single NAND flash memory with a controller embedded inside the memory chip.

[0060] Figure 4 is a diagram illustrating a data processing system 2 according to an embodiment of the present application.

[0061] Referring to Figure 4The data processing system 2 can include a host 5 and a memory system 10. The memory system 10 can include a controller 100 and a memory device 200. The controller 100 can include a flash translation layer (FTL), which is an intermediary system composed of software and hardware that manages the operations of the memory system 10. The functions of the FTL can be integrated into firmware (FW) or a file system. Firmware is a type of software that is specific to controlling various operations of the memory device 200 (e.g., read operations, write operations, and erase operations). In some embodiments, the firmware can reside in the storage device 110 and can be run by the control component 120 in the memory system 10. Figure 2

[0062] The memory device 200 can include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns as shown in FIG. 1. The cells in a particular row are connected to a word line (e.g., WL0), and the cells in a particular column are coupled to a bit line (e.g., BL0). These word lines and bit lines are used for read operations and write operations. During a write operation, data to be written (“1” or “0”) is provided on the bit line while the word line is asserted. During a read operation, the word line is again asserted, and then the threshold voltage of each cell can be obtained from the bit line. Multiple pages can share memory cells that belong to (i.e., are coupled to) the same word line. Figure 3

[0063] In the memory system 10, the controller 100 can perform operations associated with one or more workloads from the host 5. A workload can be defined as a data stream (or commands) generated by an application program of the host 5 that is treated by the memory system 10 as a set of access patterns. The memory system 10 can be implemented with a solid-state drive (SSD). According to the following report, SSDs will account for about 85% of enterprise storage capacity by 2026: David McIntyre “Annual Flash Controller Update,” Flash Memory Summit 2019, FMS’19. Flash-based storage devices are also more advantageous in terms of cost per bit compared to hard disk drives (HDDs). However, flash memory devices in SSDs are more sensitive to changes in input workloads due to a limited number of erase / write (EW) cycles and complex logical-to-physical (L2P) mapping. Therefore, workload analysis becomes important for performance and reliability improvement of flash memory devices (e.g., NAND flash memory).

[0064] ​​The workload of an SSD is not limited to spatial characteristics (i.e., random or sequential access patterns) and can therefore be described using a number of characteristics determined based on developer experience. For example, the workload analysis process can rely on a number of characteristics such as the number of commands and their duration, characteristics of access segments, input and output requests, intervals between requests, etc. However, even the most exhaustive set of characteristics can not account for important workload characteristics. Moreover, certain characteristics can be irrelevant to the flash translation layer (FTL) algorithm and should therefore be excluded.

[0065] Since real workloads are typically unknown, the first step of workload analysis can be clustering, i.e., dividing the workload into different types (i.e., clusters). The next step of workload analysis can be to make the flash translation layer (FTL) aware of the workload. Typically, the FTL algorithm and strategy (e.g., wear leveling, garbage collection, error protection, etc.) for random write-only workloads and sequential read-only workloads should be different. To this end, the type of workload should be detected and identified based on the sequence of input commands. One embodiment of a workload detector is described in U.S. Patent No. 10,802,761 B2, entitled “WORKLOAD PREDICTION IN MEMORY SYSTEM AND METHOD THEREOF”. Therefore, there is a need to provide a scheme to make the FTL aware of the input workload and optimize its performance based on the awareness of the input workload. Accordingly, embodiments provide a scheme for a compact representation of an input workload in a memory system (e.g., an SSD (e.g., a NAND flash memory device)) and a memory controller capable of making the input workload aware based on the compact representation of the input workload. Accordingly, embodiments can optimize the performance and / or reliability of the memory system.

[0066] According to embodiments, Figure 4The controller 100 can provide a compiler (i.e., an encoder and a decoder) and its encoding and decoding method for compact representation of input workloads. Since workloads can be represented as time series and further treated as sequential data, recurrent neural networks are considered effective in processing such data. Also, the internal representation of workloads should be compact in order to be stored in storage devices (e.g., volatile memory). Thus, embodiments provide compact workload representation based on recurrent neural network models, and a recurrent neural network (RNN) autoencoder has been used as a model to represent input workloads, i.e., a compiler including an encoder and a decoder. The quality of the model depends on the diversity and size of the training set. The following introduces recurrent neural network models and recurrent neural network (RNN) autoencoders: T. Mikolov et al., “Linguistic Regularities in Continuous Space Word Representation,” Proceedings of the 2013 Conference of the North American Chapter of Association for Computational Linguistics, pp. 746-751; and N. Srivastava et al., “Unsupervised Learning of Video Representations Using LSTMs,” Proceedings of the 32nd International Conference on Machine Learning, PMLR 37:843-852, 2015, each of which is incorporated herein by reference in its entirety. Compact representation of input workloads facilitates FTL reconfiguration and more accurate FW parameter adjustment. If the dataset used for training is widely diverse, embodiments will be able to detect a variety of types of different workloads.

[0067] Figure 5 FIG. 5 is a diagram illustrating a recurrent neural network compiler 500 according to embodiments of the present application. In some cases, the recurrent neural network compiler 500 can provide compact workload representation and is referred to as a recurrent neural network (RNN) autoencoder.

[0068] Referring to Figure 5The recurrent neural network compiler 500 may include an encoder 510, a storage device 520, and a decoder 530. The encoder 510 may receive data including data from the memory device (e.g., ...). Figure 4 The memory device 200) is associated with multiple input commands and an input workload. For example, the input workload is from... Figure 4 The host 5 receives the data. In some embodiments, the workload may be represented as including N commands C1 to C2. N Time series. Each command C i (where 1≤i≤N) can have at least two characteristics, namely command type (T) i Logical Block Address (LBA) i The features are not limited to the two features mentioned above. i It is an integer corresponding to the possible commands. For example, for the read command, T i The value can be 0, 1 for write commands, and 2 for erase commands. LBA i It is also an integer derived from a series of possible addresses. For example, LBA i It can be in the range of 0 to 2 32 An integer of -1.

[0069] Encoder 510 can generate compact representation vectors corresponding to multiple input commands using a set of activation functions. Storage device 520 can be coupled to encoder 510 and can store the compact representation vectors. Decoder 530 can be coupled to storage device 520 and can receive the compact representation vectors from storage device 520. Decoder 530 can generate recovery commands based on the compact representation vectors and multiple input commands. See below for reference. Figure 6A to Figure 7 Details of encoder 510, storage device 520 and decoder 530 are described.

[0070] like Figure 6A As shown, each of the encoder 510 and the decoder 530 can be implemented using a plurality of cyclic blocks 601-60N, including a first cyclic block RB1 to an Nth cyclic block RBN. The first cyclic blocks RB1 to the Nth cyclic blocks RBN are cascaded.

[0071] Figure 6B It shows Figure 6A A diagram illustrating the general structure of a loop block in a loop.

[0072] Reference Figure 6B , with index i(RB) i The cyclic block RB has two inputs and two outputs. The two inputs include the input corresponding to the previous unit RB. i-1 The hidden state vector h i-1 and the input command vector X corresponding to the elements of the input sequence.i The two outputs include those corresponding to RB. i The hidden state vector h i and corresponding to RB i The output vector Y of the output value i In some embodiments, vector X i The command corresponding to the input workload, vector Y i This corresponds to the recovery or prediction command of the input workload. Each RB shares three weight matrices W. Y W h and W X The output of RB is calculated as shown in Listing 1:

[0073] List 1:

[0074]

[0075]

[0076] Referring to List 1, for the first input command X i and the first weight matrix W X Combination X i W X Execute activation function f(X) i W X This generates a first vector. In some embodiments, the activation function includes a hyperbolic tangent function. sigmoid function and the modified linear unit (ReLU) function f(x) = x + = one of max(0, x).

[0077] For the previous hidden state vector h i-1 Second weight matrix W h Combined execution activation function f(h) i-1 W h This generates a second vector. In some embodiments, the activation function here may be different from the previous activation function.

[0078] The sum of the first and second vectors, f(X), can be expressed as... i W X )+f(h i-1 W h ) Execute activation function f(f(X) i W X )+f(h i- 1W h To generate the hidden state vector h i .

[0079] on the hidden state vector h i and a third weight matrix W Y The activation function f(h i W Y ) can generate an output vector Y i = f(h i W Y ).

[0080] In some embodiments, the described RBs can be implemented in different ways, including gated recurrent units (GRUs) and / or long short-term memory (LSTM), as described below: J. Chung et al., “Empirical Evaluation of Gated Recurrent Neural Networks on Sequence Modeling,” NIPS 2014 Workshop on Deep Learning, December 2014.

[0081] Figure 7 is a diagram showing details of a recurrent neural network compiler. Figure 5

[0082] Referring to Figure 7 , the recurrent neural network compiler can include an encoder 510, a storage 520, and a decoder 530, and can be implemented with 2N recurrent blocks (RBs) in order to generate a compact representation vector R from an input workload.

[0083] The encoder 510 can learn an internal representation vector R of a workload including N commands C1-C N In some embodiments, certain workloads can be shorter or longer than the N commands, so the workload should be padded (i.e., extra dummy commands are added to the workload) or clipped (i.e., the last command is removed from the workload). The N recurrent blocks (RBs) with weight matrices W e X , W e h , W e Y convert the workload into the compact representation vector R. Each RB can receive two inputs (i.e., a previous hidden state vector h e i-1 from a previous recurrent block and a command C i ), and can output two values (i.e., a command and a weighted hidden state vector h e i ). The matrix W​e Y may not be trainable because the encoder 510 accumulates information from the input workload and does not predict or recover any commands. Thus, the output command is always equal to the zero vector.

[0084] In Figure 7 the illustrated example, the encoder 510 can include a plurality of recurrent blocks RB e 1-RB e N Each recurrent block is configured to receive one C i of the plurality of input commands and generate a hidden state vector h e corresponding to the received input command by applying a set of activation functions f to the received input command. i The Nth recurrent block RB e N may generate a final hidden state vector h e N as the compact representation vector R.

[0085] The first recurrent block RB e 1 is configured to: receive a first input command C1 of the plurality of input commands; perform an activation function f on a combination of the first input command C1 and a first weight matrix W e X to generate a first vector f(C1W e X ); perform an activation function on a combination of an initial hidden state vector h e 0 and a second weight matrix W e h to generate a second vector f(h e 0W e h ); perform an activation function on a sum of the first vector and the second vector to generate a first hidden state vector h e 1; and perform an activation function on a combination of the first hidden state vector h e 1 and a third weight matrix W e Y to generate a first output vector In some embodiments, a value of the initial hidden state vector h e 0 can be 0, and a value of the first output vector may be 0.

[0086] The second recurrent block RB e 2 is configured to: receive a second input command C2 of the plurality of input commands; perform an activation function f on a combination of the second input command C2 and the first weight matrix W e Xthe combination of the first and second weight matrices W e X the combination of the first and second weight matrices W e 1and the second weight matrix W e h to generate a fourth vector f(h e 1W e h the combination of the third and fourth vectors to generate a second hidden state vector h e 2; and the combination of the second hidden state vector h e 2and the third weight matrix W e Y to generate a second output vector In some embodiments, the value of the second output vector may be 0.

[0087] The remaining encoding blocks among the plurality of recurrent encoding blocks can perform similar operations as the first encoding block RB e 1and the second encoding block RB e 2. The Nth encoding block RB e N may generate a final hidden state vector h e N as the compact representation vector R. The compact representation vector R can be stored in the storage device 520. In some embodiments, the storage device 520 can be a volatile memory, such as a random access memory (RAM).

[0088] The decoder 530 can receive the compact representation vector R from the storage device 520 and generate recovered commands N based on the compact representation vector R and the plurality of input commands C1-C The decoder 530 can recover workload commands which can not be exactly the same as the original workload. The structure of the decoder 530 can be symmetrical to the encoder 510 but with a reversed order of concatenation structure in terms of input commands. The decoder 530 can process the compact representation vector R with N RB units having weight matrices W d X , W d h , W d Y but in a descending order from the last command to the first command. That is, the Nth decoding block RB d 1-RB d N among the plurality of decoding blocks RB dN It can be located at the first position of decoder 530, the first decoding block RB d 1 can be located at the end of the decoder 530. In some embodiments, the first input command C N It can be the same as the zero vector because the command should be recovered from the compact representation vector R. In some embodiments, the weight matrix W d X W d h W d Y With weight matrix W respectively e X W e h W e Y Same or different.

[0089] exist Figure 7 In the example shown, the Nth decoded block RB d N Configured to receive multiple input commands C1-C N The last input command is C. N And compact representation vector R; for the last input command C N and the first weight matrix W d X The combined execution of the activation function f produces the first vector f(C). N W d X ); for the hidden state vector h as input e N The compact representation vector R and the second weight matrix W d h Combining activation functions to generate a second vector f(h) e N W d h ); Apply an activation function to the sum of the first and second vectors to generate the Nth hidden state vector h. d N And for the Nth hidden state vector h d N and the third weight matrix W d Y Combining activation functions to generate the Nth output vector

[0090] Second decoding block RB d 2 is configured to receive multiple input commands C1-C N The second input command C2; and the second input command C2 and the first weight matrix W dX the combination of the third vector and the fourth vector to generate a second hidden state vector h d X ) ; performing an activation function on a combination of the second hidden state vector h d 3 received from the third decoding block RB d 3 and the second weight matrix W d h to generate a fourth vector f(h d 3W d h ) ; performing an activation function on a sum of the third vector and the fourth vector to generate a second hidden state vector h d 2; and performing an activation function on a combination of the second hidden state vector and the third weight matrix to generate a second output vector

[0091] The first decoding block RB d 1 is configured to: receive a first input command C1 among the plurality of input commands C1-C N ; perform an activation function f on a combination of the first input command C1 and a first weight matrix W d X to generate a fifth vector f(C1W d X ) ; perform an activation function on a combination of a second hidden state vector h d 2 received from the second decoding block RB d 2 and the second weight matrix W d h to generate a sixth vector f(h d 2W d h ) ; perform an activation function on a sum of the fifth vector and the sixth vector to generate a first hidden state vector h d 1; and perform an activation function on a combination of the first hidden state vector and the third weight matrix to generate a first output vector

[0092] Figure 7 The model of the RNN compiler in FIG. 8 can be trained using a dataset containing M workloads, which can have different features. The training process can adjust the weight matrices W e X , W e h , W e Y , W d X , W d h , W d Ysuch that the difference between the source workload (C1, C2,..., C N ) and the recovered workload is minimized. Different optimization algorithms such as gradient descent, RMSProp, Adam, etc. can be used during the training process. The model can have two hyperparameters N and d. N represents the number of RBs in the encoder and the decoder, and d represents the dimension of the compact representation vector R.

[0093] Figure 8 is a diagram illustrating a recurrent neural network compiler 500 according to an embodiment of the present application.

[0094] Referring to Figure 8 , in addition to the encoder 510, the storage 520, and the decoder 530 in Figure 5 , the recurrent neural network compiler 500 can further include a predictor 540. The predictor 540 can predict the next K commands after the input workload and generate predicted commands.

[0095] Figure 9 is a diagram illustrating details of the recurrent neural network compiler 500 of Figure 8 . The encoder 510 and the decoder 530 in the recurrent neural network compiler 500 can have the same structure as illustrated in Figure 7 .

[0096] Referring to Figure 9 , the predictor 540 can include a plurality of recurrent prediction blocks RB p 1-RB p K . The predictor 540 can receive the compact representation vector R and generate predicted commands based on the compact representation vector R and the last input command C N among the plurality of input commands.

[0097] The plurality of recurrent prediction blocks can include a first prediction block to a Kth prediction block RB p 1-RB p K which have a cascaded structure in ascending order (i.e., from the first prediction block to the Kth prediction block).

[0098] The first prediction block RB p 1 is configured to receive the last input command C N among the plurality of input commands and the compact representation vector R from the storage 520; perform an activation function f on a combination of the last input command and a first weight matrix W p X to generate a first vector perform an activation function f on the compact representation vector R (= h eN ) and a second weight matrix W p h e N W p h ) ; performing an activation function on a sum of the first vector and the second vector to generate a first hidden state vector h p 1; and performing an activation function on a combination of the first hidden state vector h p 1 and a third weight matrix W p Y to generate a first output vector as a first predicted command after the last input command.

[0099] A second prediction block RB p 2 is configured to: receive the first predicted command and the first hidden state vector h p 1; perform an activation function f on a combination of the first predicted command and a first weight matrix W p X to generate a third vector perform an activation function on a combination of the first hidden state vector h p 1 and a second weight matrix W p h to generate a fourth vector f(h p 1W p h ) ; perform an activation function on a sum of the third vector and the fourth vector to generate a second hidden state vector h p 2; and perform an activation function on a combination of the second hidden state vector h p 2 and a third weight matrix W p Y to generate a second output vector as a second predicted command after the first predicted command .

[0100] The remaining prediction blocks among the plurality of recurrent prediction blocks can perform similar operations as the first prediction block RB p 1 and the second prediction block RB p 2. A Kth prediction block RB p K among the plurality of recurrent prediction blocks can generate a final hidden state vector h p K .

[0101] Thus, the predictor 540 requires an additional K RBs and weight matrices W p X , W​p h W p Y In some embodiments, the weight matrix W p X W p h W p Y With weight matrix W respectively e X W e h W e Y Same or different. The output of the predictor 540 is the input workload C1-C. N The K commands following the command Each prediction command is input to the next RB. Therefore, the following K commands are predicted and generated to continue the input workload.

[0102] The following describes an example implementation of a recurrent neural network (RNN) compiler according to an embodiment.

[0103] Note that the recurrent neural network (RNN) compiler for compact workload representation has been implemented using long short-term memory (LSTM) loop blocks and tested on each dataset containing M=900 synthetic workloads and N=10000 commands.

[0104] The dataset contains nine workload types (100 samples each), generated based on two parameters: queue depth (QD) and read / write ratio (RWR), where RWR represents the ratio of read to write commands in the workload. All workloads are randomized, and the nine workload types are shown in Listing 2.

[0105] List 2:

[0106]

[0107] The workloads in the dataset have been represented as d = 25-dimensional vectors. These vectors have been processed by a dimensionality reduction algorithm (e.g., the t-SNE algorithm) in order to visualize them in a three-dimensional (3-D) space. One implementation of the t-SNE algorithm is described below: Laurens van der Maaten and Geoffrey Hinton, "Visualizing Data using t-SNE," Journal of Machine Learning Research 9, pp. 2579-2605, 2008. For clarity, only 90 points (10 per workload type) are plotted, as the density of each workload type is high, and the additional 810 points would impede the graphical separation between points. The dataset of workloads compressed and visualized by the recurrent neural network compiler is shown in Figure 10

[0108] List 3 shows an example of how the workloads are converted into 25-dimensional vectors (i.e., compact representation vectors):

[0109] List 3:

[0110]

[0111] The Average Euclidean Distance between the centers of each workload type is shown in Table 1:

[0112] Table 1:

[0113]

[0114]

[0115] As shown in Figure 10 and Table 1, the workloads are mostly separated by a certain read / write ratio (RWR). For example, (W1, W4, W7) are separated by RWR = 0 / 100, (W2, W5, W8) are separated by RWR = 100 / 0, and (W3, W6, W9) are separated by RWR = 70 / 30. The last group (W3, W6, W9) is more diverse, with a greater influence of the queue depth feature. Thus, it can be seen that the compact workload representation scheme according to embodiments can separate workloads by important features and estimate the differences between input workloads in a NAND flash device.

[0116] ​As described above, embodiments can provide a compiler (i.e., encoder and decoder) and its encoding and decoding methods that provide a compact representation of an input workload. This implementation is described in U.S. Patent Application Serial No. 17 / 173,378, entitled “COMPACT WORKLOAD REPRESENTATION OF MEMORY SYSTEM,” the entirety of which is incorporated by reference herein.

[0117] Further, embodiments provide a scheme of a memory controller that can understand an input workload based on a compact representation of the input workload in a memory system (e.g., an SSD (e.g., a NAND flash memory device)). The following utilizes Figure 11 to Figure 14 This scheme is described.

[0118] Figure 11 is a diagram illustrating a data processing system including a memory system 10 according to embodiments of the present invention. By way of example and without any limitation, the memory system 10 can include a controller 100 as a workload-aware NAND flash controller with a self-test block.

[0119] Referring to Figure 11 , the data processing system can include a host 5 and a memory system 10. The memory system 10 can include a controller 100 and a memory device 200. In some embodiments, the memory system 10 can be a solid state drive (SSD) that includes a NAND flash memory device as the memory device 200.

[0120] The controller 100 can include a flash translation layer 1110, an encoder 1120, and a decoder 1130. The encoder 1120 and the decoder 1130 can be used to implement a workload-aware NAND flash controller with a self-test block as Figure 5 an element of the recurrent neural network compiler 500 in

[0121] Based on these components, the controller 100 can be able to change firmware (FW) parameters based on a workload type. Since the workload representation is compact, embodiments can help estimate the test coverage of the memory system. The dimensionality of the workload vector representation is much smaller than the original workload. Thus, the number of points in the low-dimensional space can be used as a coverage metric.

[0122] The recurrent neural network compiler 500 can operate in a training mode or an inference mode. In an initial phase (i.e., training mode), the recurrent neural network compiler 500 can be trained using a dataset that covers possible workload types of typical drive operation scenarios. The weight matrix of the model associated with the recurrent neural network compiler 500 and the compact representation of the typical workloads can then be stored in a storage device (e.g., DRAM) or a memory device (e.g., NAND). The training mode can be performed offline using an external computing engine. In the inference mode, the recurrent neural network compiler 500 can use the weight matrix to process an input workload. The basic FW parameters (e.g., garbage collection algorithm, read voltage threshold, error correction scheme, etc.) can be changed based on the compact workload representation and the FW state (e.g., values of counters, over-provisioned memory used, number of bad blocks, etc.). The self-test algorithm can be based on the generation of the compact workload vectors and convert them into commands inside the controller. Thus, the low-dimensional space of the compact workload representation can be covered with better diversity.

[0123] In some embodiments, the flash translation layer 1110 can include a firmware (FW) adjuster 1115 coupled to the encoder 1120. The controller 100 can include a compact vector generator 1150A, a first selector 1160A, a second selector 1160B, and a flash interface layer (FIL) 1140, which are directly or indirectly coupled to the decoder 1130. Further, a compact vector generator 1150B can be included in the host 5, which corresponds to the compact vector generator 1150A. Each of the first selector 1160A and the second selector 1160B can be implemented with a multiplexer (MUX). The encoder 1120 and the decoder 1130 can be implemented with recurrent blocks as shown in Figure 12 and Figure 13 .

[0124] Figure 12 is a diagram illustrating the encoder 1120 according to an embodiment of the application. By way of example and without any limitation, the encoder 1120 can be used to implement a workload-aware NAND flash controller with a self-test block as shown in Figure 11 .

[0125] Referring to Figure 12 , the encoder 1120 can include a plurality of recurrent encoding blocks RB e 1-RB e N . Each recurrent encoding block is configured to receive one of a plurality of input commands C i and generate a hidden state vector h e corresponding to the received input command by applying a set of activation functions f to the received input command.i The Nth recurrent encoding block RB e N The final hidden state vector h e N as a compact representation vector R corresponding to the plurality of input commands.

[0126] In the example shown in FIG. 1, a first encoding block RB Figure 12 e 1 is configured to: receive a first input command C1 among the plurality of input commands; perform an activation function f on a combination of the first input command C1 and a first weight matrix W e X to generate a first vector f(C1W e X ); perform an activation function on a combination of an initial hidden state vector h e 0 and a second weight matrix W e h to generate a second vector f(h e 0W e h ); and perform an activation function on a sum of the first vector and the second vector to generate a first hidden state vector h e 1. In some embodiments, the value of the initial hidden state vector h e 0 can be 0.

[0127] A second encoding block RB e 2 is configured to: receive a second input command C2 among the plurality of input commands; perform an activation function f on a combination of the second input command C2 and the first weight matrix W e X to generate a third vector f(C2W e X ); perform an activation function on a combination of the first hidden state vector h e 1 and the second weight matrix W e h to generate a fourth vector f(h e 1W e h ); and perform an activation function on a sum of the third vector and the fourth vector to generate a second hidden state vector h e 2.

[0128] The remaining encoding blocks among the plurality of recurrent encoding blocks can perform similar operations as the first encoding block RB e 1 and the second encoding block RB e 2. The Nth recurrent encoding block RB e N may generate a final hidden state vector h e ​N As a compact representation vector R.

[0129] As described above, encoder 1120 may include N cyclic blocks (RBs). e i (1≤i≤N), which has two inputs (i.e., command C). i With the hidden state h from the previous block e i-1 ) and an output (i.e., the hidden state h of the current block). e i In some embodiments, each command C i It can be two integers (i.e., command type (T)). i ) and Logical Block Address (LBA) i The tuple of )) has a hidden state h. e i It can be a floating-point vector containing H numbers. RB e N The hidden state (i.e., h) e N The data can be stored in a memory device (e.g., a register) capable of storing d floating-point numbers. The loop block can be implemented as a simple recurrent neural unit, a gated recurrent unit (GRU), a long short-term memory (LSTM), etc. The encoder 1120 can be implemented in both software (SW) (or firmware (FW)) and hardware (as part of the controller). Workload commands C1, C2, ..., C N It can be stored in a storage device (e.g., a shift register) so that the compact workload representation R can be changed once a new command is received from the host.

[0130] Figure 13 This is a diagram illustrating a decoder 1130 according to an embodiment of the present invention. As an example and without any limitation, the decoder 1130 can be used to implement, for example... Figure 11 The example shown is a workload-aware NAND flash controller with a self-test block.

[0131] Reference Figure 13 The decoder 1130 can receive the compact representation vector R from the storage device 1120 and generate a recovery command based on the compact representation vector R.

[0132] The structure of decoder 1130 can be symmetrical to that of encoder 1120, but the cascaded structure order is reversed. That is, multiple cyclic decoding blocks include the first to Nth decoding blocks, which are symmetrical to the first to Nth encoding blocks and have a descending cascaded structure. Specifically, multiple decoding blocks RB... d 1-RB dN The Nth decoding block RB d N It can be located at the first position of decoder 1130, the first decoding block RB d 1 can be located at the end of the decoder 1130. In some embodiments, the weight matrix W d X W d h W d Y With weight matrix W respectively e X W e h W e Y Same or different.

[0133] exist Figure 13 In the example shown, the Nth decoded block RB d N Configured to receive input commands And a compact test vector R; for the input command and the first weight matrix W d X The combination of activation functions f is used to generate the first vector. For the compact test vector R and the second weight matrix W d h Combining activation functions to generate a second vector f(RW) d h ); Apply an activation function to the sum of the first and second vectors to generate the Nth hidden state vector h. d N And for the Nth hidden state vector h d N and the third weight matrix W d Y Combining activation functions to generate the Nth output vector In some embodiments, enter command The value can be 0.

[0134] Second decoding block RB d 2 is configured as follows: from the third decode block RB d 3. Receive the third output vector and the third hidden state vector h d 3; For the third output vector and the first weight matrix W d X The activation function f is executed in combination to generate the third hidden state vector; the third hidden state vector h is then processed. d 3. Second weight matrix Wd h Combining activation functions to generate a fourth vector f(h) d 3W d h The activation function is applied to the sum of the third and fourth vectors to generate the second hidden state vector h. d 2; and for the second hidden state vector and the third weight matrix W d Y Combining activation functions to generate a second output vector

[0135] First decoding block RB d 1 is configured as follows: from the second decode block RB d 2. Receive the second output vector The second hidden state vector h d 2; For the second output vector and the first weight matrix W d X The combined execution of activation function f generates the fifth vector. For the second hidden state vector h d 2. Second weight matrix W d h Combining activation functions to generate the sixth vector f(h) d 2W d h The activation function is applied to the sum of the fifth and sixth vectors to generate the first hidden state vector h. d 1; and for the first hidden state vector and the third weight matrix W d Y The combined execution of activation functions generates the first output vector. First output vector to Nth output vector This can correspond to the input command C1-C. N The recovery command.

[0136] As described above, the decoder 1130 can have N RBs with additional outputs to recover the command from the compact representation vector R. Each block RB d i (1≤i≤N) can receive the hidden state vector h from the previous block. d i+1 and the command to restore As input, it can generate the current hidden state vector h. d i and recovery command Decoder 1130 can operate in the opposite way to encoder 1120, that is, it can take commands from the Nth output vector. revert to the first output vector

[0137] Figure 12 and Figure 13 The encoder 1120 and the decoder 1130 in Figure 11 may be used to implement a workload-aware NAND flash controller with a self-test block as shown in

[0138] Referring back to Figure 11 , the controller 100 can use the encoder 1120 and the decoder 1130 to provide adjustment of the FW parameters (e.g., garbage collection intensity) and drive self-test, respectively.

[0139] is a d-dimensional compact representation vector R. This vector can be passed to the FW adjuster 1115. The FW adjuster 1115 can change (or adjust) the FW parameters based on the FW state (e.g., wear level, counter value, etc.) and the input workload type. The workload type can be determined based on a distance function between the input vector R and the stored W typical workload vectors (R1, R2,..., R W ) in some embodiments, the distance function can be the Euclidean Distance. As is well known, the Euclidean Distance between two n-dimensional vectors p and q can be defined as the following equation: or The FW adjuster 1115 can update the parameters based on a cost function, which can be determined to maximize the performance of the SSD and / or minimize the power consumption of the SSD.

[0140] Two typical workloads can be read-intensive and write-intensive. For these types of workloads, the flash translation layer 1110 can store two compact 5-dimensional (d = 5) vectors accordingly: R1 = (0.0617, -0.0981, 0.1380, 0.0215, 0.2057) and R2 = (0.0029, -0.0038, -0.0013, -0.0014, 0.0052). For example, in the case of a read-intensive workload, the garbage collection (GC) intensity can be set to the maximum level, while in the case of a write-intensive workload, the GC intensity can be set to the minimum level.

[0141] In an example, the input workload WL contains 5 read commands and 95 write commands and is converted by the encoder 1120 to a 5-dimensional vector R = (0.0034, -0.0031, 0.0025, -0.0019, -0.0013). The Euclidean distance between R and R1 is 0.2723 and the Euclidean distance between R and R2 is 0.0076. Thus, the input workload WL can be determined to be write-intensive when the vector R is closer to the vector R2. Based on this determination, the FW adjuster 1115 can set the GC intensity to the minimum level in order to provide better performance by minimizing time-consuming GC operations.

[0142] The decoder 1130 can provide a drive self-test. The decoder 1130 can receive the compact representation vector R T from the compact vector generator and can recover the test workload WL T from the compact representation vector R T In an embodiment, the compact vector generator can be implemented as an internal component 1150A of the controller 100. In another embodiment, the compact vector generator can be implemented as an internal component 1150B of the host 5, i.e., an external component 1150B of the controller 100.

[0143] The selector 1160A can receive the compact representation vector R I T from the compact vector generator 1150A in response to the vector selection signal E and receive the compact representation vector R E T from the compact vector generator 1150B. For example, when E = “0”, the selector 1160A can receive the compact representation vector R I T from the compact vector generator 1150A and output the compact representation vector R T When E = “1”, the selector 1160A can receive the compact representation vector R E T from the compact vector generator 1150B and output the compact representation vector R T .

[0144] The decoder 1130 can receive the compact representation vector R T from the selector 1160A, decode the compact representation vector R T and output the test workload WL T The selector 1160B can receive the input workload WL from the host 5 and the test workload WL TFor example, when M = "0", the selector 1160B can receive the input workload WL from the host 5 and output the workload WL C When M = "1", the selector 1160B can receive the test workload WL T from the decoder 1130 and output the workload WL C The SSD 10 supports two modes, including a normal mode (M = "0") and a test mode (M = "1"). In the normal mode, the workload WL C is the same as the host workload WL. In the test mode, the test workload WL T is decoded from the compact representation vector R T generated by the compact vector generator 1150A or 1150B.

[0145] The flash interface layer (FIL) 1140 can receive the workload WL C from the selector 1160B and generate the final workload WL F . The final workload WL F may be passed from the FIL 1140 to the NAND memory device 200. Since the compact representation vector R T has much lower dimensionality compared to the input workload WL, fewer vectors are needed to cover the possible test space.

[0146] Figure 14 is a diagram illustrating a compact vector generator 1150 according to an embodiment of the present application. The compact vector generator 1150 can be the compact vector generator 1150A or the compact vector generator 1150B in Figure 11 .

[0147] Referring to Figure 14 , the compact vector generator 1150 can include a counter (CNT) 1152, a statistics processor 1154, a product component (Π) 1156, and a summation component (Σ) 1158. The counter (CNT) 1152 can generate a multi-dimensional compact vector in response to a clock CLK. For example, the counter (CNT) 1152 can generate a d-dimensional compact vector R C (1) -R C (d) The statistics processor 1154 can receive components of the W typical workload vectors R1-R W and generate a standard deviation value σ (i) and a mean value μ (i) for all of the typical workload vectors R1-R W . For example, the statistics processor 1154 can receive components R1 W of the W workload vectors R1-R (1)- R1 (d) to R W (1) - R W (d) and for all typical workload vectors R1-R W a standard deviation value σ (1) -σ (d) and a mean value μ (1) -μ (d) . The product component (Π) 1156 can multiply the d-dimensional compact vector R C (1) - R C (d) by the standard deviation value σ (1) -σ (d) to generate a compact vector Rσ (1) - Rσ (d) . The sum component (∑) 1158 can add the compact vector Rσ (1) - Rσ (d) by the mean value μ (1) -μ (d) to generate a compact test vector R T (1) - R T (d) .

[0148] In some embodiments, the compact vector generator 1150 generates all possible 5-dimensional vectors R C in steps of 0.2 for each coordinate, i.e., (0, 0, 0, 0, 0), (0, 0, 0, 0, 0.2), (0, 0, 0, 0.2, 0),..., (1, 1, 1, 1, 1) - a total of 7776 vectors that uniformly cover the possible 5-dimensional test space. Then, the compact vector generator 1150 transforms each vector R C according to the following equation: where R C (i) denotes the i-th dimension in the compact vector, σ (i) denotes the standard deviation for the i-th component of all typical workload vectors R1, R2,..., R W and μ (i) denotes the mean value for the i-th component of all typical workload vectors R1, R2,..., R W . Thus, a d-dimensional compact test vector R T is generated.

[0149] The decoder 1130 and the FIL 1140 can restore all vectors R T to 7776 workloads WL FThus, in the test mode (i.e., M = "1"), much fewer test vectors can be used to perform pseudo-exhaustive drive tests compared to the normal mode (i.e., M = "0").

[0150] Table 2 summarizes the estimated hardware, latency, and memory overhead:

[0151] Table 2:

[0152] N Memory (Kb) Delay (μs) Hardware (LUT / FF) 100 40 0.69 (5626，10125) 1000 40 6.72 (56260，101250) 10000 40 66.69 (562600，1012500)

[0153] Table 2 shows that the recurrent neural network blocks (RBs) of the encoder and the decoder are implemented as long short-term memory (LSTM) blocks. The memory is estimated for storing the weight matrices of the encoder and the decoder to compress the workloads into 25-dimensional vectors (d = 25). Since the weight matrices are shared among all cells, the memory overhead is almost the same for different number of LSTM blocks (N). The latency is estimated based on C program implementation to encode and decode the workloads into 25-dimensional vectors. The hardware is estimated for 2N LSTM blocks implemented in a field-programmable gate array (FPGA) in lookup table (LUT) blocks and flip-flops (FFs).

[0154] As described above, embodiments provide a scheme that uses compact representation vectors associated with input workloads. In an embodiment, a memory controller can be able to understand an input workload based on its compact representation in a memory system (e.g., an SSD (e.g., a NAND flash memory device)) and can perform operations (i.e., adjustment of firmware parameters) to optimize its performance. In another embodiment, testing of a memory system (e.g., SSD testing) can be performed with a much smaller test vector space.

[0155] While the forgoing embodiments have been described in some detail for purposes of clarity and understanding, it will be appreciated that certain changes and modifications can be practiced within the scope of the appended claims. Accordingly, the disclosed embodiments are to be considered as illustrative and not restrictive. The application is not to be limited to the details given herein, but can be modified within the scope of the appended claims.

Claims

1. A memory system comprising: a memory device; and a controller, the controller comprising an encoder and firmware (FW) coupled to the encoder, the encoder comprising a plurality of recurrent encoding blocks, the plurality of recurrent encoding blocks comprising a first encoding block to an Nth encoding block, wherein each recurrent encoding block: receives one of a plurality of input commands in an input workload associated with the memory device; and generates a hidden state vector corresponding to the received input command by applying a set of activation functions to the received input command, wherein the Nth encoding block generates a final hidden state vector as a compact representation vector corresponding to the plurality of input commands, and wherein the firmware: determines a distance function between the compact representation vector and each of a plurality of compact workload vectors; and adjusts at least one of the firmware parameters based on the determined distance function.

2. The system of claim 1, wherein, the distance function comprises a Euclidean distance.

3. The system of claim 2, wherein, the firmware: selects one of the plurality of compact workload vectors based on the determined distance function, the selected compact workload vector having a minimum distance; and adjusts at least one of the firmware parameters based on the selected compact workload vector.

4. The system of claim 3, wherein, at least one of the firmware parameters comprises a garbage collection intensity.

5. The system of claim 1, wherein, the set of activation functions comprises hyperbolic tangent, sigmoid, and rectified linear unit, and wherein the first encoding block to the Nth encoding block are connected in cascade.

6. The system of claim 5, wherein, the first encoding block: receives a first input command among the plurality of input commands; performs one of the set of activation functions on a combination of the first input command and a first weight matrix to generate a first vector; performs one of the set of activation functions on a combination of an initial hidden state vector and a second weight matrix to generate a second vector; and performs one of the set of activation functions on a sum of the first vector and the second vector to generate a first hidden state vector.

7. The system of claim 6, wherein, a second encoding block among the plurality of recurrent encoding blocks: receives a second input command among the plurality of input commands; performs one of the set of activation functions on a combination of the second input command and the first weight matrix to generate a third vector; performs one of the set of activation functions on a combination of the first hidden state vector and the second weight matrix to generate a fourth vector; and performs one of the set of activation functions on a sum of the third vector and the fourth vector to generate a second hidden state vector.

8. The system of claim 1, wherein, the controller further comprises: a decoder, the decoder comprising a plurality of recurrent decoding blocks, and receives a compact test vector and generates a test workload comprising a recovery command based on the compact test vector, and wherein the plurality of recurrent decoding blocks comprise a first decoding block to an Nth decoding block, the first decoding block to the Nth decoding block are symmetrical to the first encoding block to the Nth encoding block and have a cascaded structure in descending order.

9. The system of claim 8, wherein, the plurality of recurrent encoding blocks and the plurality of recurrent decoding blocks are implemented differently.

10. The system of claim 8, wherein, the Nth decoding block: receives an input command and the compact test vector; performing one of the set of activation functions on a combination of the input command and a first weight matrix to generate a first vector; performing one of the set of activation functions on a combination of the compact test vector and a second weight matrix to generate a second vector; performing one of the set of activation functions on a sum of the first vector and the second vector to generate an Nth hidden state vector; and performing one of the set of activation functions on a combination of the Nth hidden state vector and a third weight matrix to generate an Nth output vector.

11. The system of claim 8, wherein, the first decoding block: receiving a second output vector and a second hidden state vector from a second decoding block; performing one of the set of activation functions on a combination of the second output vector and a first weight matrix to generate a third vector; performing one of the set of activation functions on a combination of the second hidden state vector and a second weight matrix to generate a fourth vector; performing one of the set of activation functions on a sum of the third vector and the fourth vector to generate a first hidden state vector; and performing one of the set of activation functions on a combination of the first hidden state vector and a third weight matrix to generate a first output vector, wherein the restore command comprises the first output vector through the Nth output vector.

12. The system of claim 8, further comprising: a compact vector generator that generates the compact test vector; and a selector that receives the input workload and the test workload and outputs a workload selected from among the input workload and the test workload to the memory device. the compact vector generator is included in the controller or a host coupled to the controller.

13. The system of claim 12, wherein, 14. A method of operating a controller of a memory system, the method comprising: providing an encoder comprising a plurality of recurrent encoding blocks including a first encoding block through an Nth encoding block and firmware (FW) coupled to the encoder; receiving, by each recurrent encoding block, one of a plurality of input commands in an input workload associated with a memory device; generating, by each recurrent encoding block, a hidden state vector corresponding to the received input command by applying a set of activation functions to the received input command; determining, by the firmware, a distance function between a compact representation vector corresponding to the plurality of input commands and each of a plurality of compact workload vectors; and adjusting, by the firmware, at least one of firmware parameters based on the determined distance function, wherein the Nth encoding block generates a final hidden state vector as the compact representation vector. the distance function comprises a Euclidean distance, and wherein adjusting the at least one of the firmware parameters comprises:

15. The method of claim 14, wherein, selecting one of the plurality of compact workload vectors based on the determined distance function, the selected compact workload vector having a minimum distance; and adjusting the at least one of the firmware parameters based on the selected compact workload vector.

15. The method of claim 14, wherein: the distance function comprises a Euclidean distance, and wherein adjusting the at least one of the firmware parameters comprises: selecting one of the plurality of compact workload vectors based on the determined distance function, the selected compact workload vector having a minimum distance; and adjusting the at least one of the firmware parameters based on the selected compact workload vector.

16. The method of claim 15, wherein, At least one of the firmware parameters comprises a garbage collection intensity.

17. The method of claim 14, wherein, The set of activation functions comprises hyperbolic tangent, sigmoid, and rectified linear unit.

18. The method of claim 14, wherein, The first encoding block through the Nth encoding block are connected in cascade.

19. The method of claim 15, further comprising: receiving, by a decoder comprising a plurality of cycle encoding blocks, a compact test vector; and generating, by the decoder, a test workload comprising a recovery command based on the compact test vector, and wherein the plurality of cycle encoding blocks and the plurality of cycle decoding blocks are implemented differently.

20. The method of claim 19, further comprising: selecting one of the input workload and the test workload and outputting the selected workload to the memory device.

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