Linear feedback shift register for generating bounded random numbers

Abstract

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

Description

Technical Field

[0001] This disclosure relates to a linear feedback shift register for generating bounded random numbers. Background Technology

[0002] A shift register is a type of digital circuit in which a set of flip-flops (or other state storage devices) are arranged such that the output of one flip-flop drives the input of the next flip-flop. The flip-flops share a clock signal, such that during each clock cycle, data is shifted from one position to the next. A linear feedback shift register (LFSR) is a type of shift register in which the input to the LFSR (e.g., the next value of the least significant bit representing the LFSR stored in the flip-flops) is a linear function of the LFSR state (e.g., derived from the current value stored in one or more flip-flops in the LFSR). That is, the LFSR value in a given clock cycle is a linear function of the LFSR value in the previous clock cycle. An LFSR with a well-chosen linear function will produce a series of values ​​that appear random, and therefore LFSRs are often used as hardware random number generators. Summary of the Invention

[0003] In one aspect, this disclosure relates to an n-bit linear feedback shift register, comprising: a clock signal; a lower partial linear feedback shift register including m flip-flops coupled to the clock signal, the lower partial linear feedback shift register being configured to update the next clock cycle state of the m flip-flops based on a lower partial linear function of the current clock cycle state of the m flip-flops; and an upper partial linear feedback shift register including nm flip-flops coupled to the clock signal, the upper partial linear feedback shift register being configured to update the next clock cycle state of the nm flip-flops based on a lower partial linear function of the current clock cycle state of the nm flip-flops. A partial linear function is used to update the next clock cycle state of the nm flip-flops; and the output of the n-bit linear feedback shift register includes multiple bits numbered from least significant bit to most significant bit, wherein the most significant bit of the output of the n-bit linear feedback shift register is based on the current clock cycle state of the nm flip-flops of the upper partial linear feedback shift register, and the least significant bit of the output of the n-bit linear feedback shift register is based on the current clock cycle state of the m flip-flops of the lower partial linear feedback shift register.

[0004] In another aspect, this disclosure relates to a pseudo-random number generation system comprising: an input terminal, wherein a signal at the input terminal indicates a request for a bounded random number; an n-bit bounded linear feedback shift register configured to generate random numbers based on a linear function; a comparator configured to: determine whether the random number is less than a threshold; provide the random number as a system output when the random number is determined to be less than the threshold; and generate an enable pulse when the random number is determined to be not less than the threshold; and an enable signal configured, based on the signal at the input terminal and the enable pulse, to enable the n-bit bounded linear feedback shift register to generate random numbers each time the enable signal generates a pulse.

[0005] In another aspect, this disclosure relates to a method for generating n-bit bounded random numbers, comprising: generating at a first linear feedback shift register a random number between 0 and 2... m The first pseudo-random number is between -1 and n, where m is less than n; a number between 0 and 2 is generated at the second linear feedback shift register. n-m A second pseudo-random number between -2; and an n-bit bounded pseudo-random number generated based on the first pseudo-random number and the second pseudo-random number, the n-bit bounded pseudo-random number comprising multiple bits sorted from least significant bit to most significant bit, wherein the first pseudo-random number corresponds to the m least significant bits in the n-bit bounded pseudo-random number, and the second pseudo-random number corresponds to the nm most significant bits in the n-bit bounded pseudo-random number. Attached Figure Description

[0006] Many aspects of this disclosure can be better understood by referring to the following figures. The components in the figures are not necessarily to scale. In fact, the focus is on clearly illustrating the principles of this disclosure. The figures should not be construed as limiting this disclosure to the specific embodiments depicted, but are merely for explanation and understanding.

[0007] Figure 1 This is a block diagram schematically illustrating a memory device according to an embodiment of the present technology.

[0008] Figure 2 This is a block diagram of a system having a memory device configured according to embodiments of the present technology.

[0009] Figure 3 This is a simplified block diagram schematically illustrating an embodiment of the present technology for generating bounded random numbers using an LFSR.

[0010] Figure 4 This is a flowchart illustrating a process for generating bounded random numbers according to an embodiment of the present technology.

[0011] Figure 5 This is a timing diagram illustrating bounded random numbers generated according to embodiments of the present technology.

[0012] Figure 6A This is a simplified schematic diagram showing the upper portion of an LFSR for generating bounded random numbers according to an embodiment of the present technology.

[0013] Figure 6B This is a simplified schematic diagram illustrating the lower portion of an LFSR for generating bounded random numbers according to an embodiment of the present technology.

[0014] Figure 7 This is a schematic diagram illustrating an embodiment of the lower portion of an LFSR for generating bounded random numbers according to an embodiment of the present technology.

[0015] Figure 8 This is a block diagram of a system using bounded random numbers generated by an LFSR according to an embodiment of the present technology. Detailed Implementation

[0016] Linear Feedback Shift Register (LFSR) circuits are commonly used to generate pseudo-random numbers for various computational applications. The output of an LFSR is pseudo-random because the resulting sequence of values ​​is both deterministic and repeatable. That is, if the current state of the LFSR and its linear function are known, the next value in the sequence can be determined. Furthermore, the sequence of values ​​generated by an LFSR will eventually repeat. However, if given a sufficiently large LFSR (i.e., a sufficient number of storage bits to form the LFSR) and a sufficiently long sequence of values ​​before the LFSR repeats, then the LFSR appears to be generating random numbers. For clarity, "pseudo-random" and "random" are used interchangeably in this document to refer to the LFSR output.

[0017] A conventional n-bit LFSR (i.e., an LFSR formed by n flip-flops or other state storage devices, where n is a positive integer) will cycle through 2 in a seemingly random order. n -1 possible values, and then this sequence repeats. However, in some applications, certain values ​​within the maximum random length sequence of the LFSR are undesirable for the LFSR output consumer. For example, in applications where the LFSR output is used to generate random addresses, where the maximum effective address is less than 2... n But greater than 2 n-1 Some LFSR outputs within the maximum sequence will be invalid. While some solutions exist to overcome this limitation of conventional LFSRs, they have various drawbacks. For example, solutions that proceed through multiple LFSR outputs until a valid (e.g., within range) output is obtained may violate the timing requirements of other circuitry interfacing with the LFSR. Therefore, what is needed is an LFSR capable of generating sequences of less than the maximum random length.

[0018] Therefore, several embodiments of this technology relate to an LFSR (referred to herein as a “bounded LFSR”) for generating bounded random numbers, systems incorporating bounded LFSRs, and associated methods. As described herein, a bounded LFSR is configured (e.g., during circuit design) to produce a maximum value less than the maximum value of a conventional LFSR of equivalent size (e.g., less than 2). n The bounded LFSR has (1) a "bounded" sequence that is both shorter than the maximum length sequence and (2) has a maximum value that is less than the maximum length sequence of a conventional LFSR. In some embodiments, the bounded LFSR comprises an upper portion LFSR and a lower portion LFSR that operate on the same clock signal and whose outputs are combined (e.g., cascaded) to form the bounded LFSR output. For example, a bounded LFSR with n state bits (referred to herein as an "n-bit bounded LFSR" or "bounded LFSR[n-1:0]") can be composed of a lower portion LFSR with m state bits and an upper portion LFSR with nm state bits (where n and m are positive integers, and n is greater than m such that nm is a positive integer). In some embodiments, the m-bit lower portion LFSR is configured to have 2 m A sequence of values ​​(i.e., from 0 to 2). m -1). In some embodiments, the upper portion of the nm-bit LFSR is configured to have 2 n-m -1 to k values; as described herein, k reflects the configuration parameter of how many values ​​in the upper part of the LFSR sequence are omitted in the sequence (where k is a natural number or a non-negative integer, and may be zero). As described herein, because bounded LFSRs produce shorter sequences of values ​​with maximum values ​​lower than those of regular LFSR sequences, bounded LFSRs can generate acceptable random numbers in a smaller number of LFSR clock cycles (e.g., within the effective range of the consumed LFSR output).

[0019] In some embodiments, a bounded LFSR is used for a memory device or system. For example, a bounded LFSR can be used to generate addresses to detect and / or mitigate row hammering effects on a memory device. As another example, a bounded LFSR can be used to generate seed addresses in a row hammering mitigation system. The ability to generate bounded random numbers is crucial in many applications where time constraints are important, such as row hammering mitigation and other uses limited by memory device timing requirements.

[0020] Figure 1 This is a block diagram schematically illustrating a memory device 100 according to an embodiment of the present technology. The memory device 100 may include an array of memory cells, such as a memory array 150. The memory array 150 may include multiple groups (e.g., Figure 1The examples may include groups 0-15, and each group may contain multiple word lines (WL), multiple bit lines (BL), and multiple memory cells (e.g., m×n memory cells) arranged at the intersections of word lines (e.g., m word lines, which may also be referred to as rows) and bit lines (e.g., n bit lines, which may also be referred to as columns). Each of the multiple word lines may be coupled to a corresponding word line driver (WL driver) configured to control the word line voltage during memory operations.

[0021] Memory cells may include any of several different memory media types, including capacitive, phase-change, magnetoresistive, ferroelectric, etc. In some embodiments, a portion of the memory array 150 may be configured to store ECC parity bits. The selection of word lines WL may be performed by row decoder 140, and the selection of bit lines BL may be performed by column decoder 145. Sensing amplifiers (SAMPs) may be provided for and connected to at least one corresponding local I / O line pair (LIOT / B) for the corresponding bit line BL, which may then be coupled via a transfer gate (TG) to at least one corresponding main I / O line pair (MIOT / B), the transfer gate acting as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing their operation.

[0022] The memory device 100 may employ multiple external terminals including command and address terminals coupled to the command bus and address bus to receive command signal CMD and address signal ADDR, respectively. The memory device may also include a chip select terminal for receiving chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI (for data bus inversion function) and DMI (for data mask inversion function), and power supply terminals VDD, VSS and VDDQ.

[0023] Address signals and group address signals can be supplied externally to the command and address terminals. The address signals and group address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 receives the address signals and supplies the decoded row address signal (XADD) to the row decoder 140 (which may be called a row driver), and supplies the decoded column address signal (YADD) to the column decoder 145 (which may be called a column driver). The address decoder 110 can also receive the group address portion of the ADDR input and supply the decoded group address signal (BADD) and group address signal to both the row decoder 140 and the column decoder 145.

[0024] Command signal CMD, address signal ADDR, and chip select signal CS can be supplied from the memory controller to the command and address terminals. The command signal can represent various memory commands from the memory controller (e.g., refresh command, activation command, precharge command, access command that may include read and write commands). The select signal CS can be used to select the memory device 100 to respond to the commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device 100, the commands and addresses can be decoded, and memory operations can be performed. The command signal CMD can be provided as the internal command signal ICMD to the command decoder 115 via the command / address input circuit 105.

[0025] Command decoder 115 may include circuitry for decoding internal command signals ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Other instances of memory operations that memory device 100 may perform based on decoding internal command signals ICMD include refresh commands (e.g., rebuilding the full charge stored in the individual memory cells of memory array 150), activation commands (e.g., activating rows in a specific group, in some cases for subsequent access operations), or precharge commands (e.g., deactivating activated rows in a specific group). Internal command signals may also include output and input activation commands, such as timing commands CMDCK (…). Figure 1 (Not shown in the image).

[0026] In some embodiments, the command decoder 115 may further include one or more registers 118 for tracking various counts and / or values ​​(e.g., counts of refresh commands received by the memory device 100 or counts of self-refresh operations performed by the memory device 100) and / or for storing various operating conditions for the memory device 100 to perform certain functions, features, and modes (or test modes). Thus, in some embodiments, register 118 (or a subset of register 118) may be referred to as a mode register. Alternatively or additionally, the memory device 100 may include register 118 as a separate component outside of the command decoder 115. In some embodiments, register 118 may include a multipurpose register (MPR) configured to write dedicated data to and / or read dedicated data from the memory device 100.

[0027] When a read command is issued to a group with open rows and the column address is provided in a timely manner as part of the read command, read data can be read from memory cells in memory array 150 specified by the row address (possibly provided as part of an activation command identifying open rows) and the column address. The read command can be received by command decoder 115, which can provide internal commands to input / output circuitry 160 such that read data can be output from data terminals DQ, RDQS, DBI, and DMI via read / write amplifier 155 and input / output circuitry 160 according to the RDQS clock signal. Read data can be provided at a time defined by read delay information RL, which can be programmed in memory device 100, for example, in a mode register (e.g., register 118). Read delay information RL can be defined in terms of clock cycles of the CK clock signal. For example, when providing associated read data, read delay information RL can be the number of clock cycles of the CK signal after the read command is received by memory device 100.

[0028] When a write command is issued to a group with open rows and the column address is supplied in a timely manner as part of the write command, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by a command decoder 115, which can provide an internal command to the input / output circuitry 160, such that write data can be received by the data receiver in the input / output circuitry 160 and supplied to the memory array 150 via the input / output circuitry 160 and the read / write amplifier 155. Write data can be written to memory cells specified by the row and column addresses. Write data can be supplied to the data terminals at a time defined by write delay information WL. The write delay information WL can be programmed in the memory device 100, for example, in a mode register (e.g., register 118). The write delay information WL can be defined in terms of the clock cycles of the CK clock signal. For example, when receiving associated write data, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by the memory device 100.

[0029] Power supply potentials VDD and VSS can be supplied to the power supply terminals. These power supply potentials VDD and VSS can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the line decoder 140, the internal potentials VOD and VARY can be used in the sense amplifier included in the memory array 150, and the internal potential VPERI can be used in many other circuit blocks.

[0030] A power supply potential VDDQ can also be supplied to the power supply terminals. The power supply potential VDDQ can be supplied to the input / output circuit 160 together with the power supply potential VSS. In an embodiment of this technology, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of this technology, the power supply potential VDDQ can be a different potential from the power supply potential VDD. However, the input / output circuit 160 can use a dedicated power supply potential VDDQ so that power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0031] External clock signals and complementary external clock signals can be supplied to the clock terminal and the data clock terminal. External clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and simultaneously transition between said opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0032] An input buffer included in clock input circuit 120 can receive external clock signals. For example, when enabled by the CKE signal from command decoder 115, the input buffer can receive CK and CKF signals and WCK and WCKF signals. Clock input circuit 120 can receive external clock signals to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase-controlled and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from command decoder 115.

[0033] For example, the internal clock circuit 130 may include a clock path that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1(Not shown in the image). The internal clock circuit 130 can further provide input / output (I / O) clock signals. The I / O clock signals can be supplied to the input / output circuit 160 and can be used as timing signals to determine the output timing for reading data and the input timing for writing data. The I / O clock signals can be provided at multiple clock frequencies, allowing data to be output from and input to the memory device 100 at different data rates. Higher clock frequencies may be desirable when high memory speed is desired. Lower clock frequencies may be desirable when lower power consumption is desired. The internal clock signal ICLK can also be supplied to the timing generator 135, and thus various internal clock signals can be generated.

[0034] Memory devices (e.g.) Figure 1 The memory device 100 may be configured to detect and / or mitigate row hammering effects. For example, the memory device 100 (e.g., in the row decoder 140) may include one or more bounded LFSRs to generate random sampling signals. The memory device 100 may use the random sampling signals to sample row addresses to be used for detecting and / or mitigating row hammering effects.

[0035] The memory device 100 can be connected to any one or a component of a plurality of electronic devices capable of temporarily or permanently storing information using the memory. For example, the host device of the memory device 100 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, router, etc.) or a digital image, audio, and / or video recorder, vehicle, appliance, toy, or any of several other products. In one embodiment, the host device can be directly connected to the memory device 100, but in other embodiments, the host device can be indirectly connected to the memory device (e.g., via a network connection or via an intermediary device).

[0036] Figure 2 This is a block diagram of a system 201 having a memory device 200 configured according to an embodiment of the present technology. The memory device 200 may be a reference Figure 1 Examples of memory devices described or aspects including said memory devices are presented. As shown, memory device 200 includes main memory 202 (e.g., DRAM, NAND flash, NOR flash, FeRAM, PCM, etc.) and control circuitry 206 operatively coupled to host device 208 (e.g., upstream central processing unit (CPU), memory controller). Control circuitry 206 may include references to... Figure 1The description covers various components. For example, the control circuit system 206 may include aspects such as command / address input circuitry 105, address decoder 110, and command decoder 115.

[0037] Main memory 202 includes a plurality of memory cells 220, each containing a plurality of memory cells. Memory cells 220 may be individual memory dies, memory planes within a single memory die, stacks of memory dies vertically connected via through-silicon vias (TSVs), etc. For example, in one embodiment, each of the memory cells 220 may be formed from a semiconductor die and arranged in a single device package along with other memory cell dies. In other embodiments, the plurality of memory cells 220 may be located in the same position on a single die and / or distributed across multiple device packages. In some embodiments, memory cells 220 may also be subdivided into memory regions 228 (e.g., groups, levels, channels, blocks, pages, etc.).

[0038] For example, a memory cell may include a floating gate, charge trap, phase-change, capacitive, ferroelectric, magnetoresistive, and / or other suitable memory element configured to persistently or semi-persistently store data. Main memory 202 and / or each memory cell 220 may also include other circuit components, such as multiplexers, decoders, buffers, read / write drivers, address registers, data outputs / data in registers, etc., for accessing and / or programming (e.g., writing) the memory cell and other functions, such as processing information and / or communicating with control circuitry 206 or host device 208. Although a specific number of memory cells, rows, columns, areas, and memory units are shown in the illustrated embodiments for illustrative purposes, the number of memory cells, rows, columns, areas, and memory units can vary, and in other embodiments, the scale may be larger or smaller than shown in the illustrated examples. For example, in some embodiments, memory device 200 may include only one memory cell 220. Alternatively, the memory device 200 may include two, three, four, eight, ten, or more (e.g., 16, 32, 64, or more) memory cells 220. Although the memory cells 220 are... Figure 2 The diagram shows each memory cell 220 containing four memory regions 228, but in other embodiments, each memory cell 220 may contain one, two, three, eight or more (e.g., 16, 32, 64, 100, 128, 256 or more) memory regions.

[0039] In one embodiment, the control circuitry 206 may be located on the same die as the main memory 202 (e.g., including command / address / clock input circuitry, decoders, voltage and timing generators, input / output circuitry, etc.). In another embodiment, the control circuitry 206 may be a microcontroller, a special-purpose logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a control circuitry on the memory die, etc.), or other suitable processor. In one embodiment, the control circuitry 206 may include a processor configured to execute instructions stored in memory to perform various processes, logic flows, and routines to control the operation of the memory device 200, including managing the main memory 202 and handling communication between the memory device 200 and the host device 208. In some embodiments, the control circuitry 206 may include an embedded memory with memory registers for storing, for example, memory addresses, row counters, group counters, memory pointers, fetched data, etc. In another embodiment of the technology, the memory device 200 may not include a control circuitry and may instead rely on external control (e.g., provided by the host device 208 or a processor or controller separate from the memory device 200).

[0040] Host device 208 can be any one or a component of several electronic devices capable of temporarily or permanently storing information using memory. For example, host device 208 can be a computing device, such as a desktop or portable computer, server, handheld device (e.g., mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., central processing unit, coprocessor, dedicated memory controller, etc.). Host device 208 can be a networking device (e.g., switch, router, etc.) or a digital image, audio, and / or video recorder, vehicle, appliance, toy, or any of several other products. In one embodiment, host device 208 can be directly connected to memory device 200, but in other embodiments, host device 208 can be indirectly connected to memory device (e.g., via networking or via an intermediary device).

[0041] In operation, the control circuitry 206 can directly write to or otherwise program (e.g., erase) the various memory regions of the main memory 202. The control circuitry 206 communicates with the host device 208 via a host-device bus or interface 210. In some embodiments, the host device 208 and the control circuitry 206 can communicate via a dedicated memory bus (e.g., a DRAM bus). In other embodiments, the host device 208 and the control circuitry 206 can communicate via a serial interface, such as a serially connected SCSI (SAS), serial AT accessory (SATA) interface, peripheral component interconnect high speed (PCIe), or other suitable interface (e.g., a parallel interface). The host device 208 can send various requests (e.g., in packet or packet stream form) to the control circuitry 206. Requests may include commands to read, write, erase, return information, and / or perform specific operations (e.g., refresh, trim, precharge, activation, wear leveling, garbage collection, etc.).

[0042] Figure 3 This is a simplified block diagram schematically illustrating a bounded LFSR 300 configured according to an embodiment of the present technology. Figure 3 As shown, the bounded LFSR 300 is n-bit wide, corresponding to bits 0 to n-1 (i.e., [n-1:0]). The bounded LFSR 300 comprises two LFSRs: a lower portion LFSR 305 and an upper portion LFSR 310. As described herein, the lower portion LFSR 305 and the upper portion LFSR 310 may each contain separate circuitry (e.g., flip-flops or other state storage devices and / or logic gates for implementing linear functions or other sequence generation features) such that they each produce different sequences of values. That is, the lower portion LFSR 305 follows the lower portion sequence, and the upper portion LFSR 310 follows the upper portion sequence. However, the lower portion LFSR 305 and the upper portion LFSR 310 may share a clock signal 315, allowing them to update values ​​simultaneously. In embodiments of the disclosed technology, the lower portion LFSR 305 and the upper portion LFSR 310 do not share data; that is, in the embodiments described, the output of the lower portion LFSR 305 does not serve as the input to a linear function of the upper portion LFSR 310. The output of the bounded LFSR 300 is based on the outputs of the lower portion LFSR 305 and the upper portion LFSR 310. Specifically, for example, the lower bits of the bounded LFSR 300 output can be driven by the lower portion LFSR 305, and the higher bits of the bounded LFSR 300 output can be driven by the upper portion LFSR 310.

[0043] like Figure 3As shown, the lower portion LFSR 305 is m bits wide, corresponding to bits 0 to m-1 (i.e., [m-1:0]) of the output of the bounded LFSR 300. Therefore, the lower portion LFSR 305 may contain m flip-flops 320a, 320b, etc. (depending on m) up to 320x. The lower portion LFSR 305 may also contain logic (not shown) for generating the lower portion sequence. As described herein, the lower portion sequence can be configured to facilitate the generation of bounded random numbers by the bounded LFSR 300. For example, according to an embodiment of the present technology, the lower portion sequence of the m-bit lower portion LFSR 305 is processed by 2... m There are several possible values. It should be understood that, in comparison, a conventional m-bit LFSR undergoes 2... m -1 possible values, because certain values ​​(e.g., values ​​represented by all 0s or all 1s) may be disallowed, since applying a linear function of the LFSR to such values ​​would result in the LFSR value remaining unchanged.

[0044] like Figure 3 As further shown, the upper portion LFSR 310 is nm bit wide, corresponding to bits m to n-1 (i.e., [n-1:m]) of the output of the bounded LFSR 300. Therefore, the upper portion LFSR 310 may contain nm flip-flops 325a, 325b, etc. (depending on nm) up to 325y. The upper portion LFSR 310 may also contain logic (not shown) for generating the upper portion sequence. As described herein, the upper portion sequence can be configured to facilitate the generation of bounded random numbers by the bounded LFSR 300. For example, according to an embodiment of the present technology, the upper portion sequence of the nm bit upper portion LFSR 310 is processed by 2... n-m -1 to k possible values. k reflects the number of values ​​skipped in the upper part of the sequence and can be set based on design requirements (e.g., how the random numbers generated by the bounded LFSR 300 should be limited according to the requirements of the random number consumer) (using the logic of the upper part LFSR 310). In some embodiments of this technique, k is 0 (i.e., no values ​​are skipped in the upper part of the sequence). In some embodiments of this technique, k is any value, as long as the value of k is not greater than 2. m and 2 n-m Any common factor between -1 and k is required.

[0045] The n-bit bounded LFSR 300, formed by the lower m-bit portion LFSR 305 and the upper nm-bit portion LFSR 310, has a sequence range (2). n-m -1-k)x 2 m In contrast, a conventional n-bit LFSR has 2 n A sequence range of -1 possible values ​​(the maximum length of an n-bit LFSR sequence is 2). n-1 possible value, instead of 2 n There are several possible values, as certain values ​​are not allowed because they would cause the value to remain unchanged when a linear function is applied (since this would result in the LFSR value remaining unchanged). In other words, the sequence traversed by a bounded LFSR 300 is shorter than that of a conventional LFSR of the same size with the same width (i.e., the same number of flip-flops or other state storage devices). Furthermore, the sequence of a bounded LFSR 300 has a lower upper limit than that of a conventional LFSR (that is, the bounded LFSR skips the maximum number generated by a conventional LFSR). Therefore, a bounded LFSR 300 can generate range-of-number random numbers for a consumer (e.g., downstream circuitry) much faster than a conventional LFSR, which might require the consumer to skip or traverse multiple conventional LFSR outputs within several clock cycles before generating a value within the range.

[0046] For example, a circuit (e.g., a circuit system used to mitigate or detect line hammering effects) may require random numbers less than or equal to 150. A conventional 8-bit LFSR goes through 255 values ​​(e.g., 0-254 or 1-255), many of which exceed the circuit's threshold (i.e., greater than 150). Furthermore, LFSR values ​​exceeding the circuit's threshold can appear consecutively in a sequence, requiring the circuit to iterate through multiple LFSR outputs to obtain the next value below the threshold. For example, a conventional LFSR might produce six consecutive values ​​exceeding the threshold, requiring the circuit to wait up to seven LFSR clock cycles for the next valid random number, which can present a significant timing challenge. In other words, the timing requirement for the circuit could be that a new random number is available at least every three clock cycles. In contrast, an 8-bit bounded LFSR configured according to the representative bounded LFSR300 can be configured to generate random numbers in fewer clock cycles. For example, an 8-bit bounded LFSR with a 4-bit lower portion LFSR and a 4-bit upper portion LFSR, and a k value of 2 (i.e., skipping 2 extra values ​​in the upper portion sequence), can generate random numbers at least every 2 clock cycles of the bounded LFSR. In other words, an 8-bit bounded LFSR can be configured to generate at most 2 consecutive values ​​exceeding a threshold, thereby satisfying the timing requirements of the consuming circuit. It should be understood that the bounded LFSR can be designed in different ways (e.g., n, m, and k have different values) depending on the requirements of the consuming circuit (e.g., the required range of random numbers, the number of previous LFSR clock cycles that the next valid output can accept, etc.).

[0047] Figure 4This is a flowchart illustrating a process 400 for generating bounded random numbers according to an embodiment of the present technology. For example, process 400 may be executed to generate random numbers for a power-consuming circuit (e.g., a hardware circuitry system for detecting or mitigating line hammering effects). According to some embodiments of the disclosed technology, based on the requirements of the power-consuming circuit (e.g., for a power-consuming circuit using random numbers as random addresses, the random numbers must not exceed address limits), the power-consuming circuit may require the random numbers to not exceed a threshold. For example, aspects of process 400 may be implemented in a hardware circuitry system using a bounded LFSR and / or additional circuitry system as described herein (e.g., a power-consuming circuitry or circuitry system interfacing between the bounded LFSR and the power-consuming circuitry).

[0048] Procedure 400 begins at box 405, where the procedure defines a lower portion range and an upper portion range. As described herein, the lower portion range and the upper portion range specify the range of values ​​from which the procedure can generate lower and upper portion random numbers, respectively. The generation of the lower and upper portion random numbers is further described below with reference to boxes 410 and 415 of procedure 400. The lower portion range may have form 2 m Where m is partially based on the maximum permissible value (i.e., the threshold) of the random numbers to be generated by process 400. For example, when m is 2, the lower portion range is 4; when m is 4, the lower portion range is 16; when m is 6, the lower portion range is 64, and so on. The upper portion range may have form 2. n-m -1-k, where n and k are partially based on the maximum permissible value (i.e., threshold) of the random numbers to be generated by process 400, and m corresponds to the lower part of the range. According to embodiments of the disclosed technology, n makes 2 n The maximum desired random number is greater than n. For example, if a random number between 0 and 8 is desired, then n could be 4. As another example, if a random number between 0 and 150 is desired, then n could be 8. According to embodiments of the disclosed technology, n is greater than m (that is, nm is a positive value). According to embodiments of the disclosed technology, k could be in the range of 2. m and 2 n-m No value between -1 and k yields a common divisor. In embodiments of the disclosed technology, k may be zero. In some embodiments, the determination of the lower and upper partial ranges may be performed simultaneously or nearly simultaneously with the generation of random numbers (e.g., using an FPGA or other reconfigurable or reprogrammable capability). In some embodiments, the determination of the lower and upper partial ranges may be performed prior to the generation of random numbers (e.g., during the design of the bounded LFSR circuit).

[0049] At box 410, process 400 generates a lower-part random number based on a lower-part range. For example, if the lower-part range is 16, then process 400 can generate a lower-part random number between 0 and 15 (inclusive); if the lower-part range is 128, then the process can generate a lower-part random number between 0 and 127 (inclusive), and so on.

[0050] At box 415, process 400 generates an upper part random number based on the upper part range. For example, if the upper part range is 15, then process 400 can generate an upper part random number between 0 and 14 (inclusive).

[0051] At box 420, process 400 constructs a random number based on a lower part random number and an upper part random number. In some embodiments of the disclosed technique, the lower bits of the random number are based on the lower part random number, and the higher bits of the random number are based on the upper part random number. That is, the random number can be a binary concatenation of the upper part random number and the lower part random number (e.g., {upper part random number, lower part random number}). For example, if the upper part random number is 2 (corresponding to binary "10" or "2'b10") and the lower part random number is 3 (corresponding to binary "11" or "3'b11"), then the constructed random number will be 11 (corresponding to binary "1011" or "4'b1011")). As another example, if both the upper part random number and the lower part random number are 2 (corresponding to binary "10" or "2'b10"), then the constructed random number will be 10 (corresponding to binary "1010" or "4'b1011").

[0052] At decision box 425, process 400 determines whether the constructed random number is less than a threshold (i.e., does not exceed the maximum allowed value). If the constructed random number exceeds the threshold, process 400 returns to box 410 to generate a new random number. If the constructed random number does not exceed the threshold, process 400 continues to box 430.

[0053] At block 430, process 400 outputs the constructed random number. In some embodiments, process 400 drives one or more data signals (e.g., via a bus, at an interface between circuits, etc.) based on the value of the constructed random number. In some embodiments, process 400 drives a valid signal, etc., to indicate to the consumer that the output random number meets a threshold or maximum value constraint. Then, process 400 ends.

[0054] Figure 5 This is a timing diagram illustrating bounded random numbers generated according to embodiments of the present technology. Specifically, Figure 5An example is shown of generating a 4-bit bounded random number 520 in each clock cycle controlled by clock signal 505. The 4-bit bounded random number is based on a low-order bit value 510 and a high-order bit value 515, both of which are 2 bits wide and are updated according to clock signal 505. Each of the low-order bit value 510 and the high-order bit value 515 may follow a repeating sequence (e.g., a low-order sequence and a high-order sequence, respectively), such as a repeating sequence of a linear function from a shift register and / or other logic. For example, as... Figure 5 As shown, before repeating again, the high-order value 515 passes through values ​​2'b00, 2'b10, and 2'b01 in three clock cycles. Furthermore, the high-order value 515 shown does not use the value 2'b11 because... Figure 5 In a representative example, the value is not part of the high-order sequence (e.g., applying a high-order linear function to the value 2'b11 will produce the same 2'b11 value in the next clock cycle, making the high-order value remain unchanged across different cycles). In contrast, as... Figure 5 As shown, before repeating again, the low-order value 510 passes through values ​​2'b10, 2'b11, 2'b01, and 2'b00 in four clock cycles. That is, the low-order sequence contains the value 2'b11 (not present in the high-order sequence) in cycles 525a, 525b, and 525c, as configured by the linear function and / or other logic that generates the low-order sequence. The low-order value 510 and the high-order value 515, both being 2 bits, are combined to form a 4-bit bounded random number 520. That is, as... Figure 5 As shown, bits 0 and 1 of the bounded random number 520 correspond to the low-order value 510, and bits 2 and 3 of the bounded random number 520 correspond to the high-order value 515.

[0055] The bounded random number 520 follows the sequence 530. Figure 5 In the illustrative example, sequence 530 is 12 digits long (e.g., the sequence passes through 2, 11, 5, 0, 10, 7, 1, 8, 6, 3, 9, and 4 before repetition). In contrast, a typically generated 4-bit random number sequence is 15 digits long (e.g., the sequence may pass through 2, 6, 14, 13, 11, 7, 12, 9, 3, 4, 10, 5, 8, 1, and 0 before repetition) and contains larger numbers. If the consumer of bounded random number 520, as shown in sequence 530, requires random numbers less than 9, then only three values ​​(9, 10, and 11) in the sequence need to be skipped, consuming at most one extra cycle of clock signal 505. In contrast, if the same consumer uses the values ​​from the typically generated 4-bit random number sequence from the example, then six values ​​in the sequence (9, 10, 11, 12, 13, and 14) need to be skipped, and the consumer may need to wait up to three additional cycles of clock signal 505 before the next random number in the range (e.g., skipping values ​​14, 13, and 11 after 6 in the sequence before the sequence produces value 7).

[0056] Figure 6A This is a simplified schematic diagram illustrating the upper portion 600 of an LFSR for generating bounded random numbers according to an embodiment of the present technology. For example, the upper portion 600 can be used to generate the higher (e.g., most significant) bits of the bounded LFSR. Figure 6A As shown in the embodiment illustrated, for example, for an n-bit bounded LFSR (corresponding to a bit range of 0 to n-1), the upper portion 600 generates nm most significant bits of the bounded LFSR (where m describes the width of the lower portion of the bounded LFSR as described herein), corresponding to bits m to n-1 of the bounded LFSR value. Therefore, the upper portion 600 contains nm flip-flops, identified as flip-flops 605a, 605b, etc. (depending on nm) up to 605x.

[0057] Based on the linear function of the implemented upper portion, the upper portion 600 includes logic gates 610a and 610b and taps 615a, 615b, and so on, up to 615x. That is, logic gates 610a and 610b and taps 615a-615x partially determine the next state of the upper portion 600 based on the current state of the upper portion. Taps 615a-615x correspond to the bit positions where logical operations are performed on the outputs of flip-flops before they are stored in the next flip-flop in the next cycle. Figure 6A In the embodiment shown, each tap performs an XOR operation between the output of the previous flip-flop and the output of logic gate 610a; however, other logic operations using other input values ​​may be used. Although Figure 6A The illustrated embodiment shows taps 615a-615x corresponding to each bit position of the input in the upper portion 600, but in other embodiments, taps may be omitted at certain bit positions based on a desired linear function. Non-tapped bits are shifted from one flip-flop to the next without changing.

[0058] In some embodiments of the disclosed technology, the upper portion 600 includes logic for skipping values ​​within a sequence generated by a linear function. Although in a conventional LFSR, unwanted values ​​in the sequence pass through multiple cycles (i.e., by timing the LFSR to update values ​​according to a linear function), the logic for skipping values ​​in the upper portion 600 allows multiple values ​​to be skipped within a single cycle. That is, the upper portion 600 can completely omit those values ​​in the sequence instead of timing the conventional LFSR multiple times to obtain the next desired value, thereby reducing or eliminating clock cycle losses. Therefore, the upper portion 600 may include skip logic 620, which evaluates the current value of the upper portion 600 (i.e., the values ​​in flip-flops 605a-605x) and determines whether the next value in the linear function sequence should be skipped. When the skip logic 620 determines that the next value in the linear function sequence should be skipped, the skip logic 620 generates a jump value that the upper portion 600 will update to in the next cycle, replacing the next sequence value generated by the linear function. Because the resulting sequence of values ​​is deterministic (i.e., the same value always follows a given value in the sequence), the skip logic 620 can be configured to skip selected values ​​(e.g., values ​​exceeding a threshold) and jump to the next allowed value in the sequence (e.g., a value within the threshold). The skip logic 620 can also be configured to initiate multiple different skips within a sequence and can be configured to skip multiple values ​​in the sequence. For example, in a linear function sequence containing the sequence (8, 14, 3, 13, and 7), the upper portion 600 can skip values ​​greater than 12 by configuring the skip logic 620 to detect the case where the current value is 8 and skips the value 14 by jumping to 3, and to detect the case where the current value is 3 and skips the value 13 by jumping to 7. As another example, in a linear function sequence containing the sequence (8, 14, 13, and 2), the upper portion 600 can skip values ​​greater than 12 by configuring the skip logic 620 to detect the case where the current value is 8 and skips the values ​​14 and 13 by jumping to 2. In some embodiments, skip logic 620 may be configured not to skip values ​​(i.e., the upper portion 600 follows linear function logic). In some embodiments, skip logic 620 may be configured to skip any number of values ​​within the sequence of the upper portion 600. In some embodiments, skip logic 620 may be configured to skip any number of values, as long as it is within 2... m (i.e., the extent of the lower portion of the bounded LFSR) and 2 n-m-1- The number of skipped values ​​(i.e., the range of the upper portion 600) must not produce a common divisor. In embodiments of the disclosed technology, skip logic 620 and additional logic 625 are coupled to the data input and / or set / reset the inputs of flip-flops 605a-605x. Additionally, skip logic 620 and additional logic 625 can drive different values ​​to each flip-flop (e.g., based on the generated jump value). If skip logic 620 does not detect a skip condition and no jump value is generated, then skip logic 620 and additional logic 625 may not react, causing flip-flops 605a-605x to adopt a value in linear function logic (e.g., the next existing value in the sequence). It should be understood that the configuration of skip logic 620 allows flip-flops 605a-605x to adopt any jump value when a value to be skipped is detected, thereby effectively skipping one or more values ​​in the sequence within a single clock cycle.

[0059] Figure 6B This is a simplified schematic diagram illustrating the lower portion 650 of an LFSR for generating bounded random numbers according to an embodiment of the present technology. For example, the lower portion 650 can be used to generate the lower (e.g., least significant) bits of the bounded LFSR. Figure 6B As shown in the embodiment illustrated, for example, for an n-bit bounded LFSR (corresponding to the bit range 0 to n-1), the lower portion 650 generates m least significant bits of the bounded LFSR, corresponding to bits 0 to m-1 of the bounded LFSR value. Therefore, the lower portion 650 contains m flip-flops, identified as flip-flops 655a, 655b, etc. (depending on m) up to 655x.

[0060] Based on the linear function implemented in the lower part, the lower part 650 includes taps 660a, 660b, and so on, up to 660x. That is, taps 660a-660x partially determine the next state of the lower part 650 based on its current state. Taps 660a-660x correspond to the bit positions where the output of the flip-flop is logically operated on before being stored in the next flip-flop in the next cycle. Figure 6B In the illustrated embodiment, each tap performs an XOR operation with the output of the previous flip-flop and the output of the most valid flip-flop in the lower portion 650 (i.e., flip-flop 655x, corresponding to bit position m-1). In embodiments of the disclosed technology, the taps can use other logical operations with other input values. Although the embodiment shown in 6B illustrates taps 660a-660x corresponding to the inputs at each bit position in the lower portion 650, in other embodiments, taps may be omitted at certain bit positions based on a desired linear function. Non-tapped bits are shifted from one flip-flop to the next without changing.

[0061] In some embodiments of the disclosed technology, the lower portion 650 includes logic for including additional values ​​within the sequence generated by the linear function. Although the linear function of a conventional m-bit LFSR typically produces 2... m -1 value (e.g., from 0 to 2) m The sequence is -2), but the lower part 650 is used to include additional values ​​(e.g., the value 2). m The logic of -1) extends the sequence to include 2. m This allows the lower section 650 to be used in conjunction with additional circuitry, such as in... Figure 6A The upper portion 600, as described, generates bounded random numbers. Therefore, the lower portion 650 may include addition logic 665 and recovery logic 670. Addition logic 665 evaluates the current value of the lower portion 650 (i.e., the values ​​in flip-flops 655a-655x) and determines whether the lower portion 650 should use an additional value beyond the sequence generated by the linear function in the next clock cycle. Addition logic 665 may also generate additional values. In embodiments of the disclosed technology, addition logic 665 generates values ​​corresponding to 2... mThe value is -1 (that is, based on the width of the lower portion 650). Recovery logic 670 evaluates the current value of the lower portion 650 and determines whether the current value is an extra value. When recovery logic 670 determines that the current value is an extra value, it generates a recovery value for the lower portion 650 to use in the next clock cycle. In embodiments of the disclosed technology, the recovery value corresponds to a value in the sequence generated by the linear function that generally follows the value detected by addition logic 665. In other words, addition logic 665 and recovery logic 670 operate in combination to introduce an extra value into the sequence, and then recover the sequence from the position where the extra value was introduced. Because the resulting sequence of values ​​is deterministic, addition logic 665 and recovery logic 670 can be configured to add an extra value to any position in the sequence. For example, the linear function sequence of the 3-bit lower portion 650 can be a repeating sequence (1, 0, 2, 6, 5, 3, 4). Add logic 665 can be configured to add value 7 after detecting value 6, and restore logic 670 can be configured to restore with value 5 after detecting value 6, thereby generating a repeating sequence (1, 0, 2, 6, 7, 5, 3, 4). In embodiments of the disclosed technology, add logic 665 and restore logic 670 are coupled together with additional logic 675 to the data input and / or set / reset the inputs of triggers 655a-655x. Additionally, add logic 665, restore logic 670, and additional logic 675 can drive different values ​​to each trigger (e.g., based on the generated additional or restored value). If add logic 665 and restore logic 670 do not detect an add or restore condition, resulting in no additional or restored value being generated, then the add logic and restore logic may not react, causing triggers 655a-655x to take a value in linear function logic (e.g., the next existing value in the sequence).

[0062] Figure 7 This is a schematic diagram illustrating an embodiment of the lower portion 700 of an LFSR for generating bounded random numbers according to an embodiment of the present technology. Figure 7 As shown, the lower portion 700 of the LFSR is 3 bits wide, which can correspond to the 3 least significant bits of a larger bounded LFSR (4 or more bits). Therefore, the lower portion 700 of the LFSR contains flip-flops 705a-705c (corresponding to bits 0 to 2 respectively). The input of flip-flop 705c is driven by the unmodified output of flip-flop 705b, and the input of flip-flop 705a is driven by the unmodified output of flip-flop 705c. The input of flip-flop 705b is generated from a combination of XOR taps 710 from the outputs of flip-flops 705a and 705c and additional logic 715. Additional logic 715, which performs further operations based on the AddF signal 720 and the ResumeF signal 725 to generate the input of flip-flop 705b, adds the value 7 to the digital sequence of the lower portion 700 of the LFSR. Figure 7As shown, the evaluation triggers 705a-705c are assessed to determine if they have a value 3'b110 (corresponding to value 6) to generate the AddF signal 720. Figure 7 The diagram further illustrates that the ResumeF logic 735 evaluates whether flip-flops 705a-705c have the value 3'b111 (corresponding to the value 7) to generate the ResumeF signal 725. That is, the AddF signal 720 confirms when the value of the lower portion 700 of the LFSR is 6, and through the operation of the AddF signal changing the input of flip-flop 705b, causes the lower portion of the LFSR to have the value 7 in the next cycle. Similarly, the ResumeF signal 725 confirms when the value of the lower portion 700 of the LFSR is 7, and through the operation of the ResumeF signal changing the input of flip-flop 705b, causes the lower portion of the LFSR to have the value 5 in the next clock cycle. Therefore, due to the additional logic 715, a partial sequence of the lower portion 700 of the LFSR is (6, 7, 5). In embodiments of the disclosed art, the lower portion 700 of the LFSR may have a repeating sequence (1, 0, 2, 6, 7, 5, 3, 4).

[0063] Figure 8 This is a block diagram of a system 800 using bounded random numbers generated by an LFSR 805 according to an embodiment of the present technology. As described herein, system 800 provides system output 810 after an input indication 815 (at an input terminal) requiring a bounded random number. In embodiments of the present technology, system 800 is configured to provide system output 810 less than a threshold 820. For example, in embodiments of the present technology, system output 810 is used as a random address in a system (not shown) for mitigating and / or detecting row hammering effects, and threshold 820 represents the maximum permissible address range for the row hammering mitigation / detection system. In embodiments of the present technology, LFSR 805 is a bounded LFSR, as described herein.

[0064] To provide system output 810, LFSR 805 generates a random number 825 based on the presence of input indication 815 (e.g., a pulse). In embodiments of this technology, LFSR 805 operates on a clock signal (not shown) different from the input indication 815 and is partially enabled by the input indication. It should be understood that other techniques can be used to operate LFSR 805 on a clock signal and enable the LFSR based on a different signal (e.g., based on input indication 815) (e.g., an enable state change).

[0065] A digital comparator 830 compares a random number 825 generated by LFSR 805 with a threshold 820. If, based on determination logic 835, the random number 825 is less than the threshold 820, then the random number 825 is provided as system output 810. For example, system output 810 may contain the random number 825 and a valid signal (not shown). However, if the random number 825 is not less than the threshold 820, then determination logic 835 generates a pulse signal 840. Pulse signal 840, along with input indication 815 (e.g., using a logical OR operation), provides an enable signal 845 to LFSR 805. In other words, LFSR 805 is enabled to generate a new random number 825 after input indication 815 (e.g., from circuitry requesting a new bounded random number) and continues to be enabled via pulse signal 840 until a qualified bounded random number is generated and provided as system output 810. As described herein, a bounded LFSR can be configured to generate random numbers within certain limits, and thus can advantageously provide satisfactory (e.g., within limits) random numbers within a small number of bounded LFSR clock cycles. That is, for example, LFSR 805 can provide system output 810 before the next input indication 815 arrives.

[0066] It should be noted that the methods described above depict possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more embodiments from the described methods can be combined.

[0067] Although the memory modules and devices have been described and illustrated with respect to DRAM devices in the above exemplary embodiments, embodiments of the present technology can be applied to other memory technologies, including SRAM, SDRAM, NAND and / or NOR flash, phase-change memory (PCM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), etc. Furthermore, although the memory modules have been shown and described as dual in-line memory modules (DIMMs) with nine memory devices, embodiments of this disclosure may include more or fewer memory devices, and / or involve other memory modules or package formats (e.g., single in-line memory modules (SIMMs), small DIMMs (SODIMMs), single in-line pin packages (SIPPs), custom memory packages, etc.).

[0068] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some figures may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, wherein the buses may have various bit widths.

[0069] The devices containing memory devices discussed herein can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or substrate subregions can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

[0070] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations.

[0071] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items followed by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0072] As used herein (included in the claims), n and m, used to characterize the size of the LFSR (e.g., the size of the LFSR output, the number of flip-flops forming the LFSR, and / or the range of values ​​produced by the LFSR), refer to positive integers (e.g., 1, 2, 3, etc.). Additionally, n may be greater than m, such that nm (used to characterize the size of the LFSR or a portion of the LFSR) is a positive integer. As also used herein (included in the claims), k refers to a non-negative integer or a natural number (e.g., 0, 1, 2, 3, etc.).

[0073] As used herein (including in the claims), "least significant bit" is the bit position in a binary integer that gives the unit value; that is, the bit position that determines whether a number is even or odd. "Least significant bit" refers to the set of bits that are closest to and contain the least significant bit. As also used herein, "most significant bit" is the bit position in a binary integer that has the maximum value. "Most significant bit" refers to the set of bits that are closest to and contain the most significant bit.

[0074] As will be understood from the foregoing, specific embodiments of the invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the invention. Rather, numerous specific details are set forth in the foregoing description to provide a thorough and illustrative description of embodiments of the present technology. However, those skilled in the art will recognize that this disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations typically associated with memory systems and devices have not been shown or described in detail so as not to obscure other aspects of the present technology. Generally, it should be understood that various other devices, systems, and methods besides those specific embodiments disclosed herein are within the scope of the present technology.

Claims

1. An n-bit linear feedback shift register, comprising: A lower partial linear feedback shift register includes m flip-flops coupled to a clock signal. The lower partial linear feedback shift register is configured to update the next clock cycle state of the m flip-flops based on a lower partial linear function of the current clock cycle state of the m flip-flops to generate m least significant bits when the clock signal transitions from a first level to a second level. An upper-part linear feedback shift register includes nm flip-flops coupled to the clock signal. The upper-part linear feedback shift register is configured to update the next clock cycle state of the nm flip-flops based on an upper-part linear function of the current clock cycle state of the nm flip-flops to generate nm most significant bits when transitioning from a first level to a second level of the clock signal. The upper portion of the linear feedback shift register further includes a skip circuit system configured to cause the next clock cycle state of the nm flip-flops to skip multiple k states generated by the upper portion linear function. Each state corresponds to a value, wherein the skipped k states correspond to k maximum values ​​generated by the upper partial linear function, and wherein the skip circuitry is further configured to update the next clock cycle state of the nm flip-flops with a jump value in the value sequence generated by the upper partial linear feedback shift register based on the upper partial linear function, wherein the jump value is a value less than the k maximum values; and The output of the n-bit linear feedback shift register comprises n bits, which are obtained by combining the m least significant bits and the nm most significant bits, numbered from least significant bit to most significant bit. The nm most significant bits of the output of the n-bit linear feedback shift register are based on the current clock cycle state of the nm flip-flops of the upper partial linear feedback shift register, and the m least significant bits of the output of the n-bit linear feedback shift register are based on the current clock cycle state of the m flip-flops of the lower partial linear feedback shift register.

2. The n-bit linear feedback shift register of claim 1, wherein the next clock cycle state of updating the nm flip-flops of the upper partial linear feedback shift register does not depend on the current clock cycle state of the m flip-flops of the lower partial linear feedback shift register.

3. The n-bit linear feedback shift register of claim 1, wherein the next clock cycle state of updating the m flip-flops of the lower partial linear feedback shift register does not depend on the current clock cycle state of the nm flip-flops of the upper partial linear feedback shift register.

4. The n-bit linear feedback shift register according to claim 1, wherein the m flip-flops of the lower portion linear feedback shift register repeatedly pass through 2 based on the lower portion linear function. m There are several states.

5. The n-bit linear feedback shift register according to claim 4, wherein the 2 m Each state corresponds to a value from 0 to 2. m -1.

6. The n-bit linear feedback shift register of claim 4, wherein the lower portion of the linear feedback shift register further comprises a configuration such that the next clock cycle state of the m flip-flops corresponds to the value 2. m Adding a circuit system to the -1 state.

7. The n-bit linear feedback shift register according to claim 1, wherein the nm flip-flops of the upper portion of the linear feedback shift register are repeatedly processed by the upper portion linear function. n-m -1 state.

8. The n-bit linear feedback shift register according to claim 7, wherein the 2 n-m -1 states correspond to values ​​0 to 2. n-m -2.

9. The n-bit linear feedback shift register of claim 1, wherein the nm flip-flops of the upper portion of the linear feedback shift register are repeatedly passed through 2 based on the upper portion linear function and the skip circuit system. n-m -1-k states.

10. The n-bit linear feedback shift register according to claim 9, wherein the 2 n-m -1-k states correspond to values ​​from 0 to 2. n-m -2-k.

11. The n-bit linear feedback shift register of claim 1, wherein n, m, and k are configured such that 2 n-m -1-k and 2 m There is no common denominator between them.

12. The n-bit linear feedback shift register of claim 1, wherein the upper portion linear function is partially implemented by an XOR gate coupled to the outputs of the first and second flip-flops and the input of the third flip-flop, wherein the first, second, and third flip-flops are among the nm flip-flops of the upper portion linear feedback shift register.

13. The n-bit linear feedback shift register of claim 1, wherein the lower partial linear function is partially implemented by an XOR gate coupled to the outputs of the first and second flip-flops and the input of the third flip-flop, wherein the first, second, and third flip-flops are among the m flip-flops of the lower partial linear feedback shift register.

14. The n-bit linear feedback shift register according to claim 1, wherein the lower part linear function and the upper part linear function are different linear functions.

15. A method for generating n-bit bounded pseudo-random numbers, comprising: At the first linear feedback shift register, a first linear function is used to generate a register with m bits and a value between 0 and 2. m A first pseudo-random number of values ​​between -1 and n, where m is less than n, and wherein the first linear feedback shift register generates the first pseudo-random number when transitioning from a first level of the clock signal to a second level of the clock signal; At the second linear feedback shift register, a number of nm bits are generated according to the second linear function, and the bits are in the range of 0 and 2. n-m A second pseudo-random number with a value between -2, wherein the second linear feedback shift register generates the second pseudo-random number when transitioning from the first level of the clock signal to the second level of the clock signal; The second linear feedback shift register further includes a skip circuit system configured to cause the next clock cycle state of the second linear feedback shift register to skip multiple k states generated by the second linear function, and Each state corresponds to a value, wherein the skipped k states correspond to the k maximum values ​​generated by the second linear function, and wherein the skip circuit system is further configured to update the next clock cycle state of the second linear feedback shift register to a jump value in the value sequence generated by the second linear feedback shift register according to the second linear function, wherein the jump value is a value less than the k maximum values; as well as The first pseudo-random number and the second pseudo-random number are combined to generate the n-bit bounded pseudo-random number, which includes n bits sorted from least significant bit to most significant bit. The first pseudo-random number corresponds to the m least significant bits of the n-bit bounded pseudo-random number, and the second pseudo-random number corresponds to the nm most significant bits of the n-bit bounded pseudo-random number.

16. The method of claim 15, wherein generating the second pseudo-random number comprises excluding k numbers, each of the k numbers having a value between 0 and 2. n-m Values ​​between -2 and 2.

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