Shift register, display panel and display driving method thereof

Abstract

The present application discloses a shift register, a display panel and a display driving method thereof, wherein the shift register comprises: an input module, the input module is used to output a first control signal based on an input signal; a pull-down control module, the pull-down control module is used to control the potential of a first node based on a first clock signal, a high-level signal, a low-level signal and a first control signal; a pull-up control module, the pull-up control module is used to control the potential of a second node based on a first clock signal, a second clock signal, a high-level signal and a first control signal; a holding module, the holding module is used to pull down the potential of the first node based on an input signal, a first clock signal, a second clock signal and a low-level signal; a pull-down output module, the pull-down output module controls the output end of the shift register to output a low-level signal based on the potential of the first node; and a pull-up output module, the pull-up output module controls the output end of the shift register to output a high-level signal based on the potential of the second node.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and more specifically, to a shift register, a display panel and a display driving method thereof. Background Art

[0002] With the continuous advancement of science and technology, more and more electronic devices with display functions are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable and important tool for people today.

[0003] The display panel is the main component of electronic devices to realize the display function, among which the OLED display panel is one of the current mainstream display panels. In the OLED display panel, the sub-pixels are driven by the pixel circuit to display the image, and the pixel circuit needs to be scanned and controlled by the shift register and provide the light control signal.

[0004] The existing shift register has an output signal tailing problem, thereby affecting the image display quality of the display panel. Summary of the invention

[0005] In view of this, the present application provides a shift register, a display panel and a display driving method thereof, and the scheme is as follows:

[0006] A shift register, comprising:

[0007] An input module, the input module is used to output a first control signal based on an input signal;

[0008] A pull-down control module, the pull-down control module is used to control the potential of the first node based on the first clock signal, the high level signal, the low level signal, and the first control signal;

[0009] A pull-up control module, the pull-up control module is used to control the potential of the second node based on the first clock signal, the second clock signal, the high level signal, and the first control signal;

[0010] A holding module, the holding module is used to pull down the potential of the first node based on the input signal, the first clock signal, the second clock signal, and the low-level signal;

[0011] A pull-down output module, which controls the output end of the shift register to output a low level signal based on the potential of the first node;

[0012] The pull-up output module controls the output end of the shift register to output a high level signal based on the potential of the second node.

[0013] The present application also provides a display panel, comprising:

[0014] A display array including sub-pixels for image display;

[0015] A pixel circuit connected to the sub-pixel, used to generate a driving current based on the scanning signal to control the sub-pixel to emit light and display;

[0016] A shift register connected to the pixel circuit, used to provide a scanning signal for the pixel circuit;

[0017] The shift register is the above-mentioned shift register, and the output signal of the shift register is used as the scanning signal.

[0018] The present application also provides a display driving method of a display panel, wherein the display panel includes a sub-pixel and a pixel circuit connected thereto, and the display driving method includes:

[0019] The scanning signal is outputted through the shift register; wherein the shift register comprises: an input module, which is used to output a first control signal based on an input signal; a pull-down control module, which is used to control the potential of the first node based on a first clock signal, a high-level signal, a low-level signal, and a first control signal; a pull-up control module, which is used to control the potential of the second node based on a first clock signal, a second clock signal, a high-level signal, and a first control signal; a holding module, which is used to pull down the potential of the first node based on the input signal, the first clock signal, the second clock signal, and the low-level signal; a pull-down output module, which is used to control the output end of the shift register to output a low-level signal based on the potential of the first node; and a pull-up output module, which is used to control the output end of the shift register to output a high-level signal based on the potential of the second node;

[0020] Based on the scan signal, the pixel circuit is controlled to generate a driving current to control the sub-pixel to emit light for display.

[0021] In the shift register, display panel and display driving method provided by the technical solution of the present application, a holding module is integrated in the shift register. The holding module can lower the potential of the first node based on the input signal, the first clock signal, the second clock signal and the low-level signal, so that when the output signal of the shift register is a low-level signal, the stability of the low-level signal output can be maintained. Moreover, when the high-level signal jumps to the low-level signal, the holding module can avoid the capacitor from being directly connected to the first node, so that the output signal jumps quickly from the high-level signal to the low-level signal, thereby solving the output signal tailing problem and thus solving the display problem caused by the tailing problem of the shift register output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0023] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0024] Figure 1 is a schematic diagram of the structure of a pixel circuit in a display panel;

[0025] Figure 2 A circuit diagram of a conventional shift register;

[0026] Figure 3 for Figure 2 The output signal timing diagram of the shift register shown;

[0027] Figure 4 A circuit module diagram of a shift register provided in an embodiment of the present application;

[0028] Figure 5 A circuit diagram of a shift register provided in an embodiment of the present application;

[0029] Figure 6 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0030] Figure 7 A schematic diagram of the connection relationship between a shift register and a pixel circuit in a first scanning circuit provided in an embodiment of the present application;

[0031] Figure 8 A schematic diagram of the connection relationship between a shift register and an image circuit in another first scanning circuit provided in an embodiment of the present application;

[0032] Fig. 9 A schematic diagram of the connection relationship between a scanning unit and a pixel circuit in a second scanning circuit provided in an embodiment of the present application;

[0033] Fig.10 A schematic diagram of a flow chart of a display panel display driving method provided in an embodiment of the present application;

[0034] Fig.11 A signal timing diagram of a shift register provided in an embodiment of the present application;

[0035] Fig.12 This is a timing diagram of simulation signals in the shift register according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0037] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0038] refer to Figure 1 As shown, Figure 1 The schematic diagram of the structure of a pixel circuit in a display panel is a OLED display panel, and the sub-pixels in the display panel are OLEDs. The sub-pixels are controlled to emit light and display through the pixel circuit. The pixel circuit diagram is a 7T1C pixel circuit, including 7 transistors and 1 storage capacitor Cst. Among them, the 7 transistors are the first transistor M1 to the seventh transistor M7 in sequence.

[0039] The gate of the first transistor M1 is input with the light-emitting control signal E1, and the first electrode of the first transistor M1 is connected to the first power supply voltage PVDD. The gate of the second transistor M2 is input with the control signal SP, and the first electrode of the second transistor M2 is connected to the data voltage DATA. The second electrode of the second transistor M2, the second electrode of the first transistor M1, and the first electrode of the third transistor M3 are all connected to the node D2. The gate of the third transistor M3 is connected to the node D1, and the second electrode of the third transistor M3 is connected to the node D3. The gate of the fourth transistor M4 is input with the first scanning signal S1, the first electrode of the fourth transistor M4 is connected to the reference voltage VREF, and the second electrode of the fourth transistor M4 is connected to the node D1. The gate of the fifth transistor M5 is connected with the second scanning signal S2, the first electrode of the fifth transistor M5 is connected to the node D1, and the second electrode of the fifth transistor M5 is connected to the node D3. The gate of the sixth transistor M6 is connected with the light-emitting control signal E1, the first electrode of the sixth transistor M6 is connected to the node D3, and the second electrode of the sixth transistor M5, the second electrode of the seventh transistor M7, and the anode of the OLED are all connected to the node D4. The gate of the seventh transistor M7 is connected to the control signal SP, and the first electrode of the seventh transistor M7 is connected to the reference voltage VREF. The storage capacitor Cst is connected between the node D1 and the first electrode of the first transistor M1. The cathode of the OLED is connected to the second power supply voltage PVEE. The first power supply voltage PVDD and the second power supply voltage PVEE are both DC voltages, and the second power supply voltage PVEE is less than the first power supply voltage PVDD.

[0040] The fourth transistor M4 and the fifth transistor M5 are IGZO (Indium Gallium Zinc Oxide) transistors, which are turned on when the level is high and turned off when the level is low. The other transistors are PMOS, which are turned on when the level is low and turned off when the level is high.

[0041] The third transistor M3 is a driving transistor, the fourth transistor M4 is a gate reset transistor of the driving transistor and is used for resetting the voltage of the node D1, and the fifth transistor M5 is a compensation transistor and is used for performing voltage compensation on the driving transistor.

[0042] It should be noted that in the embodiment of the present application, the pixel circuit is not limited to Figure 1 The 7T1C circuit shown may also be a 6T1C or 8T1C circuit, and may be any pixel circuit including a driving transistor, a gate reset transistor of the driving transistor, and a compensation transistor of the driving transistor.

[0043] The pixel circuit needs to provide a scanning signal through a shift register.

[0044] refer to Figure 2 As shown, Figure 2The circuit diagram of a conventional shift register includes: switch tubes T1 to T10, capacitors C1 to C3. Each switch tube is a PMOS. The second electrode of the switch tube T1 and the first electrode of the switch tube T2 are connected to the output terminal OUT of the shift register. Figure 2 The output signal of the shift register shown in FIG. Figure 3 The output signal tailing problem is shown.

[0045] refer to Figure 3 As shown, Figure 3 for Figure 2 The output signal timing diagram of the shift register shown in the figure is: Figure 3 The timing diagram of the output signals OUTi-1 / OUTi / OUTi+1 of the three-stage shift register is shown in FIG. Figure 3 It can be seen that the output signal of the shift register cannot directly jump from a high-level signal to a low-level signal during the switching process from a high-level signal to a low-level signal, but needs to go through a step stage between the high-level signal and the low-level signal. After verifying the reliability of the circuit performance, the tail height is different during the step process according to the different threshold voltages Vth of the switch tube T2.

[0046] The inventors have found that the key to the high-level signal being unable to directly jump to a low-level signal is that the capacitor C1 and the node N1 are directly connected. Due to the influence of the capacitor C1, during the switching process from the high-level signal to the low-level signal, the coupling effect between the first pole of the switch tube T2 and its gate is very small, and the potential of the node N1 cannot be effectively lowered, resulting in the output signal tailing problem.

[0047] In order to solve this problem, in an embodiment of the present application, a holding module is integrated in the shift register. The holding module can lower the potential of the first node based on the input signal, the first clock signal, the second clock signal, and the low-level signal. Therefore, when the output signal of the shift register is a low-level signal, the stability of the low-level signal output can be maintained. Moreover, when the high-level signal jumps to the low-level signal, the holding module can avoid the capacitor from being directly connected to the first node, so that the output signal jumps quickly from the high-level signal to the low-level signal, thereby solving the output signal tailing problem and thus solving the display problem caused by the tailing problem of the shift register output signal.

[0048] refer to Figure 4 As shown, Figure 4 A circuit module diagram of a shift register provided in an embodiment of the present application includes:

[0049] An input module 11, the input module 11 is used to output a first control signal based on an input signal IN;

[0050] A pull-down control module 12, the pull-down control module is used to control the potential of the first node N1 based on the first clock signal XCK, the high level signal VGH, the low level signal VGL, and the first control signal;

[0051] A pull-up control module 13, the pull-up control module 13 is used to control the potential of the second node N2 based on the first clock signal XCK, the second clock signal CK, the high level signal VGH, and the first control signal;

[0052] A holding module 14, the holding module 14 is used to pull down the potential of the first node N1 based on the input signal IN, the first clock signal XCK, the second clock signal CK, and the low level signal VGL;

[0053] A pull-down output module 15, which controls the output terminal OUT of the shift register to output a low level signal based on the potential N1 of the first node;

[0054] The pull-up output module 16 controls the output terminal OUT of the shift register to output a high level signal based on the potential of the second node N2.

[0055] Figure 4 The shift register shown is integrated with a holding module 14, and the holding module 14 can lower the potential of the first node N1 based on the input signal IN, the first clock signal XCK, the second clock signal CK, and the low-level signal VGL, so that when the output signal of the shift register is the low-level signal VGL, the stability of the output of the low-level signal VGL can be maintained, and when the high-level signal VGH jumps to the low-level signal VGL, the holding module 14 can avoid the capacitor from being directly connected to the first node N1, so that the output signal quickly jumps from the high-level signal VGH to the low-level signal VGL, thereby solving the output signal tailing problem, thereby solving the display problem caused by the tailing problem of the shift register output signal.

[0056] like Figure 4 As shown, the pull-down control module 12 is connected between the output end of the input module 11 and the first node N1; the pull-up control module 13 is connected between the output end of the input module 11 and the second node N2; the pull-up control module 13 is connected to the pull-down control module 12; and the holding module 14 is connected to the first node N1.

[0057] In an embodiment of the present application, the holding module 14 is used to control the potential of the third node based on the input signal IN, the first clock signal XCK, the second clock signal CK and the low-level signal VGL; wherein, when the output signal jumps from the high-level signal VGH to the low-level signal VGL, the potential of the first node N1 is pulled down through the coupling between the output terminal OUT of the shift register and the first node N1, so that the output terminal OUT of the shift register outputs the low-level signal VGL; after the output terminal OUT of the shift register outputs the low-level signal VGL, the potential of the third node is coupled through the first capacitor to pull down the potential of the third node, so as to pull down the potential of the first node N1 through the potential of the third node N3, thereby maintaining the output of the low-level signal at the output terminal OUT of the shift register.

[0058] A switch element is connected between the first capacitor and the first node N1, so that the output signal quickly jumps from the high-level signal VGH to the low-level signal VGL, thereby solving the output signal tailing problem. The switch element connected between the first capacitor and the first node N1 can be as follows: Figure 5 A diode-connected transistor (i.e., the first switch tube T12) is shown, so that relative to Figure 2 In the circuit structure shown, the first node N1 is no longer directly coupled to the first capacitor C1. The first capacitor C1 is connected to the first clock signal XCK through a switch element to play a coupling role, so that the output signal of the shift register quickly jumps from the high-level signal VGH to the low-level signal VGL, thereby achieving a tail-free output of the output signal.

[0059] The holding module 14 includes a first capacitor C1 and a first switch tube T12, the first capacitor C1 is connected to the third node N3, and the first switch tube T12 is connected between the first node N1 and the third node N3. In this way, the first capacitor C1 and the first node N1 are isolated by the first switch tube T12, and when the output signal of the shift register is converted from the high-level signal VGH to the low-level signal VGL, the influence of the first capacitor C1 on the potential of the first node N1 is reduced, so that the output signal of the shift register can be quickly changed from the high-level signal VGH to the low-level signal VGL based on the coupling between the output terminal OUT of the shift register and the first node N1, thereby solving the problem of output signal tailing.

[0060] refer to Figure 5 As shown, Figure 5 A circuit diagram of a shift register provided in an embodiment of the present application, such as Figure 5 As shown, in the shift register provided in the embodiment of the present application, the holding module 14 includes:

[0061] A first switch tube T12, wherein the gate and the first electrode of the first switch tube T12 are both connected to the third node N3, and the second electrode of the first switch tube T12 is connected to the first node N1;

[0062] A second switch tube T11, wherein a gate of the second switch tube T11 is used to input a second clock signal CK, and a first electrode of the second switch tube T11 is used to input an input signal IN;

[0063] A third switch tube TC, a gate of the third switch tube TC is used to input a low level signal VGL, a first electrode of the third switch tube is connected to a second electrode of the second switch tube T11, and a second electrode of the third switch tube TC is connected to a third node N3;

[0064] One plate of the first capacitor C1 is used to input the first clock signal XCK, and the other plate is connected to the third node N3.

[0065] Based on Figure 5 The holding module 14 shown, when the output signal of the shift register jumps from the high level signal VGH to the low level signal VGL, pulls down the potential of the first node N1 through the coupling between the output terminal OUT of the shift register and the first node N1, so that the output terminal OUT of the shift register outputs the low level signal VGL. Moreover, at this time, since the first switch tube T12 is used to isolate the first capacitor C1 and the first node N1, the influence of the first capacitor C1 on the potential of the first node N1 is effectively reduced, so that the output signal of the shift register can be quickly jumped from the high level signal VGH to the low level signal VGL based on the coupling between the output terminal OUT of the shift register and the first node N1, and the problem of output signal tailing is solved. In addition, after the output terminal OUT of the shift register outputs the low level signal VGL, the potential of the third node N3 is coupled through the first capacitor C1 to pull down the potential of the third node N3, so as to pull down the potential of the first node N1 through the potential of the third node N3, and maintain the output terminal OUT of the shift register outputs a low level signal.

[0066] The gate of the first switch tube T12 is connected to its own first electrode and can be used as a diode. When the output signal changes from a high-level signal VGH to a low-level signal VGL, the first switch tube T12 maintains the low-level stability of the first node N1. In other embodiments, a diode can be used instead of the first switch T12.

[0067] like Figure 5 As shown, the pull-down control module 12 includes:

[0068] A fourth switch tube T7, wherein a gate of the fourth switch tube T7 is connected to a fourth node N4, and a first electrode of the fourth switch tube T7 is used to input a high level signal VGH;

[0069] A fifth switch tube T8, the gate of the fifth switch tube T8 is used to input the first clock signal XCK, the first electrode of the fifth switch tube T8 is connected to the second electrode of the fourth switch tube T7, and the second electrode of the fifth switch tube T8 is connected to the fifth node N5; the input module 11 outputs the first control signal through the fifth node N5;

[0070] A sixth switch tube T10, wherein a gate of the sixth switch tube T10 is used to input a second clock signal CK, a first electrode of the sixth switch tube T10 is connected to a fourth node N4, and a second electrode of the sixth switch tube T10 is used to input a low level signal VGL;

[0071] The seventh switch tube TB, the gate of the seventh switch tube TB is used to input the low level signal VGL, the first electrode of the seventh switch tube TB is connected to the fifth node N5, and the second electrode of the seventh switch tube TB is connected to the first node N1.

[0072] The pull-down control module 12 can realize the pull-down control of the output signal through the circuit structure formed by connecting the fourth switch tube T7 to the seventh switch tube TB, so as to control the pull-down output module 15 to output the low level signal VGL in a timing sequence.

[0073] like Figure 5 As shown, the pull-up control module 13 includes:

[0074] an eighth switch tube T6, wherein a first electrode of the eighth switch tube T6 is connected to the fourth node N4, a second electrode of the eighth switch tube T6 is used to input the second clock signal CK, and a gate of the eighth switch tube T6 is connected to the fifth node N5;

[0075] A ninth switch tube TA, a gate of the ninth switch tube TA is used to input a low level signal VGL, and a first electrode of the ninth switch tube TA is connected to a fourth node N4;

[0076] a tenth switch tube T4, wherein the gate of the tenth switch tube T4 is used to input the first clock signal XCK, the first electrode of the tenth switch tube T4 is connected to the second electrode of the ninth switch tube TA through the second capacitor C2, and the second electrode of the tenth switch tube T4 is connected to the second node N2;

[0077] an eleventh switch tube T5, wherein a gate of the eleventh switch tube T5 is connected to a second electrode of the ninth switch tube TA, and a gate of the eleventh switch tube T5 is connected to a first electrode of the eleventh switch tube T5 via a second capacitor C2, a first electrode of the eleventh switch tube T5 is connected to a first electrode of the tenth switch tube T4, and a second electrode of the eleventh switch tube T5 is used to input a first clock signal XCK;

[0078] The twelfth switch tube T3 has a gate connected to the fifth node N5 , a first electrode of the twelfth switch tube T3 is used to input the high level signal VGH, and a second electrode of the twelfth switch tube T3 is connected to the second node N2 .

[0079] The pull-up control module 13 can realize the pull-up control of the output signal through the circuit structure formed by connecting the eighth switch tube T6 to the twelfth switch tube T3, so as to control the pull-up output module 16 to output the high level signal VGH in a timing sequence.

[0080] like Figure 5 As shown, the pull-down output module 15 includes: a thirteenth switch tube T2, the gate of the thirteenth switch tube T2 is connected to the first node N1, the first electrode of the thirteenth switch tube T2 is connected to the output end OUT of the shift register, and the second electrode of the thirteenth switch tube T2 is used to input the low-level signal VGL. The pull-down output module 15 can output the low-level signal VGL in a timing sequence under the control of the pull-down control module 12 through a single switch tube, and the circuit structure is simple and the control timing is simple.

[0081] like Figure 5 As shown, the pull-up output module 16 includes:

[0082] A fourteenth switch tube T1, a gate of the fourteenth switch tube T1 is connected to the second node N2, a first electrode of the fourteenth switch tube T1 is used to input a high level signal VGH, and a second electrode of the fourteenth switch tube T1 is connected to an output terminal OUT of the shift register;

[0083] The third capacitor C3 is connected between the gate and the first electrode of the fourteenth switch tube T1.

[0084] The pull-up output module 16 can output the high level signal VGH in a timing sequence under the control of the pull-up control module 13 through the fourteenth switch tube T1 and the third capacitor C3 , and has a simple circuit structure and a simple control timing sequence.

[0085] like Figure 5 As shown, the input module 11 includes: a fifteenth switch tube T9, the gate of the fifteenth switch tube T9 is used to input the second clock signal CK, the first electrode of the fifteenth switch tube T9 is connected to the fifth node N5, the first electrode of the fifteenth switch tube T9 is used to output the first control signal, and the second electrode of the fifteenth switch tube T9 is connected to the holding module 14 and is used to receive the input signal IN. The input module 11 can output the first control signal in a timing sequence based on the second clock signal CK through the fifteenth switch tube T9, and the circuit structure is simple and the control timing sequence is simple.

[0086] In the embodiment of the present application, the input module 11, the pull-down control module 12, the pull-up control module 13, the holding module 14, the pull-down output module 15 and the pull-up output module 16 each include at least one switch tube, and each switch tube is a PMOS. Figure 5 As shown, the first switch tube T12 to the fifteenth switch tube T9 are all PMOS.

[0087] In each circuit module, the circuit structure is not limited to Figure 5 In the manner shown, for example, the pull-down output module 15 may also be provided with other transistors connected in parallel or in series with the thirteenth switch tube T2.

[0088] Relative to Figure 2 In the manner shown, the technical solution of the embodiment of the present application no longer designs a first capacitor C1 directly connected to the first node N1. Because there is no influence of the capacitor directly connected to the first node N1, when the pull-down output module 15 changes from a high-level signal VGH to a low-level signal VGL, the output terminal OUT can be coupled to pull down the first node N1, so that the output signal quickly jumps to a low-level signal VGL. Figure 2 In the manner shown, due to the influence that the first node N1 is directly connected to the first capacitor C1, the shift register output terminal OUT and the first connection node N1 are not sufficient to maintain the potential of the first node N1 very low. In the technical solution of the present application, the first capacitor C1 and the first node N1 are isolated by the first switch tube T12. In the process of the pull-down output module 15 changing from the high-level signal VGH to the low-level signal VGL, the output terminal OUT and the first node N1 can be fully utilized to pull the potential of the first node N1 very low.

[0089] Based on the above embodiment, another embodiment of the present application further provides a display panel, the display panel is as follows Figure 6 shown.

[0090] refer to Figure 6 As shown, Figure 6 The structure diagram of a display panel provided in an embodiment of the present application is shown, and the display panel 20 shown includes:

[0091] A display array including sub-pixels for image display;

[0092] A pixel circuit P connected to the sub-pixel, used to generate a driving current based on a scanning signal to control the sub-pixel to emit light and display;

[0093] The first scanning circuit 21 includes the shift register mentioned above, and the shift register is connected to the pixel circuit P to provide the pixel circuit P with a scanning signal.

[0094] exist Figure 6 The sub-pixel is not shown in the figure. The sub-pixel is an OLED device. The circuit connection structure of the pixel circuit P and the sub-pixel can be referred to. Figure 1 As shown, the embodiments of the present application are not described in detail.

[0095] The display panel 20 includes a display area 201 and a frame area 202 , wherein the frame area 202 at least surrounds a portion of the display area 201 . The sub-pixels and the pixel circuit P are located in the display area 201 , and the first scanning circuit 21 is located in the frame area 202 .

[0096] refer to Figure 7 As shown, Figure 7 The diagram is a schematic diagram of the connection relationship between a shift register and a pixel circuit in a first scanning circuit provided in an embodiment of the present application. The first scanning circuit includes a plurality of cascaded shift registers SN. Sub-pixels are connected to pixel circuits P in a one-to-one correspondence, and the sub-pixels are arranged in an array. The pixel circuits P connected to the sub-pixels have a corresponding array relationship. Figure 7 The illustrated method only shows the pixel circuits P connected to the first four rows of sub-pixels in the same column, which are pixel circuits P1-P4 in sequence, and correspondingly illustrates the first five stages of shift registers SN, which are shift registers SN1-SN5 in sequence.

[0097] In the embodiment of the present application, it is assumed that there are m rows of sub-pixels, where m is a positive integer greater than 1. The first scanning circuit has m stages of shift registers SN, which are the first stage shift register SN1 to the Nth stage shift register SNm.

[0098] The output end of the first stage shift register SN1 is connected to the pixel circuit P1 connected to the first row of sub-pixels, and is used to provide the first scanning signal S1 to the pixel circuit P1 connected to the first row of sub-pixels.

[0099] The output end of the i-th shift register SNi is connected to the pixel circuit Pi connected to the i-th row of sub-pixels, and is used to provide the second scanning signal S2 to the pixel circuit Pi connected to the i-th row of sub-pixels.

[0100] Moreover, the second scanning signal S2 of the pixel circuit P connected to the previous row of sub-pixels is used as the first scanning signal S1 of the pixel circuit P connected to the next row of sub-pixels. The output signal of the previous stage shift register SN is used as the input signal of the next stage shift register SN.

[0101] refer to Figure 8 As shown, Figure 8 A schematic diagram of the connection relationship between a shift register and an image circuit in another first scanning circuit provided in an embodiment of the present application, wherein the first scanning circuit includes a plurality of cascaded shift registers SN, sub-pixels are connected to pixel circuits P in a one-to-one correspondence, the sub-pixels are arranged in an array, and the pixel circuits P connected to the sub-pixels have a corresponding array relationship.

[0102] exist Figure 8In the manner shown, the pixel circuits P connected to each row of sub-pixels are respectively connected to two-stage shift registers, through which the first scanning signal S1 and the second scanning signal S2 are respectively input. When there are m rows of sub-pixels, there are correspondingly 2m-stage shift registers.

[0103] The 2j-1th stage shift register SN2j-1 is connected to the pixel circuits P connected to the jth row of sub-pixels, and is used to provide the first scanning signal S1 to the pixel circuits P connected to the jth row of sub-pixels. j is a positive integer not greater than m.

[0104] The 2j-th stage shift register SN2j is connected to the pixel circuits P connected to the sub-pixels in the j-th row, and is used to provide the second scanning signal S2 for the pixel circuits P connected to the sub-pixels in the j-th row.

[0105] The output signal of the 2j-1th stage shift register SN2j-1 is used as the input signal of the 2j+1th stage shift register SN2j+1. The output signal of the 2jth stage shift register SN2j is used as the input signal of the 2j+2th stage shift register SN2j+2.

[0106] The display panel described in the embodiment of the present application further includes a second scanning circuit for providing a control signal SP to the pixel circuit. The second scanning circuit includes a plurality of cascaded scanning units.

[0107] refer to Fig. 9 As shown, Fig. 9 A schematic diagram of the connection relationship between a scanning unit and a pixel circuit in a second scanning circuit provided by an embodiment of the present application. The second scanning circuit has a plurality of cascaded scanning units ScnaP, and the scanning units are connected to sub-pixel rows in a one-to-one correspondence.

[0108] When there are m rows of sub-pixels, there are correspondingly m levels of scanning units, which are the first level scanning unit 1 to the mth level scanning unit m. The jth level scanning unit ScnaPj is connected to the pixel circuit P connected to the jth row of sub-pixels, and is used to provide a control signal SP for the pixel circuit P connected to the jth row of sub-pixels. The output signal of the previous level scanning unit ScnaP is used as the input signal of the next level scanning unit ScnaP.

[0109] The first scanning circuit 21 of the display panel described in the embodiment of the present application adopts the shift register in the above embodiment, which solves the tailing problem of the shift register output signal when it jumps from the high-level signal VGH to the low-level signal VGL, solves the display problem caused by this, and improves the display quality.

[0110] Based on the above embodiment, another embodiment of the present application further provides a display driving method for a display panel, wherein the display panel includes a sub-pixel and a pixel circuit connected thereto. The display driving method is as follows: Fig.10 shown.

[0111] refer to Fig.10 As shown, Fig.10 A schematic diagram of a flow chart of a display panel display driving method provided in an embodiment of the present application, the display driving method comprising:

[0112] Step S11: Outputting a scanning signal through a shift register.

[0113] Among them, the shift register includes: an input module, which is used to output a first control signal based on an input signal; a pull-down control module is used to control the potential of a first node based on a first clock signal, a high-level signal, a low-level signal, and a first control signal; a pull-up control module is used to control the potential of a second node based on a first clock signal, a second clock signal, a high-level signal, and a first control signal; a holding module is used to pull down the potential of the first node based on the input signal, the first clock signal, the second clock signal, and a low-level signal; a pull-down output module is used to control the output end of the shift register to output a low-level signal based on the potential of the first node; and a pull-up output module is used to control the output end of the shift register to output a high-level signal based on the potential of the second node.

[0114] The circuit structure of the shift register can be described with reference to the above embodiment, and will not be described in detail in the display driving method embodiment.

[0115] Step S12: Based on the scan signal, the pixel circuit is controlled to generate a driving current to control the sub-pixel to emit light for display.

[0116] In the embodiment of the present application, the display driving method is based on the shift register in the above embodiment to provide a scanning signal for the sub-pixel, thereby solving the display problem caused by the tailing problem of the shift register output signal and improving the display quality.

[0117] Optionally, the method of the shift register outputting the scanning signal includes:

[0118] When the output signal changes from a high-level signal to a low-level signal, the potential of the first node is pulled down by coupling the output end of the shift register with the first node, so that the output end of the shift register outputs a low-level signal;

[0119] After the output end of the shift register outputs a low level signal, the third node potential is coupled through the first capacitor to pull down the third node potential, so as to pull down the potential of the first node through the third node potential to maintain the output end of the shift register outputting a low level signal.

[0120] In the embodiment of the present application, a switch element is connected between the first node and the first capacitor. In this way, when the output signal jumps from a high-level signal to a low-level signal, the influence of the first capacitor on the potential of the first node can be avoided, and the coupling effect between the output end of the shift register and the first node can be ensured, so that the low potential of the first node can make the output end quickly jump to a low-level signal. Moreover, after the output end of the shift register outputs a low-level signal, the potential of the third node can be coupled through the first capacitor to lower the potential of the third node, and then further lower the potential of the first node, so as to maintain the output end of the shift register to output a low-level signal, and ensure the stability of the output low-level signal.

[0121] A timing cycle of the input signal includes the 1st to 9th time periods based on the time sequence; the 2nd to 4th time periods are the on time periods of the input signal, and the other time periods are the off time periods of the input signal; the first clock signal and the second clock signal have the same cycle; the first clock signal is turned on in the 2i-1th time period of the input signal and is turned off in the 2ith time period of the input signal; the second clock signal is turned on in the 2ith time period of the input signal and is turned off in the 2i-1th time period of the input signal.

[0122] In the sixth period, the input signal is turned off, the first clock signal is turned off, the second clock signal is turned on, and the output signal of the output end of the shift register starts to decrease from a high-level signal, coupling the first node, pulling down the potential of the first node, so that the output end of the shift register outputs a low-level signal; the shutdown potential of the input signal is written to the third node through the second switch tube and the third switch tube, thereby turning off the first switch tube. Based on the above-mentioned holding module circuit structure, the fast jump of the output signal of the shift register can be achieved in the sixth period.

[0123] The working process of the shift register in the embodiment of the present application is further explained below in conjunction with a specific timing diagram.

[0124] refer to Fig.11 As shown, Fig.11 A signal timing diagram of a shift register provided in an embodiment of the present application, combined with Figure 5 and Fig.11 As shown, since the first node N1 is not directly connected to the first capacitor C1, the thirteenth switch tube T2 can pull down the potential of the first node N1 through the coupling effect of its own first electrode and gate, and at the same time, a holding module 14 is added to maintain the stability of the output signal at the low level signal VGL through the holding module 14. When the low level signal VGL is output, the first capacitor C1 can further pull down the potential of the first node N1 through the first switch tube T12 to maintain the first node N1 continuously at a lower potential, thereby maintaining the stability of the output signal at the low level signal VGL.

[0125] Specifically, within one timing cycle of the input signal IN:

[0126] In the first period, the first clock signal XCK is at a low level, the first capacitor C1 pulls down the third node N3, the first switch tube T12 is turned on, so that the first node N1 is at a low potential, the thirteenth switch tube T2 is turned on, and the low level signal VGL is output.

[0127] In the second period, the second clock signal CK is at a low level, the input signal IN is at a high level, the first switch tube T12 is turned off, and the low level signal VGL is written into the fourth node N4 based on the turned-on sixth switch tube T10, so the fourth node N4 is at a low level. In this period, since the fourteenth switch tube T1 is also turned off, the output signal maintains the low level signal VGL of the previous period.

[0128] In the third period, the first clock signal XCK is at a low level, the potential of the second node N2 is pulled low, the fourteenth switch tube T1 is turned on, and the output terminal OUT outputs a high level signal VGL. At the same time, the fifth switch tube T8 is turned on, and the high level signal VGH is written to the first node N1 through the fourth switch tube T7 and the fifth switch tube T8, so that the first node N1 is at a high level, and the thirteenth switch tube T2 is kept turned off.

[0129] In the fourth period, the first clock signal XCK is at a high level, the tenth switch tube T4 is turned off, the second clock signal CK is at a low level, the fifteenth switch tube T9 is turned on, the high-level input signal IN is written into the first node N1 through the turned-on seventh switch tube TB, and the thirteenth switch tube T2 is kept turned off. The output high-level signal VGH is maintained during this period.

[0130] In the fifth period, the first clock signal XCK is at a low level, the input signal IN is at a low level, and the second clock signal CK is at a high level. The low level cannot be written into the first node N1, and the thirteenth switch T2 is kept off. The high level signal VGH is output during this period.

[0131] In the sixth period, the input signal IN is at a low level, the second clock signal CK is at a low level, the low-level input signal IN is written into the first node N1 through the turned-on fifteenth switch tube T9 and the seventh switch tube TB, and the output terminal OUT starts to change from the high-level signal VGH to the low-level signal VGL. As the output signal potential becomes low, the output terminal OUT will be coupled to the first node N1, making the potential of the first node N1 lower, making the potential of the first node N1 much lower than the low-level signal VGL, making the thirteenth switch tube T2 fully turned on, and the output terminal OUT outputs the low-level signal VGL, realizing the output without tailing. At the same time, the low-level input signal IN passes through the turned-on second switch tube T11 and the third switch tube TC, and writes the low potential into the third node N3. Since the gate of the first switch tube T12 is connected to the first electrode, and the potential of the first node N1 is much lower than the low-level signal VGL, the first switch tube T12 is turned off at this time.

[0132] In the 7th and 9th time periods, the first clock signal XCK changes from a high level to a low level, and the third node N3 is pulled down through the first capacitor C1 coupling, and changes from a low level signal VGL to a level far lower than the low level signal VGL, thereby turning on the first switch tube T12, writing a very low potential into the first node N1, maintaining the thirteenth switch tube T2, and maintaining the stability of the low potential output.

[0133] In the eighth period, the second clock signal CK is at a low level first, and the low level can be written into the left side of the seventh switch tube TB and the third switch tube TC. Writing the low level into the first pole on the left side of the third switch tube TC can prevent the coupling from causing the potential of the third node N3 to jump high and low when the first clock signal XCK switches between high and low, and prevent the leakage potential of the third node N3 from becoming high after a long time. When the second clock signal CK becomes a high level, since the gate of the eighth switch tube T6 is connected to the low level of the first pole on the left side of the seventh switch tube TB, the fourth node N4 is written with the second clock signal CK at a high level, so that the fourth switch tube T7 is turned off.

[0134] In the embodiment of the present application, the high level of each signal can be equal to VGH, and the low level can be equal to VGL. In the above description, the output signal OUT1 of the first stage shift register is taken as an example for explanation, and the output principle of other stages of shift registers is the same, which will not be repeated in the embodiment of the present application.

[0135] refer to Fig.12 As shown, Fig.12 This is a timing diagram of a simulation signal in a shift register according to an embodiment of the present application. Based on simulation, it can be known that the output signal of the shift register has no tailing problem during the high-low level conversion process.

[0136] The various embodiments in this specification are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0137] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same drawings throughout the embodiments of the specification mark the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity.

[0138] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0139] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0140] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A shift register, characterized in that: include: An input module, the input module being configured to output a first control signal based on an input signal; A pull-down control module, the pull-down control module is used to control the potential of the first node based on the first clock signal, the high level signal, the low level signal, and the first control signal; A pull-up control module, the pull-up control module is used to control the potential of the second node based on the first clock signal, the second clock signal, the high level signal, and the first control signal; A holding module, the holding module is used to pull down the potential of the first node based on the input signal, the first clock signal, the second clock signal, and the low-level signal; a pull-down output module, wherein the pull-down output module controls the output end of the shift register to output the low level signal based on the potential of the first node; a pull-up output module, wherein the pull-up output module controls the output end of the shift register to output the high level signal based on the potential of the second node; The holding module is used to control the potential of the third node based on the input signal, the first clock signal, the second clock signal and the low-level signal; wherein, when the output signal jumps from the high-level signal to the low-level signal, the potential of the first node is pulled down by coupling the output end of the shift register with the first node, so that the output end of the shift register outputs the low-level signal; after the output end of the shift register outputs the low-level signal, the potential of the third node is coupled by the first capacitor to pull down the potential of the third node, so as to pull down the potential of the first node through the third node potential, and maintain the output end of the shift register outputting the low-level signal; The holding module includes: a first switch tube, the gate and the first electrode of the first switch tube are both connected to the third node, and the second electrode of the first switch tube is connected to the first node; a second switch tube, the gate of the second switch tube is used to input the second clock signal, and the first electrode of the second switch tube is used to input the input signal; a third switch tube, the gate of the third switch tube is used to input the low-level signal, the first electrode of the third switch tube is connected to the second electrode of the second switch tube, and the second electrode of the third switch tube is connected to the third node; wherein one electrode plate of the first capacitor is used to input the first clock signal, and the other electrode plate is connected to the third node; The input module includes: a fifteenth switch tube, the gate of the fifteenth switch tube is used to input the second clock signal, the first pole of the fifteenth switch tube is used to output the first control signal, and the second pole of the fifteenth switch tube is connected to the holding module and is used to access the input signal.

2. The shift register according to claim 1, characterized in that: The pull-down control module is connected between the output end of the input module and the first node; The pull-up control module is connected between the output end of the input module and the second node; The pull-up control module is connected to the pull-down control module; The maintaining module is connected to the first node.

3. The shift register according to claim 1, wherein: The pull-down control module comprises: a fourth switch tube, wherein a gate of the fourth switch tube is connected to a fourth node, and a first electrode of the fourth switch tube is used to input the high level signal; a fifth switch tube, wherein the gate of the fifth switch tube is used to input the first clock signal, the first electrode of the fifth switch tube is connected to the second electrode of the fourth switch tube, and the second electrode of the fifth switch tube is connected to a fifth node; and the input module outputs the first control signal through the fifth node; a sixth switch tube, wherein a gate of the sixth switch tube is used to input the second clock signal, a first electrode of the sixth switch tube is connected to the fourth node, and a second electrode of the sixth switch tube is used to input the low level signal; A seventh switch tube, wherein the gate of the seventh switch tube is used to input the low level signal, the first electrode of the seventh switch tube is connected to the fifth node, and the second electrode of the seventh switch tube is connected to the first node.

4. The shift register according to claim 1, wherein: The pull-up control module comprises: an eighth switch tube, wherein a first electrode of the eighth switch tube is connected to a fourth node, a second electrode of the eighth switch tube is used to input the second clock signal, and a gate of the eighth switch tube is connected to a fifth node; and the input module outputs the first control signal through the fifth node; a ninth switch tube, wherein a gate of the ninth switch tube is used to input the low level signal, and a first electrode of the ninth switch tube is connected to the fourth node; a tenth switch tube, wherein a gate of the tenth switch tube is used to input the first clock signal, a first electrode of the tenth switch tube is connected to a second electrode of the ninth switch tube via a second capacitor, and a second electrode of the tenth switch tube is connected to the second node; an eleventh switch tube, wherein the gate of the eleventh switch tube is connected to the second electrode of the ninth switch tube, and the gate of the eleventh switch tube is connected to the first electrode thereof through the second capacitor, the first electrode of the eleventh switch tube is connected to the first electrode of the tenth switch tube, and the second electrode of the eleventh switch tube is used to input the first clock signal; A twelfth switch tube, wherein a gate of the twelfth switch tube is connected to the fifth node, a first electrode of the twelfth switch tube is used to input the high level signal, and a second electrode of the twelfth switch tube is connected to the second node.

5. The shift register according to claim 1, characterized in that: The pull-down output module comprises: A thirteenth switch tube, wherein the gate of the thirteenth switch tube is connected to the first node, the first electrode of the thirteenth switch tube is connected to the output end of the shift register, and the second electrode of the thirteenth switch tube is used to input the low level signal.

6. The shift register according to claim 1, characterized in that: The pull-up output module comprises: a fourteenth switch tube, wherein a gate of the fourteenth switch tube is connected to the second node, a first electrode of the fourteenth switch tube is used to input the high level signal, and a second electrode of the fourteenth switch tube is connected to an output end of the shift register; A third capacitor is connected between the gate electrode and the first electrode of the fourteenth switch tube.

7. The shift register according to claim 1, characterized in that: The input module, the pull-down control module, the pull-up control module, the holding module, the pull-down output module and the pull-up output module each include at least one switch tube, and each switch tube is a PMOS.

8. A display panel, characterized in that: include: A display array including sub-pixels for image display; A pixel circuit connected to the sub-pixel, used to generate a driving current based on a scanning signal to control the sub-pixel to perform light-emitting display; The first scanning circuit comprises the shift register as claimed in claim 1, wherein the shift register is connected to the pixel circuit and is used to provide the scanning signal to the pixel circuit.

9. A display driving method for a display panel, wherein the display panel comprises sub-pixels and pixel circuits connected thereto, characterized in that: The display driving method comprises: Outputting a scanning signal through a shift register; wherein the shift register comprises: an input module, used to output a first control signal based on an input signal; a pull-down control module, used to control the potential of a first node based on a first clock signal, a high-level signal, a low-level signal, and the first control signal; a pull-up control module, used to control the potential of a second node based on the first clock signal, a second clock signal, the high-level signal, and the first control signal; a holding module, used to pull down the potential of the first node based on the input signal, the first clock signal, the second clock signal, and the low-level signal; a pull-down output module, used to control the output end of the shift register to output the low-level signal based on the potential of the first node; and a pull-up output module, used to control the output end of the shift register to output the high-level signal based on the potential of the second node; Based on the scanning signal, controlling the pixel circuit to generate a driving current to control the sub-pixel to emit light and display; The method for the shift register to output the scanning signal comprises: when the output signal jumps from the high level signal to the low level signal, by coupling the output end of the shift register with the first node, pulling down the potential of the first node, so that the output end of the shift register outputs the low level signal; after the output end of the shift register outputs the low level signal, by coupling the potential of a third node through a capacitor, pulling down the potential of the third node, so as to pull down the potential of the first node through the potential of the third node, and maintaining the output end of the shift register outputting the low level signal; The holding module includes: a first switch tube, the gate and the first electrode of the first switch tube are both connected to the third node, and the second electrode of the first switch tube is connected to the first node; a second switch tube, the gate of the second switch tube is used to input the second clock signal, and the first electrode of the second switch tube is used to input the input signal; a third switch tube, the gate of the third switch tube is used to input the low-level signal, the first electrode of the third switch tube is connected to the second electrode of the second switch tube, and the second electrode of the third switch tube is connected to the third node; wherein one electrode plate of the first capacitor is used to input the first clock signal, and the other electrode plate is connected to the third node; The input module includes: a fifteenth switch tube, the gate of the fifteenth switch tube is used to input the second clock signal, the first pole of the fifteenth switch tube is used to output the first control signal, and the second pole of the fifteenth switch tube is connected to the holding module and is used to access the input signal.

10. The display driving method according to claim 9, characterized in that: One timing cycle of the input signal includes the first to ninth time periods based on the time sequence; the second to fourth time periods are the on time periods of the input signal, and the other time periods are the off time periods of the input signal; The first clock signal and the second clock signal have the same period; The first clock signal is turned on in the 2i-1 period of the input signal and turned off in the 2i period of the input signal; the second clock signal is turned on in the 2i period of the input signal and turned off in the 2i-1 period of the input signal; 2i is a positive integer not greater than 9.

11. The display driving method according to claim 9, characterized in that: In the sixth period, the input signal is turned off, the first clock signal is turned off, the second clock signal is turned on, and the output signal at the output end of the shift register starts to decrease from the high level signal, coupling the first node, pulling down the potential of the first node, so that the output end of the shift register outputs the low level signal; the shutdown potential of the input signal is written into the third node through the second switch tube and the third switch tube, thereby turning off the first switch tube.

Images