Method for preparing step structure and method for preparing NAND memory

Abstract

The present invention provides a method for fabricating a step structure and a method for fabricating a NAND memory. In the step structure fabrication method, the opening size of a first opening is successively expanded through a trimming process, and an etching process is performed after each expansion of the first opening to gradually define the steps of the step structure. As a result, after N-1 trimming and etching processes, two sets of step structures are simultaneously formed within the first opening, simplifying the step structure fabrication process. Furthermore, each expansion of the first opening is performed bidirectionally from opposite sides, doubling the amount of expansion each time. This helps to increase the process window of the subsequent etching process and reduce the etching difficulty.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a step structure and a method for preparing a NAND memory. Background Art

[0002] NAND memory is a high-capacity memory device formed by stacking multiple layers of data cells. It overcomes the practical scalability limitations of planar memory, increasing storage capacity, reducing the storage cost per data bit, and lowering energy consumption. However, in current NAND memory, as the number of stacked layers increases, the corresponding step structure becomes more complex, and the number of fabrication steps increases significantly, resulting in a more complex process. The fabrication process also faces greater challenges as the number of layers increases. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for preparing a step structure and a method for preparing a NAND memory, so as to solve the problem that the existing step structure preparation process is relatively complicated.

[0004] In order to solve the above technical problems, the present invention provides a method for preparing a step structure, comprising: forming at least one stacking structure stacked from bottom to top on a substrate, each of the stacking structures having N first material layers and N second material layers alternately arranged from bottom to top, and a plurality of adjacent first material layers and second material layers constitute N levels in combination; forming an etch barrier layer on the stacking structure, wherein a first opening is formed in the etch barrier layer, and the first opening exposes the surface of the first level arranged at the top layer in the stacking structure to be etched; performing an etching process to etch the first level through the first opening, and stopping the etching on the surface of the second level; and performing N-1 trimming processes to gradually expand the opening size of the first opening toward opposite sides, and performing an etching process after each expansion of the first opening to etch the currently exposed level to the surface of the next level through the expanded first opening.

[0005] Optionally, the same stacked structure is etched to form two groups of mutually symmetrical step structures in the first opening.

[0006] Optionally, a first stacked structure located below and a second stacked structure located above are formed on the substrate. The method of etching the first stacked structure to form a stepped structure further comprises: before forming the etch stop layer, etching the second stacked structure to form a second opening, wherein the second opening exposes the stepped region of the first stacked structure; and forming the first opening in the etch stop layer within the second opening.

[0007] Optionally, during the process of performing N-1 trimming processes, the first opening is gradually expanded within the second opening; and after performing N-1 trimming processes, the opening size of the first opening is still less than or equal to the opening size of the second opening.

[0008] Optionally, a first stacked structure located below and a second stacked structure located above are formed on the substrate. The method of etching the first stacked structure and the second stacked structure to form a stepped structure within the same step region further comprises: before forming the etch stop layer, etching the second stacked structure to form a second opening, the second opening being located on one side of a centerline of the step region and exposing the first stacked structure; and the first opening in the etch stop layer being formed at the centerline of the step region to simultaneously expose a portion of the first stacked structure located at the second opening and an end of the second stacked structure near the second opening.

[0009] Optionally, the method for forming the first opening in the etch stop layer includes: forming an initial opening in the etch stop layer, aligning the side wall of the initial opening with a side wall of the second opening, and performing a trimming process to extend the side wall of the initial opening toward the end of the second stacking structure to form the first opening.

[0010] Optionally, a core region and a step region are defined on the substrate, wherein the step region is used to electrically lead out each stacked structure within the core region. At least two stacked structures are formed on the substrate, and the step regions provided for the same core region by different stacked structures are arranged at different positions within the core region and are staggered with respect to each other.

[0011] Optionally, when an etching process is performed through the first opening, the etching stops on the second material layer in each level.

[0012] Optionally, the method of etching the currently exposed layer to the surface of the next layer includes: etching the second material layer of the current layer using a first etching process; etching the first material layer of the current layer using a second etching process, and stopping the etching on the second material layer of the next layer.

[0013] The present invention also provides a method for preparing a NAND memory, which specifically includes the method for preparing the step structure as described above.

[0014] In the method for preparing a step structure provided by the present invention, the etch barrier layer is trimmed successively to gradually expand the opening size of the first opening, and an etching process is performed after each expansion of the first opening to gradually define the steps of the step structure. Thus, after N-1 trimming processes and etching processes, two sets of step structures can be formed simultaneously in the first opening, and both sets of step structures rise step by step from the center of the first opening toward the sidewalls of the first opening. Each expansion of the first opening is a bidirectional expansion from two opposite sides, so that the expansion amount of each opening is doubled, which is conducive to increasing the process window of the subsequent etching process, reducing the etching difficulty, and improving the etching accuracy. In addition, the preparation method provided by the present invention can also prepare two step structures simultaneously in the same opening, simplifying the preparation process of the step structure.

[0015] When the method for preparing the step structure provided by the present invention is applied to the preparation of a NAND memory, the preparation process of the NAND memory can be optimized accordingly, thereby improving the production efficiency of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic flow chart of a method for preparing a step structure in one embodiment of the present invention.

[0017] Figure 2-Figure 6 Schematic diagram of the structure of the step structure in the first embodiment of the present invention during its preparation process.

[0018] Figure 7-10 It is a structural schematic diagram of the step structure in the second embodiment of the present invention during its preparation process.

[0019] The accompanying drawings are numerals as follows:

[0020] 100-substrate;

[0021] 200a-first stacking structure;

[0022] 200b-second stacking structure;

[0023] 210-first material layer;

[0024] 220- second material layer;

[0025] 300-spacer dielectric layer;

[0026] 400-channel structure;

[0027] 500-etching stop layer;

[0028] 510-first opening;

[0029] 520-Second opening. DETAILED DESCRIPTION

[0030] The core idea of the present invention is to provide a method for preparing a step structure. Figure 1 As shown, a method for preparing a step structure in an embodiment of the present invention includes the following steps, for example.

[0031] In step S100 , at least one stacked structure stacked from bottom to top is formed on a substrate, wherein each stacked structure has N first material layers and N second material layers alternately arranged from bottom to top, and a plurality of adjacent first material layers and second material layers constitute N levels.

[0032] In step S200 , an etch stop layer is formed on the stack structure, wherein a first opening is formed in the etch stop layer, and the first opening exposes a surface of a first layer arranged at the topmost layer in the stack structure to be etched.

[0033] In step S300 , an etching process is performed to etch the first layer through the first opening, and the etching stops on the surface of the second layer.

[0034] In step S400 , N-1 trimming processes are performed to gradually expand the opening size of the first opening toward opposite sides, and an etching process is performed after each expansion of the first opening to etch the currently exposed layer to the surface of the next layer through the expanded first opening.

[0035] After N-1 times of trimming and etching processes, two groups of step structures can be formed in the first opening at the same time. Both groups of step structures rise step by step from the center of the first opening toward the sidewall of the first opening.

[0036] The following is a further detailed description of the method for preparing the step structure and the method for preparing the NAND memory proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be recognized that relative terms such as "above", "below", "top", "bottom", "above" and "below" shown in the drawings can be used to describe the relationship between various elements. These relative terms are intended to cover different orientations of elements other than the orientations depicted in the drawings. For example, if the device is inverted relative to the view in the drawing, an element described as being "above" another element will now be below that element.

[0037] Example 1

[0038] In step S100, refer to Figure 2As shown, at least one stacked structure is formed on a substrate 100 stacked from bottom to top. Figure 2 Schematically shows a first stacking structure 200a and a second stacking structure 200b stacked up and down.

[0039] Furthermore, the stacked structure has N first material layers 210 and N second material layers 220 alternately arranged from bottom to top, and a plurality of adjacent first material layers 210 and second material layers 220 are combined to form N levels, for example Figure 2 The m-th level Tm is exemplarily illustrated in FIG, wherein N is a positive integer greater than 1, and m is a positive integer less than or equal to N. For forming two or more stacking structures, the number of levels set in each stacking structure can be the same or different.

[0040] In a specific example, the first material layer 210 is, for example, a sacrificial material layer or a conductive material layer, and the second material layer 220 is, for example, an insulating material layer. When the first material layer 210 is a conductive material layer, the conductive material layer can be used to form a word line, and the insulating material layer isolates adjacent word lines; and when the first material layer 210 is a sacrificial material layer, the sacrificial material layer will be removed in a subsequent step and further filled with a conductive material layer to form a word line using the filled conductive material layer. The material of the second material layer 220 may specifically include silicon oxide. When the first material layer 210 is a sacrificial material layer, its material may include silicon, for example; when the first material layer 210 is a conductive material layer, its material may include tungsten, for example. Furthermore, the first material layer 210 and the second material layer 220 may be prepared and formed, for example, using a thermal chemical vapor deposition method, a plasma enhanced vapor deposition method, a physical vapor deposition method, and / or an atomic layer deposition method.

[0041] Optionally, the thickness of each first material layer 210 in the stacked structure may be the same, and the thickness of each second material layer 220 in the stacked structure may also be the same. Alternatively, the thickness of some of the plurality of second material layers 220 is the same, and the thickness of some of the second material layers is different from the thickness of the other second material layers, for example Figure 2 The thickness of the second material layer arranged at the top in the uppermost stack structure (ie, the second stack structure 200 b ) is greater than the thickness of each second material layer thereunder.

[0042] Continue to refer Figure 2 As shown, in this embodiment, a bottom insulating layer is further provided at the bottom of the stack structure, that is, a bottom insulating layer is further provided below the first material layer 210 at the bottom of the stack structure. Figure 2For example, in the first stacked structure 200a, a bottom insulating layer is disposed below the bottommost first material layer 210, and a second material layer 220 is disposed above the topmost first material layer 210. Similarly, in the second stacked structure 200b, a bottom insulating layer is disposed below the bottommost first material layer 210, and a second material layer 220 is disposed above the topmost first material layer 210. That is, the first material layer 210 in the stacked structure is always disposed in the inner layer of the stacked structure.

[0043] In addition, a spacer dielectric layer 300 may be provided below the stacked structure. In this case, the stacked structure at the bottom (eg Figure 2 The first stacking structure 200a) and the substrate 100 are provided with the spacer dielectric layer 300, and the stacking structures (eg Figure 2 The spacer dielectric layer 300 is located between the first stacked structure 200a and the second stacked structure 200b. The spacer dielectric layer 300 can be made of a material having an etching selectivity relative to the first material layer 210 and the second material layer 220. For example, the material of the spacer dielectric layer 300 can include aluminum oxide (AlO). In this embodiment, the thickness of the spacer dielectric layer 300 can be greater than the thickness of the second material layer 220.

[0044] In one example, a core region (eg, Figure 2 The first core area A1 and the second core area A2 shown) and the step area (eg Figure 2 The step area B shown is used to electrically connect the stacked structures within the core area. For example, in a NAND memory, the core area (including the first core area A1 and the second core area A2) can be used to form the memory cell array of the NAND memory. That is, the portion of the stacked structure located within the core area is used to form the memory cell array; and the step area B is used to electrically connect the word lines of the memory cells within the corresponding core area.

[0045] In this embodiment, Figure 2 For example, Figure 2 The portion of the first stacked structure 200a located in the first core area A1 is used to form a first memory cell array, and the word lines of the first memory cell array in the first stacked structure 200a are electrically led out through the step area B on the side of the first core area A1; and Figure 2The portion of the first stacked structure 200a located within the second core area A1 is used to form a second memory cell array, and the word lines of the second memory cell array in the first stacked structure 200a are electrically connected through the step area B on the side of the second core area A2. It should be noted that although the word lines in the first core area A1 and the second core area A2 can be electrically connected within the same step area B, the step structure corresponding to the first core area A1 and the step structure corresponding to the second core area A2 are separated from each other within the step area B. This will be explained in the subsequent steps of preparing the step structure.

[0046] Furthermore, the step areas provided for the same core area by different stacking structures are arranged at different positions of the core area and staggered with each other. In this embodiment, the projections of the step structure formed in the first stacking structure 200a and the step structure of the second stacking structure 200b on the substrate are staggered with each other. Taking NAND memory as an example, the word lines located in the upper and lower different stacking structures in the same core area extend in different directions to the step areas in different positions. Figure 2 In the example shown, the step area (ie, Figure 2 The step area B shown in the figure is in the X2 direction of the first core area A1, while the step area (not shown in the figure) provided by the second stacking structure 200b for the first core area A1 is provided in directions other than the X2 direction of the first core area A1. For example, the step area provided by the second stacking structure 200b for the first core area A1 can be provided in the X1 direction of the first core area A1, or in the Y direction of the first core area A1. In this way, the step areas provided by the first stacking structure 200a and the second stacking structure 200b for the first core area A1 are respectively arranged at different positions in the first core area A1 and are staggered with each other; similarly, the step areas provided by the first stacking structure 200a and the second stacking structure 200b for the second core area A2 can be respectively arranged at different positions in the second core area A2 and are staggered with each other.

[0047] Continue to refer Figure 2 As shown, a plurality of channel structures 400 are further formed in the core region of the stacked structure (including the first core region A1 and the second core region A2). The channel structures 400 penetrate the plurality of stacked structures and are used to form a memory cell string in the core region. In other words, the channel structures 400 penetrate the second stacked structure 200b and the first stacked structure 200a.

[0048] Furthermore, for the stacking structure stacked up and down, the channel structure 400 correspondingly includes a first channel and a second channel connected up and down, the first channel passes through the first stacking structure 200a, the second channel passes through the second stacking structure 200b, and the first channel and the second channel are aligned up and down and connected to each other.

[0049] In this embodiment, after each stacked structure is formed, a channel can be formed within the core region of the current stacked structure, and then an upper stacked structure can be formed above the stacked structure with the channel formed. In this way, when multiple stacked structures are stacked together and have a large thickness, the process limitations caused by the large depth when forming the channel structure at one time can be avoided. In this embodiment, the independent channel preparation for each stacked structure effectively reduces the preparation difficulty of each channel process, which is conducive to improving the quality of the formed channel structure 400.

[0050] by Figure 2 For example, the method for forming the channel structure 400 includes: after forming a first stacking structure 200a on a substrate 100, forming a plurality of channel holes in a core area of the first stacking structure 200a, the channel holes passing through the first stacking structure 200a; then, forming a channel material layer in the channel hole, the channel material layer covering the sidewalls of the channel hole; then, filling the channel hole with an insulating dielectric layer, so as to form a first channel in the core area of the first stacking structure 200a; then, forming a second stacking structure 200b above the first stacking structure 200a, and forming a plurality of channel holes in a core area of the second stacking structure 200b, the plurality of channel holes passing through the second stacking structure 200b and exposing the first channel below one by one; then, filling the channel hole with a channel material layer and an insulating dielectric layer to form a second channel in the second stacking structure 200b, at which time the second channel and the first channel are connected one by one to form the channel structure 400.

[0051] Continue to refer Figure 2 As shown, the channel structure 400 further extends into the substrate 100, such that the bottom of the channel structure 400 is connected to a first conductive line within the substrate. Furthermore, the top of the channel structure 400 is also connected to a second conductive line. Specifically, the first conductive line formed within the substrate 100 is, for example, a common source line. Furthermore, a second conductive line is formed above the topmost stacked structure, and the second conductive line, for example, serves as a bit line.

[0052] In step S200, refer to Figure 3As shown, an etch stop layer 500 is formed on the stack structure, and a first opening 510 is formed in the etch stop layer 500 . The first opening 510 exposes the surface of the first layer arranged at the top layer of the stack structure to be etched.

[0053] The stacked structure to be etched is a stacked structure to be formed into a stepped structure. In this embodiment, the stacked structure to be etched is described by taking the stacked structure located below as an example. For the stacked structure located below, before forming the etch stop layer 500, the process further includes etching the stacked structure above to form a second opening exposing the stacked structure below.

[0054] For example Figure 3 In the embodiment, a step structure needs to be formed within the first stacked structure 200a. Before forming the etch stop layer 500, the process further includes: etching the second stacked structure 200b above the first stacked structure 200a to form a second opening, wherein the second opening exposes the step region B of the first stacked structure 500a. Furthermore, when forming the etch stop layer 500, the first opening 510 in the etch stop layer 500 is formed within the second opening, i.e., the opening size of the first opening 510 is smaller than the opening size of the second opening.

[0055] In an optional solution, a method for preparing the first opening 510 in the etch stop layer 500 includes, for example, firstly, etching the etch stop layer 500 using an etching process to form an initial opening, wherein the bottom of the initial opening exposes the stacked structure to be etched below. At this time, based on the characteristics of the etching process, the sidewalls of the initial opening formed are inclined sidewalls, and the initial opening is wider at the top and narrower at the bottom; then, performing a trimming process (Trimming) to trim the sidewalls of the initial opening, wherein the trimming process trims the sidewalls of the opening into vertical sidewalls, and the opening size of the opening can be further precisely adjusted to a desired size, thereby forming the first opening 510. In a specific example, the etch stop layer 500 is, for example, a photoresist layer.

[0056] In step S300, refer to Figure 4 As shown, an etching process is performed to etch the first level T1 of the stacked structure to be etched through the first opening 510 , and the etching stops on the surface of the second level T2 .

[0057] In this embodiment, etching the first layer T1 of the first stacked structure 200a and stopping at the second layer T2. Specifically, the etching process includes sequentially etching the second material layer 220 and the first material layer 210 within the first layer T1, and stopping at the surface of the second material layer 220 of the second layer T2. In a specific example, a first etching process can be used to etch the second material layer 220, and a second etching process can be used to etch the first material layer 210. This defines the location of the lowest step.

[0058] Step S400, see Figure 5-Figure 6 As shown, N-1 trimming processes are performed to gradually expand the opening size of the first opening 510 toward opposite sides. After each expansion of the first opening, an etching process is performed to etch the currently exposed layer through the expanded first opening to the surface of the next layer. Each trimming process expands the opening size of the first opening 510 on one side by the width of a step.

[0059] Specifically, each time a trimming process is performed, the first opening 510 can further expose the position of the previous step that needs to be defined, and after exposing the previous step, the etching process is used to reveal the previous step relative to the lower step. In addition, the etching consumption of each etching process corresponds to the amount of one level, so that each etching process consumes one level of the exposed part, and then after N-1 trimming processes and etching processes, an N-level step structure corresponding to the N levels in the stacked structure can be formed. In addition, each trimming process causes the first opening 510 to expand to opposite sides, so that the steps of two step structures can be defined at the same time, effectively simplifying the preparation process of the step structure. It should also be noted that each time an etching process is performed to consume a level in the stacked structure, the etching can be stopped on the second material layer 220 in each level, or the etching can be stopped on the first material layer 210 in each level.

[0060] by Figure 5-Figure 6 For example, first refer to Figure 5 As shown, after etching the first level T1, a trimming process is performed to gradually expand the opening size of the first opening 510 toward opposite sides (each side is expanded by the width of a step), thereby simultaneously exposing the second-bottom steps in the two step structures; then an etching process is performed, at this time, the bottom step is consumed by the etching of the second level T2 and remains on the surface of the third level, and the second-bottom step is consumed by the etching of the first level T1 and remains on the surface of the second level T2. By cyclically performing the above steps, two oppositely arranged step structures can be formed in the step area B, for example Figure 6shown.

[0061] After performing N-1 trimming and etching processes, two sets of step structures are formed within the first opening 510. Both sets of step structures ascend in order from the center of the first opening toward the sidewalls of the first opening. In this embodiment, the first opening 510 is located in the center of the second opening, and during the N-1 trimming processes, the first opening continues to expand within the second opening. After performing the N-1 trimming processes, the opening size of the first opening 510 remains less than or equal to the opening size of the second opening, and the two sets of step structures formed within the first opening 510 are symmetrical to each other.

[0062] Example 2

[0063] While the first embodiment illustrates etching the same stacked structure at the bottom to simultaneously prepare symmetrical step structures, this embodiment etches stacked structures at different layers to simultaneously prepare step structures within different stacked structures.

[0064] The following references Figure 7-10 The preparation method in this embodiment is described, wherein Figure 7-10 Schematic diagram of the structure of the step structure in the second embodiment of the present invention during its preparation process.

[0065] like Figure 7 As shown, a first stacked structure 200a is formed below and a second stacked structure 200b is formed above the substrate 100. In subsequent processes, a stepped structure of the first stacked structure 200a corresponding to the first core area A1 is formed in the step area B, and a stepped structure of the second stacked structure 200b corresponding to the second core area A2 is also formed in the step area B. That is, the stacked structure to be etched in this embodiment includes the first stacked structure 200a and the second stacked structure 200b.

[0066] Specifically, the method of etching the first stacked structure 200a and the second stacked structure 200b to form a stepped structure within the same opening includes: before performing step S200, etching the second stacked structure 200b above the first stacked structure 200a to form a second opening 520, wherein the second opening 520 is located on one side of the centerline of the step region B and exposes the first stacked structure 200a. The second opening 520 specifically exposes the region of the first stacked structure 200a where the stepped structure is intended to be formed, and a sidewall of the second opening 520 is aligned with the centerline of the step region B.

[0067] Then execute step S200, for details, refer to Figure 8As shown, an etch stop layer 500 is formed, and a first opening 510 in the etch stop layer 500 is formed at the centerline of the step region B to simultaneously expose the portion of the first stacked structure 200a located at the second opening and the end of the second stacked structure 200b near the second opening. In other words, the first opening 510 is formed in a sidewall region of the second opening 520 and extends to expose the end of the second stacked structure 200b.

[0068] In an optional solution, a method for preparing the first opening 510 in the etch stop layer 500 includes, for example, firstly, etching the etch stop layer 500 using an etching process to form an initial opening, wherein the bottom of the initial opening exposes the first stacked structure 200a below, and the sidewalls of the initial opening are aligned with the sidewalls of the second opening; then, performing a trimming process to trim the sidewalls of the initial opening so that the sidewalls of the initial opening extend toward the end of the second stacked structure to expose the end of the second stacked structure 200b, thereby accurately adjusting the opening size of the initial opening to a desired size, thereby forming the first opening 510. In a specific example, the etch stop layer 500 is, for example, a photoresist layer.

[0069] Then execute step S300, and continue to refer to Figure 8 As shown, an etching process is performed to etch the first level T1 of the stacked structure to be etched through the first opening 510, and the etching stops on the surface of the second level T2. In this embodiment, the first opening 510 simultaneously exposes the portion of the first stacked structure 200a corresponding to the center position of the step region B and the portion of the second stacked structure 200b corresponding to the center position of the step region B. During the etching process, the first level T1 of the first stacked structure 200a is etched and the etching stops on the second level T2, and the first level T1 of the second stacked structure 200b is etched and the etching stops on the second level T2.

[0070] Then execute step S400, for details, refer to Figure 9-10 As shown, N-1 trimming processes are performed to gradually expand the opening size of the first opening 510 toward opposite sides. After each expansion of the first opening, an etching process is performed to etch the currently exposed layer through the expanded first opening to the surface of the next layer. Each trimming process expands the opening size of the first opening 510 on one side by the width of a step.

[0071] Similar to the first embodiment, the etching consumption of each etching process corresponds to the amount of one level, so that each etching process consumes one level for the exposed portion, and then after N-1 trimming processes and etching processes, N-level step structures corresponding to N levels can be formed in each stacking structure. In addition, each trimming process causes the first opening 510 to expand toward opposite sides, thereby simultaneously defining the step structure of the first stacking structure 200a set for the first core area A1, and the step structure of the second stacking structure 200a set for the second core area A2, effectively simplifying the preparation process of the step structure. In addition, each time the etching process is performed to consume one level in the stacking structure, the etching can be stopped on the second material layer 220 in each level, or the etching can be stopped on the first material layer 210 in each level.

[0072] by Figure 9-10 For example, first refer to Figure 9 As shown, through the trimming process, the opening size of the first opening 510 is gradually expanded to the opposite sides (the width of one step is expanded on both sides). At this time, the second bottom step in the two step structures corresponding to the first stacked structure 200a and the second stacked structure 200b can be exposed at the same time; then the etching process is performed. At this time, the bottom step is consumed by the etching of the second level T2 and stays on the surface of the third level, and the second bottom step is consumed by the etching of the first level T1 and stays on the surface of the second level T2. By repeatedly executing step S400, a step structure located below and a step structure located above can be simultaneously formed in the step area B, for example Figure 10 The etching of each layer in the stacked structure may specifically include: etching the second material layer 220 using a first etching process, and etching the first material layer 210 using a second etching process.

[0073] After performing N-1 trimming and etching processes, two sets of step structures are formed in the first opening 510 . Both sets of step structures rise step by step from the center of the first opening 510 toward the sidewall of the first opening.

[0074] In summary, the method for preparing the step structure in the above embodiment is specifically to gradually expand the opening size of the first opening by trimming the etching stop layer one by one, and to perform an etching process after each expansion of the first opening to gradually define the steps of the step structure. Thus, after N-1 trimming processes and etching processes, two groups of step structures can be formed simultaneously in the first opening, and both groups of step structures rise step by step from the center of the first opening toward the sidewall of the first opening. Among them, each expansion of the first opening is a bidirectional expansion from two opposite sides, so that the expansion amount of each opening is doubled, which is conducive to increasing the process window of the subsequent etching process, reducing the etching difficulty, and improving the etching accuracy. In addition, the preparation method provided by the present invention can also prepare two step structures in the same opening at the same time, simplifying the preparation process of the step structure.

[0075] In addition, when at least two stacking structures are stacked on the substrate, the projections of the step structures of different stacking structures on the substrate can be staggered, so that they can be prepared simultaneously in different staggered areas, further simplifying the preparation process of the step structure.

[0076] When the method for preparing the step structure provided in the above embodiment is applied to the preparation of a NAND memory, the preparation process of the NAND memory can be optimized accordingly, thereby improving the production efficiency of the device.

[0077] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0078] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0079] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for preparing a step structure, characterized in that: include: forming at least one stacked structure stacked from bottom to top on a substrate, each stacked structure having N first material layers and N second material layers alternately arranged from bottom to top, wherein a plurality of adjacent first material layers and second material layers constitute N levels; forming an etch stop layer on the stack structure, wherein a first opening is formed in the etch stop layer, and the first opening exposes a surface of a first layer arranged at the topmost layer of the stack structure to be etched; performing an etching process to etch the first level through the first opening and stop the etching on a surface of the second level; as well as, performing N-1 trimming processes to gradually expand the opening size of the first opening toward opposite sides, and performing an etching process after each expansion of the first opening to etch the currently exposed layer to the surface of the next layer through the expanded first opening; In which, a first stacking structure located below and a second stacking structure located above are formed on the substrate; the method of etching the first stacking structure and the second stacking structure to form a step structure in the same step area also includes: before forming the etch stop layer, etching the second stacking structure to form a second opening, the second opening is located on one side of the center line of the step area and exposes the first stacking structure; and the first opening in the etch stop layer is formed at the center line position of the step area to simultaneously expose the portion of the first stacking structure located at the second opening and the end of the second stacking structure close to the second opening.

2. The method for preparing a step structure according to claim 1, wherein: The method for forming the first opening in the etch stop layer includes: An initial opening is formed in the etch stop layer, a sidewall of the initial opening is aligned with a sidewall of the second opening, and a trimming process is performed so that the sidewall of the initial opening is extended toward an end of the second stack structure to form the first opening.

3. The method for preparing a step structure according to claim 1, wherein: A core area and a step area are defined on the substrate, and the step area is used to electrically lead out each stacking structure in the core area; wherein at least two stacking structures are formed on the substrate, and the step areas set for the same core area of different stacking structures are arranged at different positions of the core area and are staggered with each other.

4. The method for preparing a step structure according to claim 1, wherein: When an etching process is performed through the first opening, the etching stops on the second material layer in each level.

5. The method for preparing a step structure according to claim 4, wherein: The method of etching the currently exposed layer to the surface of the next layer includes: etching the second material layer of the current layer using a first etching process; etching the first material layer of the current layer using a second etching process, and stopping the etching on the second material layer of the next layer.

6. A method for preparing a NAND memory, characterized in that: The invention comprises a method for preparing a step structure according to any one of claims 1 to 5.

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