Display device

Abstract

A display device is provided that improves the brightness of the display device. The display device includes: a first transistor having an oxide semiconductor layer, a first gate electrode opposite to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; a first transparent conductive layer that contacts the oxide semiconductor layer in a first contact area that does not overlap with the first gate electrode when viewed from above; and a second transparent conductive layer that is connected to the first transparent conductive layer in a second contact area that overlaps with the first gate electrode when viewed from above, and is disposed in the display area of ​​a pixel.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. In particular, one embodiment of the present invention relates to a display device using transistors having an oxide semiconductor. Background Technology

[0002] Recently, the development of transistors using oxide semiconductors for the channel, replacing amorphous silicon, low-temperature polycrystalline silicon, and monocrystalline silicon, has been underway (e.g., Japanese Patent Application Publication Nos. 2014-146819 and 2015-159315). Oxide semiconductor-based channel transistors, like amorphous silicon-based channel transistors, have a simple structure and are formed using low-temperature processes. It is known that oxide semiconductor-based channel transistors have higher mobility and very low cutoff current than amorphous silicon-based channel transistors.

[0003] In recent years, efforts have been made to reduce the pixel size of display devices. Along with the reduction in pixel size, research is underway to reduce wiring width and transistor size. However, there are limits to their reduction, as the aperture ratio continuously decreases due to the configuration of the metal and semiconductor layers constituting the pixel circuit. Therefore, development is underway to use transistors with oxide semiconductor layers for the channel as transistors in the pixel circuit, achieving sufficient characteristics for driving the pixel circuit even with small transistor sizes.

[0004] In transistors using low-temperature polysilicon as the channel, direct contact between the silicon layer and the transparent conductive layer (e.g., ITO) used as the pixel electrode is not permissible. Therefore, a substrate serving as a metal layer is required between the silicon layer and the transparent conductive layer. If such a substrate is positioned in the display area of ​​the pixel, a reduction in the pixel aperture ratio occurs. The related technical concept is also common in transistors using oxide semiconductors as the channel, typically employing a structure where a transparent conductive layer is formed on a substrate serving as the metal layer. Summary of the Invention

[0005] One embodiment of the present invention addresses the issue of improving the brightness of a display device.

[0006] A display device according to one embodiment of the present invention includes: a first transistor having an oxide semiconductor layer, a first gate electrode opposite to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; a first transparent conductive layer in contact with the oxide semiconductor layer in a first contact area that does not overlap with the first gate electrode in a top view; and a second transparent conductive layer connected to the first transparent conductive layer in a second contact area that overlaps with the first gate electrode in a top view, and disposed in the display area of ​​a pixel.

[0007] One embodiment of the present invention relates to a display device comprising: a first transistor having an oxide semiconductor layer, a first gate electrode opposite to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; a first transparent conductive layer in contact with the oxide semiconductor layer in a first contact area that does not overlap with the first gate electrode in top view; and a second transparent conductive layer connected to the first transparent conductive layer and disposed in a display area of ​​a pixel. In top view, the first contact area is included in the display area.

[0008] An embodiment of the present invention relates to a display device comprising: a gate line extending in a first direction; a first wiring extending in a second direction intersecting the first direction; a second wiring adjacent to the first wiring and extending in the second direction; an oxide semiconductor layer extending in the second direction between the first wiring and the second wiring, and intersecting the gate line; a first transparent conductive layer overlapping the gate line and the oxide semiconductor layer between the first wiring and the second wiring; and a second transparent conductive layer overlapping the gate line, the oxide semiconductor layer, and the first transparent conductive layer between the first wiring and the second wiring. The first transparent conductive layer and the oxide semiconductor layer are in contact in a first contact region that does not overlap with the gate line, and the first transparent conductive layer and the second transparent conductive layer are in contact in a second contact region that overlaps with the gate line. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view illustrating an outline of a display device according to one embodiment of the present invention.

[0010] Figure 2 This is a top view illustrating an outline of a display device according to one embodiment of the present invention.

[0011] Figure 3 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0012] Figure 4 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0013] Figure 5 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0014] Figure 6This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0015] Figure 7 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0016] Figure 8 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0017] Figure 9 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0018] Figure 10 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0019] Figure 11 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0020] Figure 12 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0021] Figure 13 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention.

[0022] Figure 14 This is a cross-sectional view illustrating an outline of a display device according to one embodiment of the present invention.

[0023] Figure 15 This is a top view illustrating an outline of a display device according to one embodiment of the present invention.

[0024] Figure 16 This is a block diagram illustrating the circuit configuration of a display device according to one embodiment of the present invention.

[0025] Figure 17 This is a circuit diagram illustrating the pixel circuit of a display device according to one embodiment of the present invention.

[0026] Symbol Explanation

[0027] 10. Display device; 20B. Display device; 22B. Liquid crystal area; 24B. Sealing area; 26B. Terminal area; 300B. Array substrate; 310B. Pixel circuit; 320B. Source driver circuit; 321B. Source wiring; 330B. Gate driver circuit; 331B. Gate wiring; 333B. Terminal portion; 341B. Connecting wiring; 400B. Sealing portion; 410B. Liquid crystal element; 500B. Opposing substrate; 600B. Flexible printed circuit board; 700B. Chip; 800B. Transistor; 810B. First gate electrode; 830B. First source electrode; 840B. B, First drain electrode; 890B, Holding capacitor; CMTL, Common auxiliary electrode; CON1, First contact area; CON2, Second contact area; CTCO, Common electrode; GI1, GI2, Gate insulating layer; GL1, GL2, Gate electrode; IL1~IL5, Insulating layer; LS, Light-shielding layer; OP, Opening; OS, Oxide semiconductor layer; PCON, WCON, ZCON, Opening; PJT, Protrusion; PTCO, Pixel electrode; S, Semiconductor layer; SL, Slit; SP, Spacer; SUB, Substrate; Tr1, Tr2, Transistor; W, Wiring; ZTCO, Connecting electrode. Detailed Implementation

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. The following disclosure is merely an example. Configurations that can be readily conceived by those skilled in the art by appropriately modifying the configuration of the embodiments while maintaining the spirit of the invention are of course included within the scope of the present invention. The drawings schematically represent the width, thickness, shape, etc. of various parts compared to the actual form in order to make the description clearer. However, the shapes shown are merely examples and do not limit the interpretation of the present invention. In this specification and the accompanying drawings, for configurations identical to those described in the figures already presented, letters are sometimes appended after the same symbols, and detailed descriptions are appropriately omitted.

[0029] In various embodiments of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "above". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "below". Thus, for ease of explanation, the terms "up" or "below" are used, but for example, the vertical relationship between the substrate and the oxide semiconductor layer can be configured with orientations different from those shown in the figures. In the following description, the term "oxide semiconductor layer on the substrate" is merely an explanation of the vertical relationship between the substrate and the oxide semiconductor layer as described above; other components may also be arranged between the substrate and the oxide semiconductor layer. "Up" or "below" refers to the stacking order in a structure with multiple layers. In the case of a pixel electrode above a transistor, it can also refer to a positional relationship where the transistor and the pixel electrode do not overlap when viewed from above. On the other hand, the case of a pixel electrode vertically above a transistor implies a positional relationship where the transistor and the pixel electrode overlap when viewed from above.

[0030] The term "display device" refers to a structure that displays images using an electro-optical layer. For example, the term "display device" sometimes refers to a display panel that includes an electro-optical layer, or sometimes to a structure on which other optical components (such as polarizing components, backlights, touch panels, etc.) are mounted to the display unit. As long as there is no technical inconsistency, the "electro-optical layer" can include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, or an electrophoretic layer. Therefore, in the embodiments described below, a liquid crystal display device including a liquid crystal layer will be exemplified as a display device, but the structure in this embodiment can be applied to display devices that include other electro-optical layers described above.

[0031] In this specification, unless otherwise expressly stated, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", and "α includes one of the groups selected from A, B, and C" do not exclude the possibility that α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the possibility that α includes other elements.

[0032] It should be noted that the following implementation methods can be combined with each other as long as they do not create technical contradictions.

[0033] [1. First Implementation Method]

[0034] [1-1. Configuration of the display device 10]

[0035] use Figures 1 to 13 The configuration of a display device 10 according to one embodiment of the present invention will be described. Figure 1 This is a cross-sectional view illustrating an outline of a display device according to one embodiment of the present invention. Figure 2 This is a top view illustrating an outline of a display device according to one embodiment of the present invention. Figures 3 to 13 This is a top view illustrating the layout of each layer in a display device according to one embodiment of the present invention. Figure 1 The sectional view is used to illustrate the layer structure of the display device 10. Strictly speaking, it also has a cross-sectional view with... Figure 2 The top view is inconsistent.

[0036] like Figure 1 As shown, the display device 10 is disposed above the substrate SUB. The display device 10 includes transistor Tr1, transistor Tr2, wiring W, a connection electrode ZTCO, a pixel electrode PTCO, a common auxiliary electrode CMTL, and a common electrode CTCO. TCO is short for transparent conductive oxide. Transistor Tr1 is a transistor included in the pixel circuit of the display device 10. Transistor Tr2 is a transistor included in the peripheral circuit. Details will be provided later; the peripheral circuit is the circuit that drives the pixel circuit.

[0037] [1-2. Structure of transistor Tr1]

[0038] Transistor Tr1 has an oxide semiconductor layer OS, a gate insulating layer GI1, and a gate electrode GL1. The gate electrode GL1 is opposite to the oxide semiconductor layer OS. The gate insulating layer GI1 is disposed between the oxide semiconductor layer OS and the gate electrode GL1. In this embodiment, a top-gate transistor is illustrated where the oxide semiconductor layer OS is located on the substrate SUB side relative to the gate electrode GL1, but a bottom-gate transistor with the reversed positional relationship between the gate electrode GL1 and the oxide semiconductor layer OS can also be used.

[0039] The oxide semiconductor layer OS includes oxide semiconductor layers OS1 and OS2. Oxide semiconductor layer OS1 is the oxide semiconductor layer in the region overlapping with the gate electrode GL1 when viewed from above. Oxide semiconductor layer OS1 functions as a semiconductor layer, switching between an on and off state depending on the voltage supplied to the gate electrode GL1. That is, oxide semiconductor layer OS1 functions as the channel of transistor Tr1. Oxide semiconductor layer OS2 functions as a conductive layer. Oxide semiconductor layers OS1 and OS2 are layers formed from the same oxide semiconductor layer. For example, oxide semiconductor layer OS2 is an oxide semiconductor layer with low resistance achieved by doping impurities with the same physical properties as oxide semiconductor layer OS1.

[0040] An insulating layer IL2 is disposed above the gate electrode GL1. A wiring W1 is disposed above the insulating layer IL2. The wiring W1 is connected to the oxide semiconductor layer OS2 via an opening WCON disposed in the insulating layer IL2 and the gate insulating layer GI1. A data signal associated with the grayscale of a pixel is transmitted to the wiring W1. An insulating layer IL3 is disposed above the insulating layer IL2 and the wiring W1. A connection electrode ZTCO is disposed above the insulating layer IL3. The connection electrode ZTCO is connected to the oxide semiconductor layer OS2 via an opening ZCON disposed in the insulating layers IL3, IL2, and the gate insulating layer GI1. The connection electrode ZTCO contacts the oxide semiconductor layer OS2 at the bottom of the opening ZCON. The connection electrode ZTCO is a transparent conductive layer.

[0041] The area where the connecting electrode ZTCO contacts the oxide semiconductor layer OS2 is called the first contact area CON1. ​​Sometimes the connecting electrode ZTCO is referred to as the "first transparent conductive layer." Details will be described later. When viewed from above, the first transparent conductive layer contacts the oxide semiconductor layer OS2 within the first contact area CON1, which does not overlap with the gate electrode GL1 or the wiring W1. When viewed from above, the first contact area CON1 is included within the display area of ​​the pixel.

[0042] For example, if a transparent conductive layer such as an ITO layer is formed in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer will be oxidized by the process gas or oxygen ions during ITO film formation. The oxide layer formed on the surface of the semiconductor layer has high resistance, thus increasing the contact resistance between the semiconductor layer and the transparent conductive layer. As a result, poor electrical contact occurs between the semiconductor layer and the transparent conductive layer. On the other hand, even if the aforementioned transparent conductive layer is formed in contact with an oxide semiconductor layer, a high-resistivity oxide layer as described above does not form on the surface of the oxide semiconductor layer. Therefore, poor electrical contact does not occur between the oxide semiconductor layer and the transparent conductive layer.

[0043] An insulating layer IL4 is disposed above the connecting electrode ZTCO. The insulating layer IL4 mitigates the step difference formed by the structure disposed in the lower layer compared to the insulating layer IL4. The insulating layer IL4 is sometimes referred to as a planarization film. A pixel electrode PTCO is disposed above the insulating layer IL4. The pixel electrode PTCO is connected to the connecting electrode ZTCO via an opening PCON disposed in the insulating layer IL4. The area where the connecting electrode ZTCO and the pixel electrode PTCO contact is called the second contact area CON2. When viewed from above, the second contact area CON2 overlaps with the gate electrode GL1. The pixel electrode PTCO is a transparent conductive layer.

[0044] An insulating layer IL5 is disposed above the pixel electrode PTCO. A common auxiliary electrode CMTL and a common electrode CTCO are disposed above the insulating layer IL5. That is, the pixel electrode PTCO is opposite the common electrode CTCO via the insulating layer IL5. The common electrode CTCO is connected to the common auxiliary electrode CMTL through the opening PCON (within the second contact area CON2). As detailed later, the common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The resistance of the common auxiliary electrode CMTL is lower than that of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL blocks light from adjacent pixels, thereby suppressing color mixing. A spacer SP is disposed above the common electrode CTCO.

[0045] Spacers SP are provided on a subset of pixels. For example, spacers SP can be provided on any one of the blue, red, and green pixels. However, spacers SP can also be provided on all pixels. The height of the spacers SP is half the height of the cell gap. Spacers are also provided on the opposite substrate, and the spacers on the opposite substrate and the aforementioned spacers SP overlap when viewed from above.

[0046] A light-shielding layer LS is provided between transistor Tr1 and substrate SUB. In this embodiment, light-shielding layers LS1 and LS2 are provided as light-shielding layers LS. However, the light-shielding layer LS may be formed only by light-shielding layer LS1 or only by light-shielding layer LS2. When viewed from above, the light-shielding layer LS is provided in the region where gate electrode GL1 overlaps with oxide semiconductor layer OS. That is, when viewed from above, the light-shielding layer LS is provided in the region where it overlaps with oxide semiconductor layer OS1. The light-shielding layer LS suppresses light incident from the substrate SUB side from reaching oxide semiconductor layer OS1. When a conductive layer is used as the light-shielding layer LS, the oxide semiconductor layer OS1 can also be controlled by applying a voltage to the light-shielding layer LS. When a voltage is applied to the light-shielding layer LS, the light-shielding layer LS and gate electrode GL1 can also be connected in the peripheral region of the pixel circuit. When viewed from above, the aforementioned first contact region CON1 is provided in the region where it does not overlap with the light-shielding layer LS.

[0047] [1-3. Structure of transistor Tr2]

[0048] Transistor Tr2 has a p-type transistor Tr2-1 and an n-type transistor Tr2-2. Sometimes transistor Tr2 is referred to as the "second transistor".

[0049] Both the p-type transistor Tr2-1 and the n-type transistor Tr2-2 have a gate electrode GL2, a gate insulating layer GI2, and a semiconductor layer S. The gate electrode GL2 is opposite to the semiconductor layer S. The gate insulating layer GI2 is disposed between the semiconductor layer S and the gate electrode GL2. In this embodiment, a bottom-gate transistor is illustrated where the gate electrode GL2 is located on the substrate SUB side relative to the semiconductor layer S, but a top-gate transistor with the semiconductor layer S and the gate electrode GL2 in the opposite positional relationship can also be used. Sometimes the gate electrode GL2 is referred to as the "second gate electrode." Sometimes the gate insulating layer GI2 is referred to as the "second gate insulating layer."

[0050] The semiconductor layer S of the p-type transistor Tr2-1 includes semiconductor layers S1 and S2. The semiconductor layer S of the n-type transistor Tr2-2 includes semiconductor layers S1, S2, and S3. Semiconductor layer S1 is the semiconductor layer in the region that overlaps with the gate electrode GL2 when viewed from above. Semiconductor layer S1 functions as the channel of transistors Tr2-1 and Tr2-2. Semiconductor layer S2 functions as a conductive layer. Semiconductor layer S3 functions as a conductive layer with a higher resistance than semiconductor layer S2. Semiconductor layer S3 suppresses hot carrier degradation by attenuating hot carriers intruding towards semiconductor layer S1.

[0051] An insulating layer IL1 and a gate insulating layer GI1 are disposed on the semiconductor layer S. In transistor Tr2, the gate insulating layer GI1 functions only as an interlayer film. A wiring W2 is disposed on these insulating layers. The wiring W2 is connected to the semiconductor layer S through openings provided in the insulating layer IL1 and the gate insulating layer GI1. An insulating layer IL2 is disposed on the wiring W2. A wiring W1 is disposed on the insulating layer IL2. The wiring W1 is connected to the wiring W2 through an opening provided in the insulating layer IL2.

[0052] The gate electrode GL2 and the light-shielding layer LS2 are on the same layer. The wiring W2 and the gate electrode GL1 are on the same layer. "Same layer" means that multiple components are formed by patterning a single layer.

[0053] [1-4. Top view of the display device 10]

[0054] use Figures 2 to 13 The top-view layout of the pixels of the display device 10 will be explained. Figure 2 The pixel electrode PTCO, common auxiliary electrode CMTL, common electrode CTCO, and spacer SP are omitted. The top view layout of the pixel electrode PTCO, common auxiliary electrode CMTL, and common electrode CTCO are shown below. Figures 11 to 13 .

[0055] like Figure 2 and Figure 3As shown, the light-shielding layer LS extends in the D1 direction. The shape of the light-shielding layer LS varies depending on the pixel. In this embodiment, a protrusion PJT is provided that protrudes from a portion of the light-shielding layer LS extending in the D1 direction in the D2 direction. Figure 5 As shown, the light-shielding layer LS is disposed in the region that includes the area where the gate electrode GL1 overlaps with the oxide semiconductor layer OS when viewed from above. It should be noted that the gate electrode GL1 can also be referred to as the "gate line".

[0056] like Figure 2 , Figure 4 and Figure 5 As shown, the oxide semiconductor layer OS extends in the D2 direction. The gate electrode GL1 extends in the D1 direction, intersecting the oxide semiconductor layer OS. The pattern of the gate electrode GL1 is disposed inside the pattern of the light-shielding layer LS. In other words, the oxide semiconductor layer OS is formed as a strip that intersects the gate electrode GL1.

[0057] like Figure 2 , Figure 6 and Figure 7 As shown, the opening WCON is located near the upper end of the pattern of the oxide semiconductor layer OS in the region overlapping with the wiring W1. The main portion of the pattern of the oxide semiconductor layer OS extends along the D2 direction between adjacent wirings W1. The remaining portion of the pattern of the oxide semiconductor layer OS extends from this main portion in a direction inclined relative to both the D1 and D2 directions, and overlaps with the opening WCON.

[0058] like Figure 2 and Figure 7 As shown, multiple wirings W1 extend along the D2 direction. When it is necessary to describe adjacent wirings W1 separately, they are referred to as wiring W1-1 (first wiring) and wiring W1-2 (second wiring). In this case, the main part of the oxide semiconductor layer OS can be said to extend along the D2 direction between the first wiring W1-1 and the second wiring W1-2 and intersect with the gate electrode GL1. Alternatively, the oxide semiconductor layer OS can be described as being elongated (with a long side) in the D2 direction, and connected to wiring W1-1 (first wiring) at one end of the long side of the oxide semiconductor layer OS.

[0059] like Figure 2 , Figure 8 and Figure 9As shown, the opening ZCON is located near the lower end of the pattern of the oxide semiconductor layer OS. The opening ZCON is located in the region overlapping the pattern of the oxide semiconductor layer OS but not overlapping the gate electrode GL1. The opening ZCON is located in the region overlapping the connection electrode ZTCO. The connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS between wiring W1-1 and wiring W1-2. Therefore, the connection electrode ZTCO contacts the oxide semiconductor layer OS in the opening ZCON (first contact region CON1) that does not overlap with the gate electrode GL1.

[0060] If we express the above configuration in another way, the oxide semiconductor layer OS is connected to the connecting electrode ZTCO (first transparent conductive layer) at the other end along its long side. The connecting electrode ZTCO, like the oxide semiconductor layer OS, is formed as an elongated strip extending in the D2 direction. In the D1 direction, the width of the connecting electrode ZTCO is smaller than the width of the oxide semiconductor layer OS.

[0061] like Figure 2 , Figure 7 and Figure 8 As shown, the oxide semiconductor layer OS is in contact with the wiring W1 on the side opposite to the opening ZCON, relative to the gate electrode GL1. The opening ZCON does not overlap with the light-shielding layer LS.

[0062] like Figure 2 , Figure 10 and Figure 11 As shown, the opening PCON is located near the upper end of the pattern of the connecting electrode ZTCO. The opening PCON is located in the region overlapping with the patterns of the gate electrode GL1 and the connecting electrode ZTCO. The opening PCON is located in the region overlapping with the pixel electrode PTCO. The pixel electrode PTCO overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connecting electrode ZTCO between wiring W1-1 and wiring W1-2. Therefore, the pixel electrode PTCO contacts the connecting electrode ZTCO in the opening PCON (second contact region CON2) that overlaps with the gate electrode GL1.

[0063] The pixel electrode PTCO extends in the light-transmitting region described below. The pixel electrode PTCO is sometimes referred to as the "second transparent conductive layer." Alternatively, the pixel electrode PTCO, along with the oxide semiconductor layer OS and wiring W1-1 (first wiring), is formed as an elongated strip extending in the D2 direction. In the D1 direction, the width of the pixel electrode PTCO in the portion where the opening PCON is provided is greater than the width of the oxide semiconductor layer OS.

[0064] like Figure 11As shown, the connecting electrode ZTCO is formed as an elongated strip extending along wiring W1-1. In the D1 direction, the width of the opening PCON constituting the second contact area CON2 is greater than the width of the connecting electrode ZTCO. When viewed from above, the entire connecting electrode ZTCO overlaps with the pixel electrode PTCO.

[0065] like Figure 11 As shown, the pixel electrodes PTCO are arranged in the D2 direction. Among adjacent pixels in the D2 direction, one pixel is sometimes referred to as the "first pixel," and the other as the "second pixel." For example, the first pixel is... Figure 11 The first pixel corresponds to the upper pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction, and the second pixel corresponds to the lower pixel electrode PTCO among the pixel electrodes PTCO arranged in the D2 direction. In this case, pixel signals are supplied to the first pixel and the second pixel from wiring W1-1.

[0066] Furthermore, the pixel electrodes PTCO are arranged in the D1 direction. The pixel adjacent to the first pixel in the D1 direction is called the "third pixel," and the pixel adjacent to the second pixel in the D1 direction is called the "fourth pixel." The third and fourth pixels are adjacent in the D2 direction. Pixel signals are supplied to the third and fourth pixels from the wiring W1-2 (the second wiring) adjacent to the wiring W1-1.

[0067] As described above, the first pixel, the second pixel, the third pixel, and the fourth pixel each have a transistor Tr1 (pixel transistor), a connection electrode ZTCO, and a pixel electrode PTCO, respectively.

[0068] Transistor Tr1 includes an oxide semiconductor layer OS, a gate electrode GL1 opposite to the oxide semiconductor layer OS, and a gate insulating layer GI1 between the oxide semiconductor layer OS and the gate electrode GL1. The connection electrode ZTCO overlaps with the gate electrode GL1 and the oxide semiconductor layer OS when viewed from above, and contacts the oxide semiconductor layer OS in an opening ZCON (first contact area CON1) that does not overlap with the gate electrode GL1. The pixel electrode PTCO overlaps with the gate electrode GL1, the oxide semiconductor layer OS, and the connection electrode ZTCO when viewed from above, and is connected to the connection electrode ZTCO in an opening PCON (second contact area CON2) that overlaps with the gate electrode GL1.

[0069] exist Figure 11The pixel electrode PTCO of the first pixel, located on its upper side, overlaps with the oxide semiconductor layer OS of the first pixel and the oxide semiconductor layer OS of the second pixel, located below the first pixel, when viewed from above. Furthermore, the pixel electrode PTCO of the first pixel also overlaps with a portion of the oxide semiconductor layer OS of the fourth pixel when viewed from above.

[0070] like Figure 12 As shown, the common auxiliary electrode CMTL is arranged in a grid pattern surrounding the pixel area. That is, the common auxiliary electrode CMTL is shared by multiple pixels. In other words, the common auxiliary electrode CMTL has an opening OP. The opening OP is arranged to expose the pixel electrode PTCO. The pattern of the opening OP is set inside the pattern of the pixel electrode PTCO. The area with the opening OP corresponds to the display area. That is, the opening ZCON is included in the display area. The display area refers to the area where the user can visually confirm the light from the pixel. For example, the area where the light is blocked by the metal layer and the user cannot visually confirm the light is not included in the display area. That is, the above-mentioned display area is sometimes called the "transparent area (or opening area)".

[0071] like Figure 13 As shown, the common electrode CTCO is shared by multiple pixels. A slit SL is provided in the region corresponding to the aforementioned opening OP. The slit SL has a curved shape (a longitudinally elongated S-shape). The front end of the slit SL has a shape with a decreasing width orthogonal to the extending direction of the front end. (Refer to...) Figure 1 and Figure 13 The common electrode CTCO has a slit SL at a position opposite to the pixel electrode PTCO.

[0072] [1-5. Materials of the components of the display device 10]

[0073] As a substrate SUB, rigid substrates that are transparent but not flexible, such as glass substrates, quartz substrates, and sapphire substrates, can be used. On the other hand, when the substrate SUB needs to be flexible, flexible substrates containing resin and possessing flexibility, such as polyimide substrates, acrylic substrates, siloxane boards, or fluororesin substrates, can be used. To improve the heat resistance of the substrate SUB, impurities can also be introduced into the aforementioned resins.

[0074] Common metallic materials can be used as gate electrodes GL1, GL2, wiring W1, W2, light-shielding layer LS, and common auxiliary electrode CMTL. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), and silver (Ag), or alloys or compounds thereof, can be used as these electrode components. These materials can be used as a single layer or in a stacked configuration.

[0075] For example, a Ti / Al / Ti laminated structure can be used as the gate electrode GL1. In this embodiment, the cross-sectional shape of the patterned end of the gate electrode GL1 having the above-described laminated structure is a positive cone shape.

[0076] General insulating materials can be used as gate insulating layers GI1, GI2, and insulating layers IL1 to IL5. For example, silicon oxide (SiO2) can be used as insulating layers IL1 to IL3 and IL5. x ), silicon oxynitride (SiO) x N y ), silicon nitride (SiN) x ), silicon oxynitride (SiN) x O y ), aluminum oxide (AlO) x ), aluminum oxide (AlO) x N y ), aluminum oxynitride (AlN) x O y ), aluminum nitride (AlN) x Inorganic insulating layers such as IL4, acrylic resin, epoxy resin, silicone resin, fluororesin, or siloxane resin can be used as insulating layers. The aforementioned organic insulating materials can also be used as gate insulating layers GI1 and GI2, and insulating layers IL1 to IL3 and IL5. These materials can be used as single layers or in stacks as the aforementioned insulating layers and other components.

[0077] As an example of the aforementioned insulating layer, a SiO layer with a thickness of 100 nm was used. x GI1 is used as the gate insulating layer. IL1 is used as the insulating layer, employing SiO₂ with a total thickness of 600 nm to 700 nm. x / SiN x / SiO x As the gate insulating layer GI2, SiO₂ with a total thickness of 60–100 nm is used. x / SiN x As the insulating layer IL2, SiO2 with a total thickness of 300nm to 500nm is used.x / SiN x / SiO x As the insulating layer IL3, SiO₂ with a total thickness of 200 nm to 500 nm is used. x (single-layer), SiN x (Single layer) or stacks thereof. As insulating layer IL4, an organic layer with a thickness of 2 μm to 4 μm is used. As insulating layer IL5, SiN with a thickness of 50 nm to 150 nm is used. x (Single layer)

[0078] The above-mentioned SiO x N y and AlO x N y It is a silicon and aluminum compound containing a nitrogen (N) in a ratio less than that of oxygen (O) (x > y). SiN x O y and AlN x O y It consists of silicon and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0079] As the oxide semiconductor layer OS, an oxide metal with semiconductor properties can be used. The oxide semiconductor layer OS is transparent. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used as the oxide semiconductor layer OS. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 can be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition, and oxide semiconductors with different compositions can also be used. For example, the In ratio can be greater than the above ratio in order to improve mobility. In addition, the Ga ratio can be greater than the above ratio in order to increase the band gap and reduce the effect of light irradiation.

[0080] Other elements can also be added to the oxide semiconductor containing In, Ga, Zn, and O. For example, metal elements such as Al and Sn can also be added to the oxide semiconductor. In addition to the oxide semiconductors mentioned above, oxide semiconductors containing In and Ga (IGO), oxide semiconductors containing In and Zn (IZO), oxide semiconductors containing In, Sn, and Zn (ITZO), and oxide semiconductors containing In and W can also be used as oxide semiconductor layers OS. The oxide semiconductor layer OS can be amorphous or crystalline. The oxide semiconductor layer OS can also be a mixture of amorphous and crystalline phases.

[0081] A transparent conductive layer is used as the connecting electrode ZTCO, pixel electrode PTCO, and common electrode CTCO. This transparent conductive layer can be a mixture of indium oxide and tin oxide (ITO) or a mixture of indium oxide and zinc oxide (IZO). Other materials besides those described above can also be used as this transparent conductive layer.

[0082] As described above, according to the display device 10 of this embodiment, conduction between the oxide semiconductor layer OS of transistor Tr1 and the connection electrode ZTCO can be ensured by making them directly contacted. Therefore, it is not necessary to provide a metal layer between the oxide semiconductor layer OS and the connection electrode ZTCO. With this configuration, light is not blocked in the opening ZCON (first contact area CON1), thus suppressing the reduction of the aperture ratio. The oxide semiconductor layer is transparent. Therefore, in this embodiment, although an oxide semiconductor layer is provided in the opening area of ​​the pixel area, light from the backlight source passes through the oxide semiconductor layer. Therefore, the reduction of the transmittance of the opening area caused by the oxide semiconductor layer being provided in the opening area can be minimized. Because the oxide semiconductor layer OS is transparent, unlike the silicon layer, it is difficult to cause unevenness in transmitted light. By providing the oxide semiconductor layer OS in the display area, the generation of display unevenness can be suppressed.

[0083] [2. Second Implementation]

[0084] use Figure 14 The configuration of a display device 10A according to one embodiment of the present invention will be described. Figure 14 This is a cross-sectional view illustrating an outline of a display device according to one embodiment of the present invention. Figure 14 The display device 10A shown is Figure 1 The display device 10 shown is similar, but the positional relationship between the pixel electrode PTCO and the common electrode CTCO is different.

[0085] like Figure 14 As shown, a common auxiliary electrode CMTL and a common electrode CTCO are disposed on the insulating layer IL4. An insulating layer IL5 is disposed on the common auxiliary electrode CMTL and the common electrode CTCO. A pixel electrode PTCO is disposed on the insulating layer IL5. The pixel electrode PTCO is connected to the connecting electrode ZTCO via an opening PCON disposed in the insulating layers IL4 and IL5. As described above, the pixel electrode PTCO can be disposed above the common electrode CTCO.

[0086] According to the display device 10A of this embodiment, the same effect as that of the display device 10 of the first embodiment can be obtained.

[0087] <Third Implementation Method>

[0088] use Figures 15-17 The overall structure of the display device described in the first and second embodiments above will be explained.

[0089] [Overview of display device 20B]

[0090] Figure 15 This is a top view illustrating an outline of a display device according to one embodiment of the present invention. Figure 15 As shown, the display device 20B includes an array substrate 300B, a sealing portion 400B, a counter substrate 500B, a flexible printed circuit board 600B (FPC 600B), and an IC chip 700B. The array substrate 300B and the counter substrate 500B are bonded together by the sealing portion 400B. In the liquid crystal region 22B surrounded by the sealing portion 400B, a plurality of pixel circuits 310B are arranged in a matrix. The liquid crystal region 22B is the area that overlaps with the liquid crystal element 410B (described later) when viewed from above. The liquid crystal region 22B is an area that contributes to the display. Sometimes the liquid crystal region 22B is referred to as the "display region". The aforementioned transistor Tr1 (first transistor) is disposed in the liquid crystal region 22B (display region).

[0091] The sealing region 24B, with the sealing portion 400B, is the area surrounding the liquid crystal region 22B. The FPC 600B is located in the terminal region 26B. The terminal region 26B is the area where the array substrate 300B is exposed from the substrate 500B, and is located outside the sealing region 24B. It should be noted that the "outside" of the sealing region 24B refers to the area with the sealing portion 400B and the area surrounded by the sealing portion 400B. The IC chip 700B is located on the FPC 600B. The IC chip 700B provides signals for driving each pixel circuit 310B. The sealing region 24B, or the area of ​​the sealing region 24B combined with the terminal region 26B, is the area surrounding the liquid crystal region 22B (display area). These areas are sometimes referred to as "bezel areas." The aforementioned transistor Tr2 (second transistor) is located in this bezel area.

[0092] [Circuit configuration of display device 20B]

[0093] Figure 16 This is a block diagram illustrating the circuit configuration of a display device according to one embodiment of the present invention. Figure 16As shown, a source driver circuit 320B is disposed adjacent to the liquid crystal region 22B in the D1 direction (column direction) relative to the region where the pixel circuit 310B is disposed, and a gate driver circuit 330B is disposed adjacent to the liquid crystal region 22B in the D2 direction (row direction). The source driver circuit 320B and the gate driver circuit 330B are disposed in the aforementioned sealed region 24B. However, the region where the source driver circuit 320B and the gate driver circuit 330B are disposed is not limited to the sealed region 24B; it can be any region outside the region where the pixel circuit 310B is disposed.

[0094] Source wiring 321B extends from source driver circuit 320B in the D1 direction and is connected to a plurality of pixel circuits 310B arranged in the D1 direction. Gate wiring 331B extends from gate driver circuit 330B in the D2 direction and is connected to a plurality of pixel circuits 310B arranged in the D2 direction.

[0095] A terminal section 333B is provided in the terminal region 26B. The terminal section 333B and the source driver circuit 320B are connected via a connection wire 341B. Similarly, the terminal section 333B is connected to the gate driver circuit 330B via the connection wire 341B. By connecting the FPC 600B to the terminal section 333B, an external device connected to the FPC 600B is connected to the display device 20B, and the pixel circuits 310B provided in the display device 20B are driven by signals from the external device.

[0096] The transistor Tr1 shown in the first and second embodiments is used in the pixel circuit 310B. The transistor Tr2 shown in the first and second embodiments is applicable to the transistors included in the source driver circuit 320B and the gate driver circuit 330B.

[0097] [Pixel circuit 310B of display device 20B]

[0098] Figure 17 This is a circuit diagram illustrating the pixel circuitry of a display device according to one embodiment of the present invention. Figure 17As shown, the pixel circuit 310B includes components such as a transistor 800B, a holding capacitor 890B, and a liquid crystal element 410B. One electrode of the holding capacitor 890B is the pixel electrode PTCO, and the other electrode is the common electrode CTCO. Similarly, one electrode of the liquid crystal element 410B is the pixel electrode PTCO, and the other electrode is the common electrode CTCO. The transistor 800B has a first gate electrode 810B, a first source electrode 830B, and a first drain electrode 840B. The first gate electrode 810B is connected to the gate wiring 331B. The first source electrode 830B is connected to the source wiring 321B. The first drain electrode 840B is connected to the holding capacitor 890B and the liquid crystal element 410B. The transistor Tr1 shown in the first and second embodiments is suitable for... Figure 17 The transistor 800B is shown. In this embodiment, for ease of explanation, 830B is referred to as the source electrode and 840B as the drain electrode, but the functions of each electrode as the source and as the drain can be interchanged.

[0099] As embodiments of the present invention, the above-described embodiments can be appropriately combined to implement them as long as they do not contradict each other. Furthermore, based on the display devices of each embodiment, any additions, deletions, or design changes to constituent elements, or additions, omissions, or condition changes to processes made by those skilled in the art, as long as they possess the spirit of the present invention, are also included within the scope of the present invention.

[0100] Even if other effects are different from those brought about by the solutions described above, effects that are obvious from the description in this specification or that can be easily predicted by those skilled in the art are of course understood to be brought about by the present invention.

Claims

1. A display device, characterized in that, have: A first transistor, the first transistor having an oxide semiconductor layer, a first gate electrode opposite to the oxide semiconductor layer, and a first gate insulating layer between the oxide semiconductor layer and the first gate electrode; The first transparent conductive layer overlaps with the first gate electrode and the oxide semiconductor layer when viewed from above, and is in contact with the oxide semiconductor layer in a first contact area that does not overlap with the first gate electrode; as well as The second transparent conductive layer, when viewed from above, overlaps with the first gate electrode, the oxide semiconductor layer, and the first transparent conductive layer, and is connected to the first transparent conductive layer in the second contact region overlapping with the first gate electrode. The second transparent conductive layer extends in the light-transmitting area of ​​the pixel. When viewed from above, the first contact area is contained within the light-transmitting area. It also has a first wiring that transmits a signal associated with the grayscale of the pixel. The first contact area is located in a region that does not overlap with the first gate electrode and the first wiring. The first transparent conductive layer is formed as a strip extending along the first wiring. In a direction orthogonal to the long side of the first transparent conductive layer, the width of the opening forming the second contact area is larger than the width of the first transparent conductive layer.

2. The display device according to claim 1, characterized in that, It also has a light-shielding layer, which is disposed at least in the region where the first gate electrode overlaps with the oxide semiconductor layer when viewed from above. The first contact area is located in a region that does not overlap with the light-shielding layer.

3. The display device according to claim 2, characterized in that, It also includes a second transistor, which has a semiconductor layer, a second gate electrode opposite to the semiconductor layer, and a second gate insulating layer disposed between the semiconductor layer and the second gate electrode. The second gate electrode and the light-shielding layer are disposed on the same layer.

4. The display device according to claim 3, characterized in that, It also has wiring connected to the semiconductor layer. The first gate electrode and the wiring are disposed on the same layer.

5. The display device according to claim 3, characterized in that, It has a display area that facilitates display and a border area that surrounds the display area. The first transistor is disposed in the display area, and the second transistor is disposed in the border area.

6. The display device according to claim 1, characterized in that, The oxide semiconductor layer is formed into a long strip shape that intersects with the first gate electrode, and is connected to the first wiring at one end in the long side direction of the oxide semiconductor layer, and to the first transparent conductive layer at the other end in the long side direction of the oxide semiconductor layer.

7. The display device according to claim 6, characterized in that, The first transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side, the width of the first transparent conductive layer is smaller than the width of the oxide semiconductor layer.

8. The display device according to claim 7, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

9. The display device according to claim 6, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

10. The display device according to claim 1, characterized in that, The second transparent conductive layer is formed as a strip extending along the first wiring. When viewed from above, the entire first transparent conductive layer overlaps with the second transparent conductive layer.

11. The display device according to claim 1, characterized in that, The second transparent conductive layer is opposite to the common electrode through an insulating film.

12. The display device according to claim 11, characterized in that, The common electrode has a slit at a position opposite to the second transparent conductive layer.

13. The display device according to claim 11, characterized in that, The common electrode is connected to a common auxiliary electrode made of metal.

14. The display device according to claim 13, characterized in that, The common auxiliary electrode is connected to the common electrode in the second contact area.

15. A display device, characterized in that, have: A gate line extending in a first direction; A first wiring, the first wiring extending in a second direction intersecting the first direction; A second wiring is adjacent to the first wiring and extends in the second direction; An oxide semiconductor layer extends in the second direction between the first wiring and the second wiring, and intersects the gate line; A first transparent conductive layer overlaps with the gate line and the oxide semiconductor layer between the first wiring and the second wiring; as well as A second transparent conductive layer overlaps with the gate line, the oxide semiconductor layer, and the first transparent conductive layer between the first wiring and the second wiring. The first transparent conductive layer and the oxide semiconductor layer are in contact in a first contact region that does not overlap with the gate line. The first transparent conductive layer and the second transparent conductive layer are in contact at a second contact region that overlaps with the gate line. The first contact area is contained within the light-transmitting area. The first transparent conductive layer is formed as a strip extending along the first wiring. In a direction orthogonal to the long side of the first transparent conductive layer, the width of the opening forming the second contact area is larger than the width of the first transparent conductive layer.

16. The display device according to claim 15, characterized in that, When viewed from above, the oxide semiconductor layer is in contact with the first wiring on the side opposite to the first contact area relative to the gate line.

17. The display device according to claim 15, characterized in that, It also includes a light-shielding layer, which is disposed at least in the region where the gate line overlaps with the oxide semiconductor layer and extends along the first direction. The first contact area does not overlap with the light-shielding layer.

18. The display device according to claim 15, characterized in that, The oxide semiconductor layer is formed into a long strip that intersects the gate line, and is connected to the first wiring at one end in the long side direction of the oxide semiconductor layer, and to the first transparent conductive layer at the other end in the long side direction of the oxide semiconductor layer.

19. The display device according to claim 18, characterized in that, The first transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side, the width of the first transparent conductive layer is smaller than the width of the oxide semiconductor layer.

20. The display device according to claim 19, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

21. The display device according to claim 18, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

22. The display device according to claim 15, characterized in that, The second transparent conductive layer is formed as a strip extending along the first wiring. When viewed from above, the entire first transparent conductive layer overlaps with the second transparent conductive layer.

23. The display device according to claim 15, characterized in that, The second transparent conductive layer is opposite to the common electrode through an insulating film.

24. The display device according to claim 23, characterized in that, The common electrode has a slit at a position opposite to the second transparent conductive layer.

25. The display device according to claim 23, characterized in that, The common electrode is connected to a common auxiliary electrode made of metal.

26. The display device according to claim 25, characterized in that, The common auxiliary electrode is connected to the common electrode in the second contact area.

27. A display device, characterized in that, It has a first pixel and a second pixel that receive pixel signals from the first wiring. The first pixel and the second pixel each have: A pixel transistor, the pixel transistor comprising an oxide semiconductor layer, a gate electrode opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode; The first transparent conductive layer overlaps with the gate electrode and the oxide semiconductor layer when viewed from above, and is in contact with the oxide semiconductor layer in a first contact area that does not overlap with the gate electrode; as well as The second transparent conductive layer, when viewed from above, overlaps with the gate electrode, the oxide semiconductor layer, and the first transparent conductive layer, and is connected to the first transparent conductive layer in the second contact region overlapping with the gate electrode. The second transparent conductive layer of the first pixel overlaps with the oxide semiconductor layer of the first pixel and the oxide semiconductor layer of the second pixel. The first transparent conductive layer is formed as a strip extending along the first wiring. In a direction orthogonal to the long side of the first transparent conductive layer, the width of the opening forming the second contact area is larger than the width of the first transparent conductive layer.

28. The display device according to claim 27, characterized in that, The oxide semiconductor layer is formed into a long strip shape that intersects with the gate electrode, and is connected to the first wiring at one end in the long side direction of the oxide semiconductor layer, and to the first transparent conductive layer at the other end in the long side direction of the oxide semiconductor layer.

29. The display device according to claim 28, characterized in that, The first transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side, the width of the first transparent conductive layer is smaller than the width of the oxide semiconductor layer.

30. The display device according to claim 29, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

31. The display device according to claim 28, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

32. The display device according to claim 27, characterized in that, The second transparent conductive layer is formed as a strip extending along the first wiring. When viewed from above, the entire first transparent conductive layer overlaps with the second transparent conductive layer.

33. The display device according to claim 27, characterized in that, The second transparent conductive layer of the first pixel and the second pixel is opposite to the common electrode through an insulating film.

34. The display device according to claim 33, characterized in that, The common electrode has a slit at a position opposite to the second transparent conductive layer of the first pixel and the second pixel.

35. The display device according to claim 33, characterized in that, The common electrode is connected to a common auxiliary electrode made of metal.

36. The display device according to claim 35, characterized in that, The common auxiliary electrode is connected to the common electrode in the second contact area of ​​the first pixel and the second pixel.

37. A display device, characterized in that, The device includes a first pixel and a second pixel that receive pixel signals from a first wiring, and a third pixel and a fourth pixel that receive pixel signals from a second wiring adjacent to the first pixel. Each pixel of the first pixel, the second pixel, the third pixel, and the fourth pixel has: A first transistor, the first transistor having an oxide semiconductor layer, a gate electrode opposite to the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode; The first transparent conductive layer overlaps with the gate electrode and the oxide semiconductor layer when viewed from above, and is in contact with the oxide semiconductor layer in a first contact area that does not overlap with the gate electrode; as well as The second transparent conductive layer, when viewed from above, overlaps with the gate electrode, the oxide semiconductor layer, and the first transparent conductive layer, and is connected to the first transparent conductive layer in the second contact region overlapping with the gate electrode. The first pixel and the third pixel are adjacent to each other, and the second pixel and the fourth pixel are adjacent to each other. The second transparent conductive layer of the first pixel overlaps with the oxide semiconductor layer of the first pixel and the oxide semiconductor layer of the second pixel, and also overlaps with the oxide semiconductor layer of the fourth pixel.

38. The display device according to claim 37, characterized in that, The oxide semiconductor layer is formed into a strip shape that intersects with the gate electrode. One end of the oxide semiconductor layer of the first pixel and the second pixel is connected to the first wiring along its long side, and the other end of the oxide semiconductor layer is connected to the first transparent conductive layer. One end of the oxide semiconductor layer of the third and fourth pixels is connected to the second wiring along its long side, and the other end of the oxide semiconductor layer is connected to the first transparent conductive layer.

39. The display device according to claim 38, characterized in that, The first transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side, the width of the first transparent conductive layer is smaller than the width of the oxide semiconductor layer.

40. The display device according to claim 39, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

41. The display device according to claim 38, characterized in that, The second transparent conductive layer is formed as a strip extending in the same direction as the oxide semiconductor layer. In a direction orthogonal to the long side direction, the width of the second transparent conductive layer is larger than the width of the oxide semiconductor layer.

42. The display device according to claim 37, characterized in that, In each pixel from the first pixel to the fourth pixel The first transparent conductive layer is formed as a strip extending along the first wiring or the second wiring. In a direction orthogonal to the long side of the first transparent conductive layer, the width of the opening forming the second contact area is larger than the width of the first transparent conductive layer.

43. The display device according to claim 37, characterized in that, In each pixel from the first pixel to the fourth pixel The second transparent conductive layer is formed as a strip extending along the first or second wiring. When viewed from above, the entire first transparent conductive layer overlaps with the second transparent conductive layer.

44. The display device according to claim 37, characterized in that, The second transparent conductive layer of each pixel from the first pixel to the fourth pixel is opposite to the common electrode through an insulating film.

45. The display device according to claim 44, characterized in that, The common electrode has a slit at a position opposite to the second transparent conductive layer of each of the first to fourth pixels.

46. ​​The display device according to claim 44, characterized in that, The common electrode is connected to a common auxiliary electrode made of metal.

47. The display device according to claim 46, characterized in that, The common auxiliary electrode is connected to the common electrode in the second contact area.

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