Apparatus and method for low latency memory access

Abstract

The present disclosure provides a storage device, an access method of the storage device, and a storage medium. The storage device includes a plurality of storage blocks, each of which includes a plurality of storage cells; a word line communicatively coupled with the plurality of storage blocks and configured to activate storage cells associated with the word line in the plurality of storage blocks; a column selection line communicatively coupled with the plurality of storage blocks and configured to select a column of storage blocks in the plurality of storage blocks; a global data line communicatively coupled with the plurality of storage blocks and configured to transceive data with the selected column of storage blocks; a first switch disposed at a first position on the column selection line; and a second switch disposed at a second position on the global data line, wherein the first switch and the second switch are configured to partition at least one storage block in the plurality of storage blocks from other storage blocks in the plurality of storage blocks. The present disclosure reduces access latency of the storage device.

Description

[0001] Cross-reference to related applications

[0002] This disclosure claims priority to U.S. Patent Application No. 16 / 789,382, filed February 12, 2020, which is incorporated herein by reference. Background Technology

[0003] Random access memory (RAM) consists of multiple memory blocks. These memory blocks can be accessed via signal lines (e.g., bit lines, word lines, data lines, etc.). The signal lines transmit and receive signals / data along with the multiple memory blocks through the voltage on the signal lines.

[0004] To reduce the cost per bit of RAM, signal lines can be lengthened to link more memory blocks. However, signal lines have associated parasitic capacitance, which is proportional to the length of the signal line. Therefore, while lengthening signal lines to reduce the cost per bit, the associated parasitic capacitance also increases. With the increase in associated parasitic capacitance, it takes more time to change the potential on the signal line to the target potential. This, in turn, increases the latency of the RAM. Summary of the Invention

[0005] Embodiments of this disclosure provide a storage device. The storage device may include: a plurality of storage blocks, each storage block including a plurality of storage cells; a word line, communicatively coupled to the plurality of storage blocks and configured to activate storage cells associated with the word line in the plurality of storage blocks; a column select line, communicatively coupled to the plurality of storage blocks and configured to select a column of storage blocks among the plurality of storage blocks; a global data line, communicatively coupled to the plurality of storage blocks and configured to transmit and receive data together with the selected column of storage blocks; a first switch disposed at a first position on the column select line; and a second switch disposed at a second position on the global data line, wherein the first switch and the second switch are configured to separate at least one of the plurality of storage blocks from the other storage blocks in the plurality of storage blocks.

[0006] Embodiments of this disclosure also provide a method for accessing a storage device, wherein the storage device includes: a column select line having a first switch thereon; and a global data line having a second switch thereon. The method may include: receiving an access request for accessing the storage device, the storage device including a plurality of storage blocks; determining whether the access request is directed to a region having at least one of the plurality of storage blocks; in response to the access request being directed to the region, generating a first type of access signal based on the access request to deactivate the first switch and the second switch, thereby separating the at least one storage block from the other storage blocks in the plurality of storage blocks; and accessing the separated at least one storage block based on the first type of access signal.

[0007] Embodiments of this disclosure also provide a non-transitory computer-readable medium storing a set of instructions executable by one or more processors of a computer system to cause the computer system to perform a method for accessing a storage device. The storage device may include: a column select line having a first switch thereon; and a global data line having a second switch thereon. The method may include: receiving an access request for accessing the storage device, the storage device including a plurality of storage blocks; determining whether the access request is directed to a region having at least one of the plurality of storage blocks; in response to the access request being directed to the region, generating a first type of access signal based on the access request to deactivate the first and second switches to separate the at least one storage block from the other storage blocks of the plurality of storage blocks; and accessing the separated at least one storage block based on the first type of access signal.

[0008] It should be understood that, as described above, the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the embodiments of this disclosure. Attached Figure Description

[0009] Embodiments and aspects of this disclosure are illustrated in the following detailed description and accompanying drawings. The various features shown in the figures are not drawn to scale.

[0010] Figure 1A A schematic diagram of an exemplary storage block according to some embodiments of the present disclosure is shown.

[0011] Figure 1B A schematic diagram of a dynamic random access memory (DRAM) according to some embodiments of the present disclosure is shown.

[0012] Figure 2 A schematic diagram of an exemplary storage device according to some embodiments of the present disclosure is shown.

[0013] Figure 3 A schematic diagram of another exemplary storage device according to some embodiments of the present disclosure is shown.

[0014] Figure 4 A flowchart illustrating an exemplary method for accessing a storage device according to some embodiments of the present disclosure is shown.

[0015] Figure 5 An exemplary storage system according to some embodiments of the present disclosure is shown. Detailed Implementation

[0016] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein the same numbers in different drawings denote the same or similar elements unless otherwise stated. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Rather, they are merely examples of apparatuses and methods consistent with aspects related to embodiments of this disclosure as described in the appended claims.

[0017] As used herein, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, composition, article, or apparatus that includes a list of elements may include not only those elements but also other elements not expressly listed or inherent to such a process, method, composition, article, or apparatus. The term “exemplary” is used in the sense of “example” rather than “ideal.”

[0018] To address the increased latency of RAM, embodiments of this disclosure provide a storage device. In some embodiments, the storage device may provide a first switch at a first location on the column select line and a second switch at a second location on the global data line. The first and second switches are configured to separate at least one memory block from the other memory blocks in response to a fast access signal. Therefore, by reducing the access latency of the storage device, the column select line and the global data line, which serve as signal lines, can be shortened. In another embodiment, the storage device may also provide a third switch on the data bus. The third switch is configured to disconnect the data bus in response to a fast access signal. Therefore, by further reducing the access latency of the storage device, the data bus can also be shortened.

[0019] The embodiments of this disclosure can be applied to various types of memory, such as dynamic random access memory (DRAM), phase change memory (PCM), and resistive random-access memory (ReRAM). DRAM will be used only as an example to illustrate embodiments of this disclosure.

[0020] Figure 1A A schematic diagram of an exemplary storage block 100 according to some embodiments of the present disclosure is shown.

[0021] Storage block 100 may include multiple storage cells 110 electrically connected to multiple word lines 1002 and multiple bit lines 1004. Typically, each column storage cell may be connected to the same word line, and each row storage cell may be connected to the same data line. It can be understood that a word line can be a row line, and a data line can be a column line. For clarity, Figure 1AOnly exemplary word lines and exemplary data lines are shown. Storage cell 110 may include capacitor 112 and transistor 114. One bit of data may be represented by the charge stored in capacitor 112.

[0022] A column of memory cells 110 can be selected via word line 1002, which allows connection between bit line 1004 and capacitor 112. For example, by applying a high potential to transistor 114 via word line 1002, transistor 114 can connect capacitor 112 to bit line 1004. Therefore, the charge stored in capacitor 112 can cause a potential change on bit line 1004. Thus, by increasing the potential of word line 1002, a row of memory cells can be connected to the bit line corresponding to that row of memory cells.

[0023] A sense amplifier 1006 can be connected to bit line 1004 to sense or induce potential changes on bit line 1004. For example, when reading a memory cell, sense amplifier 1006 can be used to sense potential changes on bit line 1004 caused by capacitor 112 and can process the sensed potential changes to generate a "0" or "1". In other words, when a word line is selected, data in the corresponding cell is fed to the sense amplifier through the corresponding bit line. Similarly, when writing a memory cell, potential changes on bit line 1004 can be used to charge or deplete the memory capacitor. For example, bit line 1004 can be charged or depleted by sense amplifier 1006 to further charge or deplete capacitor 112 of memory cell 110.

[0024] The selection of a column of memory cells by word lines and the sensing or inducing of potential changes by a sensing amplifier can also be referred to as the activation phase.

[0025] The sensing amplifier 1006 can also be connected to the data line to further sense or drive the data line through potential changes on the data line. A column of memory (and the memory cells within it) can be selected via a column selection line (CSL), such that the sensing amplifier of the selected column of memory, including the selected memory cells, senses or drives the data line 106. The data line 106 ultimately transmits and receives data via the data bus and the I / O interface of the dynamic random access memory (DRAM). This process can also be referred to as the input / output (I / O) stage. DRAM, the data bus, and the data line will be further explained below.

[0026] After the input / output phase, the potential of the boosted word line 1002 can be reduced, thereby disconnecting a column of memory cells from the bit line 1004. Simultaneously, the sense amplifier (e.g., sense amplifier 1006) and bit line (e.g., bit line 1004) corresponding to the column of memory cells can be initialized. This process can also be referred to as the pre-charge phase.

[0027] Figure 1B A schematic diagram of an exemplary dynamic random access memory (DRAM) 1000 according to some embodiments of the present disclosure is shown. The DRAM 1000 can be used by any computing system, such as a personal computer, cloud server, mobile device, processor-in-memory (PIM) device, etc.

[0028] like Figure 1B As shown, DRAM 1000 may include Figure 1A The system includes multiple memory blocks 100 (e.g., 100a, 100b, 100c, 100d, 100e, 100f, etc.), a controller 102, multiple column select lines 104, multiple data lines 106, and a data bus 108. The memory blocks may be part of a memory stack and include, as referenced... Figure 1A The aforementioned multiple storage units and sensing amplifier.

[0029] The controller 102 may be communicatively coupled to the column select line 104, the data line 106, and the data bus 108. In some embodiments, the controller 102 may generate an access signal based on an access request for accessing the DRAM 1000.

[0030] Column select line 104 is communicatively coupled to controller 102 and multiple memory blocks 100, and is used to select a column of memory blocks 100 for sending and receiving data. A column of memory blocks 100 can be selected based on the address of the memory to be accessed. For example, based on an access request, controller 102 can determine the memory block to be accessed and send an access signal to select the column select line 104 corresponding to the access request. It is understood that each memory block can further decode the access signal to determine the address of the memory cell corresponding to the access request. Therefore, the corresponding memory cell can be selected via column select line 104, and the data of the corresponding memory cell can be transmitted to the data line.

[0031] Data line 106 can be communicatively coupled to data bus 108 and multiple memory blocks 100, and is used for further sending and receiving data with a selected column of memory blocks. Data line 106 can also be referred to as a global data line. (See reference...) Figure 1A The data line discussed can transmit and receive data together with the storage unit. Therefore, by using the data line, data corresponding to the storage unit can be transmitted and received together with the data bus 108.

[0032] Data bus 108 may include other logic, such as pads, interfaces, etc. Data bus 108 can be connected to data line 106 to transmit and receive data together. For example, when reading DRAM 1000, data line 106 can send data to data bus 108, and data bus 108 can further send data to the input / output (I / O) interface of DRAM 1000 (not shown). When writing to DRAM 1000, data bus 108 can transfer data received from the I / O interface to data line 106, and data line 106 can further change the state of the capacitors in the memory cells through the potential on data line 106.

[0033] To reduce the cost per bit of DRAM, the conductors (e.g., column select line 104, data line 106, and data bus 108) can be lengthened to link more memory blocks. However, conductors have associated parasitic capacitances that are proportional to their length. Therefore, when conductors are lengthened to reduce the cost per bit, the associated parasitic capacitance increases proportionally. With the increase in associated parasitic capacitance, it takes more time to induce a potential change on the conductors, which further increases the latency of the DRAM.

[0034] Embodiments of this disclosure provide storage devices and methods for low-latency memory access.

[0035] Figure 2 A schematic diagram of an exemplary storage device 2000 according to some embodiments of the present disclosure is shown.

[0036] like Figure 2 As shown, storage device 2000 may include multiple storage blocks 200, controller 202, column select line 204, global data line 206, and the functions of all these components are consistent with reference to Figures 1A-1B The corresponding components described herein have similar functions. Therefore, for clarity, the description of the multiple storage blocks 200, column select line 204, global data line 206, and controller 202 is omitted here. The storage device 2000 may also include a switch 212 disposed at a given position on the column select line 204 and a switch 214 disposed at another given position on the global data line 206.

[0037] Switches 212 and 214 can be disconnected to interrupt column select line 204 and global data line 206, respectively. For example, switches 212 and 214 can be disconnected in response to a fast access signal generated by controller 202.

[0038] By interrupting column select line 204 by switch 212, column select line 204 is divided into isolated select lines (by...). Figure 2 The thin lines in the text represent the selection lines (represented by the selected lines). Figure 2 (The bold lines in the text indicate this). See reference. Figure 1B As discussed, before switch 212 is opened, the entire column select line 204 can be connected to controller 202. After switch 212 is opened, a portion of the column select line 204 between controller 202 and switch 212 remains connected to controller 202, and is therefore referred to as the connected select line. The connected select line can be connected to at least one memory block. Figure 2 As shown, block 200a is connected to the connected select line, therefore, block 200a can still be selected by controller 202 via the connected select line. It can be understood that, depending on the position of switch 212, controller 202 can select more than one memory block via the connected select line. On the other hand, after switch 212 is opened, a portion of column select line 204 (i.e., the elongated portion of column select line 204) loses its connection to controller 202; therefore, this portion of column select line 204 is referred to as the isolated select line. Thus, when switch 212 is opened, only a portion of column select line 204 is connected to controller 202, and column select line 204 is "shortened." Consequently, the associated parasitic capacitance of column select line 204 is also reduced, resulting in a reduction in delay on column select line 204.

[0039] Similarly, by disconnecting the global data line 206 via switch 214, the global data line 206 is divided into isolated data lines (by...). Figure 2 The thin lines in the diagram represent the data lines (represented by the thin lines in the diagram) and the connected data lines (represented by the thin lines in the diagram). Figure 2 (The bold lines in the text indicate this). See reference. Figure 1B Before switch 214 is opened, the entire conductor of global data line 206 is connected to data bus 208. After switch 214 is opened, a portion of global data line 206 between data bus 208 and switch 214 remains connected to data bus 208, and is therefore referred to as the connected data line. The connected data line can be connected to at least one memory block. Figure 2 As shown, block 200a is connected to the connected data line, therefore, block 200a can still send and receive data with the data bus 208 through the connected data line. It can be understood that, depending on the position of switch 214, more than one memory block can be connected to the data bus 208 through the connected data line. On the other hand, after switch 214 is opened, a portion of the global data line 206 (i.e., the elongated portion of the global data line 206) loses its connection to the data bus 208, and is therefore referred to as an isolated data line. Therefore, when switch 214 is opened, only a portion of the global data line 206 is connected to the data bus 208, thus the global data line 206 is "shortened". Consequently, the associated parasitic capacitance of the global data line 206 is also reduced, resulting in a reduction in latency on the global data line 206.

[0040] Switches 212 and 214, and the data bus 208 can separate at least one memory block (e.g., memory block 200a) of the plurality of memory blocks 200 from the other memory blocks of the plurality of memory blocks 200. Switches 212 and 214 can enable the separated at least one memory block to serve as a fast-access area relative to the other memory blocks. Figure 2 As shown, the connected select line and the connected data line can serve as the two boundaries of the fast access region 210, and switches 212 and 214 are the two corners of the fast access region 210. It should be understood that, based on the positions of switches 212 and 214 in the storage device 2000, more than one storage block can be included in the fast access region 210.

[0041] Figure 3 A schematic diagram of another exemplary storage device 3000 according to some embodiments of the present disclosure is shown.

[0042] In storage device 3000, with Figure 2 Compared to storage device 2000, switch 314 on column select line 204 is positioned near storage block 200b. Therefore, the fast access region 310, divided by switches 214 and 314, may include storage blocks 200a and 200b. Controller 202 may receive an access request for accessing fast access region 210 or 310 and generate a fast access signal based on the access request. The fast access signal may disconnect the switches to enable fast access region 210 or 310. For example, when reading storage device 3000, controller 202 may receive a request to read data stored, for example, in storage block 200b, and may generate a fast access signal to disconnect switches 214 and 314. Similarly, when writing to storage device 3000, controller 202 may receive a request to write data to, for example, storage block 200b, and may generate another fast access signal to disconnect switches 214 and 314. Access methods for storage devices according to some embodiments of this disclosure will be further described below.

[0043] Since the latency of column select line 204 and data line 206 can be reduced by disconnecting the switch, the access speed of memory cells in fast access area 210 or 310 can be improved.

[0044] In some embodiments, in addition to switches 214 and 314, the storage device 3000 may also include a switch 318 disposed at a given position on the data bus 208. It is understood that the given position of switch 318 may correspond to the position of switch 314 on the column select line 204.

[0045] After switch 318 is opened, a portion of the data bus 208 located between the input / output interface and switch 318 remains connected, while the rest of the data bus 208 loses its connection to the input / output interface. Therefore, when switch 318 is opened, only a portion of the data bus 208 is connected to the input / output interface, thus the data bus 208 is "shortened." Consequently, the associated parasitic capacitance of the data bus 208 is also reduced, resulting in a reduction in delay on the data bus 208. It is understood that switch 318 can also be opened in response to a fast access signal.

[0046] By providing a switch 318 on the data bus 208, the latency of the data bus 208 can be reduced by disconnecting the switch 318, thereby further improving the access speed of the memory cells in the fast access area 310.

[0047] It should be understood that in some embodiments, in addition to switch 314, other switches may be retained. Figure 2 Switch 212. Therefore, the fast access area 310 itself can also be configurable. For example, when switch 212 is closed and switches 214 and 314 are open, the fast access area 310 may include blocks 200a and 200b. In another example, when switches 212 and 214 are open, the fast access area 310 may only include block 200a, regardless of whether switch 314 is closed or open.

[0048] Figure 4 This is a flowchart of an exemplary storage device access method 400 according to some embodiments of the present disclosure. The storage device may include, for example, the above-described reference... Figures 2-3 The storage device is 2000 or 3000. Therefore, the storage device may include a column select line having a first switch disposed thereon and a global data line having a second switch disposed thereon. Method 400 may be implemented by the storage device (e.g., a controller of the storage device) and includes the following steps.

[0049] In step 402, the controller (e.g., controller 202) may receive an access request for accessing the storage device. The access request may include a request to read data stored in the storage device or a request to write data to the storage device.

[0050] In step 404, the controller may determine whether the access request is directed to a fast access region defined based on the first and second switches. In some embodiments, the controller may parse the access request and determine the access address associated with the access request. For example, when the access request is a read request, the controller may parse the read request and determine the address of the memory block to be read. The controller may then determine whether the access address is within the fast access region. As discussed above, the first and second switches on the column select line and the global data line may define a fast access region including at least one memory block, and therefore, the fast access region may also provide the address of the at least one memory block. For example, the address of the at least one memory block in the fast access region may be stored in a table. Therefore, the controller may determine whether the access address is within the fast access region by comparing the access address with the table. In response to the access address being within the fast access region, the controller may determine that the access request is directed to the fast access region.

[0051] In some embodiments, the access request may further include an indicator field. The indicator field can be used to indicate whether the access request is directed to a fast access area. For example, when the indicator field is assigned the value "1", it can indicate that the access request is directed to a fast access area. Therefore, the controller can determine whether the indicator field meets a given condition (e.g., the indicator field is "1"), and in response to the indicator field meeting the given condition, the controller can determine that the access request is directed to a fast access area.

[0052] In step 406, in response to the access request being directed to the fast access region, the controller may generate a fast access signal based on the access request to deactivate the first and second switches. In some embodiments, the first and second switches may be field-effect transistors (FETs), and the fast access signal may include a "turn-off" signal applied to turn off the FETs. It is understood that, in addition to the "turn-off" signal, the fast access signal may also include other instructions to cause the storage device to perform the requested action (e.g., read / write data). Method 400 may then proceed to step 410.

[0053] In step 408, in response to the access request not being directed to the fast access region, the controller may generate a regular access signal. The regular access signal may include regular instructions for memory access. In some embodiments, the difference between the fast access signal and the regular access signal is the aforementioned "off" signal. Therefore, in the case of a regular access signal, both the first and second switches may remain closed.

[0054] In step 410, the controller may perform access to the storage device based on a fast access signal or a regular access signal.

[0055] In some embodiments, the storage device may further include a data bus with a third switch disposed thereon. Similarly, a fast access signal may also cause the third switch to be turned off.

[0056] Figure 5 An exemplary storage system 500 according to some embodiments of the present disclosure is shown. The storage system 500 may include the aforementioned storage device and perform the described methods. Figure 5 As shown, the storage system 500 may include a processor 501 and a storage device 502.

[0057] Processor 501 may be a computational processor that executes memory generation commands for storage device 502. In some embodiments, processor 501 may include a command scheduler for scheduling memory commands according to instructions received from a compiler.

[0058] Storage device 502 may be a DRAM device and may store data and instructions. These instructions may be part of a computational program that accesses the data stored in storage device 502. Storage device 502 may include multiple storage blocks, each storage block having multiple rows for storing data. Depending on the size of the data elements, each row of a storage block may store one or more data elements.

[0059] Storage system 500 may also include compiler 503. Compiler 503 can run on a processing unit. The processing unit may be an external processing unit (e.g., a host CPU) or component of storage system 500. Compiler 503 can compile computational programs (e.g., machine learning programs) into instruction sets, such as "read" instructions, "write" instructions, "copy" instructions, "allocate" instructions, etc. It is understood that "copy" instructions may include both "read" and "write" instructions, both of which can be associated with a request to allocate storage space in storage device 502. Furthermore, the "allocate" instruction itself may be a request to allocate storage space in storage device 502.

[0060] The processor 501 can then process the generated instructions (e.g., "write" instructions, "copy" instructions, "allocate" instructions). The processor 501 may include a processing pipeline 504, an instruction buffer 506, an execution management unit 508, and a memory management unit (MMU) 510. Each unit and buffer may include a set of combinational and sequential logic circuits constructed based on, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). The execution management unit 508 can control and manage the execution of instructions through the processing pipeline 504. For example, after receiving (e.g., from the operating system) an instruction to execute a computational program (including, for example, a memory allocation request), the execution management unit 508 can create a computational process that can provide indications of the computational program's execution status through the processing pipeline 504. After the computing process is created, the execution management unit 508 can load the computing program from an auxiliary storage device (such as a hard disk drive) into the storage device 502 and control the instruction buffer 506 to retrieve the instruction set associated with the computing program from the storage device 502.

[0061] The instruction set can be stored and executed according to the sequence reflected in the computation program. For example, such as Figure 5 As shown, the instruction buffer 506 includes a buffer head pointer and a buffer tail pointer. Under the control of the execution management unit 508, the instruction buffer 506 can fetch instructions stored at the buffer position associated with the buffer head pointer and deliver them to the processing pipeline 504 for execution. When the instruction is executed, the processing pipeline 504 can access the storage device 502 to send or receive data according to the instruction. After fetching the instruction, the instruction buffer 506 can remove the instruction from the buffer and move the buffer head pointer to the next buffer position to fetch the next instruction for execution.

[0062] The execution management unit 508 can control instruction fetching through the instruction buffer 506 based on various criteria. For example, the execution management unit 508 can determine whether an instruction will cause an exception. An exception occurs when the execution of an instruction could lead to improper or abnormal operation of the computer processor. As an illustrative example, an "allocate" instruction in a computing program could cause the processor 501 to access a storage location that does not exist in the storage device 502, or to access a storage location that the processor 501 does not have access permission for.

[0063] MMU 510 allocates and manages storage space for different computing processes. After the execution management unit 508 creates a computing process for executing a computing program, MMU 510 can allocate a set of device storage locations in storage device 502, where each storage location is associated with a device address. MMU 510 can also create virtual storage spaces and provide them as aliases to the set of physical storage locations for the computing process. A virtual storage space can include a set of pages, and each page can include a set of contagious virtual storage locations. Each virtual storage location can be associated with a virtual storage address and can be mapped to a device storage location allocated by MMU 510. A page typically contains 4096 bytes of storage space.

[0064] In some embodiments, processor 501 may determine whether a memory command is directed to a fast access region. If a memory command is directed to a fast access region, processor 501 may further generate a signal for disconnecting a switch associated with the fast access region.

[0065] In some embodiments, a computer program product may include a non-transitory computer-readable storage medium having computer-readable program instructions thereon to cause one or more processors to perform the methods described above. For example, one or more processors of a computing system may execute the computer-readable program instructions to compile instructions that cause the storage device to implement the methods described above.

[0066] A computer-readable storage medium can be a tangible device capable of storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory cards, floppy disks, mechanical encoding devices (e.g., punched cards or protrusions in recesses having instructions recorded thereon), and any suitable combination of the foregoing.

[0067] The computer-readable program instructions used to perform the above methods can be assembly instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​and conventional procedural programming languages). The computer-readable program instructions can be executed entirely on the computing device as a standalone software package, or partially on the first computing device and partially on a second computing device located remotely from the first computing device. In the latter case, the remote second computing device can be connected to the first computing device via any type of network, including local area networks (LANs) or wide area networks (WANs).

[0068] Computer-readable program instructions may be provided to one or more processors of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute through one or more processors of a computer or other programmable data processing apparatus, create means for implementing the methods described above.

[0069] When implemented, embodiments of this disclosure can provide significant improvements over conventional designs. For example, when comparing a conventional design with a memory structure using memory blocks to a similar memory structure utilizing embodiments of this disclosure, the latency in the conventional system is approximately twice that in the column select line and data bus, and approximately four times that in the global data line. Therefore, embodiments of this disclosure can significantly reduce the latency of the storage device. It is understood that the reduction in latency can be related to the size of the fast access region, and the result can vary depending on the parameters of the storage device.

[0070] Although the above embodiments utilize a pair of switches on the global data line and column select line to implement a device and method for low-latency memory access, more pairs of switches can be provided to offer the flexibility to define multiple fast access regions.

[0071] According to various embodiments of this disclosure, the flowcharts and diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products. In this regard, blocks in flowcharts or diagrams may represent software programs, code segments, or portions of code, including one or more executable instructions for implementing a specific function. It should also be noted that in some alternative implementations, the functions marked in the blocks may differ in order from those marked in the drawings. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or sometimes in reverse order, depending on the functions involved. It will also be noted that each block in a diagram or flowchart, as well as combinations of blocks in diagrams and flowcharts, may be implemented by a system based on dedicated hardware or a combination of dedicated hardware and computer instructions that performs the specified function or action.

[0072] Embodiments of this disclosure are further described using the following claims:

[0073] 1. A storage device, comprising:

[0074] Multiple storage blocks, each storage block comprising multiple storage units;

[0075] A word line, communicatively coupled to the plurality of memory blocks, and configured to activate a memory cell in the plurality of memory blocks associated with the word line;

[0076] A column selection line, communicatively coupled to the plurality of storage blocks, is configured to select a column of storage blocks from the plurality of storage blocks;

[0077] A global data line, communicatively coupled to the plurality of storage blocks, is configured to send and receive data together with the activated storage cells in the selected column of storage blocks;

[0078] A first switch is set at a first position on the column selection line; and

[0079] A second switch is disposed at a second position on the global data line, wherein the first switch and the second switch are configured to separate at least one of the plurality of memory blocks from the other memory blocks.

[0080] 2. The storage device of claim 1, wherein the first switch and the second switch cause the at least one partitioned storage block to serve as a fast access region relative to the other storage blocks.

[0081] 3. The storage device according to claim 1 or 2, further comprising:

[0082] A data bus, connected to the global data line and configured to transmit and receive data together with the global data line, wherein the data bus further includes a third switch disposed at a third position corresponding to the second position.

[0083] 4. The storage device according to claim 3, further comprising:

[0084] The controller is communicatively coupled to the column select line and the global data line.

[0085] 5. The storage device according to claim 4, wherein the controller is further configured to:

[0086] Receive an access request for accessing the fast access area; and

[0087] A fast access signal is generated based on the access request.

[0088] 6. The storage device of claim 5, wherein, in separating at least one of the plurality of storage blocks from the other storage blocks, the first switch is configured to, in response to the fast access signal, disconnect the column select line to form a connected column select line and a disconnected column select line; and,

[0089] The second switch is configured to disconnect the global data line in response to the fast access signal, thus forming a connected global data line and a disconnected global data line.

[0090] 7. The storage device of claim 6, wherein, in response to the fast access signal, the third switch is configured to disconnect the data bus to form a connected data bus and a disconnected data bus.

[0091] 8. The storage device of claim 7, wherein the parasitic capacitance associated with the connected column select line, the connected global data line, and the connected data bus is smaller than the parasitic capacitance of the column select line, the global data line, and the data bus, thereby reducing latency on the connected column select line, the connected global data line, and the connected data bus, wherein the connected column select line, the connected global data line, and the connected data bus form the fast access region.

[0092] 9. The storage device of claim 5, wherein the access request includes a request to read data stored in the storage device or a request to write data to the storage device.

[0093] 10. The storage device according to any one of claims 1-9, wherein the first switch and the second switch comprise field-effect transistors.

[0094] 11. A method for accessing a storage device, wherein the storage device includes a column select line having a first switch disposed thereon and a global data line having a second switch disposed thereon, the access method comprising:

[0095] Receive an access request for accessing the storage device, which has multiple storage blocks;

[0096] Determine whether the access request is directed to a region having at least one of the plurality of storage blocks;

[0097] In response to the access request being directed to the region, a first type of access signal is generated based on the access request to deactivate the first switch and the second switch, thereby separating the at least one storage block from the other storage blocks of the plurality of storage blocks; and

[0098] Access the at least one segmented storage block based on the first type of access signal.

[0099] 12. The access method according to claim 11, further comprising:

[0100] In response to the access request not being directed to the area, a second type of access signal is generated; and

[0101] Access the plurality of storage blocks based on the second type of access signal.

[0102] 13. The access method according to claim 11 or 12, wherein determining whether the access request is directed to the area further includes:

[0103] Determine the access address associated with the access request;

[0104] Determine whether the access address is within the region;

[0105] In response to the fact that the access address is located within the region, it is determined that the access request is directed to the region.

[0106] 14. The access method according to claim 11 or 12, wherein the access request further includes an indication field, and determining whether the access request is directed to the area further includes:

[0107] Determine whether the indicated field meets the given conditions;

[0108] In response to the indication field satisfying the given condition, it is determined that the access request is directed to the region.

[0109] 15. The access method according to any one of claims 11-14, wherein the storage device further includes a data bus having a third switch disposed thereon, and the first type of access signal further causes the third switch to be turned off.

[0110] 16. The access method according to any one of claims 11-15, wherein the access request for accessing the storage device includes a request to read data stored in the storage device or a request to write data to the storage device.

[0111] 17. A non-transitory computer-readable medium storing a set of instructions, the set of instructions being executed by one or more processors of a computer system, causing the computer system to perform a method for accessing a storage device of the computer system, wherein the storage device includes a column select line having a first switch disposed thereon and a global data line having a second switch disposed thereon, the access method comprising:

[0112] Receive an access request for accessing the storage device, which has multiple storage blocks;

[0113] Determine whether the access request is directed to a region having at least one of the plurality of storage blocks;

[0114] In response to the access request being directed to the region, a first type of access signal is generated based on the access request to deactivate the first switch and the second switch, thereby separating the at least one storage block from the other storage blocks of the plurality of storage blocks; and

[0115] Access the at least one segmented storage block based on the first type of access signal.

[0116] 18. The non-transitory computer-readable medium of claim 17, wherein the one or more processors are configured to execute the set of instructions to further cause the computer system to perform:

[0117] In response to the access request not being directed to the area, a second type of access signal is generated; and

[0118] Access the plurality of storage blocks based on the second type of access signal.

[0119] 19. The non-transitory computer-readable medium of claim 17 or 18, wherein, upon determining whether the access request is directed to the region, the one or more processors are configured to execute the set of instructions to further cause the computer system to perform:

[0120] Determine the access address associated with the access request;

[0121] Determine whether the access address is within the region;

[0122] In response to the fact that the access address is located within the region, it is determined that the access request is directed to the region.

[0123] 20. The non-transitory computer-readable medium of claim 17 or 18, wherein the access request further includes an indication field, and in determining whether the access request is directed to the region, the one or more processors are configured to execute the set of instructions to further cause the computer system to perform:

[0124] Determine whether the indicated field meets the given conditions;

[0125] In response to the indication field satisfying the given condition, it is determined that the access request is directed to the region.

[0126] 21. The non-transitory computer-readable medium according to any one of claims 17-20, wherein the storage device further includes a data bus having a third switch disposed thereon, and the first type of access signal further causes the third switch to be turned off.

[0127] 22. A non-transitory computer-readable medium according to any one of claims 17-21, wherein an access request for accessing the storage device includes a request to read data stored in the storage device or a request to write data to the storage device.

[0128] It should be understood that, for clarity, certain features of this disclosure described in the context of different embodiments may also be provided in combination in a single embodiment. Conversely, for brevity, various features of this disclosure described in the context of a single embodiment may also be provided separately, or in any suitable sub-combination, or in any other described embodiment of the appropriate disclosure. Certain features described in the context of various embodiments should not be considered as essential features of those embodiments unless the embodiment cannot be practiced without those elements.

Claims

1. A storage device, comprising: Multiple storage blocks, each storage block comprising multiple storage units; A word line, communicatively coupled to the plurality of memory blocks, and configured to activate a memory cell in the plurality of memory blocks associated with the word line; A column selection line, communicatively coupled to the plurality of storage blocks, is configured to select a column of storage blocks from the plurality of storage blocks; A global data line, communicatively coupled to the plurality of storage blocks, is configured to send and receive data together with the activated storage cells in the selected column of storage blocks; The first switch is set at the first position on the column selection line; as well as A second switch is disposed at a second position on the global data line, wherein the first switch and the second switch are configured to separate at least one of the plurality of memory blocks from the other memory blocks in the plurality of memory blocks; The first switch and the second switch enable the at least one partitioned storage block to be used as a fast access region relative to the other storage blocks.

2. The storage device according to claim 1, wherein, Also includes: A data bus, connected to the global data line and configured to transmit and receive data together with the global data line, wherein the data bus further includes a third switch disposed at a third position corresponding to the second position.

3. The storage device according to claim 2, wherein, Also includes: The controller is communicatively coupled to the column select line and the global data line.

4. The storage device according to claim 3, wherein, The controller is also configured to: Receive an access request for accessing the fast access area; and A fast access signal is generated based on the access request.

5. The storage device according to claim 4, wherein, In separating at least one of the plurality of memory blocks from the other memory blocks, the first switch is configured to, in response to the fast access signal, disconnect the column select line to form a connected column select line and a disconnected column select line; as well as, The second switch is configured to disconnect the global data line in response to the fast access signal, thus forming a connected global data line and a disconnected global data line.

6. The storage device according to claim 5, wherein, In response to the fast access signal, the third switch is configured to disconnect the data bus to form a connected data bus and a disconnected data bus.

7. The storage device according to claim 6, wherein, The parasitic capacitance associated with the connected column select line, the connected global data line, and the connected data bus is smaller than the parasitic capacitance of the column select line, the global data line, and the data bus. This reduces the latency on the connected column select line, the connected global data line, and the connected data bus, which form the fast access area.

8. The storage device according to claim 4, wherein, The access request includes a request to read data stored in the storage device or a request to write data to the storage device.

9. The storage device according to claim 1, wherein, The first switch and the second switch include field-effect transistors.

10. A method for accessing a storage device, the storage device including a column select line having a first switch disposed thereon and a global data line having a second switch disposed thereon, the access method comprising: Receive an access request for accessing the storage device, which has multiple storage blocks; Determine whether the access request is directed to a region having at least one of the plurality of storage blocks; In response to the access request being directed to the area, a first type of access signal is generated based on the access request to disconnect the first switch and the second switch to separate the at least one storage block from the other storage blocks of the plurality of storage blocks; as well as Access the at least one segmented storage block based on the first type of access signal; The first switch and the second switch enable the at least one partitioned storage block to be used as a fast access region relative to the other storage blocks.

11. The access method according to claim 10, wherein, Also includes: In response to the access request not being directed to the area, a second type of access signal is generated; as well as Access the plurality of storage blocks based on the second type of access signal.

12. The access method according to claim 10, wherein, Determining whether the access request is directed to the region further includes: Determine the access address associated with the access request; Determine whether the access address is within the region; In response to the fact that the access address is located within the region, it is determined that the access request is directed to the region.

13. The access method according to claim 10, wherein, The access request also includes an indication field, and determining whether the access request is directed to the region further includes: Determine whether the indicated field meets the given conditions; In response to the indication field satisfying the given condition, it is determined that the access request is directed to the region.

14. The access method according to claim 10, wherein, The storage device also includes a data bus with a third switch disposed thereon, and the first type of access signal further causes the third switch to be turned off.

15. The access method according to claim 10, wherein, Access requests for the storage device include requests to read data stored in the storage device or requests to write data to the storage device.

16. A non-transitory computer-readable storage medium storing a set of instructions, the set of instructions being executed by one or more processors of a computer system, causing the computer system to perform a method for accessing a storage device of the computer system, wherein... The storage device includes a column select line with a first switch disposed thereon and a global data line with a second switch disposed thereon, and the access method includes: Receive an access request for accessing the storage device, which has multiple storage blocks; Determine whether the access request is directed to a region having at least one of the plurality of storage blocks; In response to the access request being directed to the region, a first type of access signal is generated based on the access request to deactivate the first switch and the second switch, thereby separating the at least one storage block from the other storage blocks of the plurality of storage blocks; and Access the at least one segmented storage block based on the first type of access signal; The first switch and the second switch enable the at least one partitioned storage block to be used as a fast access region relative to the other storage blocks.

17. The non-transitory computer-readable storage medium according to claim 16, wherein, The one or more processors are configured to execute the set of instructions to further cause the computer system to perform: In response to the access request not being directed to the area, a second type of access signal is generated; and Access the plurality of storage blocks based on the second type of access signal.

18. The non-transitory computer-readable storage medium according to claim 16, wherein, Upon determining whether the access request is directed to the region, the one or more processors are configured to execute the set of instructions to further cause the computer system to perform: Determine the access address associated with the access request; Determine whether the access address is within the region; In response to the fact that the access address is located within the region, it is determined that the access request is directed to the region.

19. The non-transitory computer-readable storage medium according to claim 16, wherein, The access request also includes an indication field, wherein, in determining whether the access request is directed to the region, the one or more processors are configured to execute the set of instructions to further cause the computer system to perform: Determine whether the indicated field meets the given conditions; In response to the indication field satisfying the given condition, it is determined that the access request is directed to the region.

20. The non-transitory computer-readable storage medium according to claim 16, wherein, The storage device also includes a data bus with a third switch disposed thereon, and the first type of access signal further causes the third switch to be turned off.

21. The non-transitory computer-readable storage medium according to claim 16, wherein, Access requests for the storage device include requests to read data stored in the storage device or requests to write data to the storage device.

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