Testing device and testing method

Abstract

The disclosed embodiments provide a testing device and a testing method. The testing device includes a mainboard and a control module, wherein the control module is integrated with the mainboard. The mainboard includes a connector for mounting a chip to be tested via the connector. The control module is configured to adjust the refresh interval of the chip to be tested. The chip to be tested is subjected to read and write tests using different test data at different refresh intervals to obtain the data retention time corresponding to each test data. The minimum value of the data retention time corresponding to each test data is the data retention time of the chip to be tested. Thus, the disclosed embodiments provide a testing device with a simple structure that can conveniently perform data retention time testing, is low-cost, and is easy to deploy in batches.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a testing device and a testing method. Background Art

[0002] Dynamic random access memory (DRAM) uses transistors to store charge (data) in capacitors. Over time, the charge stored in the capacitors may disappear, so DRAM must be refreshed to maintain the data. Therefore, testing DRAM's data retention time is a critical task. Summary of the Invention

[0003] The present disclosure provides a testing device and a testing method, which can test the data retention time of a chip to be tested. The testing device has a simple structure and low testing cost.

[0004] In a first aspect, an embodiment of the present disclosure provides a testing device, the testing device comprising a mainboard and a control module, wherein the control module is integrated on the mainboard;

[0005] The mainboard includes a connector for mounting the chip to be tested via the connector;

[0006] The control module is used to adjust the refresh interval of the chip to be tested; and perform read and write tests on the chip to be tested using different test data at different refresh intervals to obtain the data retention time corresponding to all test data;

[0007] The minimum value of the data retention time corresponding to all the test data is the data retention time of the chip to be tested.

[0008] In some embodiments, the chip to be tested is a memory chip or a direct-plug memory module; wherein the direct-plug memory module is directly mounted on the connector, and the memory chip is mounted on the connector through a socket assembly.

[0009] In some embodiments, the testing device further includes a heat sink connected to the mainboard and located above the control module; the testing device further includes a display connected to the mainboard and placed on the mainboard.

[0010] In some embodiments, the control module is used to send a refresh disable instruction to the chip to be tested, and the refresh disable instruction is used to disable the refresh operation of the chip to be tested; and, after a target time interval, send a refresh enable instruction to the chip to be tested to change the refresh interval of the chip to be tested; wherein, the refresh enable instruction is used to instruct the chip to be tested to perform a periodic refresh operation.

[0011] In some embodiments, the control module is used to generate a refresh adjustment instruction based on a target time interval; and, when the chip to be tested performs a periodic refresh operation, send the refresh adjustment instruction to the chip to be tested to change the refresh interval of the chip to be tested; wherein, the refresh adjustment instruction is used to adjust the refresh period of the chip to be tested when performing a periodic refresh operation.

[0012] In a second aspect, an embodiment of the present disclosure provides a testing method, applied to a testing device, the method comprising:

[0013] Write test data to the chip to be tested;

[0014] Sending a refresh disable instruction to the chip under test; and sending a refresh enable instruction to the chip under test after a target time interval to control the chip under test to perform a periodic refresh operation;

[0015] Reading data from the chip to be tested to obtain verification data;

[0016] If the verification data is consistent with the test data, the value of the target time interval is increased to obtain a new target time interval, and the process returns to the step of writing the test data to the chip to be tested;

[0017] If the verification data is inconsistent with the test data, determining the data retention time corresponding to the test data; resetting the value of the target time interval to an initial value, determining new test data, and returning to the step of writing the test data to the chip to be tested;

[0018] After traversing all types of test data, the data retention time of the chip to be tested is determined.

[0019] In some embodiments, the method further comprises:

[0020] After writing test data to the chip to be tested, the chip to be tested is controlled to perform a periodic refresh operation. After all storage units in the chip to be tested are refreshed, the step of sending a refresh disable instruction to the chip to be tested is executed; before reading data from the chip to be tested, the chip to be tested is controlled to perform a periodic refresh operation. After all storage units in the chip to be tested are refreshed, the step of reading data from the chip to be tested is executed.

[0021] In some embodiments, when the verification data is inconsistent with the test data, the method further includes:

[0022] Record the numerical value of the target time interval, and determine the last value of the recorded target time interval as the data retention time corresponding to the test data; record the error position, and the error position refers to the position of the storage unit where the verification data and the test data are different; wherein the error position is used to generate process feedback information.

[0023] In some embodiments, determining the data retention time of the chip to be tested includes:

[0024] The data retention time corresponding to all the test data is obtained; and the minimum value of the data retention time corresponding to all the test data is determined as the data retention time.

[0025] In some embodiments, the method further comprises:

[0026] After traversing all types of test data, a test cycle is completed; after executing a preset number of test cycles, at least one data retention time corresponding to each test data is obtained, and the minimum value of all data retention times is determined as the data retention time of the chip to be tested.

[0027] In a third aspect, an embodiment of the present disclosure provides a testing method, applied to a testing device, the method comprising:

[0028] Write test data to the chip to be tested;

[0029] generating a refresh adjustment instruction based on a target time interval, and sending the refresh adjustment instruction and a refresh enable instruction to the chip under test to control the chip under test to perform a periodic refresh operation with the target time interval as a refresh period;

[0030] Reading data from the chip to be tested to obtain verification data;

[0031] If the verification data is consistent with the test data, replacing the new test data and returning to the step of writing the test data to the chip to be tested; if the verification data is inconsistent with the test data, determining the data retention time corresponding to the test data; and replacing the new test data and returning to the step of writing the test data to the chip to be tested;

[0032] After traversing all types of test data, increasing the value of the target time interval to obtain a new target time interval, resetting the test data to an initial value, and returning to the step of writing the test data to the chip to be tested;

[0033] After traversing all values ​​of the target time interval, the data retention time of the chip to be tested is determined.

[0034] In some embodiments, the method further comprises:

[0035] After sending a refresh adjustment instruction and a refresh enable instruction to the chip under test, and after all storage units in the chip under test are refreshed, the step of reading data from the chip under test is performed.

[0036] In some embodiments, when the verification data is inconsistent with the test data, the method further includes:

[0037] Record the numerical value of the target time interval, and determine the previous value of the recorded target time interval as the data retention time corresponding to the test data; record the error position, and the error position refers to the position of the storage unit where the verification data and the test data are different; wherein the error position is used to generate process feedback information.

[0038] In some embodiments, determining the data retention time of the chip to be tested includes:

[0039] The data retention time corresponding to all the test data is obtained; and the minimum value of the data retention time corresponding to all the test data is determined as the data retention time.

[0040] In some embodiments, the method further comprises:

[0041] After traversing all values ​​of the target time interval, a test cycle is completed; after executing a preset number of test cycles, at least one data retention time corresponding to each test data is obtained, and the minimum value of all data retention times is determined as the data retention time of the chip to be tested.

[0042] The disclosed embodiments provide a testing device and a testing method. The testing device includes a mainboard and a control module, wherein the control module is integrated with the mainboard. The mainboard includes a connector for mounting a chip to be tested via the connector. The control module is configured to adjust the refresh interval of the chip to be tested. The chip to be tested is subjected to read and write tests using different test data at different refresh intervals to obtain the data retention time corresponding to each test data. The minimum value of the data retention time corresponding to each test data is the data retention time of the chip to be tested. Thus, the disclosed embodiments provide a testing device with a simple structure that can conveniently perform data retention time testing, is low-cost, and is easy to deploy in batches. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 A schematic structural diagram of a testing device provided in an embodiment of the present disclosure;

[0044] Figure 2 A schematic structural diagram of another testing device provided in an embodiment of the present disclosure;

[0045] Figure 3 A schematic structural diagram of another testing device provided in an embodiment of the present disclosure;

[0046] Figure 4 A schematic diagram of the use process of a testing device provided in an embodiment of the present disclosure;

[0047] Figure 5 A schematic diagram of a partial structure of a testing device provided in an embodiment of the present disclosure;

[0048] Figure 6 A flow chart of a testing method provided in an embodiment of the present disclosure;

[0049] Figure 7 A schematic diagram of a specific process of a testing method provided in an embodiment of the present disclosure;

[0050] Figure 8 A flowchart of another testing method provided in an embodiment of the present disclosure;

[0051] Figure 9 A schematic diagram of a specific process of another testing method provided in an embodiment of the present disclosure;

[0052] Figure 10 A schematic diagram of the structure of a test system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the relevant applications and are not intended to limit the relevant applications. It should also be noted that for ease of description, only the portions relevant to the relevant applications are shown in the drawings.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0055] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0057] The following describes the English words and abbreviations involved in the embodiments of the present disclosure.

[0058] Dynamic Random Access Memory, DRAM: Dynamic Random Access Memory;

[0059] Synchronous Dynamic Random Access Memory, SDRAM: Synchronous dynamic random access memory;

[0060] Double Data Rate SDRAM, DDR: Double Data Rate SDRAM;

[0061] Low Power SDRAM, LPDDR: Low Power DDR

[0062] Dual-Inline-Memory-Modules, DIMM: Dual-Inline Memory Module

[0063] It should be understood that DRAM memory cells store data by depositing charge in capacitors. Over time, this charge leaks from the capacitors, ultimately leading to data loss. To prevent this data loss, DRAM memory cells must be regularly refreshed. However, DRAM refresh operations not only increase power consumption but also reduce bandwidth utilization. These issues are becoming increasingly severe as DRAM density increases and process technology becomes more streamlined.

[0064] The duration that a DRAM memory cell safely stores data without losing it, without being refreshed, is called the data retention time. The retention time of all memory cells in a DRAM is not identical. To ensure that all memory cells do not lose data, the refresh cycle must be based on the minimum retention time, which further increases power consumption and reduces bandwidth utilization.

[0065] In other words, manufacturers need to promptly and comprehensively identify the memory cells with the shortest retention times in DRAM, thereby optimizing refresh intervals. This not only reduces power consumption and increases bandwidth utilization, but also provides timely feedback to the design team to improve chip design. However, current chip data retention time testing is complex and time-consuming, resulting in suboptimal testing costs and efficiency.

[0066] Based on this, an embodiment of the present disclosure provides a test device, which includes a mainboard and a control module, wherein the control module is integrated with the mainboard; wherein the mainboard includes a connector for mounting a chip to be tested via the connector; and the control module is used to adjust the refresh interval of the chip to be tested; and at different refresh intervals, read and write tests are performed on the chip to be tested using different test data to obtain the data retention time corresponding to each of the test data; wherein the minimum value of the data retention time corresponding to each of the test data is the data retention time of the chip to be tested. Thus, an embodiment of the present disclosure provides a test device with a simple structure, which can conveniently perform data retention time testing, is low-cost, and is easy to deploy in batches.

[0067] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0068] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic structural diagram of a testing device 10 provided by an embodiment of the present disclosure. Figure 1 As shown, the testing device 10 includes a mainboard 11 and a control module 12 , and the control module 12 is integrated on the mainboard 11 ;

[0069] The main board 11 includes a connector 111 for mounting a chip to be tested via the connector 111 ;

[0070] The control module 12 is used to adjust the refresh interval of the chip to be tested; and perform read and write tests on the chip to be tested using different test data at different refresh intervals to obtain data retention times corresponding to all test data.

[0071] Here, the minimum value of the data retention time corresponding to all the test data is the data retention time of the chip to be tested.

[0072] It should be noted that the chip under test refers to a dynamic random access memory (DRAM), such as DDR, LPDDR, etc. In other words, whether it is DDR or LPDDR, as long as the interface meets the corresponding timing / voltage specifications, it can be tested as a chip under test. Thus, the simple test device 10 can perform data retention time testing on the chip under test, with low cost, easy large-scale deployment, and strong compatibility.

[0073] Specifically, the chip to be tested can be a memory chip (such as a DDR or LPDDR chip) or a plug-in memory module (such as a DIMM). The plug-in memory module can be directly installed on the connector 111. In this case, the essence of the chip to be tested refers to the memory chip on the plug-in memory module. For details, please refer to Figure 2 ; The memory chip needs to be installed on the connector 111 through the slot assembly 15. For details, see Figure 3 .

[0074] For example, Figure 4 As shown, the socket assembly 15 may include a base plate 151, a socket (DRAM Socket) 152 and a screw cover 153, wherein the socket 152 is provided on the base plate 151, and the screw cover 153 is detachably connected to the socket 152. The specific installation process of the memory particles is as follows: First, as shown in FIG. Figure 4 As shown in (a), the memory chip is installed in the slot 152; secondly, as shown in Figure 4 As shown in (b), the screw cap 153 is fixed on the top of the slot 152 and tightened to fix the memory chip in the slot 152; finally, as shown in Figure 3 As shown, the substrate 151 is mounted on the connecting member 111 .

[0075] In some embodiments, as Figure 2 or Figure 3 As shown, the test device 10 further includes a heat sink 14, which is connected to the mainboard 11 and is located above the control module 12 ( Figure 2The control module 12 is covered by the heat sink 14 and is therefore not shown. Here, the heat sink 14 can be a fan for dissipating heat during the operation of the test device 10.

[0076] In some embodiments, the test device 10 further includes a display 13, which is connected to the motherboard 11 and is placed on the motherboard 11. In this way, the data retention time test can be completed using the miniaturized test device 10, which is low-cost and easy to deploy in batches.

[0077] In some other embodiments, the display 13 may also be a large independent display, so that the staff can understand the details of the test process. In this case, the mainboard 11 is connected to the display 13 via the display interface integrated thereon.

[0078] In some embodiments, as Figure 5 As shown, the connector 111 and the control module 12 are connected via address lines, control lines, clock lines, and data lines; the control module 12 is also used to send operation instructions to the chip to be tested according to instructions input by the user; the operation instructions include at least one of the following: activation instructions, pre-charge instructions, read instructions, write instructions, refresh enable instructions, refresh disable instructions, and refresh adjustment instructions.

[0079] It should be noted that the activate, precharge, read, write, and refresh enable instructions are all standard instructions specified in industry standard documents (SPEC). The refresh disable instruction is used to prohibit the refresh operation of the chip under test, the refresh enable instruction is used to instruct the chip under test to perform a periodic refresh operation, and the refresh adjust instruction is used to adjust the refresh cycle of the chip under test during a periodic refresh operation.

[0080] In this way, the user only needs to input corresponding instructions according to the prompts, and the control module 12 sends corresponding operation instructions to the chip to be tested according to the user's instructions to complete the test operation of the data retention time. The method of use is simple.

[0081] In some embodiments, the control module 12 is written using a field programmable logic array (FPGA) or a complex programmable logic device (CPLD), and is implemented using register translation level (RTL) language. Thus, the control module 12 is implemented using modular program code, and various parameters can be adjusted according to different test requirements and process technologies to accommodate various application scenarios, while also facilitating upgrades and updates.

[0082] The following provides two methods for adjusting the refresh interval.

[0083] In a specific embodiment, the refresh interval can be adjusted by disabling refresh operations for a period of time. Accordingly, the control module 12 is configured to send a refresh disable instruction to the chip under test; and after a target time interval, send a refresh enable instruction to the chip under test to change the refresh interval of the chip under test.

[0084] In another specific embodiment, the refresh interval can be adjusted by directly adjusting the refresh period of the periodic refresh operation. Accordingly, the control module 12 is configured to generate a refresh adjustment instruction based on the target time interval; and, when the chip under test is performing the periodic refresh operation, send the refresh adjustment instruction to the chip under test to change the refresh interval of the chip under test.

[0085] In other words, the control module 12 provides multiple refresh interval adjustment methods, which personnel can choose based on actual application scenarios. Thus, at different refresh intervals, the chip under test is subjected to read and write tests, and the data retention time of the chip under test is determined by comparing the written test data with the read verification data. Specifically, if the verification data and the test data are consistent, it means that the chip under test can retain the data within the corresponding target time interval; if the verification data and the test data are inconsistent, it means that the chip under test cannot retain the data within the corresponding target time interval. Ultimately, the minimum data retention time is determined, and the refresh parameters of the chip under test can be set accordingly to achieve optimal performance. In addition, the number and specific location of the "storage cells with lost data" can be determined based on the location of the erroneous data, which can be provided to process personnel for improvement.

[0086] In summary, test device 10 is essentially a DRAM controller developed based on an FPGA / CPLD. It can send standard commands specified by the Semiconductor Industry Association (JEDEC), such as activation instructions (Activate), precharge instructions (Precharge), read instructions (Read), write instructions (Write), and refresh enable instructions (Auto Refresh), to the DRAM in any order. Test device 10 can disable Auto Refresh processing using a refresh disable instruction, re-enable Auto Refresh after a certain time interval, and read back verification data to confirm whether any errors occurred during the time interval. Alternatively, test device 10 can also detect variable retention time (VRT) situations by controlling tREFI (Auto Refresh refresh cycle).

[0087] The disclosed embodiments provide a test device that utilizes an FPGA / CPLD platform to write RTL code and send relevant instructions to a chip under test, thereby completing a data retention time test. The device has at least the following advantages: Firstly, a single device has a simple structure, low cost, and is easy to deploy in batches, which can further reduce costs. Secondly, the device is easy to operate; simply inputting instructions as prompted allows data retention time testing. Thirdly, the device has strong compatibility; regardless of DDR / LPDDR, as long as the interface meets the corresponding timing / voltage specifications, testing can be performed. Finally, the device is easy to upgrade; the control module is implemented using modular program code, and various parameters can be adjusted according to different test requirements / process technologies to accommodate a variety of application scenarios.

[0088] In another embodiment of the present disclosure, see Figure 6 , which shows a flow chart of a testing method provided by an embodiment of the present disclosure. Figure 6 As shown, the method may include:

[0089] S201: Writing test data to the chip to be tested.

[0090] S202: Send a refresh disable instruction to the chip under test; and after a target time interval, send a refresh enable instruction to the chip under test to control the chip under test to perform a periodic refresh operation.

[0091] S203: Read data from the chip to be tested to obtain verification data.

[0092] S204: If the verification data is consistent with the test data, the value of the target time interval is increased to obtain a new target time interval, and the process returns to step S201;

[0093] S205: When the verification data and the test data are inconsistent, determine the data retention time corresponding to the test data; reset the value of the target time interval to the initial value, determine new test data, and return to step S201.

[0094] S206: After traversing all types of test data, determine the data retention time of the chip to be tested.

[0095] It should be noted that the testing method in the disclosed embodiments is applied to the aforementioned testing device 10. The control module 12 in the testing device 10 is capable of adjusting the refresh interval of the chip under test. By performing read and write tests on the chip under test at different refresh intervals, the data retention time is determined. In other words, steps S201 to S205 are an optional operation of the control module 12.

[0096] In the embodiment of the present disclosure, the adjustment of the refresh interval is achieved by prohibiting the refresh operation within the target time interval.

[0097] It should be understood that in order to improve the comprehensiveness of the test, it is necessary to use multiple types of test data for read and write tests. The types of test data may at least include: data of all 0s, data of all 1s, test data arranged in sequence of 0101, etc. In the embodiment of the present disclosure, for the selected test data, the read and write test is performed starting from the minimum refresh interval (e.g., 100 milliseconds). If the test data and the verification data are the same, the refresh interval is extended (e.g., it can be accumulated in steps of 100 milliseconds) to continue the read and write test. If the test data and the verification data are different in a certain read and write test, the previous value of the target time interval can be used as the data retention time corresponding to the test data, and the new test data can be replaced for testing.

[0098] In one optional implementation, an upper limit for the refresh interval can be set. If the test data and verification data remain identical at the upper limit, the data retention time corresponding to the test data can be temporarily recorded as the upper limit of the refresh interval, and new test data can be used for testing. It should be understood that the upper limit of the refresh interval is generally set to a relatively large value, so the situation where "test data and verification data remain identical at the upper limit of the refresh interval" rarely occurs.

[0099] Specifically, in some embodiments, when the verification data is inconsistent with the test data, the method further includes:

[0100] Record the numerical value of the target time interval, and determine the last value of the recorded target time interval as the data retention time corresponding to the test data; record the error position, and the error position refers to the position of the storage unit where the verification data and the test data are different; wherein the error position is used to generate process feedback information.

[0101] In this way, when the verification data is inconsistent with the test data, not only the data retention time corresponding to the test data is determined, but also the location of the erroneous storage unit can be determined, so as to be provided to the process department for improvement.

[0102] Exemplarily, assuming that the test data includes test data A (all 0s), test data B (all 1s), and test data C (0101...interleaved data), the refresh intervals include: 100 milliseconds, 200 milliseconds, 300 milliseconds...1000 milliseconds. Then the following test results may exist: for test data A, in the read and write tests corresponding to 100 milliseconds to 800 milliseconds, the test data and the verification data are consistent, and in the read and write tests corresponding to 900 milliseconds, the test data and the verification data are inconsistent. The data retention time corresponding to test data A is 800 milliseconds, and error position 1 is recorded; then, test data B is tested starting from 100 milliseconds, and in the read and write tests corresponding to 100 milliseconds to 700 milliseconds, the test data and the verification data are consistent, and in the read and write tests corresponding to 800 milliseconds, the test data and the verification data are inconsistent. The data retention time corresponding to test data B is 700 milliseconds, and error position 2 is recorded; thereafter, test data C is tested starting from 100 milliseconds, and in the read and write tests corresponding to 100 milliseconds to 800 milliseconds, the test data and the verification data are consistent, and in the read and write tests corresponding to 900 milliseconds, the test data and the verification data are inconsistent. The data retention time corresponding to test data C is 800 milliseconds, and error position 3 is recorded.

[0103] Thus, the data retention time for test data A is 800 milliseconds, the data retention time for test data B is 700 milliseconds, and the data retention time for test data C is 800 milliseconds. To ensure that data on the chip under test is not lost under any circumstances, the data retention time of the chip under test needs to be the minimum of the above data retention times, 700 milliseconds. In addition, the data for error locations 1, 2, and 3 will be provided to the process department for process improvement.

[0104] That is, in some embodiments, determining the data retention time of the chip to be tested includes:

[0105] The data retention time corresponding to all the test data is obtained; and the minimum value of the data retention time corresponding to all the test data is determined as the data retention time.

[0106] In this way, the data retention time of the chip under test can be conveniently determined by the aforementioned testing device 10, so as to set the refresh interval of the chip under test and optimize the power consumption and bandwidth of the chip under test.

[0107] In some embodiments, the method further comprises:

[0108] After writing test data to the chip to be tested, the chip to be tested is controlled to perform a periodic refresh operation. After all storage units in the chip to be tested are refreshed, step S202 is executed; before reading data from the chip to be tested, the chip to be tested is controlled to perform a periodic refresh operation. After all storage units in the chip to be tested are refreshed, step S203 is executed.

[0109] That is, after writing the test data, all memory cells in the chip under test are refreshed at least once, ensuring that the test data is written properly and improving test accuracy. Furthermore, after adjusting the refresh interval, all memory cells in the chip under test are refreshed at least once to ensure that the internal data in the chip under test remains in the state it was in at the end of the target time interval. Correct data remains correct, and incorrect data remains incorrect, preparing for subsequent result verification.

[0110] In some embodiments, the method further comprises:

[0111] After traversing all types of test data, a test cycle is completed; after executing a preset number of test cycles, at least one data retention time corresponding to each test data is obtained, and the minimum value of all data retention times is determined as the data retention time of the chip to be tested.

[0112] For example, assume that after multiple cycles, the test data obtained is as shown in Table 1. At this time, it is necessary to select the minimum value of the data retention time in Table 1 as the data retention time of the chip to be tested, that is, 600 milliseconds.

[0113] Table 1

[0114]

[0115] In this way, through repeated test cycles, more accurate test results can be obtained, the influence of occasional errors can be avoided, and extreme situations can be covered as much as possible.

[0116] In some embodiments, since there are many factors that affect the data retention time of the chip to be tested, such as the current voltage, temperature, surrounding stored data, and the number of previous read and write operations, randomness may occur. For example, the minimum data retention time cannot be reflected in one round of testing. Therefore, this application reduces the occurrence of random events by repeatedly performing several rounds of test cycles.

[0117] Based on the above, a specific test process description is provided below as an example.

[0118] See Figure 7 , the testing process may include:

[0119] S301: The testing device writes test data into the memory array of the chip to be tested in sequence.

[0120] S302: The testing device starts periodic automatic refresh Auto-Refresh and maintains a first time interval; sends a refresh prohibition instruction to turn off Auto-Refresh.

[0121] Here, the first time interval may be at the millisecond level, which at least ensures that all storage arrays in the chip to be tested are refreshed and the test data are written normally.

[0122] S303: Start countdown.

[0123] Here, the countdown duration is the aforementioned target time interval.

[0124] S304: Determine whether the countdown is over.

[0125] Here, for step S304, if the judgment result is no, the process returns to step S303; if the judgment result is yes, the process goes to step S305.

[0126] Thus, during the countdown period, the chip to be tested will not perform a refresh operation. As time passes, the memory cells therein may lose data, so as to determine the data retention time.

[0127] S305: The test device sends a refresh enable instruction to restart the periodic Auto-Refresh.

[0128] It should be noted that after the countdown ends, the chip to be tested restarts and automatically refreshes to ensure that the internal data of the chip to be tested remains in the state at the end of the countdown, preparing for subsequent read verification.

[0129] S306: The testing device sequentially reads data from all storage arrays in the chip to be tested to obtain verification data.

[0130] S307: Determine whether the verification data and the test data are consistent.

[0131] Here, for step S307, if the judgment result is yes, step S308 is executed; if the judgment result is no, step S310 is executed.

[0132] S308: Determine whether the countdown value upper limit has been reached.

[0133] Here, for step S308, if the judgment result is no, step S309 is executed; if the judgment result is yes, step S311 is executed.

[0134] S309: Extend the countdown value and return to step S301.

[0135] Here, the countdown value after extension is equivalent to the aforementioned new target time interval, so as to implement read and write tests on the test data at different refresh intervals.

[0136] S310: Record the error location and the countdown setting value, and execute step S311.

[0137] Thus, whenever the test device detects a verification error (i.e., the verification data is not equal to the test data), it records the error location and the current countdown value (equivalent to the target time interval). It should be understood that the current countdown value is used to determine the data retention time corresponding to the test data, and the data retention time should be the previous value of the recorded value.

[0138] S311: Determine whether to traverse all types of test data.

[0139] Here, for step S311, if the judgment result is no, step S312 is executed; if the judgment result is yes, step S313 is executed.

[0140] S312: Replace the new test data, reset the countdown to the initial value, and return to step S301.

[0141] In this way, the read and write tests of different types of test data are completed under different countdown values ​​(target time intervals). At this time, the minimum target time interval in which the test data and the verification data are consistent can be used as the data retention time of the entire chip to be tested, thereby completing a test cycle.

[0142] S313: Determine whether the number of test cycles reaches a preset number.

[0143] Here, for step S313, if the judgment result is no, step S314 is executed; if the judgment result is yes, step S315 is executed.

[0144] S314: Reset the type of test data, reset the countdown to the initial value, add 1 to the number of test cycles, and return to step S301.

[0145] Here, the initial value of the number of test cycles is 0.

[0146] S315: Output the record of the error result.

[0147] In this way, based on the record of error results (including error locations and corresponding countdowns), the data retention time of the chip to be tested can be determined, and the error locations can be fed back to the process department for process improvement.

[0148] As can be seen from the above, in the embodiment of the present disclosure, the test device 10 disables AutoRefresh of the chip to be tested, re-enables Auto Refresh after a certain time interval, and reads back the verification data to confirm whether any data errors occur during the time interval, and finally determines the data retention time.

[0149] Specifically, if Figure 7 As shown in the figure, the process includes three layers of loop testing:

[0150] First-level loop: For the same test data, different target time intervals (i.e., countdowns) are changed to complete the read and write tests, including the countdown time from disabling Auto Refresh to re-enabling Auto Refresh, i.e., step 301 to step S310. Exemplarily, the initial countdown value can be 100 milliseconds. After the 100-millisecond test is completed, the countdown setting is increased in steps of 100 milliseconds until a data error occurs or the countdown setting upper limit (e.g., 1000 milliseconds) is reached, and then the second-level loop begins. In other words, if a data error occurs when the countdown is set to 300 milliseconds, the data retention time corresponding to the test data is determined to be 200 milliseconds, and the second-level loop is entered directly; if no data error occurs until the countdown is set to 1000 milliseconds, the second-level loop is entered directly. The first-level loop uses the default type of test data, for example, the test data is all 0.

[0151] The second loop changes the test data type (e.g., all 0s, all 1s, 0101, etc.). When the test data changes, the countdown is reset to the initial value, and the first loop is executed again. Once all test data types have been traversed, the third loop begins. The second loop includes steps S311 and S312, followed by repeated steps S301 and S310.

[0152] The third cycle repeats the first and second cycles multiple times until a preset number is reached (e.g., 8). This prevents extreme conditions from being missed. At this level, the number of test cycles is incremented by 1, and the countdown and test data are reset. The first and second cycles are restarted until the preset number of cycles is reached, ending the entire test process and outputting the test results. The test results include the data retention time corresponding to different test data.

[0153] In this way, the minimum value of all data retention times is selected from the test results as the data retention time of the chip to be tested, and the refresh interval of the chip to be tested is subsequently set accordingly to achieve optimal power consumption and optimal bandwidth utilization.

[0154] The embodiment of the present disclosure provides a testing method, which is applied to a testing device 10 and can conveniently test the data retention time of a chip to be tested. The testing process is simple, and the test parameters are easy to modify, and the method is compatible with various application scenarios.

[0155] In another embodiment of the present disclosure, see Figure 8 , which shows a flow chart of a testing method provided by an embodiment of the present disclosure. Figure 8 As shown, the method may include:

[0156] S401: Writing test data to the chip to be tested.

[0157] S402: Generate a refresh adjustment instruction based on the target time interval, and send the refresh adjustment instruction and a refresh enable instruction to the chip under test to control the chip under test to perform a periodic refresh operation with the target time interval as the refresh period.

[0158] S403: Read data from the chip to be tested to obtain verification data.

[0159] S404: When the verification data is consistent with the test data, new test data is replaced and the process returns to step S401.

[0160] S405: When the verification data and the test data are inconsistent, determine the data retention time corresponding to the test data; and replace with new test data, and return to step S401.

[0161] S406: After traversing all types of test data, the value of the target time interval is increased to obtain a new target time interval, the test data is reset to the initial value, and the process returns to step S401.

[0162] S407: After traversing all values ​​of the target time interval, determine the data retention time of the chip to be tested.

[0163] It should be noted that the testing method in the disclosed embodiment is applied to the aforementioned testing device 10. Testing device 10 is capable of adjusting the refresh interval of the chip under test; data retention time is obtained by performing read and write tests on the chip under test at different refresh intervals. In other words, steps S401 to S407 are another optional operating process of control module 12.

[0164] In the embodiment of the present disclosure, the adjustment of the refresh interval may be achieved by adjusting the refresh period of the chip under test when performing a periodic refresh operation.

[0165] It should be understood that in order to improve the comprehensiveness of the test, it is necessary to use multiple types of test data for read and write tests, and the types of test data can at least include: data of all 0s, data of all 1s, 0101...test data arranged in sequence, etc. In the embodiment of the present disclosure, starting from the smallest refresh interval (for example, 100 milliseconds), read and write tests are performed on different test data in sequence; after traversing all the test data, the refresh interval is extended (for example, it can be accumulated in steps of 100 milliseconds), and read and write tests are continued on different test data in sequence until the upper limit of the refresh interval is reached (for example, 1000 milliseconds). In this process, if the test data and the verification data are different in a certain read and write test, the data retention time corresponding to the test data can be recorded as the previous value of the refresh interval.

[0166] Specifically, in some embodiments, when the verification data is inconsistent with the test data, the method further includes:

[0167] Record the numerical value of the target time interval, and determine the last value of the recorded target time interval as the data retention time corresponding to the test data; record the error position, and the error position refers to the position of the storage unit where the verification data and the test data are different; wherein the error position is used to generate process feedback information.

[0168] In this way, when the verification data is inconsistent with the test data, not only the data retention time corresponding to the test data is determined, but also the location of the erroneous storage unit can be determined, so as to be provided to the process department for improvement.

[0169] In another example, assuming that the test data includes test data D (odd row data is 0, even row data is 1), test data B (odd row data is 1, even row data is 0), and test data C (odd column data is 0, even column data is 1), the refresh interval includes: 100 milliseconds, 200 milliseconds, 300 milliseconds...1000 milliseconds. Then the following test results may exist: for test data D, in the read and write tests corresponding to 100 milliseconds to 1000 milliseconds, the test data and the verification data are consistent, then the data retention time corresponding to test data D is 1000 milliseconds, and the error position 4 is recorded; then, test data E is tested starting from 100 milliseconds, in the read and write tests corresponding to 100 milliseconds to 900 milliseconds, the test data and the verification data are consistent, and in the read and write tests corresponding to 1000 milliseconds, the test data and the verification data are inconsistent, then the data retention time corresponding to test data E is 900 milliseconds, and the error position 5 is recorded; thereafter, test data F is tested starting from 100 milliseconds, in the read and write tests corresponding to 100 milliseconds to 800 milliseconds, the test data and the verification data are consistent, and in the read and write tests corresponding to 900 milliseconds, the test data and the verification data are inconsistent, then the data retention time corresponding to test data F is 800 milliseconds, and the error position 6 is recorded.

[0170] Thus, the data retention time for test data D is 1000 milliseconds, the data retention time for test data E is 900 milliseconds, and the data retention time for test data F is 800 milliseconds. Therefore, the data retention time of the chip under test is the minimum of the above data retention times, 800 milliseconds. In addition, error locations 4, 5, and 6 will be provided to the process department for improvement.

[0171] In some embodiments, the method further comprises:

[0172] After the refresh adjustment instruction and the refresh enable instruction are sent to the chip under test, and after all the storage units in the chip under test are refreshed, step S403 is executed.

[0173] That is, after writing the test data, all memory cells in the chip under test are refreshed at least once, improving test accuracy. Furthermore, after adjusting the refresh interval, all memory cells in the chip under test are refreshed at least once to ensure that the internal data in the chip under test remains in the state it was in at the end of the target time interval. Correct data remains correct, and incorrect data remains incorrect, preparing for subsequent result verification.

[0174] In addition, after each read / write test, the refresh cycle can be restored to a default value using a refresh adjustment command. This way, after writing new test data, the refresh cycle is maintained until all memory cells in the chip under test are refreshed, ensuring normal writing of test data. The refresh cycle is then adjusted to the target refresh interval, improving test accuracy.

[0175] In some embodiments, determining the data retention time of the chip to be tested includes:

[0176] The data retention time corresponding to all the test data is obtained; and the minimum value of the data retention time corresponding to all the test data is determined as the data retention time.

[0177] In this way, by determining the data retention time of the chip to be tested, the refresh interval of the chip to be tested can be set accordingly, so that the power consumption and bandwidth of the chip to be tested are optimized.

[0178] In some embodiments, the method further comprises:

[0179] After traversing all types of test data, a test cycle is completed; after executing a preset number of test cycles, at least one data retention time corresponding to each test data is obtained, and the minimum value of all data retention times is determined as the data retention time of the chip to be tested.

[0180] For example, assume that after multiple cycles, the test data obtained is as shown in Table 2. At this time, it is necessary to select the minimum value of the data retention time in Table 2 as the data retention time of the chip to be tested, that is, 800 milliseconds.

[0181] Table 2

[0182]

[0183] In this way, through repeated test cycles, more accurate test results can be obtained, the influence of occasional errors can be avoided, and extreme situations can be covered as much as possible.

[0184] Based on the above, a specific test process description is provided below as an example.

[0185] See Figure 9 , the testing process may include:

[0186] S501: The testing device writes test data into the memory array of the chip to be tested in sequence.

[0187] S502: The testing device sends a refresh adjustment instruction to the chip under test, sets the refresh period tREFI of Auto-Refresh, starts a new Auto-Refresh, and maintains a second time interval.

[0188] It should be noted that, in the embodiment of the present disclosure, the refresh period tREFI is equivalent to the aforementioned target time interval. Here, the second time interval at least ensures that all memory arrays in the chip under test are refreshed.

[0189] S503: The testing device sequentially reads data from all storage arrays in the chip to be tested to obtain verification data.

[0190] S504: Determine whether the verification data and the test data are consistent.

[0191] Here, for step S504, if the judgment result is yes, step S506 is executed; if the judgment result is no, step S505 is executed.

[0192] S505: Record the error location and the countdown setting value, and execute step S506.

[0193] S506: Determine whether all types of test data are traversed.

[0194] Here, for step S506, if the judgment result is no, step S507 is executed; if the judgment result is yes, step S508 is executed.

[0195] S507: Replace the new test data and return to step S501.

[0196] S508: Determine whether the refresh period tREFI reaches an upper limit.

[0197] Here, for step S508, if the judgment result is no, step S509 is executed; if the judgment result is yes, step S510 is executed.

[0198] S509: Extend the refresh period tREFI, reset the type of the test data, and return to step S501.

[0199] In this way, read and write tests of different types of test data are completed at different target time intervals. The minimum target time interval at which the test data and the verification data are consistent is the data retention time, thereby completing a test cycle.

[0200] S510: Determine whether the number of test cycles reaches a preset number.

[0201] Here, for step S510, if the judgment result is no, step S511 is executed; if the judgment result is yes, step S512 is executed.

[0202] S511: Reset the type of test data and the refresh period tREFI to the initial value, add 1 to the number of test cycles, and return to step S501

[0203] Here, the initial value of the number of test cycles is 0.

[0204] S512: Output the record of the error result.

[0205] As can be seen from the above, in this embodiment, the chip under test always maintains Auto Refresh, but the automatic refresh interval is gradually increased during testing. In other words, when the automatic refresh interval increases to a certain extent, the data stored in the chip under test will be lost due to untimely refresh, thereby determining the data retention time.

[0206] The disclosed embodiment also includes three layers of loops:

[0207] The first-level loop performs read and write tests on different types of test data at a fixed target time interval (i.e., refresh period tREFI), and determines the data retention time corresponding to the different types of test data, i.e., steps S501 to S507. For example, assuming a data error occurs when tREFI is 600 milliseconds, the data retention time corresponding to the test data is determined to be 500 milliseconds.

[0208] Second-level loop: The target time interval is changed, and the test data is reset at the same time, and the first-level loop is executed again. After all values ​​of the target time interval have been traversed, the third-level loop begins. This second-level loop includes steps S508 and S509, followed by repeated steps S501 to S507.

[0209] The third loop repeats the first and second loops multiple times until the preset number of times is reached, ending the entire test process and outputting the test results. The test results include the data retention time corresponding to different test data.

[0210] In this way, the minimum value of all data retention times is selected from the test results as the data retention time of the chip to be tested, and the refresh interval of the chip to be tested is subsequently set accordingly to achieve optimal power consumption and optimal bandwidth utilization.

[0211] In other words, in Figure 7 In the test, the test is adjusted by prohibiting the chip to be tested from performing Auto Refresh within a certain period of time. The first layer of the loop is to change the type of test data, and the second layer is to change the value of the target time interval. Figure 9In this scenario, the chip under test maintains Auto Refresh at all times, but the auto-refresh interval is gradually increased during testing. The first level of looping involves changing the target interval value, while the second level changes the test data type. However, this isn't fixed. For example, if the test is adjusted by disabling Auto Refresh for the chip under test during a certain period, the first level of looping can also involve changing the target interval value and the second level of looping can also involve changing the test data type. Alternatively, if the test is performed by maintaining Auto Refresh at all times but gradually increasing the auto-refresh interval, the first level of looping can also involve changing the test data type and the second level of looping can also involve changing the target interval value.

[0212] The embodiment of the present disclosure provides specific execution steps of a testing method, which is applied to a testing device 10 and can conveniently test the data retention time of a chip to be tested. The testing process is simple, and the test parameters are easy to modify, and it is compatible with various application scenarios.

[0213] In another embodiment of the present disclosure, see Figure 10 , which shows a schematic diagram of the structure of a test system 60 provided by an embodiment of the present disclosure. The method is applied to the aforementioned test device 10. Figure 10 As shown, the test system 60 includes the aforementioned test device 10 and a chip to be tested 601 .

[0214] In some embodiments, the chip under test 601 is a double data rate synchronous dynamic random access memory DDR or a low power double data rate synchronous dynamic random access memory LPDDR.

[0215] The embodiments of the present disclosure provide a testing system that can conveniently test data retention time, has a simple structure, strong compatibility, low cost, and is easy to deploy in batches.

[0216] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure.

[0217] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0218] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0219] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0220] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0221] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0222] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A testing device, characterized in that: The testing device includes a mainboard and a control module, wherein the control module is integrated on the mainboard; The mainboard includes a connector for mounting the chip to be tested via the connector; The control module is configured to adjust the refresh interval of the chip to be tested, and after writing test data to the chip to be tested, perform a read test at different refresh intervals to obtain a data retention time corresponding to the test data; and after traversing all types of test data, determine the data retention time of the chip to be tested; The minimum value of the data retention time corresponding to all the test data is the data retention time of the chip to be tested.

2. The testing device according to claim 1, characterized in that The chip to be tested is a memory chip or a plug-in memory module; The in-line memory module is directly mounted on the connector, and the memory particles are mounted on the connector via a slot assembly.

3. The testing device according to claim 1, wherein: The testing device further includes a heat sink connected to the mainboard and located above the control module; The testing device further comprises a display connected to the mainboard and placed on the mainboard.

4. The testing device according to claim 1, wherein: The control module is configured to send a refresh prohibition instruction to the chip under test, wherein the refresh prohibition instruction is configured to prohibit a refresh operation of the chip under test; and After a target time interval, a refresh enable instruction is sent to the chip under test to change the refresh interval of the chip under test; wherein the refresh enable instruction is used to instruct the chip under test to perform a periodic refresh operation.

5. The testing device according to claim 1, wherein: The control module is configured to generate a refresh adjustment instruction based on a target time interval; and, when the chip under test performs a periodic refresh operation, send the refresh adjustment instruction to the chip under test to change the refresh interval of the chip under test; The refresh adjustment instruction is used to adjust the refresh period of the chip under test when performing a periodic refresh operation.

6. A testing method, characterized in that: Applied to a test device, the method comprises: Write test data to the chip to be tested; Sending a refresh disable instruction to the chip under test; and sending a refresh enable instruction to the chip under test after a target time interval to control the chip under test to perform a periodic refresh operation; Reading data from the chip to be tested to obtain verification data; If the verification data is consistent with the test data, the value of the target time interval is increased to obtain a new target time interval, and the process returns to the step of writing the test data to the chip to be tested; If the verification data is inconsistent with the test data, determining the data retention time corresponding to the test data; resetting the value of the target time interval to an initial value, determining new test data, and returning to the step of writing the test data to the chip to be tested; After traversing all types of test data, the data retention time of the chip to be tested is determined.

7. The testing method according to claim 6, characterized in that: The method further comprises: After writing test data to the chip under test, controlling the chip under test to perform a periodic refresh operation, and after all storage units in the chip under test are refreshed, executing the step of sending a refresh prohibition instruction to the chip under test; Before reading data from the chip under test, the chip under test is controlled to perform a periodic refresh operation, and after all storage units in the chip under test are refreshed, the step of reading data from the chip under test is performed.

8. The testing method according to claim 6, wherein: In the case where the verification data is inconsistent with the test data, the method further includes: Recording the value of the target time interval, and determining the last value of the recorded target time interval as the data retention time corresponding to the test data; Recording an error location, where the error location refers to a location of a storage unit where verification data and test data are different; wherein the error location is used to generate process feedback information.

9. The testing method according to claim 7, characterized in that: Determining the data retention time of the chip to be tested includes: Get the data retention time corresponding to all test data; The minimum value of the data retention time corresponding to all the test data is determined as the data retention time.

10. The testing method according to claim 7, wherein: The method further comprises: After traversing all types of test data, a test cycle is completed; After executing a preset number of test cycles, at least one data retention time corresponding to each test data is obtained, and a minimum value of all the data retention times is determined as the data retention time of the chip to be tested.

11. A testing method, characterized in that: Applied to a test device, the method comprises: Write test data to the chip to be tested; generating a refresh adjustment instruction based on a target time interval, and sending the refresh adjustment instruction and a refresh enable instruction to the chip under test to control the chip under test to perform a periodic refresh operation with the target time interval as a refresh period; Reading data from the chip to be tested to obtain verification data; If the verification data is consistent with the test data, replacing the new test data and returning to the step of writing the test data to the chip to be tested; if the verification data is inconsistent with the test data, determining the data retention time corresponding to the test data; and replacing the new test data and returning to the step of writing the test data to the chip to be tested; After traversing all types of test data, increasing the value of the target time interval to obtain a new target time interval, resetting the test data to an initial value, and returning to the step of writing the test data to the chip to be tested; After traversing all values ​​of the target time interval, the data retention time of the chip to be tested is determined.

12. The testing method according to claim 11, characterized in that: The method further comprises: After sending a refresh adjustment instruction and a refresh enable instruction to the chip under test, and after all storage units in the chip under test are refreshed, the step of reading data from the chip under test is performed.

13. The testing method according to claim 11, characterized in that: In the case where the verification data is inconsistent with the test data, the method further includes: Recording the value of the target time interval, and determining the last value of the recorded target time interval as the data retention time corresponding to the test data; Recording an error location, where the error location refers to a location of a storage unit where verification data and test data are different; wherein the error location is used to generate process feedback information.

14. The testing method according to claim 11, characterized in that: Determining the data retention time of the chip to be tested includes: Get the data retention time corresponding to all test data; The minimum value of the data retention time corresponding to all the test data is determined as the data retention time.

15. The testing method according to claim 11, characterized in that: The method further comprises: After traversing all values ​​of the target time interval, completing a test cycle; After executing a preset number of test cycles, at least one data retention time corresponding to each test data is obtained, and a minimum value of all the data retention times is determined as the data retention time of the chip to be tested.

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