Array substrate and display panel

Abstract

This disclosure provides an array substrate and a display panel. The array substrate includes a central display area and an edge display area. The central display area includes at least one channel area, and the edge display area includes at least one channel area. The dimensions of the at least one channel area in the edge display area are different from the dimensions of the at least one channel area in the central display area. This is beneficial for mitigating linewidth differences caused by etching rate differences due to inconsistent pattern density between the interior and edges of the display area. It ensures that when minimizing polysilicon linewidth during overexposure processes, the polysilicon traces in the edge display area will not exhibit excessively thin linewidths or even breakage, thus ensuring that the linewidth meets design requirements and improving the yield of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of displays, and more specifically, to an array substrate and a display panel. Background Technology

[0002] Critical Dimension (CD) uniformity is a crucial indicator in display panel manufacturing. For processes with a critical dimension less than 0.15 micrometers, limitations in exposure machine resolution (2µm) and variations in the impact of etching load on CD loss often prevent the achievement of ideal critical dimension values ​​after photolithography, development, and etching processes. This frequently results in excessively thin and broken traces at the edges of the display panel, leading to edge-like bright spots and impacting product yield. Summary of the Invention

[0003] This disclosure provides an array substrate in which the size of at least one channel region located in the edge display area is different from the size of at least one channel region located in the center display area, thereby solving the problem of excessively thin or even broken traces at the edge of the display area.

[0004] The first aspect of this disclosure provides an array substrate including a central display region and an edge display region. The central display region includes at least one channel region, and the edge display region includes at least one channel region. The size of the at least one channel region located in the edge display region is different from the size of the at least one channel region located in the central display region.

[0005] In one specific implementation of the first aspect of this disclosure, the size of at least one channel region located in the edge display area is smaller than the size of at least one channel region located in the center display area.

[0006] In one specific implementation of the first aspect of this disclosure, the size of a plurality of channel regions located in the edge display area increases along the direction from the edge display area to the center display area.

[0007] In one specific embodiment of the first aspect of this disclosure, the channel region corresponds to at least one groove, and the area of ​​a plurality of grooves located in the edge display region increases along the direction from the edge display region to the center display region.

[0008] In one specific implementation of the first aspect of this disclosure, the groove has a length in a first direction and a width in a second direction. Along the direction from the edge display area to the center display area, the length of the plurality of grooves increases in the first direction, and / or the width of the plurality of grooves increases in the second direction.

[0009] In one specific implementation of the first aspect of this disclosure, the dimensions of the multiple channel regions located in the central display area are all the same.

[0010] In one specific implementation of the first aspect of this disclosure, the array substrate further includes a driving circuit region adjacent to the edge display region. The driving circuit region includes at least one set of dummy traces. Preferably, the driving circuit region is located on the side of the edge display region that is farther from the center display region.

[0011] In one specific implementation of the first aspect of this disclosure, the central display area includes at least one set of polysilicon traces, the set of polysilicon traces including at least one channel region, and the at least one set of dummy traces located in the driving circuit area has the same trace shape and / or wiring density as the set of polysilicon traces located in the central display area.

[0012] In one specific implementation of the first aspect of this disclosure, the array substrate further includes a substrate and an active layer located on one side of the substrate, with at least one channel region located in the active layer.

[0013] A second aspect of this disclosure provides a display panel fabricated using the array substrate described in the first aspect.

[0014] This disclosure designs the dimensions of the channel region within the edge display area to be different from those within the center display area. By adjusting the size of the channel regions in the edge and center display areas differently, it helps to mitigate the linewidth differences caused by the etching rate differences between the interior and edges of the display area due to inconsistent pattern density. This ensures that when minimizing the polysilicon linewidth during the overexposure process, the polysilicon traces within the edge display area will not have excessively thin linewidths or even breakages, thus guaranteeing that the linewidth meets design requirements and improving the yield of the display panel. Attached Figure Description

[0015] Figure 1 This is a top view schematic diagram of an array substrate provided in an embodiment of the present disclosure.

[0016] Figure 2 This is a top view of a display area provided in an embodiment of the present disclosure.

[0017] Figure 3 This is a top view of a display area provided in another embodiment of the present disclosure.

[0018] Figure 4 This is a top view schematic diagram of an array substrate provided in another embodiment of the present disclosure.

[0019] Figure 5 This is a top view schematic diagram of an array substrate provided in yet another embodiment of the present disclosure.

[0020] Figure 6 This is a flowchart illustrating a graphical method provided in one embodiment of the present disclosure. Detailed Implementation

[0021] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0022] As wearable products demand increasingly longer standby times, they require even lower frequencies for standby display. Some wearable device manufacturers require standby frequencies below 10Hz. Improving flicker in low-frequency displays primarily involves reducing the Ioff of the switching thin-film transistor (TFT). There are many methods to improve Ioff using Low Temperature Poly-Silicon (LTPS) technology, one important method being reducing the aspect ratio of the switching TFT (the most effective way being to reduce the linewidth of the polysilicon (P_Si), i.e., the channel width). Therefore, the channel width of the switching TFT needs to be less than 2µm after development inspection (ADI) and less than 1.5µm after etching inspection (AEI). Due to limitations in the exposure machine's resolution (2µm) and the varying impact of etching load on linewidth loss (CD loss), achieving P_Si linewidths below 1.5µm often requires overexposure. However, the edge P_Si trace design exhibits a load effect during both development and etching in the photolithography process, leading to uneven development and etching. Areas with lower load experience more etching, resulting in narrower linewidths or even line breaks. Furthermore, the significant difference in pattern density between the P_Si edge traces within the display area and at the edge of the display area causes more severe line breaks closer to the outer edge of the display area, resulting in linear bright spots appearing at the screen edges during touch-up.

[0023] In view of this, the present disclosure provides an array substrate and a display panel that can solve the problem of linear bright spots appearing at the edge of the screen when the existing array substrate is turned on.

[0024] It should be noted that patterning processes are frequently used in the fabrication of array substrates for display panels. A single photolithography process typically includes steps such as cleaning, film deposition, exposure, development, etching, and lift-off. Etching refers to the process of removing unwanted portions of the film layer within or on the surface of the substrate using chemical solutions, corrosive gases, or plasma. Wet etching is typically performed using chemical solutions, while dry etching uses corrosive gases or plasma.

[0025] When etching patterns of varying areas using plasma etching, a common phenomenon is that larger etching areas experience faster plasma consumption and slower etching rates, while smaller etching areas experience slower plasma consumption and faster etching rates. This results in shallower etching depths in larger areas and deeper etching depths in smaller areas. This difference in etching depth is known as the loading effect in the etching process. Due to this loading effect, the etching process may result in either over-etching or under-etching of the pattern.

[0026] After-Develop Inspection (ADI) is performed on the chip after the development process is completed. It is done to ensure that the patterns between the photolithography layers are stacked accurately and to ensure that the development process of this photolithography stage meets the specifications.

[0027] Screen activation refers to lighting up the display panel to enable it to display images; it is an operation that initializes the terminal's display panel.

[0028] In semiconductor manufacturing, as design dimensions continue to shrink, the diffraction effect of light becomes increasingly pronounced. As a result, the optical image of the design pattern is degraded, and the actual pattern formed on the silicon wafer by photolithography eventually differs from the design pattern. This phenomenon is known as the Optical Proximity Effect (OPE).

[0029] To correct the optical proximity effect, Optical Proximity Correction (OPC) was developed. The core idea of ​​OPC is to establish an OPC model based on the consideration of counteracting the optical proximity effect. The photomask pattern is designed according to the OPC model. In this way, although the lithographic pattern and the corresponding photomask pattern have an optical proximity effect, the cancellation of this phenomenon has been considered when designing the photomask pattern according to the OPC model. Therefore, the lithographic pattern after photolithography is close to the target pattern actually desired by the user.

[0030] Figure 1 This is a top view schematic diagram of an array substrate provided in an embodiment of the present disclosure. Figure 2 This is a top view of a display area provided in another embodiment of this disclosure. Figure 1 As shown, an embodiment of this disclosure provides an array substrate 1 including a display area 21 and a non-display area, the non-display area including a driving circuit area 12. The display area 21 includes a central display area 210 and an edge display area 211. The central display area 210 corresponds to the central area of ​​the display area 21, and the edge display area 211 corresponds to the edge area of ​​the display area 21. Both the central display area 210 and the edge display area 211 can be used for display. Figure 2 As shown, the central display area 210 includes at least one channel area 10, which corresponds to the optical proximity correction area of ​​the photomask, and all channel areas 10 within the central display area 210 have the same size. The edge display area 211 includes at least one channel area 10, and the size of each of the at least one channel area 10 located in the edge display area 211 is different from the size of the at least one channel area 10 located in the central display area 210.

[0031] For example, the channel region 10 corresponds to the area on the substrate after photolithography where the pattern is prone to distortion due to optical proximity effect. The size of the channel region 10 reflects the size of the correction area. The size of the channel region 10 includes the region width and the region length. The shape of the channel region 10 can be square, rectangular, quadrilateral, etc., and this implementation does not impose a specific limitation on it. The number of channel regions 10 in the edge display area 211 can be 10 or 9, and the specific number can be determined according to the actual situation. The size of the channel region 10 is determined by the actual design rules and actual manufacturing process.

[0032] In this implementation, the dimensions of the channel region 10 in the edge display region 211 and the channel region 10 in the center display region 210 are designed to be different. By making differentiated adjustments to the size of the channel region 10 in the edge display region 211 and the center display region 210, it is beneficial to improve the linewidth difference caused by the difference in etching rate due to the inconsistent pattern density in the interior and edge of the display area 21. This ensures that when the polysilicon linewidth is minimized during the overexposure process, the polysilicon traces in the edge display region 211 will not have excessively thin linewidths or even breakages, thus ensuring that the linewidth meets the design requirements and improving the yield of the array substrate 1.

[0033] In one implementation of the embodiments of this disclosure, such as Figure 2 As shown, the central display area 210 includes a plurality of channel areas 10 arranged in an array, and the plurality of channel areas 10 in the edge display area 211 are also arranged in an array. The plurality of channel areas 10 located in the edge display area 211 have different sizes, and are all smaller than the size of at least one channel area 10 located in the central display area 210.

[0034] Figure 3 This is a top view schematic diagram of a display area provided in yet another embodiment of this disclosure. (See diagram below.) Figure 3 As shown, from left to right, there are the first group of polysilicon traces, the second group of polysilicon traces, ..., the (N-1)th group of polysilicon traces, and the Nth group of polysilicon traces, where N ≤ 10. Each group of polysilicon traces corresponds to one pixel. The first to the (N-1)th groups of polysilicon traces are located in the edge display area 211, and the Nth group of polysilicon traces is located in the center display area 210. Each group of polysilicon traces includes two channel regions 10, and the two channel regions 10 are of the same size. The size of the multiple channel regions 10 located in the edge display area 211 is smaller than the size of the Nth channel region 10 located in the center display area 210. That is, along the direction from the edge display area 211 to the center display area 210, the size of the first channel region 10 < the size of the second channel region 10 < ... < the size of the (N-1)th channel region 10 < the size of the Nth channel region 10.

[0035] In this implementation, when manufacturing the minimum P_Si linewidth that exceeds the process capability, it is necessary to optimize the size of at least one channel region 10 located in the edge display area 211 to solve the problem of poor uniformity caused by exceeding the process limit. Especially at the edge of the display screen where the load effect is different, this non-uniformity will be amplified and cause abnormal line breaks. This implementation can completely improve the problem of P_Si achieving the minimum linewidth (below 1.5um) without line breaks by designing the channel region 10 of the edge display area 211 differently from the outside to the inside of the edge of the display area 21.

[0036] In one implementation of this disclosure, the compensation values ​​of a plurality of channel regions 10 located in the edge display area 211 increase along the direction from the edge display area 211 to the center display area 210. The size of the plurality of channel regions 10 located in the edge display area 211 increases along the direction from the edge display area 211 to the center display area 210. The outermost channel region 10 has the smallest compensation value and therefore the smallest size. The closer to the center display area 210, the larger the compensation value of the channel regions 10 in the edge display area 211, and the larger the size of the channel regions 10.

[0037] In one embodiment, the channel region corresponds to at least one groove, and the area of ​​the plurality of grooves located in the edge display region increases along the direction from the edge display region to the center display region.

[0038] In one embodiment, the groove has a length in a first direction and a width in a second direction. Along the direction from the edge display area to the center display area, the length of the plurality of grooves increases in the first direction, and / or the width of the plurality of grooves increases in the second direction.

[0039] Continue as Figure 3 As shown, each channel region 10 is a groove, and each groove has a first direction (i.e., Figure 3 The length in the L direction and the second direction (i.e. Figure 3 In this embodiment, since each channel region 10 is a square groove, the length and width of the square groove are the same. The size of the channel region 10 corresponds to the area of ​​the square groove. The areas of the N square grooves from left to right are (a-0.9)*(a-0.9), (a-0.8)*(a-0.8)......(a-0.1)*(a-0.1), a*a. Among them, the 1st to the (N-1)th square grooves are located in the edge display area 211, and the Nth square groove is located in the center display area 210 and adjacent to the edge display area 211. Along the direction from the edge display area 211 to the center display area 210, the length of the multiple square grooves increases in the first direction L, and the width of the multiple square grooves increases in the second direction W. The area of ​​the multiple square grooves located in the edge display area 211 increases in a gradient until the area of ​​the Nth square groove is a*a. The area of ​​the channel region 10 located in the center display area 210 is a*a. The widths of the polysilicon traces corresponding to the N channel regions 10 are D1>D2>....>DN-1>DN. By gradually increasing the compensation value of the channel regions 10 from the outer edge display area 211 inwards, it is equivalent to gradually increasing the area of ​​the channel regions 10. The outermost first channel region 10 has the smallest area, which is equivalent to widening the width of the polysilicon traces near the first channel region 10. Even after minimizing the P_Si linewidth through an overexposure scheme, the outermost first channel region 10 will not experience line breaks, and the linewidth can be maintained at around 1.5um.

[0040] It should be understood that, limited by the actual resolution of the exposure machine and the process capability, the linewidth of polysilicon is usually designed to be 2.0um when designing the array substrate 1. After exposure, the actual polysilicon linewidth produced by the array substrate 1 is about 1.5um.

[0041] In this implementation, the area of ​​the channel region 10 in the edge display area 211 is adjusted differentially from the outside to the inside, so that the area of ​​at least one channel region 10 in the edge display area 211 increases in the direction from the edge display area 211 to the center display area 210. This improves the linewidth difference caused by the difference in development and etching load inside and at the edge of the display area 21, thereby ensuring that when the P_Si linewidth is minimized in the overexposure process, the P_Si traces at the channel region 10 position at the edge of the display area 21 will not have the problem of excessively thin linewidth or even broken lines.

[0042] In one implementation of the present disclosure, when fabricating the array substrate 1, the channel region 10 can correspond to the light-shielding part of the mask plate. The shading area of ​​the light-shielding part is proportional to the size of the channel region 10. The smaller the size of the channel region 10, the smaller the shading area of ​​the light-shielding part.

[0043] In one implementation of this disclosure, the array substrate 1 includes thin-film transistors, and the channel region 10 corresponds to the channel of the thin-film transistor. Specifically, as the size of the channel region 10 increases, the channel width of the thin-film transistor increases.

[0044] In one embodiment, the array substrate further includes a substrate and an active layer located on one side of the substrate, with at least one channel region located in the active layer.

[0045] Specifically, the array substrate includes a thin-film transistor, which includes a substrate, a gate, a gate insulating layer, an active layer, a source, a drain, a passivation layer, and a pixel electrode stacked from bottom to top. The active layer is formed on the gate insulating layer and is insulated from the gate, and at least one channel region is disposed in the active layer.

[0046] Figure 4 This is a top view schematic diagram of an array substrate provided in another embodiment of the present disclosure. Figure 5 This is a top view schematic diagram of an array substrate provided in yet another embodiment of this disclosure. (See attached diagram.) Figure 4 As shown, the array substrate 1 also includes a driving circuit region 12 adjacent to the edge display region 211, the driving circuit region 12 being located on the side of the edge display region 211 away from the central display region 210. Figure 5 As shown, the driving circuit area 12 includes at least one set of dummy traces 14, that is, a set of dummy traces 14 can be a pixel pattern corresponding to a pixel. A set of dummy traces 14 includes at least one channel region 10. A set of polysilicon traces 14 can be prepared by a set of pixel patterns on a mask.

[0047] For example, the number of dummy traces in the drive circuit area 12 can be 10 groups or 9 groups. This embodiment of the disclosure does not make a specific limitation, and the number of traces can be set according to the actual situation.

[0048] Specifically, there are blank areas in the driving circuit area 12 surrounding the edge display area 211. At least one set of dummy traces 14 are added to the blank areas, so that the original low pattern density of the edge display area 211 increases after the dummy traces are filled in the driving circuit area 12. This minimizes the difference in wiring density between the polysilicon traces at the edge of the screen in the display area 21 and the outer driving circuit area 12, and improves the problem of broken lines at the edge of the screen caused by differences in development or etching load.

[0049] It should be understood that at least one set of dummy traces in the drive circuit area 12 does not participate in the circuit connection and is only used as virtual traces.

[0050] In one embodiment, the central display area 210 includes at least one set of polysilicon traces 15, each set of polysilicon traces 15 including at least one channel region 10, and the at least one set of dummy traces 14 located in the drive circuit area 12 has the same trace shape and / or wiring density as the set of polysilicon traces 15 located in the central display area 210.

[0051] like Figure 5 As shown, the dashed line is the boundary between the edge display area 211 and the driving circuit area 12. To the right of the dashed line corresponds to the display area 21 of the array substrate 1, and to the left of the dashed line corresponds to the driving circuit area 12 of the array substrate 1. For the multiple sets of polysilicon traces 15 in the edge display area 211, multiple sets of dummy traces 14 are added in the outermost driving circuit area 12. Each pixel pattern corresponds to a set of dummy traces 14. The multiple sets of dummy traces 14 located in the driving circuit area 12 have the same trace shape and / or wiring density as the set of polysilicon traces 15 located in the central display area 210. This is equivalent to adding multiple sets of P_Si dummy traces in the driving circuit area 12 at the edge of the display area 21, so as to increase the development or etching load of the P_Si traces at the edge of the display area 21, and keep the development and etching load inside and at the edge of the display area 21 as equal as possible, reducing the problem of P_Si line breakage at the edge of the screen in the case of overexposure.

[0052] In one implementation of this disclosure, at least one set of dummy traces 14 located in the driving circuit area 12 and a set of polysilicon traces 15 located in the central display area 210 have the same trace shape and wiring density. Dummy traces are added only in the blank areas of the driving circuit area 12, which can make the pattern trace density more uniform to a certain extent, ensuring the uniformity of the exposure and etching amount of the polysilicon traces. This minimizes the difference in wiring density between the polysilicon traces in the display area 21 and the driving circuit area 12 of the screen, and keeps the development and etching load inside and at the edge of the display area 21 as equal as possible, thus improving the problem of edge breakage caused by differences in development or etching load.

[0053] Figure 6This is a flowchart illustrating a graphical method provided in one embodiment of the present disclosure. Figure 6 As shown, the method includes the following steps.

[0054] Step 800: Provide a light-transmitting substrate.

[0055] Step 801: Form a photoresist layer on a transparent substrate.

[0056] Specifically, photoresist is coated onto a light-transmitting substrate to form a photoresist layer. In the embodiments of this disclosure, the coated photoresist can be a positive photoresist, which is a substance that undergoes a photoacid reaction upon exposure to ultraviolet light, thereby decomposing into a substance that can be dissolved in a corresponding developer.

[0057] Step 802: Expose the photoresist layer using a mask corresponding to the array substrate 1 in the first aspect above, so as to pattern the photoresist layer.

[0058] In one embodiment, the array substrate 1 prepared by the above patterning method has a differentiated design for the size of the channel region 10 from the edge of the display area 21 to the inside. The minimum linewidth of the polysilicon traces in the edge display area 211 of the display area 21 can be less than 1.5 μm without the problem of broken lines.

[0059] This disclosure provides a display panel that includes the array substrate 1 described in the first aspect above.

[0060] This disclosure provides a display device that includes the display panel described in the second aspect above.

[0061] For example, the display panel can be applied to various electronic display products, including but not limited to wearable products such as smartwatches and smart bracelets, and the display device can achieve standby display at a lower frequency.

[0062] The display device provided according to any embodiment of this disclosure and the array substrate provided in the embodiments of this disclosure belong to the same inventive concept, and have corresponding film layer structures and beneficial effects. Details not described in detail in the embodiments of the display device can be found in the embodiments section of the array substrate, and will not be repeated here.

[0063] The above are merely preferred embodiments of this disclosure and are not intended to limit this disclosure. Any modifications or equivalent substitutions made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An array substrate, characterized by, The array substrate includes a center display area and an edge display area, the center display area includes at least one channel area, the edge display area includes at least one channel area, the size of the at least one channel area in the edge display area is smaller than the size of the at least one channel area in the center display area, the size of the channel area in the edge display area increases in the direction from the edge display area to the center display area, the channel area corresponds to the area of the pattern on the array substrate after photoetching, and the size of the channel area is used to reflect the size of the correction area.

2. The array substrate of claim 1, wherein, The channel area corresponds to at least one groove, and the area of the groove in the edge display area increases in the direction from the edge display area to the center display area.

3. The array substrate of claim 2, wherein, The groove has a length in a first direction and a width in a second direction, the length of the groove in the first direction increases in the direction from the edge display area to the center display area, and / or the width of the groove in the second direction increases.

4. The array substrate according to any one of claims 1 to 3, wherein, The size of the channel area in the center display area is the same.

5. The array substrate according to any one of claims 1 to 3, wherein, The array substrate further includes a driving circuit area adjacent to the edge display area, and the driving circuit area includes at least one set of dummy wires.

6. The array substrate of claim 5, wherein, The driving circuit area is located on the side of the edge display area away from the center display area.

7. The array substrate of claim 6, wherein, The center display area includes at least one set of polysilicon wires, the set of polysilicon wires includes the at least one channel area, the shape of the wire and / or the wiring density of the at least one set of dummy wires in the driving circuit area is the same as the set of polysilicon wires in the center display area.

8. The array substrate according to any one of claims 1 to 3, wherein, The array substrate further includes a substrate and an active layer on one side of the substrate, and the at least one channel area is located in the active layer.

9. A display panel, characterized by, An array substrate as claimed in any one of claims 1 to 8.

Images