A process method for front-side super junction back-side IGBT

Abstract

The present invention provides a process method for a front super junction back IGBT, wherein the first and second epitaxial layers are sequentially formed on the front of the substrate; a plurality of deep grooves are formed penetrating the first and second epitaxial layers into the substrate; a P-type epitaxial material is filled in the deep grooves to form a P column; an N-type buried layer is formed on the surface of the second epitaxial layer; a third epitaxial layer is formed on the upper surface of the N-type buried layer and the P column; grooves are formed on both sides above each P column in the third epitaxial layer; a body region is formed between each groove; an ILD layer is formed to cover the grooves, the body region and the third epitaxial layer; a metal passivation layer is formed on the third epitaxial layer; the substrate is thinned on the back side to a thickness of 1 to 5 microns after the P column is removed; a field stop injection layer is formed on the back side of the substrate; a boron injection layer is formed at the end of the P column on the back side of the substrate; and a metal electrode is formed on the back side of the substrate. The present invention stabilizes the breakdown voltage by thinning and removing the chamfered area at the bottom of the P column, and reduces the conduction voltage drop by thinning the chip thickness.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a process method for a front-side super junction back-side IGBT. Background Art

[0002] IGBT is one of the important switching components for energy control and conversion in power electronic systems. Its performance directly affects the conversion efficiency, volume and weight of power electronic systems.

[0003] The performance of power electronic devices is always developing towards higher current density, smaller on-state voltage drop, and lower turn-off loss. Traditional IGBT is based on the front Trench MOS structure. However, traditional IGBT often has low performance, so it is crucial to improve the performance of traditional IGBT. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a process method for a front-side super junction back-side IGBT, so as to solve the problem of low performance of the IGBT in the prior art.

[0005] To achieve the above-mentioned and other related purposes, the present invention provides a process method for a front-side super junction back-side IGBT, which at least comprises:

[0006] Step 1: providing a substrate, and sequentially forming a first epitaxial layer and a second epitaxial layer located on the first epitaxial layer on the front side of the substrate;

[0007] Step 2: forming a plurality of deep trenches penetrating the first and second epitaxial layers into the substrate; and filling the deep trenches with P-type epitaxial material to form P columns;

[0008] Step 3, forming an N-type buried layer on the surface of the second epitaxial layer; forming a third epitaxial layer on the N-type buried layer and the upper surface of the P column; then forming grooves on both sides above each of the P columns in the third epitaxial layer; then forming a body region between each of the grooves;

[0009] Step 4: forming an ILD layer to cover the trench, the body region and the third epitaxial layer; and then forming a metal passivation layer on the third epitaxial layer;

[0010] Step 5: thinning the back side of the substrate until the thickness of the P column is 1 to 5 microns;

[0011] Step 6: forming a field stop injection layer on the back side of the substrate; and then forming a boron injection layer on the P column end on the back side of the substrate;

[0012] Step 7: forming a layer of metal electrode on the back side of the substrate.

[0013] Preferably, the first and second epitaxial layers in step 1 are N-type epitaxial layers, and the resistivity of the first epitaxial layer is lower than the resistivity of the second epitaxial layer.

[0014] Preferably, in step 1, the bulk concentration of the first epitaxial layer is E15-E18.

[0015] Preferably, in step three, N-type implantation regions closely attached to the trench are formed on both sides of each body region.

[0016] Preferably, before forming the metal passivation layer in step 4, a groove is formed in the ILD layer above the body region; then the metal passivation layer is formed on the third epitaxial layer, and the metal passivation layer fills the groove.

[0017] Preferably, the bulk concentration of the field stop injection layer in step six is ​​E11-E14.

[0018] Preferably, the implantation concentration of the boron implantation layer in step six is ​​E11-E15.

[0019] Preferably, the depth of the field stop injection layer in step six is ​​1 to 30 microns.

[0020] As described above, the process method of the front super junction and back IGBT of the present invention has the following beneficial effects: The present invention is based on the Super-IGBT (front super junction + back IGBT) structure to develop a self-aligned RC Super IGBT structure. Through double-layer epitaxy, and the first layer of epitaxy uses a high-concentration N-type layer, the concentration is higher than the concentration of the back Boron injection. Thinning to the front P column (Pillar) area, remove the arc area at the bottom of the Pillar. By increasing the back field stop injection layer FS and P+ area, an IGBT is formed and the on-state voltage drop of the IGBT is reduced, thereby improving the overall FOM of the IGBT. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 6 It shows a schematic diagram of the process structure of each step of the front super junction back IGBT of the present invention. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] See also Figures 1 to 6It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0024] The present invention provides a process method for a front-side super junction back-side IGBT, which at least comprises:

[0025] Step 1: providing a substrate, and sequentially forming a first epitaxial layer and a second epitaxial layer located on the first epitaxial layer on the front side of the substrate; Figure 1 As shown, in step 1, a first epitaxial layer 02 and a second epitaxial layer 03 located on the first epitaxial layer 02 are sequentially formed on the front surface of the substrate 01 .

[0026] Furthermore, in the present invention, the first and second epitaxial layers in step 1 of this embodiment are N-type epitaxial layers, and the resistivity of the first epitaxial layer is lower than the resistivity of the second epitaxial layer.

[0027] Furthermore, in the present invention, in step 1 of this embodiment, the body concentration of the first epitaxial layer is E15-E18.

[0028] Step 2: forming a plurality of deep trenches penetrating the first and second epitaxial layers into the substrate; and filling the deep trenches with P-type epitaxial material to form P columns; Figure 2 As shown, in step 2, a plurality of deep trenches are formed penetrating the first and second epitaxial layers into the substrate 01; and P-type epitaxial material is filled in the deep trenches to form P columns (A).

[0029] Step 3: forming an N-type buried layer on the surface of the second epitaxial layer; forming a third epitaxial layer on the N-type buried layer and the upper surface of the P column; then forming grooves on both sides above each of the P columns in the third epitaxial layer; then forming a body region between each of the grooves; Figure 3 As shown, an N-type buried layer 04 is formed on the surface of the second epitaxial layer 03 in step three; a third epitaxial layer 05 is formed on the N-type buried layer 04 and the upper surface of the P column; then, grooves 06 are formed on both sides above each of the P columns in the third epitaxial layer 05; then, a body region 09 is formed between each of the trenches 06, and the body region material is polycrystalline silicon.

[0030] According to the present invention, in step three of this embodiment, N-type implantation regions 10 closely attached to the trench are formed on both sides of each body region.

[0031] Step 4: forming an ILD layer 07 to cover the trench, the body region and the third epitaxial layer; and then forming a metal passivation layer 08 on the third epitaxial layer;

[0032] The present invention further comprises that before forming the metal passivation layer in step 4 of this embodiment, a groove is formed in the ILD layer above the body region; then the metal passivation layer is formed on the third epitaxial layer, and the metal passivation layer fills the groove.

[0033] Step 5: thinning the back side of the substrate until the thickness of the P column is 1 to 5 microns; Figure 4 As shown, in step five, the back side of the substrate 01 is thinned to remove the P column with a thickness of 1 to 5 microns.

[0034] Step 6: forming a field stop injection layer on the back of the substrate; and then forming a boron injection layer on the P column end on the back of the substrate; Figure 5 As shown, in step six, a field stop injection layer 11 is formed on the back side of the substrate; and then a boron injection layer 13 is formed on the P column end on the back side of the substrate.

[0035] Furthermore, in the present invention, the body concentration of the field stop injection layer in step six of this embodiment is E11-E14.

[0036] According to the present invention, further, the implantation concentration of the boron implantation layer in step six of this embodiment is E11-E15.

[0037] According to the present invention, the depth of the field stop injection layer in step six of this embodiment is 1 to 30 micrometers.

[0038] According to the present invention, the implantation depth of the boron implantation layer in step six of this embodiment is 0.1 to 5 micrometers.

[0039] Step 7: forming a metal electrode layer on the back of the substrate. Figure 6 As shown, in step seven, a layer of metal electrode 12 is formed on the back side of the substrate.

[0040] In summary, the present invention stabilizes the breakdown voltage BVCES by thinning and removing the chamfered area at the bottom of the P column (Pillar), and reduces the thickness of the chip to reduce the on-state voltage drop VCESAT. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A process method for front-side super junction back-side IGBT, characterized in that: At least: Step 1: providing a substrate, and sequentially forming a first epitaxial layer and a second epitaxial layer located on the first epitaxial layer on the front side of the substrate; Step 2: forming a plurality of deep trenches penetrating the first and second epitaxial layers into the substrate; and filling the deep trenches with P-type epitaxial material to form P columns; Step 3, forming an N-type buried layer on the surface of the second epitaxial layer; forming a third epitaxial layer on the N-type buried layer and the upper surface of the P column; then forming grooves on both sides above each of the P columns in the third epitaxial layer; then forming a body region between each of the grooves; Step 4: forming an ILD layer to cover the trench, the body region and the third epitaxial layer; and then forming a metal passivation layer on the third epitaxial layer; Step 5: thinning the back side of the substrate until the thickness of the P column is 1 to 5 microns; Step 6: forming a field stop injection layer on the back side of the substrate; and then forming a boron injection layer on the P column end on the back side of the substrate; Step 7: forming a layer of metal electrode on the back side of the substrate.

2. The process method for producing a front-side super junction back-side IGBT according to claim 1, characterized in that: The first and second epitaxial layers in step 1 are N-type epitaxial layers, and the resistivity of the first epitaxial layer is lower than the resistivity of the second epitaxial layer.

3. The process method of the front-side super junction back-side IGBT according to claim 2, characterized in that: In step 1, the bulk concentration of the first epitaxial layer is E15-E18.

4. The process method for front-side super junction back-side IGBT according to claim 1, characterized in that: In step three, N-type implantation regions closely attached to the trench are formed on both sides of each body region.

5. The process method of the front-side super junction back-side IGBT according to claim 1, characterized in that: Before forming the metal passivation layer in step 4, a groove is formed in the ILD layer above the body region; then the metal passivation layer is formed on the third epitaxial layer, and the metal passivation layer fills the groove.

6. The process method for front-side super junction back-side IGBT according to claim 1, characterized in that: The body concentration of the field stop injection layer in step six is ​​E11-E14.

7. The process for producing a front-side super junction back-side IGBT according to claim 1, characterized in that: The implantation concentration of the boron implantation layer in step six is ​​E11-E15.

8. The process method of the front-side super junction back-side IGBT according to claim 1, characterized in that: The depth of the field stop injection layer in step six is ​​1 to 30 microns.

9. The process method of the front-side super junction back-side IGBT according to claim 1, characterized in that: The implantation depth of the boron implantation layer in step six is ​​0.1 to 5 microns.

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