Construction method and processing device, storage medium, and coding and decoding method

Abstract

A method for constructing a permutation matrix or a check matrix, a processing device, a storage medium and a coding method. The method for constructing the permutation matrix comprises: obtaining a base matrix for the permutation matrix; and performing lifting on the base matrix to obtain the permutation matrix. The lifting on the base matrix to obtain the permutation matrix comprises: obtaining a modulus graph of the base matrix, obtaining each macro ring in the modulus graph, and for each macro ring in the modulus graph, determining the size of a short ring corresponding to the macro ring in a Tanner graph of a check matrix corresponding to the permutation matrix from an equivalent cycle value ECS of the macro ring, and determining whether at least one cycle value in the macro ring needs to be set according to the size of the short ring. The method can more efficiently obtain a required permutation matrix.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a method for constructing a permutation matrix or a check matrix, a processing device, a storage medium, and a coding and decoding method. BACKGROUND

[0002] In a communication system, in order to combat the interference caused by the channel and improve the reliability of information transmission, a forward error correction code (FEC) technique is often used, that is, the redundancy of information is increased at the sending end, and the redundancy information is used for error correction at the receiving end.

[0003] As shown in Figure 1 , a typical coding and decoding process includes a source, source coding, channel coding, modulation, a channel, demodulation, channel decoding, source decoding, and a sink, wherein the channel coding and decoding can use forward error correction technology. Current channel coding and decoding technologies mainly include block codes, convolutional codes, Turbo codes, LDPC codes, etc.

[0004] The basic principle of channel coding and decoding is taken as an example of binary coding, as shown in Figure 2 , some redundancy bit sequences p are added to the tail of the information bit sequence u to obtain the code word sequence c = [u, p]. Then, the code word sequence is modulated and sent to the channel. At the receiving end, the received redundancy information p is used to correct and detect the information bit sequence part u. This correction and detection operation is called decoding.

[0005] LDPC codes are widely used in various communication systems, such as 5G NR (5th Generation Mobile Communication Network Air Interface Standard), WiFi (Wireless Fidelity), DVB (Digital Video Broadcasting), or optical communication systems, due to their close-to-Shannon-limit performance and high throughput brought by parallel decoding. SUMMARY

[0006] At least one embodiment of the present disclosure provides a method for constructing a permutation matrix for a QC-LDPC code, the method comprising: obtaining a base matrix for the permutation matrix; and performing lifting on the base matrix to obtain the permutation matrix. Wherein the lifting on the base matrix to obtain the permutation matrix comprises: obtaining a prime modulus graph of the base matrix, obtaining each macro ring in the prime modulus graph, and for each macro ring in the prime modulus graph, determining the size of a short ring corresponding to the macro ring in a Tanner graph of a check matrix corresponding to the permutation matrix from an equivalent cycle value ECS of the macro ring, and determining whether at least one cycle value in the macro ring needs to be set according to the size of the short ring.

[0007] At least one embodiment of the present disclosure provides a method for constructing a check matrix of a QC-LDPC code, comprising: obtaining the permutation matrix according to the method described above, and obtaining the check matrix from the permutation matrix.

[0008] At least one embodiment of the present disclosure provides a processing device, comprising: a processing unit and a memory, wherein one or more computer program modules are stored on the memory; wherein the one or more computer program modules are configured to be executed by the processing unit to implement the method for constructing a permutation matrix or constructing a check matrix as described above.

[0009] At least one embodiment of the present disclosure provides a non-transitory readable storage medium, wherein the non-transitory readable storage medium stores computer instructions, wherein the computer instructions are executed by a processor to implement the method for constructing a permutation matrix or constructing a check matrix as described above.

[0010] At least one embodiment of the present disclosure provides a coding method, comprising: using the check matrix of a QC-LDPC code obtained by the method for constructing a check matrix as described above to perform channel encoding or channel decoding on a code stream. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described in the following are only related to some embodiments of the present disclosure, but not limited to the present disclosure.

[0012] Figure 1 A schematic diagram of an exemplary coding process;

[0013] Figure 2 A schematic diagram of obtaining a codeword sequence c from an information bit sequence u and a redundancy bit sequence p;

[0014] Figure 3 A schematic diagram of a Tanner graph of an exemplary check matrix;

[0015] Figure 4 A schematic diagram of a protograph of an exemplary base matrix;

[0016] Figure 5A A schematic diagram of a Tanner graph of a permutation matrix;

[0017] Figure 5B A schematic diagram of performing interleaving permutation on a protograph;

[0018] Figure 6A , Figure 6B and Figure 6C are in the form of permutation matrices for code rates of 1 / 6, 1 / 4 and 1 / 3, respectively;

[0019] Figure 7 A schematic diagram of a method for constructing a base matrix of a permutation matrix for a QC-LDPC code according to an embodiment of the present disclosure;

[0020] Figure 8 A flowchart of a process for designing a base matrix according to an embodiment of the present disclosure;

[0021] Figure 9 A flowchart of a process for constructing a permutation matrix for a QC-LDPC code according to an embodiment of the present disclosure;

[0022] Figure 10 A schematic diagram of a short cycle in a Tanner graph of an exemplary permutation matrix;

[0023] Figure 11 A schematic diagram of a short cycle in a Tanner graph of an exemplary permutation matrix;

[0024] Figure 12 A schematic diagram of an exemplary tree rooted at a variable node of a base matrix;

[0025] Figure 13 A flowchart of a process for tree search;

[0026] Figure 14 A schematic diagram showing the performance of permutation matrices corresponding to three code lengths at a code rate of 1 / 6;

[0027] Figure 15 A schematic diagram showing the performance of permutation matrices corresponding to three code lengths at a code rate of 1 / 4;

[0028] Figure 16 A schematic diagram showing the performance of permutation matrices corresponding to three code lengths at a code rate of 1 / 3;

[0029] Figure 17 A schematic diagram of a processing device according to at least one embodiment of the present disclosure;

[0030] Figure 18 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, which may change accordingly when the absolute position of the described objects changes.

[0033] LDPC codes are essentially linear block codes, but with a relatively low proportion of "1"s in the parity-check matrix. Each LDPC code can be identified by a generator matrix G, and codewords are generated by multiplying the information bits by the generator matrix, i.e., c = u G. On the other hand, LDPC codes can be represented without a generator matrix G, but instead using a parity-check matrix H. The relationship between the parity-check matrix and the generator matrix is: G H T = 0. Assume the parity-check matrix can be written as: H = [H u H p ], where H u H corresponds to the information bit portion of the parity check matrix. p This corresponds to the parity bit portion of the parity check matrix. Therefore, the generator matrix can be written as... .

[0034] The number of 1s in a row of the parity-check matrix is ​​called the row weight, and the number of 1s in a column is called the column weight. If all rows have the same row weight and all columns have the same column weight, the LDPC code is called a regular code; otherwise, it is called an irregular code. The distribution of row and column weights can also be used to analyze LDPC codes. v d represents the number of column weights. c λ represents the number of rows with the same number of rows. d This indicates that the column weight is d in d. v The proportion of each column in the weight, ρ d This indicates that the column weight is d in d. c The proportion of row weight in the total row weight can be represented by the following formula:

[0035] , .

[0036] In density evolution theory, column weight and row weight determine the performance of LDPC codes.

[0037] Another representation of LDPC codes is Tanner graph, which is a bipartite graph. Take the code represented by the following simple check matrix H as an example:

[0038]

[0039] The corresponding Tanner graph is shown in FIG. 1. Figure 3 In the Tanner graph, the nodes corresponding to the rows of matrix H are called check nodes, the nodes corresponding to the columns of matrix H are called variable nodes, and if the value at the intersection of a row and a column in matrix H is 1, then there is a line connecting the two nodes, which is called an edge. In the Tanner graph shown in FIG. 1, there are 10 variable nodes and 5 check nodes. Figure 3

[0040] Tanner graph is very helpful for studying LDPC codes, such as loops and girth in the Tanner graph. A loop in the Tanner graph refers to a group of lines that starts from a node S, proceeds along the lines, and returns to the node S, and the size of the loop is the number of lines or edges. In FIG. 1, the bold lines form a loop. The girth of the Tanner graph refers to the size of the smallest loop. In addition, there is also the concept of extrinsic information freedom in the Tanner graph, which refers to the number of edges connected to the check nodes in a loop. Figure 3

[0041] Structured LDPC codes are also called quasi-cyclic (QC-LDPC) codes, which are easy to parallelize in hardware and can achieve high throughput, so they are adopted by many systems. The following matrix P is a permutation matrix of a QC-LDPC code, and each value in the matrix represents a Z Z sub-matrix, and Z is called a lifting factor.

[0042]

[0043] When the value in matrix P is -1, it represents a Z Z all-zero matrix. Other values x represent a Z Z identity matrix cyclically right-shifted by x, as shown in the following example. The real check matrix is the expansion of P. Taking Z = 8 as an example, the following circulant matrix can be obtained,

[0044] .

[0045] ​​The basis matrix corresponding to the permutation matrix is ​​defined as follows: elements greater than or equal to zero in the permutation matrix are 1, and all others are 0. That is, matrix B below is the basis matrix of the permutation matrix above:

[0046]

[0047] When designing QC-LDPC codes, the basis matrix can be designed first, and then the basis matrix can be lifted (i.e., the cyclic values ​​of the positions where 1 is in the basis matrix is ​​determined) to obtain the permutation matrix. The Tanner graph obtained based on the basis matrix is ​​called the protograph. For example, the protograph of the B matrix above is as follows: Figure 4 As shown.

[0048] The lifting of the basis matrix is ​​essentially a permutation of the original schema. This process involves copying the original schema by Z (the lifting factor), where Z is a positive integer. For example, with Z=8, the original schema is first copied 8 times, resulting in the following: Figure 5A The Tanner plot shown. Taking P(1,1) = 1 as an example,

[0049]

[0050] This represents the matrix obtained by cyclically shifting right by 1 bit. Therefore, by performing an interleaving permutation on the original model diagram, we obtain the following: Figure 5B The Tanner diagram shown is illustrated. Similarly, by interleaving and permuting all elements greater than or equal to 0 in the base matrix, we can obtain the corresponding Tanner diagram for the parity check matrix.

[0051] The optimal decoders for both Turbo codes and LDPC codes employ iterative decoding methods. During iteration, the decoder passes messages, and the probability density of these messages continuously changes throughout the iteration process. Density evolution (DE) theory is based on this principle to predict the performance of an LDPC code. Specifically, DE calculates the probability density of a message based on the distribution of row and column weights. Density evolution tools can be used to determine the optimal distribution of row and column weights when constructing LDPC codes. For example, consider the following distribution of row and column weights:

[0052] ,

[0053] Assume the probability of the verification node passing information to the variable node is p. (c) The probability of the variable node passing information to the verification node is p. (v) The probability change relationship between the variable node and the verification node is as follows, where l is the iteration number and the function Γ is... -1 (x) represents ф in the decoding calculation.-1 (x) the change in probability introduced by the operation of the function.

[0054]

[0055]

[0056] For generating QC-LDPC codes based on a base matrix, the base matrix can be computed using a density evolution method. For example, the density evolution method can use a protograph extrinsic-information-transfer (PEXIT) algorithm to compute the base matrix, resulting in probabilities of the transferred information, for example, the steps of the algorithm are as follows:

[0057] (1) Initialization: Choose an E b / N o , initialize σ ch = (σ ch,0 , …, σ ch,N-1 ),

[0058] R is the code rate

[0059] (2) Variable node to check node: b ij is the number of edges between variable node j and check node i, δ ci = 1 when c=i, otherwise δ ci = 0,

[0060]

[0061] (3) Check node to variable node: δ vj = 1 when v=j, otherwise δ vj = 0,

[0062]

[0063] (4) Cumulative mutual information computation:

[0064]

[0065] (5) Stopping iteration criterion, if is close to 1, stop, otherwise go to step (2) to continue iteration.

[0066] In the above steps, the function J(x) is:

[0067]

[0068] J(x) and J-1 (x) can be calculated using the following simplified algorithm:

[0069] ,

[0070]

[0071] ,

[0072]

[0073] WiFi, as a wireless local area network technology, is popular all over the world because of its convenience, easy use and low price. WiFi introduces structured QC-LDPC code in the 802.11n standard to improve the throughput of WiFi network. However, the QC-LDPC of the 802.11n standard has only several code rates such as 1 / 2, 2 / 3, 3 / 4 and 5 / 6, and lacks low code rate LDPC code. The QC-LDPC of WiFi adopts an irregular repeat-accumulate (Irregular Repeat-Accumulate) structure of irregular code, and the LDPC code of this structure is easy to implement in hardware while ensuring that the performance meets the requirements.

[0074] Taking 1 / 2 code rate as an example, as shown in the following permutation matrix, the size of the permutation matrix is 12 24, the lifting factor Z = 27 / 54 / 81, and the part corresponding to the check bits in the dashed line range is 12 12 size, and this part has a fixed structure, which is easy to implement in the encoder. The part outside the red dashed line box is the part to be designed. The row weights of each row of the base matrix of the QC-LDPC of the above WiFi 802.11n standard under each code rate differ by at most 1, and the total number of 1s in the base matrix is between 79 and 88. For example, taking 1 / 2 code rate as an example, the row weights of each row in the base matrix are two values {7, 8}, and the total weight of the base matrix is 88.

[0075]

[0076] The QC-LDPC of the 802.11n standard has only several code rates such as 1 / 2, 2 / 3, 3 / 4 and 5 / 6, and lacks low code rate LDPC code. At least one embodiment of the present disclosure provides low code rate LDPC codes suitable for the 802.11n standard in the case that the existing encoder structure can be reused, and these code rates include 1 / 6, 1 / 4 and 1 / 3 code rates, which can be used in low signal-to-noise ratio and long distance transmission environment.

[0077] In at least one embodiment of the present disclosure, the permutation matrices for 1 / 6, 1 / 4 and 1 / 3 code rates can adopt similar structures as those for 1 / 2, 2 / 3, 3 / 4 and 5 / 6 code rates, and the LDPC encoders for 1 / 2, 2 / 3, 3 / 4 and 5 / 6 code rates of the QC-LDPC of the preceding 802.11n standard can be reused, for example, Figure 6A , Figure 6B and Figure 6C are in the form of permutation matrices for 1 / 6, 1 / 4 and 1 / 3 code rates respectively, and x in each matrix is a cyclic value to be designed. The sizes of these permutation matrices are 20 24, 18 24 and 16 24 respectively.

[0078] The present disclosure provides a method for designing a QC-LDPC code and the obtained QC-LDPC code, which includes methods for designing a base matrix, designing a permutation matrix from the base matrix, etc. The methods and the LDPC code and permutation matrix obtained therefrom are described below.

[0079] At least one embodiment of the present disclosure provides a method for constructing a base matrix of a permutation matrix for a QC-LDPC code, referring to the schematic diagram of Figure 7 , the method includes:

[0080] Step 710, obtaining a code rate of the permutation matrix, and determining the number of columns Ns corresponding to systematic bits in the base matrix and the number of rows Nrow of the base matrix according to the code rate;

[0081] Step 720, determining the maximum row weight dc of the base matrix and the total weight range of the base matrix, wherein the row weight of each row in the base matrix is dc or dc-1;

[0082] Step 730, determining a first range of the number of rows with a row weight of dc-1 and a second range of the number of rows with a row weight of dc in the base matrix according to the total weight range of the base matrix and the number of rows Nrow of the base matrix;

[0083] Step 740, filling each row corresponding to the systematic bit part of the initial base matrix of the base matrix to obtain an intermediate base matrix according to the number of rows Nrow of the base matrix, the total weight range, the first range and the second range;

[0084] Step 750, performing convergence calculation on the intermediate base matrix to determine whether the intermediate base matrix converges, and in response to the intermediate base matrix converging, determining the intermediate base matrix as the base matrix.

[0085] For example, the systematic bit part of the initial base matrix is completely blank or at least part of the elements have been filled.

[0086] The method for constructing the base matrix of the permutation matrix of the QC-LDPC code according to the embodiments of the present disclosure can conveniently construct the base matrix meeting the performance requirement, so as to further construct the corresponding permutation matrix, especially the permutation matrix for the code rates of 1 / 6, 1 / 4 and 1 / 3.

[0087] For example, in at least one embodiment of the present disclosure, the method for constructing the base matrix of the permutation matrix of the QC-LDPC code further comprises: in response to the intermediate base matrix not converging, resetting at least part of the parameters of the intermediate base matrix, re-performing the padding processing of each row of the reset intermediate base matrix to obtain a new intermediate base matrix, performing the convergence calculation on the new intermediate base matrix again, and in response to the new intermediate base matrix converging, determining the new intermediate base matrix as the base matrix.

[0088] For example, in at least one embodiment of the present disclosure, in one example of step 750, performing the convergence calculation comprises: obtaining a signal noise ratio (SNR) and an iteration number, and performing the convergence calculation by using a density evolution tool (for example, a protograph extrinsic information transfer (PEXIT)) according to the signal noise ratio and the iteration number.

[0089] It should be noted that the steps 710-750 are not limited to be executed in the above-mentioned order, and each step can be exchanged or executed in parallel as long as there is no conflict, for example, the step 710 and the step 720 can be exchanged or executed in parallel.

[0090] In at least one embodiment, the code rate of the permutation matrix to be designed is 1 / 6, 1 / 4 or 1 / 3. For example, the total weight range of the corresponding base matrix is 79-88; for the code rate of 1 / 6, the maximum row weight dc = 5 or 4; for the code rate of 1 / 4, the maximum row weight dc = 5; and for the code rate of 1 / 3, the maximum row weight dc = 6 or 5. In this way, the LDPC code can be multiplexed with the code rate of 1 / 2-5 / 6, which can be used in low signal-to-noise ratio and long distance transmission environment, and also reduces the development cost and manufacturing cost.

[0091] In at least one embodiment of the present disclosure, the encoder or decoder encodes or decodes based on the permutation matrix, processes according to the rows of the permutation matrix, for example, one clock cycle processes one element in the permutation matrix, and sets, for example, two processing units to process the elements in the permutation matrix in a pipelined manner in sequence (for example, row by row). At this time, the inventors have noticed that if the row weights of two adjacent rows (for example) of the permutation matrix differ greatly, the speeds of the two processing units will not match, and at this time, more additional clock cycles are needed for waiting, and the implementation of the decoder hardware will be more troublesome, and the decoding speed will be affected. Therefore, when designing the base matrix, in at least one embodiment of the present disclosure, the row weights of two adjacent rows differ by at most 1 (the same strategy as the WiFi high-rate QC-LDPC code). In addition, the total decoding speed depends on the number of 1s in the base matrix, so the total weight of the base matrix is limited to 79~88, and the clock frequency of the encoder or decoder for LDPC codes with code rates of, for example, 1 / 2~5 / 6 is scaled or the clock frequency is scaled in proportion to the bandwidth. In addition, the storage unit of the encoder or decoder is set according to the total weight of the base matrix, so that the total weight is within 79~88, and the encoder or decoder for LDPC codes with code rates of, for example, 1 / 2~5 / 6 does not need to additionally increase the storage unit. In addition, the above row weights can make the LDPC code have better performance than smaller row weights.

[0092] The following takes the code rates of 1 / 6, 1 / 4 or 1 / 3 as an example to describe the process of designing the base matrix, as shown in Figure 8 In addition, for code rates of 1 / 6, 1 / 4 and 1 / 3, the sizes of the permutation matrices are 20 24, 18 24 and 16 24, respectively, and the corresponding permutation matrix forms are Figure 6A , Figure 6B and Figure 6C respectively, and x in each to-be-designed permutation matrix is a to-be-designed cyclic value.

[0093] As shown in Figure 8 , in step 810, the maximum row weight dc of the to-be-designed base matrix is determined, for example, the row weight of each row of the base matrix is randomly selected from {dc, dc-1}, for example:

[0094] a) for a code rate of 1 / 6, the maximum row weight dc = 5 or 4;

[0095] b) for a code rate of 1 / 4, the maximum row weight dc = 5;

[0096] c) for a code rate of 1 / 3, the maximum row weight dc = 6 or 5.

[0097] The total weight of the base matrix to be designed is set in the range of 79~88, in step 820, the range of the number of rows with row weight dc-1 in the base matrix is determined, for example, at most M, the range of the number of rows with row weight dc in the base matrix is determined, for example, at most N, for example:

[0098] a) for 1 / 6 code rate, dc = 5: M = 20, N = 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0;

[0099] b) for 1 / 6 code rate, dc = 4: M = 1, N = 20;

[0100] c) for 1 / 4 code rate, dc = 5: M = 18, N = 16 / 15 / 14 / 13 / 12 / 11 / 10 / 9 / 8 / 7;

[0101] d) for 1 / 3 code rate, dc = 6: M = 16, N = 8 / 7 / 6 / 5 / 4 / 3 / 2 / 1 / 0;

[0102] e) for 1 / 3 code rate, dc = 5: M = 1, N = 16.

[0103] The above value mode is only an example, for example, the value range of M can be given while fixing the value of N, for example, for 1 / 6 code rate, dc = 5: N = 8, M = 12~20.

[0104] In step 830, the number of columns Ns corresponding to the system bits in the base matrix is set, which is used when randomly generating the element positions of the base matrix, and the number of rows Nrow of the base matrix is determined, for example, further reference can be made to Figure 6A~Figure 6C :

[0105] a) for 1 / 6 code rate, Ns = 4, Nrow = 20;

[0106] b) for 1 / 4 code rate, Ns = 6, Nrow = 18;

[0107] c) for 1 / 3 code rate, Ns = 8, Nrow = 16.

[0108] In step 840, the signal-to-noise ratio (SNR) and the number of iterations for the PEXIT tool are set.

[0109] After setting the above parameters, the processing starts from the first row to the last row of the base matrix to be designed, for example, sequentially processing each row. In each processing, the number of rows with row weight dc and the number of rows with row weight dc-1 in the base matrix to be designed are recorded as Ndc and Ndc1, respectively, and the initial values of the two examples are both 0. In step 850, Ndc and Ndc1 are initialized to 0, and the index rowindex of the current row is initialized to 0 (corresponding to the 0th row).

[0110] For the current row, if Ndc < N and Ndc1 < M, a row weight is randomly selected from {dc, dc-1} as the row weight of this row, assuming that the row weight is d, and Ndc or Ndc1 is increased by 1 accordingly; if Ndc ≥ N, dc-1 is selected as the row weight d of this row; and if Ndc1 ≥ M, dc is selected as the row weight d of this row. It should be noted that there is no case where Ndc ≥ N and Ndc1 ≥ M at the same time. Further, the current row weight of the current row is determined (for example, there is an element that is non-zero (for example, 1) in addition to the cyclic value x to be designed, then the current row weight is greater than 1), which is denoted as dcurr, and the row weight to be supplemented is ds = d - dcurr, and then ds non-zero values, for example, 1, are randomly selected and filled in the x position in the current row of the above base matrix, and the remaining positions are filled with 0.

[0111] When all the rows in the base matrix to be designed have been processed in the above manner, a base matrix with randomly configured system bits is obtained, which can be referred to as an intermediate base matrix. According to the code rate (for example, 1 / 6, 1 / 4, or 1 / 3) of the base matrix, the signal-to-noise ratio (SNR) (for example, set in advance) and the number of iterations are selected, and then the density evolution tool (for example, the PEXIT tool) is used to calculate the intermediate base matrix. If the calculation converges, it is considered that a suitable candidate base matrix is found; if the calculation does not converge, the current obtained intermediate base matrix is abandoned, and all the parameters of the base matrix to be designed are reset, for example, the system bits corresponding to the cyclic value x in the base matrix in Figure 6A~Figure 6C are reset, Ndc and Ndc1 are reset, and the processing starts from the first row of the base matrix to be designed, for example, sequentially processing each row, to obtain a new intermediate base matrix with randomly configured system bits again. The density evolution tool is still used to determine whether the calculation converges for the new base matrix. Through the above process, multiple suitable candidate base matrices can be obtained for the same code rate.

[0112] For details, please refer to Figure 8In the example shown, in step 860, the row weight dp of the check bit part in the current row (i.e. the row pointed to by rowindex) is determined; in step 870, it is first determined whether Ndc < N is true, if not (N), the row weight d of the current row is set to dc-1, i.e. d = dc-1, otherwise (Y) it is determined whether Ndc1 < M is true, if not (N), the row weight d of the current row is set to dc, otherwise (Y) d is randomly assigned a value from dc and dc-1, if dc is selected, Ndc is incremented by 1, if dc-1 is selected, Ndc1 is incremented by 1; in step 880, d-dp different values are randomly selected from the set {0, 1, …, Ns-1} as the values assigned to the d-dp positions in the system bits in the current row of the base matrix B; in step 890, the parameter rowindex is incremented by 1, and it is then determined whether rowindex is less than Nrow, if yes, it indicates that all the rows of the base matrix have not been processed, therefore the row pointed to by the incremented rowindex is processed in step 860, otherwise the processing of all the rows of the base matrix has been completed, the base matrix is calculated using the PEXIT tool, if it converges, the base matrix search is completed, if it does not converge, the new base matrix search is restarted in step 850.

[0113] At least one embodiment of the present disclosure also provides a method for constructing a permutation matrix for a QC-LDPC code, as shown in Figure 9 The method comprises:

[0114] In step 910, a base matrix for the permutation matrix is obtained;

[0115] In step 920, the base matrix is lifted to obtain the permutation matrix.

[0116] In the above method, the base matrix in step 910 is not limited to the base matrix obtained according to the above-mentioned embodiments, for example Figure 7 The base matrix is lifted in step 920 to obtain the required permutation matrix.

[0117] For example, step 920 comprises: obtaining a prime modulus graph of the base matrix, obtaining each macro ring in the prime modulus graph, and for each macro ring in the prime modulus graph, determining the size of the short ring corresponding to the macro ring in the Tanner graph of the check matrix corresponding to the permutation matrix from the equivalent cycle value ECS of the macro ring, and determining whether at least one cycle value in the macro ring needs to be set according to the size of the short ring. The permutation matrix obtained in step 920 can be used to obtain the check matrix of the QC-LDPC code.

[0118] The method for constructing a permutation matrix of a QC-LDPC code can conveniently and quickly obtain a candidate permutation matrix, and is beneficial to judging the performance of the permutation matrix.

[0119] In the embodiments of the present disclosure, a "macro ring" refers to a ring in the original graph, and a "short ring" refers to a ring in the corresponding check matrix. As described above, for a macro ring in the original graph, there is at least one short ring in the corresponding check matrix.

[0120] In at least one embodiment of the present disclosure, the step 920 can further include: making the ECS of all macro rings in the original graph satisfy the requirement of the Tanner graph of the check matrix for the minimum short ring and the requirement of the extrinsic information freedom degree.

[0121] The lifting of the base matrix is to determine the cyclic value of the position of 1 in the base matrix, and the position of 0 in the base matrix is, for example, assigned a value of -1 (which represents a full 0 submatrix). The lifting process includes the process of performing interleaving permutation on the original graph to generate the Tanner graph (i.e., the real Tanner graph) of the corresponding check matrix. The ring of the Tanner graph has a relatively large impact on the performance of the LDPC code. The information transfer decoding algorithm of the LDPC code assumes that the variable nodes are independent of each other, but the existence of the short ring in the Tanner graph of the corresponding check matrix necessarily destroys the independence assumption, which makes the decoding performance decline. Generally, the longer the length of the shortest ring in the Tanner graph of the corresponding check matrix, the closer the decoding performance is to the optimal algorithm. For example, in the embodiments of the present disclosure, the length of the shortest ring can be selected to be 6 or more, i.e., the minimum ring threshold is 6 or more. For the Tanner graph of the check matrix, the greater the extrinsic information freedom degree, the better the performance of the corresponding LDPC code, and in particular, the steeper the bit error rate curve, so after judging that a ring satisfies the length constraint, it is also necessary to judge whether the extrinsic information freedom degree is greater than a certain value.

[0122] The inventors have found the number relationship between the ring on the original graph and the ring on the Tanner graph of the corresponding check matrix in the research, and according to this number relationship, the information of the ring on the Tanner graph of the corresponding check matrix can be obtained through the search of the base matrix.

[0123] In at least one embodiment of the present disclosure, the step 920 further includes: obtaining the equivalent cycle value (ECS) of the macro ring, wherein it is assumed that in the original graph, 2 The macro ring of size L is composed of the cycle values {P(i0,j0), P(i0,j1), P(i1,j1), P(i1,j2),…, P(i (L-1) ,j L )}. LIf j = 0 and L is a positive integer, then the equivalent cycle value (ECS) is determined by the following formula:

[0124] .

[0125] Therefore, the following conclusion can be drawn:

[0126] If the greatest common divisor of the ECS of a macrocycle in the original model graph and the boost factor Z is q, then the size of the short cycle in the Tanner graph corresponding to the parity-check matrix of the macrocycle in the original model graph is 2. L The Tanner plot of the parity-check matrix corresponding to Z / q corresponds to the macrocycle of the original model diagram, resulting in a size of... The number of short rings is q.

[0127] In one example, suppose Z=8, and the permutation matrix is ​​as follows P. Therefore, the protograph corresponding to P has a macrocycle of size 4 (2*L, L=2).

[0128]

[0129] Since ECS = -3 + 5 - 2 + 1 = 1, the greatest common divisor of ECS and Z is q = 1. Therefore, the size of the short ring in the Tanner graph of the parity-check matrix corresponding to the original model graph is... The corresponding check matrix Tanner graph contains one short ring of size 32. See below. Figure 10 As shown, a permutation matrix can be used to draw a graph to illustrate that there is only one short cycle of 32 in the Tanner graph. The numbers in the graph are the cycle values, and the black dots in the graph represent the cyclic identity matrix corresponding to the cycle values. Starting from H(6,1), the adjacent nodes are connected in sequence, and finally it returns to H(6,1), indicating that there is only one short cycle.

[0130] In another example, suppose Z=8, and the permutation matrix is ​​as follows P. Therefore, the original graph corresponding to P has a size of 4 ( Macrocycles (L=2)

[0131]

[0132] Since ECS = -3 + 6 - 2 + 1 = 2, the greatest common divisor of ECS and Z is q = 2. Therefore, the size of the short ring in the Tanner graph of the parity-check matrix corresponding to the original model graph is... In the Tanner diagram, there are two short rings of size 16. For example... Figure 11 As shown, there are two short rings with a size of 16.

[0133] In at least one embodiment of the present disclosure, the lifting of the base matrix employs a method of recursive calling tree search. In this embodiment, a tree is expanded with each variable node in the original graph of the base matrix as a root node, and the tree is searched to check whether there is a macro loop corresponding to the tree.

[0134] Figure 12 A tree is shown that is expanded with a variable node of the base matrix as a root node for tree search. Each variable node of the base matrix will expand into a tree, and there can be one or more macro loops on the tree, as shown in Figure 12 As shown, the dashed part indicates a macro loop formed. For each macro loop, each cycle value in the macro loop is assigned appropriately according to the relationship between the equivalent cycle value ECS and the short loop as described above, to meet the minimum loop threshold on the Tanner graph of the set check matrix.

[0135] In at least one embodiment of the present disclosure, in the tree search, the entire search is divided into processing of two kinds of nodes in a recursive calling manner: a variable node processing function and a check node processing function. The variable node processing function is called initially from the root node to start processing, because the neighbor nodes of the variable node in the tree are check nodes, the check node processing function is continuously called in the variable node processing function to process the neighbor nodes of the variable node, and the neighbor nodes of the check node are another variable node, so the variable node processing function is continuously called in the check node processing function to process the neighbor nodes of the check node. This goes on and on until all macro loops originating from the root node are found, and each macro loop is assigned a cycle value to form a permutation matrix P, and the ECS of all macro loops meets the requirement of the minimum loop on the Tanner graph and the requirement of the extrinsic degree of freedom.

[0136] For example, in at least one example, as shown in the schematic diagram shown in Figure 13 A tree is expanded with each variable node in the original graph of the base matrix as a root node, and the tree is searched to check whether there is a macro loop corresponding to the tree, including:

[0137] Step 1310, according to the base matrix, establishing variable node information and check node information of the original graph of the base matrix;

[0138] Step 1320, based on the variable node information and the check node information, establishing a combination of passing information used for passing between nodes in the tree search;

[0139] Step 1330, setting the initial value of the combination of passing information, recursively calling the tree to perform tree search to check whether there is a macro loop corresponding to the tree.

[0140] For example, the variable node information and the check node information each include a node index, a number of neighbor nodes, and an index array of the neighbor nodes.

[0141] For example, the passing information combination includes a root node index, a parent node index, a current search depth, and a loop node index used to record node indices of all nodes constituting a loop. For another example, the passing information combination can further include a minimum loop threshold of a Tanner graph of the check matrix and a minimum threshold of extrinsic degrees of freedom of the Tanner graph of the check matrix.

[0142] For example, in the process of the tree search, for each currently searched variable node in the tree: if the current search depth has met the minimum loop threshold of the Tanner graph of the check matrix, the tree search is stopped and a success flag is returned; if the current search depth has not reached the minimum loop threshold, but a first macro loop has been found in the tree search, equivalent cycle values ECS of the first macro loop are used to check or assign each cycle value constituting the first macro loop, so that short loops on the Tanner graph of the check matrix satisfy a condition of being greater than or equal to the minimum loop threshold; or if the current search depth has not reached the minimum loop threshold and any macro loop has been found in the tree search, the tree search is continued.

[0143] For example, in the process of the tree search, for each currently searched check node in the tree: if the current search depth has met the minimum loop threshold of the Tanner graph of the check matrix, the tree search is stopped and a success flag is returned; if the current search depth has not reached the minimum loop threshold, but a second macro loop has been found in the tree search, equivalent cycle values ECS of the second macro loop are used to check or assign each cycle value constituting the second macro loop, so that short loops on the Tanner graph of the check matrix satisfy a condition of being greater than or equal to the minimum loop threshold; or if the current search depth has not reached the minimum loop threshold and any macro loop has been found in the tree search, the tree search is continued.

[0144] For example, in the process of the tree search, for each currently searched variable node in the tree, it is further checked whether a deadlock occurs, and if the deadlock occurs, the tree search is stopped.

[0145] The equivalent cycle value ECS of the first macro ring or the second macro ring is checked or assigned to each cycle value constituting the first macro ring or the second macro ring, respectively, including: if a certain cycle value constituting the first macro ring or the second macro ring has not been assigned, a value is randomly selected in [0, Z-1], if the ECS of the first macro ring or the second macro ring satisfies the minimum ring threshold, the tree search is stopped, and a success flag is returned; or if all cycle values constituting the first macro ring or the second macro ring have been assigned, but the ECS of the first macro ring does not satisfy the minimum ring threshold, a cycle value that can be changed in the first macro ring or the second macro ring is selected, 1 is added to the cycle value, and a new cycle value is obtained by taking the modulus Z, and then a new round of search is started from the root node, wherein Z is a lifting factor.

[0146] The exemplary method of the embodiment of the present disclosure is described below in combination with specific examples of the cases where the code rates are 1 / 6, 1 / 4 and 1 / 3.

[0147] The base matrix and its original modulus graph are obtained, and when the code rates are 1 / 6, 1 / 4 and 1 / 3, the sizes of the base matrix are , and , respectively. The variable node information VNode

[24] and the check node information CNode[Nrow] are established for the base matrix, where Nrow is 20, 18 and 16. Here, it is assumed that the base matrix B is m x n dimensional, and the node information NodeInf of each node (referred to as the "current node" below) can include the following contents:

[0148]

[0149] wherein nodeID represents the index of the current node, for example, for a variable node, the index value is in [0, n-1], and for a check node, the index value is in [0, m-1]; size represents the number of neighbor nodes of the current node, that is, the number of nodes connected to the node in the original modulus graph; and index

[24] represents the index array of the neighbor nodes of the current node, and as described above, the maximum number of rows and columns of the base matrix is 24, so the maximum number of elements in the array is 24.

[0150] In order to facilitate tree search, transmission information transmitted between nodes during tree search is established, which can include the following contents:

[0151]

[0152] In the original graph, a macro cycle is a cycle that starts from a variable node, proceeds through the search and returns to the variable node. Therefore, the initial root node in the tree search is always a variable node. Conversely, each variable node in the original graph of the base matrix is expanded into a tree with the variable node as the root node. The tree is searched to check whether a macro cycle corresponding to the tree exists. When the tree is searched, each node above the root node needs to know the index of the root node, so as to know whether a macro cycle has been formed. Here, origVnID represents the index of the root node.

[0153] parent represents the parent node of the current node. Since the parent node is in the neighbor list of the current node, the parent node is not searched in the search, so that the search direction is unidirectional and deadlock is avoided.

[0154] depth represents the search depth of the current node in the tree. The search depth is used to determine whether the search target has been reached. If the search depth exceeds the minimum cycle threshold defined below, the search can be terminated, thereby saving search resources and reducing search time.

[0155] cycleThresh represents the minimum cycle threshold of the Tanner graph of the target check matrix, i.e., the length of the shortest cycle. As described above, the longer the length of the shortest cycle, the closer the decoding performance to the optimal algorithm. The minimum cycle threshold can be selected according to the required decoding performance to balance the decoding performance and the search resources and time described above. For example, the minimum cycle threshold can be 6 or greater.

[0156] emdThresh represents the minimum threshold of the extrinsic information degrees of freedom.

[0157] IDsInCycle is, for example, an array with a length greater than cycleThresh, which is used to record all node indices that form a cycle.

[0158] In another example, cycleThresh and emdThresh can be saved and called as system parameters without being part of the passing information. For example, cycleThresh can be selected to be greater than or equal to 6, and emdThresh can be selected to be greater than or equal to 3.

[0159] Before the recursive call of the tree search, the initial values of the passing information are set, for example:

[0160]

[0161] When the tree search is performed with a variable node of the base matrix as the root node, each variable node is expanded into a tree. An example of the obtained tree is shown in FIG. 2. Figure 12In the tree, in the process of searching upwards along the root node, at each node it can be known through the node information that the node is a variable node or a check node, the number of its neighbor nodes and which nodes specifically, and at the same time through the passing information it can be known the history information of the current search process. For example, in Figure 12 the root node is adjacent to 4 check nodes, for example, in the search process the search is started from the right neighbor node, then the first check node CNx on the right is searched first, the check node has two adjacent variable nodes VNa and VNb, then the variable node VNa on the right is searched first, but the branch terminates here, so the search of the branch is ended, then the variable VNb on the left is searched, but the branch terminates here, so the search of the branch is ended, at this time the first check node CNx has been searched completely, then the second check node CNy on the right of the root node is further searched in the above-mentioned manner.

[0162] The processing of each variable node (hereinafter referred to as “current variable node”) is as follows.

[0163] First, it is judged whether the search depth depth corresponding to the current variable node has met the minimum cycle threshold, if yes, i.e. depth>cycleThresh, the search of the branch reaching the current variable node is stopped, and a success flag is returned.

[0164] If the search depth does not reach the minimum cycle threshold, i.e. depth>cycleThresh is not met, but a macro cycle (hereinafter referred to as “first macro cycle”) has been found through the search, i.e. the index of the current variable node is the same as the index of the root node origVnID, then the equivalent cycle value (ECS) is applied to check or assign the cycle values of each node constituting the macro cycle, to ensure that the short cycle on the Tanner graph of the corresponding check matrix satisfies cycleThresh. As mentioned above, each node of the macro cycle can be obtained through the IDsInCycle array. Next, the cycle values on the macro cycle are assigned (assigned values), if a cycle value has not been assigned, a value is randomly selected in [0, Z-1], if after assigning the cycle values of each node the ECS of the macro cycle obtained satisfies the condition of the minimum cycle on the Tanner graph of the corresponding check matrix, i.e. then the branch search is stopped, and a success flag is returned; if all the cycle values have been assigned, but the ECS of the macro cycle obtained does not satisfy the condition of the minimum cycle on the Tanner graph, i.e. If the condition is met, then the loop value that can be changed (the loop value corresponding to the parity bit cannot be changed, while the loop value corresponding to the system bit can be changed) in this macrocycle is incremented by 1 and modulo Z to obtain a new loop value. For example, the loop value that can be changed at the deepest search depth is incremented by 1 and modulo Z to obtain a new loop value. Then, a new round of search begins from the first variable node. For a macrocycle that satisfies the condition of the minimum cycle on the Tanner graph of the corresponding parity matrix, it is checked whether the Tanner graph of the parity matrix corresponding to the macrocycle satisfies the condition of the minimum threshold of the external information degrees of freedom, that is, whether the external information degrees of freedom of the Tanner graph of the parity matrix is ​​> emdThresh. If it is satisfied, the subsequent operation continues to retain the corresponding permutation matrix; otherwise, the search ends, and the next candidate basis matrix can be obtained and improved to obtain the permutation matrix.

[0165] If the search depth does not reach the minimum cycle threshold (depth≤cycleThresh) and no macrocycle is found, then the nodeID of the current variable node is added to the IDsInCycle array, i.e., IDsInCycle[depth] = nodeID, and depth is incremented by 1. Then, the check nodes among the neighboring nodes of the current variable node, except for the ID parent, are called and processed one by one. The processing of check nodes will be as follows.

[0166] Because deadlock can occur during tree search, such as Figure 13 As shown, at depth=2, variable node 5 (VN5) itself contains a macrocycle of size 4 (shown by the dashed line in the diagram, sequentially from node VN5, node CN5, node VN3, node CN4, and back to node VN5). If this macrocycle is not removed when the search reaches variable node 5 again at depth=6, continuing the search will result in a deadlock. Therefore, it is necessary to check for deadlock at each variable node. If a deadlock occurs, the search on that branch of the tree needs to be stopped. Since IDsInCycle already stores all ancestor nodes, checking for deadlocks becomes easy; simply compare the variable node IDs of all ancestor nodes except the first variable node with the current variable node ID to determine if a deadlock exists.

[0167] The processing for each verification node (hereinafter referred to as "current verification node") is as follows.

[0168] First, determine whether the search depth corresponding to the current verification node has met the minimum cycle threshold. If depth > cycleThresh, stop searching the branch that leads to the current verification node and return a success flag.

[0169] If the search depth does not reach the minimum cycle threshold (i.e., depth > cycleThresh), but a macrocycle has been found through the search (e.g., referred to here as the "second macrocycle"), meaning the index of the current check node is the same as the index origVnID of the root node, then the equivalent cycle value (ECS) is applied to check or assign the cycle values ​​of each node constituting this macrocycle to ensure that the short cycles on the Tanner graph of the corresponding check matrix satisfy a condition greater than or equal to cycleThresh. As mentioned above, each node of this macrocycle can be obtained through the IDsInCycle array. Next, the cycle values ​​on this macrocycle are assigned (assigned). If a cycle value has not yet been assigned, a value is randomly selected from [0, Z-1]. If the ECS of the macrocycle obtained after assigning the cycle values ​​satisfies the condition of the minimum cycle on the Tanner graph of the corresponding check matrix, i.e. If the search for this branch fails, the search stops and a success flag is returned; if all cycle values ​​have been assigned, but the ECS of the resulting macrocycle does not satisfy the minimum cycle condition on the Tanner graph, then... If the condition is met, then the loop value that can be changed (the loop value corresponding to the parity bit cannot be changed, while the loop value corresponding to the system bit can be changed) in this macrocycle is incremented by 1 and modulo Z to obtain a new loop value. For example, the loop value that can be changed at the deepest search depth is incremented by 1 and modulo Z to obtain a new loop value. Then, a new round of search begins from the first variable node. Similarly, for a macrocycle that satisfies the condition of the minimum cycle on the Tanner graph of the corresponding parity matrix, it is checked whether the Tanner graph of the parity matrix corresponding to the macrocycle satisfies the condition of the minimum threshold of the external information degrees of freedom, that is, whether the external information degrees of freedom of the Tanner graph of the parity matrix is ​​> emdThresh. If it is satisfied, the subsequent operation continues to retain the corresponding permutation matrix; otherwise, the search ends, and the next candidate basis matrix can be obtained and improved to obtain the permutation matrix.

[0170] If the search depth does not reach the minimum cycle threshold (depth≤cycleThresh) and no macrocycle is found, then the nodeID of the current verification node is added to the IDsInCycle array (IDsInCycle[depth] = nodeID), and depth is incremented by 1. Then, the variable nodes among the neighboring nodes of the current verification node, except for the node with the ID parent, are processed one by one. The processing of the verification node is as described above.

[0171] Likewise, at each check node, it is checked whether a deadlock has occurred, and if a deadlock has occurred, the search of this branch of the tree is stopped. Since the IDsInCycle already stores all the ancestor nodes, checking for a deadlock becomes easy, as it is only necessary to compare the ID of the check node with the ID of the current check node, except for the first check node, to determine whether a deadlock has occurred.

[0172] By the above-mentioned way, one or more (alternative) permutation matrices are obtained which meet the requirements.

[0173] In at least one embodiment of the present disclosure, one or more permutation matrices are provided, wherein for 1 / 6 code rate, the permutation matrix of 1944 code length is as follows:

[0174] ;

[0175] The permutation matrix of 1296 code length is as follows:

[0176] ;

[0177] Or, the permutation matrix of 648 code length is as follows:

[0178] .

[0179] Figure 14 The performance corresponding to the above three code lengths of permutation matrices for 1 / 6 code rate is shown. As shown in the figure, the QC-LDPC codes of the three code lengths have excellent performance, for example, the encoder and decoder of 5 / 6 code rate LDPC code can be reused, with lower development cost.

[0180] For 1 / 4 code rate, the permutation matrix, wherein the permutation matrix of 1944 code length is as follows:

[0181] ;

[0182] The permutation matrix of 1296 code length is as follows:

[0183] ;

[0184] Or, the permutation matrix of 648 code length is as follows:

[0185] .

[0186] Figure 15 The performance corresponding to the above three code lengths of permutation matrices for 1 / 4 code rate is shown. As shown in the figure, the QC-LDPC codes of the three code lengths have excellent performance, for example, the encoder and decoder of 3 / 4 code rate LDPC code can be reused, with lower development cost

[0187] For a permutation matrix with a 1 / 3 code rate, the permutation matrix with a length of 1944 code points is as follows:

[0188] ;

[0189] The permutation matrix with a length of 1296 is as follows:

[0190] ;

[0191] Alternatively, the 648-code permutation matrix is ​​as follows:

[0192] .

[0193] Figure 16 The performance of the permutation matrices for the three code lengths at 1 / 3 code rate is shown. As illustrated, these three code lengths of QC-LDPC codes exhibit excellent performance; for example, they can reuse codecs for 2 / 3 code rate LDPC codes, resulting in lower development costs.

[0194] At least one embodiment of this disclosure provides a channel coding / decoding method, the method comprising: channel coding or channel decoding of a code stream using a generator matrix or a parity check matrix of a QC-LDPC code, wherein the code rate of the generator matrix or the parity check matrix is ​​1 / 6, 1 / 4, or 1 / 3. (Reference) Figure 1 As shown, channel coding is performed on the source-coded bitstream to obtain a bitstream to be further modulated, or channel decoding is performed on the demodulated bitstream to obtain a bitstream to be further source-decoded. For example, these bitstreams include object data and / or control signaling. That is, at least one embodiment of this disclosure correspondingly provides a channel coding method; at least one embodiment of this disclosure correspondingly also provides a channel decoding method. For example, this method can be used in a wireless communication system that may include transceivers communicating with each other, such as base stations, UEs, etc. (e.g., for mobile communication systems), or these transceivers may include access devices (e.g., wireless routers) and clients (e.g., mobile phones, computers, etc.), which can perform the aforementioned channel coding method and / or channel decoding method. For example, this method uses the parity-check matrix of the QC-LDPC code obtained by the method of constructing the parity-check matrix as described in any of the above embodiments to perform channel coding or channel decoding on the bitstream.

[0195] At least one embodiment of this disclosure also provides a communication method, which includes using the channel encoding / decoding method described above to perform channel encoding or channel decoding.

[0196] At least one embodiment of the present disclosure further provides a processing apparatus for channel coding and decoding, comprising a receiving unit and a processing unit. The receiving unit is configured to receive a code stream; and the processing unit is configured to perform channel coding or channel decoding on the code stream using a generator matrix or a check matrix of a QC-LDPC code, wherein the code rate of the generator matrix or the check matrix is 1 / 6, 1 / 4 or 1 / 3. The receiving unit and the processing unit can be implemented by software, hardware, firmware or any combination of these, for example, by an analog / digital circuit. Reference Figure 1 As shown, the code stream obtained by source coding is channel coded to obtain a code stream to be further modulated, or the code stream obtained by demodulation is channel decoded to obtain a code stream to be further source decoded; for example, the code streams include object data and / or control signaling. That is, at least one embodiment of the present disclosure correspondingly provides a channel coding apparatus; at least one embodiment of the present disclosure correspondingly further provides a channel decoding apparatus. For example, the processing apparatus for channel coding and decoding can be used in a wireless communication system, which can include transceiver devices in communication with each other, for example, including base stations, UEs, etc. (for example, for a mobile communication system), or including access devices (for example, wireless routers) and clients (for example, mobile phones, computers, etc.), which can perform the above-mentioned channel coding apparatus and / or channel decoding apparatus.

[0197] At least one embodiment of the present disclosure further provides a communication apparatus comprising the above-mentioned channel coding and decoding apparatus for channel coding or channel decoding; as needed, the communication apparatus can further comprise a source coding apparatus or a source decoding apparatus, for example, comprising a radio frequency apparatus, etc.

[0198] For example, the channel coding and decoding method and apparatus can be used in, for example, 5G NR, WiFi, DVB and optical communication systems, and embodiments of the present disclosure do not limit this.

[0199] For example, the number of columns corresponding to system bits in the permutation matrix corresponding to the generator matrix or the check matrix is Ns, and the number of rows of the permutation matrix is Nrow,

[0200] For a code rate of 1 / 6, Ns = 4 and Nrow = 20;

[0201] For a code rate of 1 / 4, Ns = 6 and Nrow = 18;

[0202] For a code rate of 1 / 3, Ns = 8 and Nrow = 16.

[0203] For example, the total weight range of the permutation matrix is 79-88;

[0204] For a code rate of 1 / 6, the row weight of each row in the base matrix is 5 or 4;

[0205] For 1 / 4 code rate, the row weight of each row in the base matrix = 5;

[0206] For 1 / 3 code rate, the row weight of each row in the base matrix = 6 or 5.

[0207] Further, the above exemplary permutation matrix can be used.

[0208] At least one embodiment of the present disclosure further provides a processing apparatus for performing the above base matrix construction method, permutation matrix construction method or coding and decoding method. Figure 17 A schematic diagram of the processing apparatus provided by at least one embodiment of the present disclosure is shown.

[0209] As shown in Figure 17 The processing apparatus 600 of the instruction pipeline includes a processing unit 610 and a memory 620, and the memory 620 stores one or more computer program modules 621, each of which includes computer executable instructions; the computer program modules 621 are executed by the processing unit 610 to perform the base matrix construction method, permutation matrix construction method or coding and decoding method of any of the above embodiments, and the base matrix construction method, permutation matrix construction method or coding and decoding method of any of the above embodiments are implemented.

[0210] At least one embodiment of the present disclosure provides a non-transitory readable storage medium, which stores computer instructions, and the computer instructions are executed by a processor to perform the base matrix construction method, permutation matrix construction method or coding and decoding method of any of the above embodiments, and the base matrix construction method, permutation matrix construction method or coding and decoding method of any of the above embodiments are implemented.

[0211] For example, the non-transitory readable storage medium is implemented as a memory, such as a volatile memory and / or a non-volatile memory. In the above embodiments, the memory can be a volatile memory, which can include a random access memory (RAM) and / or a cache, etc. The non-volatile memory can include a read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, a flash memory, etc. The memory can also store various application programs and various data used by the application programs and various data generated by the application programs, etc.

[0212] At least one embodiment of the present disclosure provides an electronic device, which includes the processing apparatus for performing the above base matrix construction method, permutation matrix construction method or coding and decoding method according to any of the above embodiments, and the base matrix construction method, permutation matrix construction method or coding and decoding method of any of the above embodiments are implemented.

[0213] For example, in at least one example, the electronic device is a processor. For example, the processor can be a single-core processor or a multi-core processor, and the processor core includes the processing device of the instruction pipeline described above; for example, the processor can be a scalar processor or a superscalar processor, and the like, and embodiments of the present disclosure do not limit this.

[0214] Figure 18 A schematic block diagram of an electronic device 700 is provided for at least one embodiment of the present disclosure. The electronic device in embodiments of the present disclosure can include, but is not limited to, a mobile terminal such as a wireless communication base station, a wireless access device (for example, an access point device), a wireless router, a mobile phone, a notebook computer, a digital broadcast receiver, a PDA (Personal Digital Assistant), a PAD (Tablet Personal Computer), a PMP (Portable Multimedia Player), a vehicle terminal (for example, a car navigation terminal), and the like, and a fixed terminal such as a digital TV, a desktop computer, and the like. Figure 18 The electronic device 700 shown is only an example and should not bring any limitation to the function and use range of embodiments of the present disclosure.

[0215] For example, as shown in Figure 18 In some examples, the electronic device 700 includes a processor (for example, a central processing unit) 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 into a random access memory (RAM) 703, for performing the base matrix construction method, the permutation matrix construction method, or the encoding and decoding method of any of the embodiments described above, and implementing the base matrix construction method, the permutation matrix construction method, or the encoding and decoding method of any of the embodiments described above. In the RAM 703, various programs and data required for the operation of the computer system are also stored. The processor 701, the ROM 702, and the RAM 703 are connected to each other by a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0216] For example, the following components can be connected to the I / O interface 705: input devices 706 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, and the like; output devices 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, and the like; storage devices 708 including, for example, a magnetic tape, a hard disk, and the like; and communication devices 709, which can further include, for example, a network interface card such as a LAN card, a modem, and the like. The communication devices 709 can allow the electronic device 700 to wirelessly or wiredly communicate with other devices to exchange data, perform communication processing via a network such as the Internet. Drivers 710 are also connected to the I / O interface 705 as necessary. Removable media 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like are mounted on the drivers 710 as necessary, so that computer programs read out therefrom are installed in the storage devices 708 as necessary. Although Figure 18 The electronic device 700 is shown to include various devices, but it is understood that not all of the shown devices are required to be implemented or included. More or fewer devices can alternatively be implemented or included.

[0217] For example, the electronic device 700 can further include a peripheral interface (not shown in the figure) and the like. The peripheral interface can be various types of interfaces, for example, a USB interface, a lightning interface, and the like. The communication devices 709 can communicate with networks and other devices through wireless communication, the networks being, for example, the Internet, an intranet, and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication can use any of a plurality of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (for example, based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0218] For example, the electronic device 700 can be any of a wireless communication base station, a wireless access device (for example, an access point device), a wireless router, a mobile phone, a tablet computer, a notebook computer, an electronic book, a game machine, a television, a digital photo frame, a navigator, and the like, and can also be any data processing device and combination of hardware, embodiments of the present disclosure not being limited thereto.

[0219] The following points are to be noted with respect to the present disclosure.

[0220] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0221] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined to obtain new embodiments.

[0222] The above only describes exemplary embodiments of the present disclosure, and is not intended to limit the protection scope of the present disclosure, and the protection scope of the present disclosure is determined by the appended claims.

Claims

1. A method for constructing a permutation matrix for QC-LDPC codes, comprising: Obtain the basis matrix used for the permutation matrix; The basis matrix is ​​enhanced to obtain the permutation matrix, which includes: Obtain the original model diagram of the basis matrix. Each macrocycle in the original model graph is obtained. For each macrocycle in the original model graph, the size of the short cycle corresponding to the macrocycle in the Tanner graph of the parity check matrix corresponding to the permutation matrix is ​​determined by the equivalent cycle value (ECS) of the macrocycle. Based on the size of the short cycle, it is determined whether at least one cycle value in the macrocycle needs to be set. Wherein, it is assumed that on the original model diagram 2 A macrocycle of size L consists of cyclic values ​​{P(i0,j0), P(i0,j1), P(i1,j1), P(i1,j2), …, P(i (L-1) ,j L )} constitute, j L If j = j0, and L is a positive integer, then the equivalent cycle value ECS is determined by the following formula: 。 2. The method according to claim 1, wherein, Improving the basis matrix to obtain the permutation matrix further includes: This ensures that the equivalent cyclic values ​​(ECS) of all macrocycles in the original model graph satisfy the requirements of the Tanner graph of the verification matrix for the minimum shortest cycle and the external information degrees of freedom.

3. The method according to claim 1, wherein, Improving the basis matrix to obtain the permutation matrix further includes: Obtain the equivalent cyclic value ECS of the macrocycle.

4. The method according to any one of claims 1-3, wherein, Obtain each macrocycle in the original model graph, and for each macrocycle in the original model graph, determine the size of the short cycle corresponding to the macrocycle in the Tanner graph of the parity check matrix corresponding to the permutation matrix by using the equivalent cycle value (ECS) of the macrocycle. Determine whether at least one cycle value in the macrocycle needs to be set based on the size of the short cycle, including: The original model graph of the basis matrix is ​​expanded into a tree with each variable node as the root node, and a tree search is performed on the tree to check whether there is a macrocycle corresponding to the tree.

5. The method according to claim 4, wherein, Expanding the tree using each variable node in the original graph of the basis matrix as the root node, and performing a tree search on the tree to check for the existence of a macrocycle corresponding to the tree, including: Based on the basis matrix, establish the variable node information and check node information of the original model graph of the basis matrix; Based on the variable node information and the verification node information, a combination of transmission information used to be passed between nodes during tree search is established. Set the initial value of the information combination, and recursively call the tree to perform the tree search to check whether there is a macrocycle corresponding to the tree.

6. The method according to claim 5, wherein, The variable node information and the verification node information each include a node index, the number of neighboring nodes, and an array of neighboring node indices.

7. The method according to claim 5, wherein, The transmitted information combination includes the root node index, parent node index, current search depth, and link node index. The link node index is used to record the node indexes of all nodes that make up a ring.

8. The method according to claim 7, wherein, The information transmission combination also includes the minimum loop threshold of the Tanner graph of the verification matrix and the minimum threshold of the external information degrees of freedom of the Tanner graph of the verification matrix.

9. The method according to claim 5, wherein, The process further includes: obtaining each macrocycle in the original model graph; determining the size of the short cycle corresponding to the macrocycle in the Tanner graph of the parity check matrix corresponding to the permutation matrix based on the equivalent cycle value (ECS) of the macrocycle; determining whether to set at least one cycle value in the macrocycle based on the size of the short cycle; and further including: During the tree search process, for each currently found variable node in the tree: If the current search depth already meets the minimum cycle threshold of the Tanner graph of the verification matrix, then stop the tree search and return a success flag; If the current search depth has not reached the minimum cycle threshold, but a first macrocycle has been found in the tree search, then the equivalent cycle value (ECS) of the first macrocycle is used to check or allocate the cycle values ​​that make up the first macrocycle, so that the short cycles on the Tanner graph of the parity check matrix satisfy a condition greater than or equal to the minimum cycle threshold; or If the current search depth has not reached the minimum cycle threshold, and any macrocycle is found in the tree search, then the tree search continues.

10. The method according to claim 9, wherein, During the tree search process, each currently searched variable node in the tree is checked for deadlock. If a deadlock occurs, the tree search is stopped.

11. The method according to claim 9, wherein, The equivalent cycle value (ECS) of the first macroloop is used to check or assign the cycle values ​​that make up the first macroloop, including: If a certain cyclic value that makes up the first macro-loop has not yet been assigned, a value is randomly selected in [0, Z-1]. If the equivalent cyclic value ECS of the first macro-loop satisfies the minimum loop threshold, the tree search is stopped and a success flag is returned. If all the cycle values ​​that make up the first macrocycle have been assigned, but the equivalent cycle value ECS of the first macrocycle does not meet the minimum cycle threshold, then select a cycle value that can be changed in the first macrocycle, add 1 and modulo Z to get a new cycle value, and then start a new round of search from the root node, where Z is the boosting factor.

12. The method according to claim 11, wherein, In the first macrocycle, select a changeable loop value, increment it by 1, and obtain a new loop value modulo Z, including: Select the loop value with the largest search depth from the changeable loop values ​​in the first macroloop, add 1, and modulo Z to obtain a new loop value.

13. The method according to claim 5, wherein, The process further includes: obtaining each macrocycle in the original model graph; determining the size of the short cycle corresponding to the macrocycle in the Tanner graph of the parity check matrix corresponding to the permutation matrix based on the equivalent cycle value (ECS) of the macrocycle; determining whether to set at least one cycle value in the macrocycle based on the size of the short cycle; and further including: During the tree search process, for each currently found verification node in the tree: If the current search depth already meets the minimum cycle threshold of the Tanner graph of the verification matrix, then stop the tree search and return a success flag; If the current search depth has not reached the minimum cycle threshold, but a second macrocycle has been found in the tree search, then the equivalent cycle value (ECS) of the second macrocycle is used to check or allocate the cycle values ​​that make up the second macrocycle, so that the short cycles on the Tanner graph of the parity check matrix satisfy a condition greater than or equal to the minimum cycle threshold; or If the current search depth has not reached the minimum cycle threshold, and any macrocycle is found in the tree search, then the tree search continues.

14. The method according to claim 13, wherein, During the tree search process, each currently searched verification node in the tree is checked for deadlock. If a deadlock occurs, the tree search is stopped.

15. The method according to any one of claims 1-3, wherein, The code rate of the permutation matrix is ​​1 / 6, 1 / 4, or 1 / 3.

16. The method according to claim 15, wherein, The total weight of the base matrix ranges from 79 to 88; For a 1 / 6 code rate, the row weight of each row in the base matrix is ​​either 5 or 4; For a 1 / 4 bit rate, the row weight of each row in the base matrix is ​​5; For a 1 / 3 bit rate, the row weight of each row in the base matrix is ​​either 6 or 5.

17. A method for constructing a parity-check matrix for a QC-LDPC code, comprising: The permutation matrix is ​​obtained according to any one of claims 1-16. The verification matrix is ​​obtained from the permutation matrix.

18. A processing apparatus, comprising: Processing unit A memory on which one or more computer program modules are stored; When the one or more computer program modules are configured to be executed by the processing unit, the method described in any one of claims 1-16 or the method described in claim 17 is implemented.

19. A non-transitory readable storage medium, wherein, The non-transitory readable storage medium stores computer instructions, wherein when the computer instructions are executed by a processor, the method described in any one of claims 1-16 or the method described in claim 17 is implemented.

20. A method for encoding and decoding, comprising: The QC-LDPC code parity check matrix obtained by the method as described in claim 17 is used to perform channel coding or channel decoding on the code stream.

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