Memory management method, memory controller and memory storage device

Abstract

The present invention belongs to the field of memory technology and provides a memory management method, a memory controller, and a memory storage device. The method divides multiple physical cells into groups based on the number of erases of the physical cells to obtain multiple first groups, each corresponding to a read disturb threshold. Within each first group, the physical cells with read counts exceeding the read disturb threshold are recorded as target physical cells. First data in the target physical cells are copied to the physical cells with the smallest operation value in the memory module. This method reduces the number of data transfers caused by the rapid accumulation of read counts for the physical cells, thereby improving the system performance of the memory storage device.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a memory management method, a memory controller, and a memory storage device. Background Art

[0002] Rewritable non-volatile memory (RNV) boasts non-volatile data, power savings, compact size, and the absence of mechanical structures, making it widely used in various electronic devices. RNV has multiple physical blocks, each of which consists of multiple physical pages. A physical block is the smallest unit for erasing data, while a physical page is the smallest unit for writing data.

[0003] When a host system wants to read stored data from a memory storage device, the memory storage device reads data from a physical block according to a read instruction. Generally, when performing data operations on a physical programming unit multiple times, data operations on other physical programming units in the same physical block may interfere with each other, causing read data errors.

[0004] How to deal with the read disturbance problem is one of the research topics that those skilled in the art have devoted themselves to. Summary of the Invention

[0005] The present invention provides a memory management method, a memory controller and a memory storage device, which can solve the technical problem of read disturbance of physical units in the memory storage device.

[0006] One embodiment of the present invention provides a memory management method, which is applied to a memory storage device, wherein the memory storage device includes a memory module, and the memory module includes multiple physical units. The method includes: dividing the multiple physical units into groups according to the number of erase times of the physical units to obtain multiple first groups, each of the first groups corresponding to a read disturbance threshold value; recording the physical units in each of the first groups whose read times exceed the read disturbance threshold value as target physical units; copying first data in the target physical units to first physical units, wherein the first physical unit is the physical unit with the smallest operation value in the memory module; and updating the logical-to-physical mapping relationship of the first data according to the physical address of the first physical unit.

[0007] In one embodiment, the step of recording the physical units in each of the first groups whose read times exceed the read disturbance threshold value as target physical units includes: establishing a read time table; the read time table is used to record the read times of the multiple physical units, and sorting the physical units in the read time table according to the read times, wherein the greater the read times, the higher the ranking of the physical unit; recording the physical units in the read time table whose read times exceed the read disturbance threshold value as target physical units.

[0008] Furthermore, in another embodiment, the step of dividing the multiple physical units into groups according to the number of times the physical units are erased to obtain multiple first groups includes: dividing the multiple physical units in the memory module into a data area and an idle area; the physical units in the data area are physical units that are regarded as having stored valid data, and the physical units in the idle area are physical units that are regarded as storing invalid data; and dividing the multiple physical units in the data area into groups according to the number of times the physical units are erased to obtain multiple first groups.

[0009] Further, in another embodiment, the step of copying the first data in the target physical unit to the first physical unit includes: selecting a first physical unit from the idle area, performing an erase operation on the first physical unit, and writing the first data into the first physical unit; marking the first data in the target physical unit as invalid data or dividing the target physical unit into the idle area.

[0010] Furthermore, in another embodiment, the step of selecting a first physical unit from the idle area includes: dividing the multiple physical units in the idle area into groups according to the number of erase times of the physical units to obtain multiple second groups, each second group corresponding to a different erase time value range; according to the size of the first data, selecting a suitable number of physical units from the second group with the smallest erase time value range as the first physical unit.

[0011] One embodiment of the present invention also provides a memory controller for controlling a memory module, wherein the memory module includes multiple physical units; the memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; a memory control circuit connected to the host interface and the memory interface; and a numerical comparison circuit connected to the memory control circuit; the memory control circuit divides the multiple physical units into groups according to the number of erase times of the physical units to obtain multiple first groups, each of the first groups corresponding to a read disturbance threshold value; the numerical comparison circuit records the physical units in each first group whose read times exceed the read disturbance threshold value as target physical units; the memory control circuit copies the first data in the target physical unit to the first physical unit, and the first physical unit is the physical unit with the smallest operation value in the memory module; the memory control circuit updates the logical-to-physical mapping relationship of the first data according to the physical address of the first physical unit.

[0012] Further, in another embodiment, the operation of the numerical comparison circuit for recording the physical units in each of the first group whose read times exceed the read interference threshold value as target physical units also includes: establishing a read time table; the read time table is used to record the read times of the multiple physical units, and sorting the physical units in the read time table according to the read times, wherein the greater the read times, the higher the ranking of the physical unit; the memory control circuit obtains the read times in the read times and sends the read times to the numerical comparison circuit, and the numerical comparison circuit records the physical units whose read times exceed the read interference threshold value as target physical units.

[0013] Further, in another embodiment, the memory control circuit divides the multiple physical units into groups according to the number of times the physical units are erased to obtain multiple first groups, including: the memory control circuit divides the multiple physical units in the memory module into a data area and an idle area; the physical units in the data area are regarded as physical units that have stored valid data, and the physical units in the idle area are regarded as physical units that store invalid data; the memory control circuit divides the multiple physical units in the data area into groups according to the number of times the physical units are erased to obtain multiple first groups.

[0014] Further, in another embodiment, the operation of the memory control circuit copying the first data in the target physical unit to the first physical unit includes: the memory control circuit selecting a first physical unit from the idle area, performing an erase operation on the first physical unit, and writing the first data into the first physical unit; the memory control circuit marking the first data in the target physical unit as invalid data or dividing the target physical unit into the idle area.

[0015] Furthermore, in another embodiment, the operation of the memory control circuit selecting the first physical unit from the idle area includes: the memory control circuit groups the multiple physical units in the idle area according to the number of erase times of the physical units to obtain multiple second groups, each second group corresponding to a different erase time value range; the memory control circuit selects an appropriate number of physical units as the first physical unit from the second group with the smallest erase time value range according to the size of the first data.

[0016] One embodiment of the present invention also provides a memory storage device, which includes a connection interface, a memory module and a memory controller; the connection interface is used to connect the memory storage device to a host system; the memory module includes multiple physical units; the memory controller is connected to the connection interface and the memory module; the memory controller divides the multiple physical units into groups according to the number of erase times of the physical units to obtain multiple first groups, each of the first groups corresponding to a read interference threshold value; the memory controller records the physical units in each first group whose read times exceed the read interference threshold value as target physical units; the memory controller copies the first data in the target physical unit to the first physical unit, and the first physical unit is the physical unit with the smallest operation value in the memory module; the memory controller updates the logical to physical mapping relationship of the first data according to the physical address of the first physical unit.

[0017] Further, in another embodiment, the operation of the memory controller recording the physical units in each of the first group whose read times exceed the read interference threshold value as target physical units also includes: establishing a read time table; the read time table is used to record the read times of the multiple physical units, and sorting the physical units in the read time table according to the read times, wherein the greater the read times, the higher the ranking of the physical unit; the memory controller obtains the read times in the read times and sends the read times to the numerical comparison circuit, and the numerical comparison circuit records the physical units whose read times exceed the read interference threshold value as target physical units.

[0018] Further, in another embodiment, the memory controller divides the multiple physical units into groups according to the number of times the physical units are erased to obtain multiple first groups, including: the memory controller divides the multiple physical units in the memory module into a data area and an idle area; the physical units in the data area are physical units that are regarded as having stored valid data, and the physical units in the idle area are physical units that are regarded as storing invalid data; the memory controller divides the multiple physical units in the data area into groups according to the number of times the physical units are erased to obtain multiple first groups.

[0019] Further, in another embodiment, the operation of the memory controller copying the first data in the target physical unit to the first physical unit includes: the memory controller selects a first physical unit from the idle area, performs an erase operation on the first physical unit, and writes the first data into the first physical unit; the memory controller marks the first data in the target physical unit as invalid data or divides the target physical unit into the idle area.

[0020] Furthermore, in another embodiment, the operation of the memory controller selecting the first physical unit from the idle area includes: the memory controller groups the multiple physical units in the idle area according to the number of erase times of the physical units to obtain multiple second groups, each second group corresponding to a different erase time value range; the memory controller selects an appropriate number of physical units as the first physical unit from the second group with the smallest erase time value range according to the size of the first data.

[0021] Based on the above, the present invention provides a memory management method, a memory controller, and a memory storage device. These methods group multiple physical cells according to their erase counts to obtain multiple first groups, each corresponding to a read disturb threshold. Within each first group, the physical cells with read counts exceeding the read disturb threshold are recorded as target physical cells. The first data in the target physical cells is then copied to the physical cells with the smallest operation value in the memory module. This reduces the number of data transfers caused by the rapid accumulation of physical cell read counts, thereby improving the system performance of the memory storage device.

[0022] In order to make the above technical features and beneficial effects of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a memory storage device according to an embodiment of the present invention;

[0024] Figure 2 A structural block diagram of a memory controller according to an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram showing the number of physical unit reads according to an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of different erase count ranges and different read disturbance thresholds for a physical unit according to an embodiment of the present invention;

[0029] Figure 7 A schematic diagram of a physical unit erase count table according to an embodiment of the present invention;

[0030] Figure 8 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0031] Figure 9 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0032] Figure 10 A schematic diagram of a bad block table according to an embodiment of the present invention;

[0033] Figure 11 A schematic diagram of a memory management module according to an embodiment of the present invention;

[0034] Figure 12 A structural block diagram of a memory controller according to an embodiment of the present invention;

[0035] Figure 13 A flowchart of a memory management method according to an embodiment of the present invention DETAILED DESCRIPTION

[0036] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0037] In the following description, suffixes such as "module," "component," or "unit" used to represent components are used only to facilitate the description of the present invention and have no specific meaning. Therefore, "module," "component," or "unit" may be used interchangeably.

[0038] The specific structure and implementation scheme of the memory storage device described in the embodiment of the present application are described in detail below with reference to the accompanying drawings and examples.

[0039] Figure 1 FIG is a schematic diagram of a memory storage device according to an embodiment of the present invention. Figure 1 The storage system 10 includes a host system 11 and a memory storage device 12. The host system 11 can be any type of computer system. For example, the host system 11 can be a laptop computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, a game console, a digital camera, and other electronic systems. The memory storage device 12 is used to store data from the host system 11. For example, the memory storage device 12 may include a solid-state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices. The host system 11 can be electrically connected to the memory storage device 12 via a Serial Advanced Technology Attachment (SATA) interface, a high-speed peripheral component interconnect express (PCI Express), a universal serial bus (USB), or other types of connection interfaces. Therefore, the host system 11 can store data in the memory storage device 12 and / or read data from the memory storage device 12.

[0040] The memory storage device 12 may include a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the memory storage device 12 to the host system 11. For example, the connection interface 121 may support a connection interface standard such as SATA, PCI Express, or USB. The memory storage device 12 can communicate with the host system 11 via the connection interface 121.

[0041] Memory module 122 is used to store data. Memory module 122 may include a rewritable non-volatile memory module. Memory module 122 includes a memory cell array. The memory cells in memory module 122 store data in the form of voltage. For example, memory module 122 may include a single-level cell (SLC) NAND flash memory module, a multi-level cell (MLC) NAND flash memory module, a triple-level cell (TLC) NAND flash memory module, a quad-level cell (QLC) NAND flash memory module, or other memory modules with similar characteristics.

[0042] Furthermore, SLC (Single-Level Cell) is the full name of Single-Level Cell, a single-layer electronic structure, each cell can store 1 bit of data, SLC reaches 1 bit / cell, the voltage change range is small when writing data, P / E life is long, and the theoretical number of erase times is more than 100,000 times; MLC (Double-Level Cell) is the full name of Multi-Level Cell, which uses a double-layer electronic structure with high and low voltages and different constructions. MLC reaches 2 bits / cell, P / E life is long, and the theoretical number of erase times is about 3000-5000 times; TLC (Triple-Level Cell) is the full name of Trinary-Level Cell, a three-layer storage cell, which is an extension of MLC flash memory. TLC reaches 3 bits / cell. Due to its higher storage density, its capacity is theoretically 1.5 times that of MLC, and its cost is lower, but its P / E life is relatively lower, and the theoretical number of erase times ranges from 1000 to 3000 times; QLC (Quad-Level Cell) is the full name of Quad-Level Cell, a four-layer storage unit, QLC flash memory particles have a higher storage density than TLC and a lower cost than TLC. The advantage is that the capacity can be made larger and the cost is lower. The disadvantage is that the P / E life is shorter and the theoretical number of erase times is only 150 times.

[0043] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be used to control the memory storage device 12. For example, the memory controller 123 can control the connection interface 121 and the memory module 122 to perform data access and data management. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other similar devices, or a combination of these devices.

[0044] In one embodiment, the memory controller 123 is also referred to as a flash memory controller. In one embodiment, the memory module 122 is also referred to as a flash memory module. The memory module 122 can receive a command sequence from the memory controller 123 and access memory cells according to the command sequence.

[0045] Figure 2 FIG is a block diagram of a memory controller according to an embodiment of the present invention. Figure 2 The memory controller 123 includes a memory control circuit 204 , a host interface 202 , and a memory interface 206 .

[0046] The memory control circuit 204 is used to control the overall operation of the memory controller 123. Specifically, the memory control circuit 204 has multiple control instructions, and when the memory storage device 12 is in operation, these control instructions are executed to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory control circuit 204 is equivalent to the description of the operation of the memory controller 123.

[0047] In this embodiment, the control instructions of the memory control circuit 204 are operated in the form of firmware. For example, the memory control circuit 204 has a microprocessor unit ( Figure 2 Not shown) and read-only memory ( Figure 2 (not shown), and control instructions are burned into this read-only memory. When the memory storage device 12 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

[0048] In another embodiment, the control instructions of the memory control circuit 204 may also be stored in a specific area of the memory module 122 (e.g., a system area of the memory module dedicated to storing system data) in the form of program code. Furthermore, the memory control circuit 204 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). Specifically, the ROM includes a boot code. When the memory controller 123 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the memory module 122 into the RAM of the memory control circuit 204. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.

[0049] Furthermore, in another embodiment, the control instructions of the memory control circuit 204 can also be implemented in hardware. For example, the memory control circuit 204 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the memory module 122. The memory write circuit issues a write instruction sequence to the memory module 122 to write data to the memory module 122. The memory read circuit issues a read instruction sequence to the memory module 122 to read data from the memory module 122. The memory erase circuit issues an erase instruction sequence to the memory module 122 to erase data from the memory module 122. The data processing circuit processes data to be written to the memory module 122 and data to be read from the memory module 122. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or instruction codes and are used to instruct the memory module 122 to perform corresponding write, read, and erase operations. In one embodiment, the memory control circuit 204 may also issue other types of command sequences to the memory module 122 to instruct it to perform corresponding operations.

[0050] The host interface 202 is electrically connected to the memory control circuit 204 and is used to receive and identify instructions and data transmitted by the host system 11. In other words, the instructions and data transmitted by the host system 11 are transmitted to the memory control circuit 204 through the host interface 202. In this embodiment, the host interface 202 is compatible with the SATA standard. However, it should be understood that the present invention is not limited to this, and the host interface 202 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard, or other suitable data transmission standards.

[0051] The memory interface 206 is electrically connected to the memory control circuit 204 and is used to access the memory module 122. In other words, data to be written to the memory module 122 will be converted into a format acceptable to the memory module 122 via the memory interface 206. Specifically, if the memory control circuit 204 wants to access the memory module 122, the memory interface 206 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasing of data, and corresponding instruction sequences for instructing various memory operations (for example, changing the read voltage level or performing garbage collection operations, etc.). These instruction sequences are generated by the memory control circuit 204 and transmitted to the memory module 122 via the memory interface 206. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as a read identification code and a memory address.

[0052] In this embodiment, the memory controller 123 can perform single-frame encoding on data stored in the same physical programming unit, or multi-frame encoding on data stored in multiple physical programming units. Depending on the encoding algorithm used, the memory controller 123 can encode the data to be protected to generate corresponding error correction codes and / or error checking codes.

[0053] In one embodiment, the memory controller 123 further includes a buffer memory 210, an error checking and correction circuit 212, and a power management circuit 208. The buffer memory 210 is electrically connected to the memory control circuit 204 and is used to temporarily store data and commands from the host system 11 or data from the memory module 122. The power management circuit 208 is electrically connected to the memory control circuit 204 and is used to control the power supply of the memory storage device 12. The error checking and correction circuit 212 is electrically connected to the memory control circuit 204 and is used to perform error checking and correction operations to ensure data accuracy.

[0054] Specifically, when the memory control circuit 204 receives a write command from the host system 11, the error checking and correction circuit 212 generates an error correcting code (ECC) and / or an error detecting code (EDC) corresponding to the data of the write command, and the memory control circuit 204 writes the data of the write command and the corresponding error correcting code and / or error detecting code into the memory module 122. Thereafter, when the memory control circuit 204 reads data from the memory module 122, it simultaneously reads the error correcting code and / or error detecting code corresponding to the data, and the error checking and correction circuit 212 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0055] Figure 3 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figure 3 , the memory module 122 includes a plurality of physical units 301(0)--301(A). Each physical unit includes a plurality of storage cells and is used to store data non-volatilely. For example, a physical unit may include one or more physical blocks. Each physical block may include a plurality of physical programming units. A physical programming unit may include one or more storage cells. Multiple storage cells in a physical programming unit can be programmed simultaneously to store data. In addition, all physical programming cells in a physical unit can be erased simultaneously.

[0056] Further, if Figure 3As shown, the memory control circuit 204 can configure multiple logical units 302 (0)--302 (B) to map physical units 301 (1)--301 (A). For example, a logical unit can be composed of one or more logical addresses. The mapping relationship between the logical unit and the physical unit can be recorded in a logical to physical mapping table (L2P). For example, the mapping of the logical physical unit to the physical physical unit is called block (block) mapping; the mapping of the logical physical programming unit to the physical physical programming unit is called physical programming unit (page) mapping. Hereinafter, the logical to physical mapping table can be understood as a logical to physical mapping table. When receiving an access instruction from the host system 11, the memory control circuit 204 can access data to the physical unit according to the corresponding logical to physical mapping table.

[0057] Figure 4 FIG is a schematic diagram of a management memory module according to an embodiment of the present invention. Figure 4 As shown, in one embodiment, the memory control circuit 204 logically groups the physical units 301 ( 0 )- 301 (A) into a data area 506 , a spare area 504 , a system area 502 , and a replacement area 508 .

[0058] It should be understood that in this embodiment, when describing the operations of the physical units of the memory module 122, the terms "extract," "group," "partition," and "associate" are used to refer to the physical units. In other words, the actual locations of the physical units of the memory module 122 do not change; rather, the operations are performed logically on the physical units of the memory module 122.

[0059] The physical units logically belonging to the data area 506 and the idle area 504 are used to store data from the host system 11. Specifically, the physical units in the data area 506 are considered to have stored data, while the physical units in the idle area 504 are used to replace the physical units in the data area 506. That is, when a write command and data to be written are received from the host system 11, the memory control circuit 204 extracts physical units from the idle area 504 to write the data. The physical units with written data are then moved from the idle area 504 to the data area 506 and are no longer allocated to the idle area 504. When a read command and data to be read are received from the host system 11, the memory control circuit 204 reads the data from the physical units in the data area 506 according to the corresponding logical-to-physical mapping table.

[0060] Specifically, the data area 506, the idle area 504, the system area 502, and the replacement area 508 each include one or more physical cells. The physical cells in the data area 506 are considered to have stored valid data. The physical cells in the idle area 504 also store data, but this data is invalid data. Storing data (even if invalid data) in the physical cells can prevent leakage in the physical cells and effectively extend the life of the physical cells or memory module 122. When the physical cells in the idle area 504 are needed later, the data (invalid data) in them is first erased, and then new data is written to these physical cells.

[0061] The physical units logically belonging to the system area 502 are used to record system data. For example, the system data includes information about the manufacturer and model of the memory module 122, the number of physical units in the memory module 122, and the number of physical programmable units in each physical unit. Specifically, the system area 502 is used to store a logical-to-physical mapping table, a read count table, a physical unit erase count table, and a physical unit bad block table.

[0062] The physical cells logically belonging to the replacement area 508 are used for the bad physical cell replacement process to replace the damaged physical cells. Specifically, if there are still healthy physical cells in the replacement area 508 and the physical cells in the data area 506, the spare area 504, or the system area 502 are damaged, the memory control circuit 204 will extract healthy physical cells from the replacement area 508 to replace the damaged physical cells in the data area 506, the spare area 504, or the system area 502.

[0063] Furthermore, the number of physical cells in the data area 506, the spare area 504, the system area 502, and the replacement area 508 may vary depending on the memory specifications. Furthermore, it should be understood that the grouping of physical cells associated with the data area 506, the spare area 504, the system area 502, and the replacement area 508 may change dynamically during operation of the memory storage device 12. For example, if a physical cell in the spare area 504 is damaged and replaced by a physical cell in the replacement area 508, the physical cell originally in the replacement area 508 will be associated with the spare area 504.

[0064] Furthermore, the physical cells in the data area 506 are considered to have stored data, while the physical cells in the idle area 504 are physical cells to be used for storing new data. When new data is written to a physical cell, it is assigned to the data area 506 and becomes a physical cell in the data area 506. In other words, when a write instruction and data to be written are received from the host system 11, the memory control circuit 204 extracts a physical cell from the idle area 504 according to the corresponding logical-to-physical mapping table to write the data, and updates the region relationship of the physical cell, that is, the physical cell originally belonging to the idle area 504 storing the new data becomes a physical cell in the data area 506. When a read instruction and data to be read are received from the host system 11, the memory control circuit 204 reads the data from the physical cell in the data area 506 according to the corresponding logical-to-physical mapping table.

[0065] Physical cells have a read count threshold. As the memory storage device 10 is used, the read count of some physical cells may reach their read disturb threshold, necessitating a data migration operation to move the data in these physical cells to new physical cells. This ensures the stability of the data stored in the memory module 122.

[0066] Based on this, in one embodiment, the memory control circuit 204 determines whether the number of reads of the physical cells in the memory module 122 is greater than a read disturb threshold value (K). The memory control circuit 204 obtains the number of reads of the multiple physical cells in the memory module 122 and records or marks the physical cells whose read counts exceed the read disturb threshold value as target physical cells.

[0067] In detail, the memory control circuit 204 establishes and maintains a physical unit read count table, such as Figure 5 shown. Figure 5 FIG. 1 is a schematic diagram showing the number of physical unit reads according to an embodiment of the present invention. Figure 5 In the figure, H is used to represent the number of reads of entity unit 301(C)--301(D), 301(C) represents the entity unit with serial number C. Hc represents the number of reads of entity unit with serial number c. After the memory control circuit 204 executes the read instruction for a certain entity unit, Figure 5 The number of times the entity unit of this serial number is read is increased by 1 to achieve Figure 5 maintenance.

[0068] Furthermore, the entity units in the reading count table are sorted according to the number of readings, wherein the entity units with greater reading times have higher rankings. Figure 5 This will make it easier to select the target entity unit based on the number of reads. Figure 5 The target entity unit is selected by using the header of the read count table in the READ_NUMBER_TABLE table. In this way, the operation speed of selecting the target entity unit is increased.

[0069] In another embodiment, in detail, the memory control circuit 204 will Figure 5 All physical units in the memory form a queue. If a physical unit is read, the memory control circuit 204 not only adds 1 to the read count of the physical unit, but also places the physical unit at the front of the queue. Similarly, the physical unit at the front of the queue is the most recently read physical unit. This facilitates subsequent selection of target physical units based on the number of reads, allowing the target physical unit to be selected from the front of the queue, thereby improving the speed and accuracy of selecting the target physical unit.

[0070] Furthermore, in one embodiment, a table of erase counts and read disturbance thresholds is maintained. Figure 6 . Figure 6 The relationship between the number of erase cycles and the read disturb threshold may vary for different memory cells. For single-level cell (SLC) NAND flash memory modules, the read disturb threshold decreases as the number of erase cycles increases. On the other hand, for multi-level cell (MLC) NAND flash memory modules, the read disturb threshold first increases and then decreases with the number of erase cycles.

[0071] In one embodiment, a physical unit erase count table (P / E table) is also established to record the usage status of the physical units in the memory module 122. The P / E table records the erase counts of all physical units in the memory module 122, such as Figure 7 shown. Figure 7 In the table 301(M), M represents the serial number of the physical unit 301, and N represents the erasure count of the serial number physical unit 301(M). The physical unit erasure count table can be stored in the system area.

[0072] In one embodiment, the memory control circuit 204 sorts the multiple physical units according to the number of erasures of the physical units. The memory control circuit 204 arranges the sorted multiple physical units at the head of the erase count table according to the physical unit number with the smallest erase count, so as to facilitate subsequent Figure 7 In the process, the physical unit is selected according to the number of erasures, which can improve the selection speed of the physical unit.

[0073] Furthermore, in one embodiment, the memory control circuit 204 divides the plurality of physical cells in the data area 506 into groups based on the number of erase times of the physical cells, thereby obtaining a plurality of first groups. Each first group corresponds to a different erase time value range; each first group may include one or more physical cells, and each physical cell can only belong to one first group based on the number of erase times in a certain time period; and each first group has a different erase time value range.

[0074] from Figure 6 As can be seen, the read disturbance threshold (K) corresponding to different physical units has different erase counts. The physical units in the memory module 122 are managed in groups, and each first group has its own corresponding read disturbance threshold K. This can improve the precision of physical unit management. For some physical units with a small erase count, the read disturbance threshold can be set larger to reduce the number of data transfer operations for such physical units. For some physical units with a large erase count, the read disturbance threshold can be set smaller than the read disturbance threshold for physical units with a small erase count, to increase the number of data transfer operations for such physical units.

[0075] For example, see Figure 8 As shown, Figure 8 In order to construct a plurality of different first groups according to different erase count value intervals of physical cells, each first group has a different read disturbance threshold value. The memory module 122 includes 2000 physical cells, namely B0-B1999. Among them, the number of physical cells in the first group 51(0) with an erase count of 0-50 is 500, the number of physical cells in the first group 51(1) with an erase count of 51-150 is 600, the number of physical cells in the first group 51(2) with an erase count of 151-500 is 300, the number of physical cells in the first group 51(3) with an erase count of 501-1000 is 400, and the number of physical cells in the first group 51(4) with an erase count of 1001-5000 is 200. The memory module 122 is divided into a plurality of first groups according to the erase count interval value, and each first group has its own read disturbance threshold value K. Figure 8 In the example, the read disturbance threshold value K1 is smaller than K2, K1 is smaller than K3, K1 is smaller than K4, and K1 is larger than K5.

[0076] Furthermore, after completing the recording or selection of the target physical unit, the memory control circuit 204 needs to perform a data migration operation on the target physical unit. In one embodiment, the data migration operation is to copy the valid data (first data) in the target physical unit to the first physical unit, while the invalid data (second data) in the physical unit is not subjected to the data migration operation. After performing the data migration operation on the first data, the physical unit (i.e., the target physical unit) that originally stored the first data is marked to indicate that the data stored in one (or some) of the physical programming units in these (or some) physical units is invalid data. If the data stored in all of the physical programming units in these (or some) physical units is invalid data, then the physical unit (or some) is reclassified from the data area 506 to the idle area 504.

[0077] In one embodiment, the first physical unit is the physical unit with the smallest operation value in the memory module 122. Regarding the first physical unit being the physical unit with the smallest operation value in the memory module 122, in one embodiment, the operation value can be considered as the number of erases. In other words, the physical unit with the smallest operation value can be considered as the physical unit with the smallest number of erases.

[0078] Preferably, in one embodiment, the target physical unit is a physical unit in the data area 506 , and the physical unit with the smallest erase count is selected from the idle area 504 .

[0079] Furthermore, in another embodiment, a method for managing physical units in the idle area 504 is provided to provide first physical units that meet the needs.

[0080] Specifically, the memory control circuit 204 divides the plurality of physical units in the idle area 504 into groups according to the number of erase times of the physical units, and obtains a plurality of second groups 61(0)--61(G) [G+1 represents the number of second groups], each second group corresponding to a different erase times value interval; wherein, each second group may include one or more physical units and the number of erase times of each physical unit in a certain time period can only belong to a certain second group; the erase times value interval of each second group is different; the memory control circuit 204 selects a suitable number of physical units from the second group with the smallest erase times value interval to store the first data according to the amount of data of the first data stored in the target physical unit. Preferably, a suitable number of physical units with the smallest erase times value interval are selected from the second group with the smallest erase times value interval to store the first data. Managing the physical units in the memory module 122 in a group manner can increase the speed of selecting the first physical unit that meets the needs, thereby increasing the speed of data transfer.

[0081] For example, the idle area 504 includes 200 physical units, assuming that these 200 physical units are Block 15 to Block 214. These 200 physical units are divided into groups according to the number of erase times of the physical units, and the following is obtained: Figure 9 The four groups shown are 61(0), 61(1), 61(2) and 61(3). Figure 9 This is a schematic diagram showing an embodiment of the present invention, in which a plurality of physical units are divided into groups according to the number of erase times of the physical units to obtain a plurality of second groups, each second group corresponding to a different erase time value range.

[0082] Specifically, if Figure 9 As shown, the group number with the smallest erase count range is 61(0). The erase count range of group 61(0) is 0-200, which includes 50 physical units. The erase count details of these 50 physical units are 30 physical units with an erase count of 80 times, 10 physical units with an erase count of 120 times, and 10 physical units with an erase count of 180 times. If the number of first physical units is required to be 2, then 2 physical units are selected from the 30 physical units with an erase count of 80 times as the first physical units.

[0083] Furthermore, in another embodiment, the selection operation of the first physical unit further includes: the memory control circuit 204 selects the physical unit with the smallest erase count and the smallest error bit value from the subgroup with the smallest erase count value interval and the smallest error bit value interval as the first physical unit.

[0084] Specifically, the memory control circuit 204 further divides the second group having the smallest erase count value interval into groups based on the error bit values of the physical units, thereby obtaining a plurality of subgroups having the same erase count value interval but different error bit value value intervals; wherein each subgroup may include one or more physical units, and the error bit value of each physical unit in a certain time period can only belong to a certain subgroup; each subgroup may belong to the same erase count value interval but correspond to different error bit value value intervals; the number of physical units included in each subgroup may be the same or different; and the memory control circuit 204 selects the physical unit having the smallest erase count value interval and the smallest error bit value interval from the subgroup having the smallest erase count value interval and the smallest error bit value interval as the first physical unit.

[0085] For example, the number of error bits of a physical unit can be obtained from a bad block table (stored in the system area), such as Figure 10 shown. Figure 10In 301(F), F represents the serial number of the entity unit 301, and S represents the number of error bits of the serial number entity unit 301(F).

[0086] For example, the memory control circuit 204 obtains the number of error bits of each physical unit in the group 61(0), and further divides the group 61(0) into groups according to the number of error bits of each physical unit, thereby obtaining a plurality of subgroups having the same erase count value interval but different error bit value value intervals, such as Figure 11 shown. Figure 11 This is a schematic diagram showing an embodiment of the present invention in which the second group with the smallest erasure count value interval is further divided into groups according to the error bit value of the physical unit to obtain multiple subgroups with the same erasure count value interval but different error bit value value intervals.

[0087] Specifically, Figure 11 Among them, Block 15 and Block 17 have the smallest number of erase times and the smallest error bit value. Therefore, Block 15 and Block 17 are selected as the first physical unit.

[0088] Furthermore, in another embodiment, based on the size of the first data, the memory control circuit 204 selects an appropriate number of physical units as the first physical units. Specifically, based on the size of the first data, the memory control circuit 204 selects an appropriate number of physical units from the second group having the smallest erase count value range as the first physical units. Furthermore, based on the size of the first data, the memory control circuit 204 selects the physical units having the smallest erase count value range and the smallest error bit value range as the first physical units from the subgroup having the smallest erase count value range and the smallest error bit value range.

[0089] It should be understood that the above description of the operation of the physical units of the memory module in this embodiment using terms such as "grouping" to operate the physical units is a logical concept. In other words, the actual positions of the physical units in the memory module 122 do not change; rather, the operations are performed on the physical units in the memory module 122 logically.

[0090] In one embodiment, the sorting algorithm may be any one of insertion sort, shell sort, selection sort, bubble sort, quick sort, merge sort, counting sort, and bucket sort.

[0091] In one embodiment, the logical-to-physical mapping relationship of the first data is updated based on the physical address of the first physical unit. Since the data move operation is performed on the target physical unit, the physical address of the first data is changed from the physical address of the original target physical unit to the physical address of the first physical unit. That is, the physical address storing the first data has changed. For example, the first logical address is mapped to the first physical address, and the first physical address is the physical address originally storing the first data. Now the physical address storing the first data is the second physical address. Then the memory control circuit 204 will remove the mapping relationship between the first logical address and the first physical address, and the memory control circuit 204 will re-establish the mapping relationship between the first logical address and the second physical address. The second physical address is the new physical address of the first data. It is also the physical address of the first physical unit.

[0092] In one embodiment, the memory control circuit 204 selects the first physical unit, and the step of copying the first data in the target physical unit to the first physical unit further includes:

[0093] The memory control circuit 204 first performs an erase operation on the first physical unit to erase the data (invalid data) in the first physical unit, and then writes the first data into the first physical unit.

[0094] Further, in another embodiment, see Figure 12 The memory controller 123 further includes a value comparison circuit 214, which is electrically connected to the memory control circuit 204 and receives monitoring and control from the memory control circuit 204. The memory control circuit 204 obtains the read counts of multiple physical units in the memory module 122 and sends the read counts to the value comparison circuit 214. The value comparison circuit 214 records or marks the physical units whose read counts exceed the read disturbance threshold as risky physical units.

[0095] Specifically, the memory control circuit 204 maintains multiple first groups based on the number of erases of the physical cells. Each first group has a different read disturb threshold value K, such as K1, K2, etc. Specifically, the different read disturb threshold values K for each first group are pre-set in a register of the value comparison circuit 214. The memory control circuit 204 captures the physical cell read count value from the physical cell read count table and stores it in the value comparison circuit 214. The value comparison circuit 214 then receives the physical cell read count value from the memory control circuit 204, compares it with the pre-set read disturb threshold value K for each first group, and outputs the value comparison result. Physical cells with a read count greater than the read disturb threshold value K are recorded as target physical cells. Using the value comparison circuit 214 to retrieve the target physical cell is advantageous over using only the memory control circuit 204 in that the former allows for faster target cell retrieval, thereby increasing the data transfer speed of the memory storage device.

[0096] Figure 13 FIG. 4 is a flowchart of a memory management method according to an embodiment of the present invention.

[0097] Please refer to Figure 13 In step S100, the plurality of physical cells are grouped according to the number of erase times of the physical cells to obtain a plurality of first groups, each of which corresponds to a read disturbance threshold value. In step S200, the physical cells in each of the first groups whose number of reads exceeds the read disturbance threshold value are recorded as target physical cells. In step S300, the first data in the target physical cell is copied to the first physical cell, which is the physical cell with the smallest operation value in the memory module. In step S400, the logical-to-physical mapping relationship of the first data is updated according to the physical address of the first physical cell.

[0098] However, Figure 13 The steps have been described in detail above and will not be repeated here. Figure 13 Each step can be implemented as multiple codes or circuits, and the present invention is not limited thereto. Figure 13 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0099] In summary, the present invention provides a memory management method, a memory controller, and a memory storage device. The method groups multiple physical cells according to the number of erase times of the physical cells to obtain multiple first groups, each of which corresponds to a read disturb threshold value. Physical cells in each first group whose read times exceed the read disturb threshold value are recorded as target physical cells. After the target physical cells are selected, a data migration operation is performed on the first data. A method is also provided for selecting a first physical cell from the idle area 504 of the memory module 122 to store the first data. Specifically, the first physical cell is the physical cell with the smallest operation value in the memory module 122. Furthermore, the physical cell with the smallest operation value can be understood as the physical cell with the smallest erase times. Since the smaller the number of erase times of a physical cell, the larger its read disturb threshold value, the number of times the first data is repeatedly subjected to the data migration operation can be reduced. This reduces the number of erase times of the physical cells storing the first data, thereby increasing the lifespan of the memory storage device.

[0100] Furthermore, the physical unit with the smallest operation value can be understood as selecting the physical unit with the smallest number of erases and the smallest error bit value from the subgroup with the smallest range of erase count values and the smallest range of error bit values. Moving (copying) the first data to the physical unit with the smaller error bit value improves the security and stability of data storage in the memory storage device and increases the speed at which the first data can be read, thereby improving the system performance of the memory storage device.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, applied to a memory storage device, characterized in that: The memory storage device includes a memory module, the memory module includes a plurality of physical units, and the method includes: Dividing multiple physical units in the memory module into a data area and an idle area, and dividing the multiple physical units in the data area and the idle area into groups according to the number of erase times of the physical units to obtain multiple first groups and second groups, each of the first groups corresponds to a read disturbance threshold value, and each of the second groups corresponds to a different erase number value range; Recording each physical unit in the first group whose read times exceeds the read disturbance threshold as a target physical unit; copying the first data in the target physical unit to the first physical unit, selecting the first physical unit from the idle area, performing an erase operation on the first physical unit, and selecting a suitable number of physical units with the smallest erase counts from the second group with the smallest erase count value interval as the first physical unit based on the size of the first data in the target physical unit, the first physical unit being the physical unit with the smallest operation value in the memory module; The logical-to-physical mapping relationship of the first data is updated according to the physical address of the first physical unit.

2. The memory management method according to claim 1, wherein: The step of recording each physical unit in the first group whose read times exceeds the read disturbance threshold as a target physical unit includes: Create a table of reading times; The reading number table is used to record the reading number of the plurality of entity units, and the entity units in the reading number table are sorted according to the reading number, wherein the greater the reading number, the higher the ranking of the entity unit; The physical unit whose read count exceeds the read disturbance threshold in the read count table is recorded as a target physical unit.

3. The memory management method according to claim 1, wherein: Also includes: The physical units in the data area are considered to have stored valid data, and the physical units in the idle area are considered to have stored invalid data.

4. The memory management method according to claim 1, wherein: Also includes: The first data in the target physical unit is marked as invalid data or the target physical unit is divided into an idle area.

5. A memory controller for controlling a memory module, wherein the memory module comprises a plurality of physical units; The memory controller includes: a host interface for connecting to a host system; a memory interface for connecting to the memory module; a memory control circuit connected to the host interface and the memory interface; and a value comparison circuit connected to the memory control circuit; characterized in that, The memory control circuit divides multiple physical cells in the memory module into a data area and an idle area, and divides the multiple physical cells in the data area and the idle area into groups according to the number of erase times of the physical cells to obtain multiple first groups and second groups, each of the first groups corresponds to a read disturbance threshold value, and each of the second groups corresponds to a different erase number value range; The value comparison circuit records each physical unit in the first group whose read times exceeds the read disturbance threshold as a target physical unit; The memory control circuit copies the first data in the target physical unit to the first physical unit, selects the first physical unit from the idle area, performs an erase operation on the first physical unit, and selects an appropriate number of physical units with the smallest erase count from the second group with the smallest erase count value interval as the first physical unit based on the size of the first data in the target physical unit, wherein the first physical unit is the physical unit with the smallest operation value in the memory module; The memory control circuit updates the logic-to-physical mapping relationship of the first data according to the physical address of the first physical unit.

6. The memory controller according to claim 5, wherein: The operation of the value comparison circuit for recording each physical unit in the first group with a read count exceeding the read disturbance threshold as a target physical unit further includes: Create a table of reading times; The reading number table is used to record the reading number of the plurality of entity units, and the entity units in the reading number table are sorted according to the reading number, wherein the greater the reading number, the higher the ranking of the entity unit; The memory control circuit obtains a read count in the read counts and sends the read count to the value comparison circuit. The value comparison circuit records the physical unit whose read count exceeds a read disturbance threshold as a target physical unit.

7. The memory controller according to claim 5, wherein: The operation of the memory control circuit further includes: The physical units in the data area are regarded as physical units storing valid data, and the physical units in the idle area are regarded as physical units storing invalid data; The memory control circuit divides the plurality of physical cells in the data area into groups according to the number of times the physical cells are erased, to obtain a plurality of first groups.

8. The memory controller according to claim 5, wherein: The operation of the memory control circuit further includes: The memory control circuit marks the first data in the target physical unit as invalid data or divides the target physical unit into an idle area.

9. A memory storage device, comprising a connection interface, a memory module, and a memory controller; the connection interface is used to connect the memory storage device to a host system; the memory module comprises a plurality of physical units; the memory controller is connected to the connection interface and the memory module; characterized in that The memory controller divides multiple physical units in the memory module into a data area and an idle area, and divides the multiple physical units in the data area and the idle area into groups according to the number of erase times of the physical units to obtain multiple first groups and second groups, each of the first groups corresponds to a read disturbance threshold value, and each of the second groups corresponds to a different erase number value range; The memory controller records each physical cell in the first group whose read times exceeds the read disturbance threshold as a target physical cell; The memory controller copies the first data in the target physical unit to the first physical unit, selects the first physical unit from the idle area, performs an erase operation on the first physical unit, and selects an appropriate number of physical units with the smallest erase counts from the second group with the smallest erase count value interval as the first physical unit based on the size of the first data in the target physical unit, wherein the first physical unit is the physical unit with the smallest operation value in the memory module; The memory controller updates a logical-to-physical mapping relationship of the first data according to a physical address of the first physical unit.

10. The memory storage device according to claim 9, wherein: The operation of the memory controller recording each physical cell in the first group with a read count exceeding the read disturbance threshold as a target physical cell further includes: Create a table of reading times; The reading number table is used to record the reading number of the plurality of entity units, and the entity units in the reading number table are sorted according to the reading number, wherein the greater the reading number, the higher the ranking of the entity unit; The memory controller obtains a read count in the read counts and sends the read count to a value comparison circuit. The value comparison circuit records a physical unit whose read count exceeds a read disturbance threshold as a target physical unit.

11. The memory storage device according to claim 9, wherein: The operations of the memory controller further include: The physical units in the data area are considered to have stored valid data, and the physical units in the idle area are considered to have stored invalid data.

12. The memory storage device according to claim 9, wherein: The operations of the memory controller further include: The memory controller marks the first data in the target physical unit as invalid data or divides the target physical unit into an idle area.

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