Vector instruction identification method and apparatus, electronic device, and computer readable storage medium

Abstract

Embodiments of the present disclosure disclose a vector instruction identification method and device, electronic equipment and a computer readable storage medium. The vector instruction identification method comprises: obtaining a scalar instruction; mapping the scalar instruction to a vector instruction according to a vector instruction dimension mapping rule and an instruction configuration table; and determining the validity of the vector instruction according to a vector instruction dimension validity rule, wherein the vector instruction dimension validity rule comprises a rule for verifying the validity of the instruction mapping result; and if the vector instruction is valid, the vector instruction identification is successful. The above method identifies the vector instruction through the vector instruction dimension mapping rule, the instruction configuration table and the vector instruction dimension validity rule, and solves the technical problems in the prior art that the conversion of the scalar instruction to the vector instruction is complex, not highly versatile and unable to distinguish the vector instruction.

Description

Technical Field

[0001] This disclosure relates to the fields of program compilation and processors, and more particularly to a method, apparatus, electronic device, and computer-readable storage medium for identifying vector instructions. Background Technology

[0002] Dedicated or vector processors, such as GPUs (Graphics Processing Units) and NPUs (neural-network processing units), have become one of the main ways to improve the performance of modern computers. With dedicated or vector processors, scalar software code needs to be converted into vectorized code or instructions. There are generally two ways to achieve this conversion: First, the compiler automatically vectorizes the scalar program, automatically generating vector instructions. For example, GCC (GNU Compiler Collection) or LLVM (Low Level Virtual Machine) automatically vectorizes some simple loops. The automatic vectorization of general-purpose compilers can only vectorize simple vector instructions such as addition and subtraction, and simple scenarios. Second, an explicit programming model is used, mainly through the compiler's intrinsics functions or inline assembly. This method requires a higher level of skill from the programmer, who needs to be familiar with vectorized programming interfaces, and has poor code portability.

[0003] In the field of deep learning, dedicated or vector processors provide different forms of vector instructions based on the input and output parameter types. Currently, in implementing vector instructions to accelerate code efficiency, the compiler toolchain first optimizes the custom scalar form of the IR (Intermediate Representation). After optimization, the scalar form IR is converted into vector instructions and executed on the dedicated or vector processor. When converting the scalar form IR to vector instructions, the most efficient and convertible vector instruction must be selected from different forms. An essential step in achieving this conversion is vector instruction identification—identifying the vector instructions that can be successfully converted from the scalar form IR.

[0004] Existing solutions for converting custom scalar form IRs into vector instructions:

[0005] Option 1: Based on the constraints of each dimension of the input and output parameters of a specific vector instruction, perform logical checks on the loop variable to be vectorized. If the dimensional requirements of the instruction parameters are met, the mapping succeeds; otherwise, it fails. The drawback of Option 1 is its complexity, relying on logical checks. It requires writing logical branch statements for analysis based on the constraints of each dimension of the input and output parameters for each vector instruction, resulting in low versatility.

[0006] Option 2: Establish a Tree-Pattern-style IR description based on the scalar form of the IR, and confirm the vectorizable scalar form of the IR through Tree-Pattern similarity matching. Currently, this option only supports vector commands: vector addition, vector subtraction, etc. However, when the input and output parameters of the vector addition command are of different types, the vector addition command does not support differentiation between different forms of vector addition commands. Summary of the Invention

[0007] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0008] To address the aforementioned technical problems in the prior art, the present disclosure proposes the following technical solutions:

[0009] In a first aspect, embodiments of this disclosure provide a method for recognizing vector instructions, including:

[0010] Obtain scalar instruction;

[0011] The scalar instructions are mapped to vector instructions according to the vector instruction dimension mapping rules and the instruction configuration table; wherein, the vector instruction dimension mapping rules include rules for mapping scalar instructions to vector instructions; and the instruction configuration table includes a set of vector instructions.

[0012] The validity of the vector instruction is determined according to the vector instruction dimension validity rules; wherein, the vector instruction dimension validity rules include rules for verifying the validity of the instruction mapping results;

[0013] If the vector instruction is valid, then the vector instruction is successfully recognized.

[0014] Furthermore, the vector instruction dimension mapping rule includes:

[0015] The data type of the parameters in a vector command;

[0016] The rule for mapping loop iteration variables in scalar instructions to parameters in vector instructions.

[0017] Furthermore, when the data type of the parameter is 1*1 type data, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter does not map to the loop iteration variable.

[0018] When the data type of the parameter is 1*n, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter maps to the loop iteration variable with a step size of 1.

[0019] When the data type of the parameter is m*1, the mapping rule is that the row dimension of the parameter maps to the loop iteration variable with a step size of not 1, and the column dimension of the parameter does not map to the loop iteration variable.

[0020] When the data type of the parameter is m*n type, the mapping rule is that the row dimension mapping step of the parameter is not 1 and the column dimension mapping step of the parameter is 1.

[0021] Furthermore, the vector instruction dimension validity rules include:

[0022] When the data type of the parameter is 1*1, there are no constraints on the mapping of the loop iteration variable in the row and column dimensions;

[0023] When the data type of the parameter is 1*n, the parameter has no constraint on mapping the loop iteration variable in the row dimension, and the parameter has a mapping loop iteration variable in the column dimension;

[0024] When the data type of the parameter is m*1, the parameter has a mapping loop iteration variable in the row dimension, and the parameter has no constraint on the mapping loop iteration variable in the column dimension;

[0025] When the data type of the parameter is m*n type, the parameter has no constraint on mapping the loop iteration variable in the row dimension, and the parameter has a mapping loop iteration variable in the column dimension;

[0026] When the vector instruction is an instruction to eliminate loop iteration variables, the parameter has a mapping loop iteration variable in the row dimension or the parameter has a mapping loop iteration variable in the column dimension.

[0027] Furthermore, the instruction configuration table includes:

[0028] The data types of all vector instructions to be identified and the parameters in each vector instruction.

[0029] Furthermore, the data type of the parameters in the vector instruction is constrained by the step size of the data type; wherein,

[0030] When the data type is 1*1, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 0.

[0031] When the data type is 1*n, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 1.

[0032] When the data type is m*1, its step size constraint is that the step size in the row dimension is 1 and the step size in the column dimension is 0.

[0033] When the data type is m*n, its step size constraint is that the step size in the row dimension is max and the step size in the column dimension is 1; where max represents the maximum value that the register can represent.

[0034] Furthermore, the step of mapping the scalar instruction to a vector instruction according to the vector instruction dimension mapping rule and the instruction configuration table includes:

[0035] Retrieve vector instructions from the instruction configuration table;

[0036] Determine the data type of the parameters of the vector instruction;

[0037] Retrieve the loop iteration variable from the scalar instruction;

[0038] The loop iteration variable is mapped to the parameter of the vector instruction according to the data type of the parameter of the vector instruction.

[0039] Furthermore, mapping the loop iteration variable to the parameters of the vector instruction based on the data type of the parameters of the vector instruction includes:

[0040] A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0041] The vector instruction dimension mapping rule corresponding to the data type of the parameter of the vector instruction is obtained.

[0042] The loop iteration variable used to select the parameters of the vector instruction from the set of loop iteration variables;

[0043] The selected loop iteration variables are mapped to the row and column dimensions of the parameters according to the vector instruction dimension mapping rules to obtain the set of loop iteration variables of the vector instruction parameters.

[0044] Furthermore, when the vector instruction is a non-elimination instruction for loop iteration variables, mapping the loop iteration variables to parameters of the vector instruction according to the vector instruction dimension mapping rule includes:

[0045] A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0046] Based on the data type of the output parameter of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the output parameter;

[0047] Select the loop iteration variable used for the output parameter from the set of loop iteration variables;

[0048] The loop iteration variables used by the selected output parameters are mapped to the row dimension and column dimension of the output parameters according to the vector instruction dimension mapping rule of the output parameters to obtain the set of loop iteration variables of the output parameters of the vector instruction;

[0049] Based on the data type of the input parameters of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the input parameters;

[0050] Select the loop iteration variable used for the input parameter from the set of loop iteration variables of the output parameter;

[0051] The loop iteration variables used by the selected input parameters are mapped to the row and column dimensions of the input parameters according to the vector instruction dimension mapping rules of the input parameters, respectively, to obtain the set of loop iteration variables of the input parameters of the vector instruction.

[0052] Furthermore, when the vector instruction is an instruction to eliminate loop iteration variables, mapping the loop iteration variables to the parameters of the vector instruction according to the data type of the parameters of the vector instruction includes:

[0053] A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0054] Based on the data type of the input parameters of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the input parameters;

[0055] Select the loop iteration variable used for the input parameter from the set of loop iteration variables;

[0056] The loop iteration variables used by the selected input parameters are mapped to the row dimension and column dimension of the input parameters according to the vector instruction dimension mapping rule of the input parameters to obtain the set of loop iteration variables of the input parameters of the vector instruction.

[0057] The set of iterative variables for all input parameters is merged to obtain the joint set of iterative variables for the input parameters;

[0058] Based on the data type of the output parameter of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the output parameter;

[0059] Select the loop iteration variable used by the output parameter from the joint set of loop iteration variables of the input parameters;

[0060] The loop iteration variables used by the selected output parameters are mapped to the row and column dimensions of the output parameters according to the vector instruction dimension mapping rules of the output parameters to obtain the set of loop iteration variables of the output parameters of the vector instruction.

[0061] Furthermore, determining the validity of the vector instruction based on the vector instruction dimension validity rule includes:

[0062] The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables of the parameters; or,

[0063] The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables of the output parameters and the dimension and step size of the loop iteration variables in the set of loop iteration variables of the input parameters.

[0064] Secondly, embodiments of this disclosure provide a vector instruction recognition device, comprising:

[0065] The instruction acquisition module is used to acquire scalar instructions;

[0066] A mapping module is used to map scalar instructions to vector instructions according to vector instruction dimension mapping rules and an instruction configuration table; wherein, the vector instruction dimension mapping rules include rules for mapping scalar instructions to vector instructions; and the instruction configuration table includes a set of vector instructions.

[0067] The identification and verification module is used to determine the validity of the vector instruction according to the vector instruction dimension validity rules; wherein, the vector instruction dimension validity rules include rules for verifying the validity of the instruction mapping result; if the vector instruction is valid, the vector instruction is successfully identified.

[0068] Thirdly, embodiments of this disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the methods described in the first aspect above.

[0069] Fourthly, embodiments of this disclosure provide a computer-readable storage medium that stores computer instructions for causing a computer to perform any of the methods described in the first aspect above.

[0070] Fifthly, embodiments of this disclosure provide a computer program product including computer instructions, which, when executed by a computing device, enable the computing device to perform any of the methods described in the first aspect above.

[0071] This disclosure provides a method, apparatus, electronic device, and computer-readable storage medium for identifying vector instructions. The method includes: acquiring a scalar instruction; mapping the scalar instruction to a vector instruction according to a vector instruction dimension mapping rule and an instruction configuration table; wherein the vector instruction dimension mapping rule includes rules for mapping scalar instructions to vector instructions; the instruction configuration table includes a set of vector instructions; determining the validity of the vector instruction according to a vector instruction dimension validity rule; wherein the vector instruction dimension validity rule includes rules for verifying the validity of the instruction mapping result; if the vector instruction is valid, the vector instruction is successfully identified. This method identifies vector instructions through vector instruction dimension mapping rules, an instruction configuration table, and vector instruction dimension validity rules, solving the technical problems in the prior art where converting scalar instructions to vector instructions is complex, lacks versatility, and cannot distinguish between vector instructions.

[0072] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0073] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0074] Figure 1 Example diagram of code in scalar form;

[0075] Figures 2a-2dA schematic diagram illustrating the data type of parameters in a vector instruction provided in this embodiment of the disclosure;

[0076] Figure 3 A flowchart illustrating the vector instruction recognition method provided in this embodiment of the disclosure;

[0077] Figures 4a-4r A diagram illustrating the types of input and output parameters in various vector commands;

[0078] Figure 5 A further flowchart illustrating the vector instruction recognition method provided in this embodiment of the disclosure;

[0079] Figure 6a This is an example schematic diagram of the scalar code block used in the embodiments of this disclosure;

[0080] Figure 6b This is a schematic diagram of an example instruction configuration table used in the embodiments of this disclosure;

[0081] Figure 7 A further flowchart illustrating the vector instruction recognition method provided in this embodiment of the disclosure;

[0082] Figure 8 This is an example schematic diagram of a scalar code block used in another embodiment of this disclosure;

[0083] Figure 9 A further flowchart illustrating the vector instruction recognition method provided in this embodiment of the disclosure;

[0084] Figure 10a This is an example schematic diagram of a scalar code block used in another embodiment of this disclosure;

[0085] Figure 10b This is an example schematic diagram of an instruction configuration table used in another embodiment of this disclosure. Detailed Implementation

[0086] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0087] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0088] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0089] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0090] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0091] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0092] Figure 1 This is an example of code in this disclosure that needs to be converted into scalar form of vector instructions. For example... Figure 1 As shown, the scalar form of the for loop statement block needs to be converted into the corresponding vector instruction. The loop iteration variables i and j in the for loop need to be mapped to the dimensions corresponding to the input parameters A and B and the output parameter C in the vector instruction, so as to vectorize the loop iteration variables.

[0093] Figures 2a-2d This diagram illustrates the data types of parameters in vector instructions provided in this embodiment. Vector instructions support the following four data types for input and output parameters: such as... Figure 2a The parameter type shown is scalar / vector, which can be understood as a matrix with a shape and size of [1,1]([row,col]); for example Figure 2b The parameter type shown is vector type, which can be understood as a matrix with a shape and size of [1, n] ([row, col]); for example Figure 2c The parameter type shown is vector type, which can be understood as a matrix with a shape and size of [m,1]([row,col]); for example Figure 2d The parameter type shown is a vector type, which can be understood as a matrix with shape and size of [m,n]([row,col]); where row represents the row dimension, col represents the column dimension, m>1, n>1.

[0094] Figure 3 A flowchart illustrating the vector instruction recognition method provided in this embodiment of the disclosure.

[0095] The vector instruction recognition method is used to identify vector instructions that can be mapped from scalar instructions. The vector instruction recognition method can be executed by a vector instruction recognition device, which can be implemented as software or hardware, or as a combination of software and hardware. The vector instruction recognition device can be integrated into a device in the vector instruction recognition system, such as a vector instruction recognition terminal device.

[0096] like Figure 3 As shown, the method includes the following steps:

[0097] Step S301: Obtain scalar instructions;

[0098] The scalar instruction includes a block of statements in scalar form, and the scalar instruction includes loop iteration variables, such as... Figure 1 The for loop statement block shown uses loop iteration variables i and j.

[0099] return Figure 3 The method for recognizing the vector command further includes:

[0100] Step S302: Map the scalar instruction to a vector instruction according to the vector instruction dimension mapping rule and the instruction configuration table; wherein, the vector instruction dimension mapping rule includes rules for mapping scalar instructions to vector instructions; the instruction configuration table includes a set of vector instructions.

[0101] The vector instruction dimension mapping rules include: the data type of the parameters in the vector instruction; and the rules for mapping loop iteration variables in scalar instructions to the parameters in the vector instruction.

[0102] Specifically, the vector instruction dimension mapping rules include the data type of the parameters in the vector instruction, and the rules for mapping scalar loop variables to the row and / or column dimensions of the parameters of the vector instruction corresponding to the data type of different parameters.

[0103] Optionally, the vector instruction dimension mapping rule includes:

[0104] When the data type of the parameter is 1*1 type, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter does not map to the loop iteration variable.

[0105] When the data type of the parameter is 1*n, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter maps to the loop iteration variable with a step size of 1.

[0106] When the data type of the parameter is m*1, the mapping rule is that the row dimension of the parameter maps to the loop iteration variable with a step size of not 1, and the column dimension of the parameter does not map to the loop iteration variable.

[0107] When the data type of the parameter is m*n type, the mapping rule is that the row dimension mapping step of the parameter is not 1 and the column dimension mapping step of the parameter is 1.

[0108] That is, when the type of the parameter of the vector instruction is Figure 2a When dealing with data of type [1,1] as shown, neither the row dimension nor the column dimension of the parameter maps to the scalar's loop iteration variable.

[0109] When the type of the parameter of the vector instruction is Figure 2b When dealing with data of type [1, n] as shown, the row dimension of the parameter does not map to the scalar loop iteration variable, while the column dimension of the parameter maps to a scalar loop iteration variable with a step size of 1. For example... Figure 1 In the scalar instructions shown, i is in the inner loop, and it needs to be incremented by 1 in each iteration, so the step size of i is 1; j is in the outer loop, and the value of j is incremented by 1 only after i iterates 30 times, so the step size of j is 30.

[0110] When the type of the parameter of the vector instruction is Figure 2c When dealing with data of type [m,1], the row dimension of the parameter maps to a loop iteration variable with a step size of not 1, and the column dimension of the parameter does not map to a loop iteration variable.

[0111] When the type of the parameter of the vector instruction is Figure 2d When the data is of type [m,n], the parameter is a loop iteration variable with a row dimension mapping step size of not 1 and a column dimension mapping step size of 1.

[0112] The instruction configuration table includes: all vector instructions to be identified and the data type of the parameters in each vector instruction.

[0113] Wherein, the data type of the parameters in the vector instruction is constrained by the step size of the data type; wherein,

[0114] When the data type is 1*1, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 0.

[0115] When the data type is 1*n, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 1.

[0116] When the data type is m*1, its step size constraint is that the step size in the row dimension is 1 and the step size in the column dimension is 0.

[0117] When the data type is m*n, its step size constraint is that the step size in the row dimension is max and the step size in the column dimension is 1; where max represents the maximum value that the register can represent.

[0118] The data type of the parameters in the vector instruction can be represented by the step size of the row and column dimensions mentioned above. For example... Figure 2a The data type shown, with a step size of 0 in both the row and column dimensions, can be represented as: RowTable:{0}, ColTable:{0}; for example... Figure 2b The data type shown, with a step size of 0 in the row dimension and a step size of 1 in the column dimension, can be represented as: RowTable:{0}, ColTable:{1}; For example... Figure 2c The data type shown, with a step size of 1 in the row dimension and a step size of 0 in the column dimension, can be represented as: RowTable:{1}, ColTable:{0}; For example... Figure 2d The data type shown has a step size of max in the row dimension and a step size of 1 in the column dimension, which can be represented as: RowTable:{max}, ColTable:{1}.

[0119] like Figures 4a-4r This refers to the types of input and output parameters in various vector instructions.

[0120] Figure 4a The instructions shown are configured as follows in their instruction configuration table:

[0121] RowTable:{max,max} / / dst,src

[0122] ColTable:{1,1} / / dst,src

[0123] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter src is of type [RowTable[1], ColTable[1]], which is [max, 1].

[0124] Figure 4b The instructions shown are configured as follows in their instruction configuration table:

[0125] RowTable:{max,1} / / dst,src

[0126] ColTable:{1,0} / / dst,src

[0127] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter is of type [RowTable[1], ColTable[1]], which is [1, 0].

[0128] Figure 4c The instructions shown are configured as follows in their instruction configuration table:

[0129] RowTable:{max,0} / / dst,src

[0130] ColTable:{1,1} / / dst,src

[0131] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter is of type [RowTable[1], ColTable[1]], which is [0, 1].

[0132] Figure 4d The command input shown is configured as follows in the command configuration table:

[0133] RowTable:{max,0} / / dst,src

[0134] ColTable:{1,0} / / dst,src

[0135] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter is of type [RowTable[1], ColTable[1]], which is [1, 0].

[0136] Figure 4e The reduce operation command shown is configured as follows in the command configuration table:

[0137] RowTable:{1,max} / / dst,src

[0138] ColTable:{0,1} / / dst,src

[0139] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [1, 0]. The input parameter is of type [RowTable[1], ColTable[1]], which is [max, 1].

[0140] Figure 4f The reduce operation command shown is configured as follows in the command configuration table:

[0141] RowTable:{0,max} / / dst,src

[0142] ColTable:{1,1} / / dst,src

[0143] The output parameter dst is of type [RowTable[0], ColTable[0], which is [0, 1]. The input parameter is of type [RowTable[1], ColTable[1]], which is [max, 1].

[0144] Figure 4g The reduce operation command shown is configured as follows in the command configuration table:

[0145] RowTable:{0,max} / / dst,src

[0146] ColTable:{0,1} / / dst,src

[0147] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [0,0]. The input parameter is of type [RowTable[1], ColTable[1]], which is [max,1].

[0148] Figure 4h The command input shown is configured as follows in the command configuration table:

[0149] RowTable:{max,max,max} / / dst,src1,src2

[0150] ColTable:{1,1,1} / / dst,src1,src2

[0151] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [max, 1].

[0152] Figure 4i The command input shown is configured as follows in the command configuration table:

[0153] RowTable:{max,max,1} / / dst,src1,src2

[0154] ColTable:{1,1,0} / / dst,src1,src2

[0155] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [1, 0].

[0156] Figure 4j The command input shown is configured as follows in the command configuration table:

[0157] RowTable:{max,max,0} / / dst,src1,src2

[0158] ColTable:{1,1,1} / / dst,src1,src2

[0159] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [0, 1].

[0160] Figure 4k The command input shown is configured as follows in the command configuration table:

[0161] RowTable:{max,max,0} / / dst,src1,src2

[0162] ColTable:{1,1,0} / / dst,src1,src2

[0163] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [0, 0].

[0164] Figure 4l The reduce operation command shown is configured as follows in the command configuration table:

[0165] RowTable:{0,max,max} / / dst,src1,src2

[0166] ColTable:{0,1,1} / / dst,src1,src2

[0167] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [0,0]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max,1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [max,1].

[0168] Figure 4m The reduce operation command shown is configured as follows in the command configuration table:

[0169] RowTable:{0,max,max} / / dst,src1,src2

[0170] ColTable:{1,1,1} / / dst,src1,src2

[0171] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [0, 1]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [max, 1].

[0172] Figure 4n The reduce operation command shown is configured as follows in the command configuration table:

[0173] RowTable:{1,max,max} / / dst,src1,src2

[0174] ColTable:{0,1,1} / / dst,src1,src2

[0175] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [1, 0]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [max, 1].

[0176] Figure 4o The reduce operation command shown is configured as follows in the command configuration table:

[0177] RowTable:{0,max,1} / / dst,src1,src2

[0178] ColTable:{1,1,0} / / dst,src1,src2

[0179] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [0, 1]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [1, 0].

[0180] Figure 4p The reduce operation command shown is configured as follows in the command configuration table:

[0181] RowTable:{1,max,0} / / dst,src1,src2

[0182] ColTable:{0,1,1} / / dst,src1,src2

[0183] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [1, 0]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [0, 1].

[0184] Figure 4q The reduce operation command input shown is configured as follows in the command configuration table:

[0185] RowTable:{0,max,0} / / dst,src1,src2

[0186] ColTable:{1,1,0} / / dst,src1,src2

[0187] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [0,1]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max,1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [0,0].

[0188] Figure 4r The reduce operation command shown is configured as follows in the command configuration table:

[0189] RowTable:{1,max,0} / / dst,src1,src2

[0190] ColTable:{0,1,0} / / dst,src1,src2

[0191] The output parameter dst is of type [RowTable[0], ColTable[0]], which is [1,0]. The input parameter src1 is of type [RowTable[1], ColTable[1]], which is [max,1]. The input parameter src2 is of type [RowTable[2], ColTable[2]], which is [0,0].

[0192] The reduce operation instruction refers to an operation instruction that reduces the output parameters relative to the input parameters in the row dimension and / or column dimension.

[0193] Optionally, step S302 includes:

[0194] Retrieve vector instructions from the instruction configuration table;

[0195] Determine the data type of the parameters of the vector instruction;

[0196] Retrieve the loop iteration variable from the scalar instruction;

[0197] The loop iteration variable is mapped to the parameter of the vector instruction according to the data type of the parameter of the vector instruction.

[0198] In the above steps, after obtaining the vector instructions and the data types of the parameters of the vector instructions in the instruction configuration table, the loop iteration variables in the scalar instructions are mapped to the parameters of the vector instructions according to the dimension mapping rules of the vector instructions. The parameters of the vector instructions can be scalar parameters or vector parameters.

[0199] Optionally, mapping the loop iteration variable to the parameters of the vector instruction based on the data type of the parameters of the vector instruction includes:

[0200] Step S501: Generate a set of loop iteration variables based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0201] Step S502: Obtain the vector instruction dimension mapping rule corresponding to the data type of the parameter of the vector instruction;

[0202] Step S503: Select the loop iteration variable used for the parameters of the vector instruction from the set of loop iteration variables;

[0203] Step S504: Map the selected loop iteration variables to the row and column dimensions of the parameters according to the vector instruction dimension mapping rule to obtain the set of loop iteration variables of the vector instruction parameters.

[0204] In the above optional embodiments, it is not distinguished whether the vector instruction is a non-reduce instruction or a reduce instruction.

[0205] In step S501, a set of loop iteration variables is generated based on the obtained loop iteration variables.

[0206] like Figure 6a The example shown is a scalar code block. It includes the instruction veadd, whose loop iteration variables include i and j, where the step size of j is 1 and the step size of i is 10; then the set of loop iteration variables generated based on the obtained loop iteration variables is axeses:{(i,10),(j,1)}.

[0207] In steps S502-S504, for each vector instruction in the instruction configuration table, the vector instruction dimension mapping rule corresponding to the parameter type and the loop iteration variables used to select the parameters of the vector instruction from the loop iteration variable set are obtained according to the type of its parameters. Then, the selected loop iteration variables are mapped to a set of loop iteration variables for the parameters of the vector instruction according to the vector instruction dimension mapping rule, wherein the set of loop iteration variables for the parameters of the vector instruction includes the set of loop iteration variables for the vector instruction parameters in the row dimension and the set of loop iteration variables for the vector instruction parameters in the column dimension.

[0208] like Figure 6b The instruction configuration table shown includes the vector instructions veadd_mm, veadd_mv_dimh, veadd_mv_dimw, and veadd_mf.

[0209] For the vector instruction veadd_mm:

[0210] veadd_mm has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0211] RowTable:{max,max,max} / / C,A,B

[0212] ColTable:{1,1,1} / / C,A,B

[0213] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [max, 1].

[0214] Therefore, the mapping rules for C, A, and B are all:

[0215] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0216] Based on the set `axises`, the loop iteration variables of output C are mapped. Here, the loop iteration variables used by C are `i` and `j`. The stride of loop iteration variable `i` is 10, which is not 1, therefore it can be mapped to `row` in C. The stride of loop iteration variable `j` is 1, therefore it can be mapped to `col` in C. The set `dst_row_axises` of C is: {(i, 10)}, and the set `dst_col_axises` is: {(j, 1)}.

[0217] Based on the set `axises`, map the loop iteration variables of input A. Here, the loop iteration variables used by A are `i` and `j`. The stride of loop iteration variable `i` is 10, which can be mapped to `row` in A. The stride of loop iteration variable `j` is 1, which can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(j, 1)}.

[0218] Based on the set `axises`, map the loop iteration variables of input B. Here, the loop iteration variable used by B is `j`. The loop iteration variable `j` has a stride of 1, so it can be mapped to `col` in B, but not to `row`, because `row` in B can only map loop iteration variables with a stride not equal to 1. The set of `src_row_axises` for B is: {}, and the set of `src_col_axises` is: {(j,1)}.

[0219] Similarly, for the vector instruction veadd_mv_dimh:

[0220] veadd_mv_dimh has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0221] RowTable:{max,max,0} / / C,A,B

[0222] ColTable:{1,1,1} / / C,A,B

[0223] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [0, 1].

[0224] Therefore, the mapping rules for C and A are both:

[0225] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0226] The mapping rule for B is:

[0227] Row dimensions do not map to loop iteration variables, while column dimensions map to loop iteration variables with a step size of 1.

[0228] Based on the set `axises`, the loop iteration variables of output C are mapped. Here, the loop iteration variables used by C are `i` and `j`. The stride of loop iteration variable `i` is 10, which can be mapped to `row` in C. The stride of loop iteration variable `j` is 1, which can be mapped to `col` in C. The set `dst_row_axises` of C is: {(i, 10)}, and the set `dst_col_axises` is: {(j, 1)}.

[0229] Based on the set `axises`, map the loop iteration variables of input A. Here, the loop iteration variables used by A are `i` and `j`. The stride of loop iteration variable `i` is 10, which can be mapped to `row` in A. The stride of loop iteration variable `j` is 1, which can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(j, 1)}.

[0230] Based on the set `axises`, map the loop iteration variables of input B. Here, the loop iteration variable used by B is `j`. According to the mapping rules above, the stride of the loop iteration variable `j` is 1, and it can be mapped to `col` in B; however, the `row` direction of B does not map the loop iteration variable. The set of `src_row_axises` for B is: {}, and the set of `src_col_axises` is: {(j,1)}.

[0231] For the vector instruction veadd_mv_dimw:

[0232] veadd_mv_dimw has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0233] RowTable:{max,max,1} / / C,A,B

[0234] ColTable:{1,1,0} / / C,A,B

[0235] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [1, 0].

[0236] Therefore, the mapping rules for C and A are both:

[0237] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0238] The mapping rule for B is:

[0239] Row dimensions map to loop iteration variables with a step size of 1, while column dimensions do not map to loop iteration variables.

[0240] Based on the set `axises`, the loop iteration variables of output C are mapped. Here, the loop iteration variables used by C are `i` and `j`. The stride of loop iteration variable `i` is 10, which can be mapped to `row` in C. The stride of loop iteration variable `j` is 1, which can be mapped to `col` in C. The set `dst_row_axises` of C is: {(i, 10)}, and the set `dst_col_axises` is: {(j, 1)}.

[0241] Based on the set `axises`, map the loop iteration variables of input A. Here, the loop iteration variables used by A are `i` and `j`. The stride of loop iteration variable `i` is 10, which can be mapped to `row` in A. The stride of loop iteration variable `j` is 1, which can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(j, 1)}.

[0242] Based on the set `axises`, the loop iteration variable used by input B is mapped, where `j` is the loop iteration variable. The stride of loop iteration variable `j` is 1, so it cannot be mapped in the `row` direction of B; and according to the mapping rules, the `col` dimension of B does not map to loop iteration variables. Therefore, the set of `src_row_axises` for B is {}, and the set of `src_col_axises` is {}.

[0243] For the vector instruction veadd_mv_mf:

[0244] veadd_mv_mf has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0245] RowTable:{max,max,0} / / C,A,B

[0246] ColTable:{1,1,0} / / C,A,B

[0247] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [0, 0].

[0248] Therefore, the mapping rules for C and A are both:

[0249] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0250] The mapping rule for B is:

[0251] Row dimensions do not map to loop iteration variables, and column dimensions do not map to loop iteration variables.

[0252] Based on the set `axises`, the loop iteration variables of output C are mapped. Here, the loop iteration variables used by C are `i` and `j`. The stride of loop iteration variable `i` is 10, which can be mapped to `row` in C. The stride of loop iteration variable `j` is 1, which can be mapped to `col` in C. The set `dst_row_axises` of C is: {(i, 10)}, and the set `dst_col_axises` is: {(j, 1)}.

[0253] Based on the set `axises`, map the loop iteration variables of input A. Here, the loop iteration variables used by A are `i` and `j`. The stride of loop iteration variable `i` is 10, which can be mapped to `row` in A. The stride of loop iteration variable `j` is 1, which can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(j, 1)}.

[0254] Based on the set `axises`, map the loop iteration variables of input B. Here, the loop iteration variable used by B is `j`. The stride of loop iteration variable `j` is 1, so it cannot be mapped in the `row` direction of B; while the `col` dimension of B does not map loop iteration variables. The set of `src_row_axises` for B is: {}, and the set of `src_col_axises` is: {}.

[0255] After steps S501-S504, scalar instructions are mapped to vector instructions. Since it cannot be determined which vector instructions in the vector instruction configuration table can execute the operations in the scalar instructions before the mapping is complete, in step S302, the scalar instructions need to be mapped to each vector instruction in the vector instruction configuration table. For example, in the above example, the scalar instruction `veadd` is mapped to the vector instructions `veadd_mm`, `veadd_mv_dimh`, `veadd_mv_dimw`, and `veadd_mf`, respectively.

[0256] Optionally, in the specific implementation of step S302, non-reduce instructions and reduce instructions can be distinguished, and different mapping processes can be used for the two different types of instructions.

[0257] Optionally, for non-reduce instructions, step S302 includes:

[0258] Step S701: Generate a set of loop iteration variables based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0259] Step S702: Obtain the vector instruction dimension mapping rule of the output parameter corresponding to the data type according to the data type of the output parameter of the vector instruction;

[0260] Step S703: Select the loop iteration variable used for the output parameter from the set of loop iteration variables;

[0261] Step S704: Map the loop iteration variables used by the selected output parameters to the row dimension and column dimension of the output parameters according to the vector instruction dimension mapping rule of the output parameters to obtain the set of loop iteration variables of the output parameters of the vector instruction;

[0262] Step S705: Obtain the vector instruction dimension mapping rule of the input parameter corresponding to the data type according to the data type of the input parameter of the vector instruction;

[0263] Step S706: Select the loop iteration variable used by the input parameter from the set of loop iteration variables of the output parameter;

[0264] Step S707: Map the loop iteration variables used by the selected input parameters to the row dimension and column dimension of the input parameters according to the vector instruction dimension mapping rule of the input parameters to obtain the set of loop iteration variables of the input parameters of the vector instruction.

[0265] In steps S701-S707 above, loop iteration variables are first mapped onto the output parameters, then the obtained set of output parameter loop iteration variables is used as the set of input parameter selection loop iteration variables, and then loop iteration variables are mapped onto the input parameters.

[0266] like Figure 8 The following is an example of another scalar code block. It includes the instruction veadd, whose loop iteration variable includes i, where the step size of i is 1; then the set of loop iteration variables generated based on the obtained loop iteration variables is axeses:{(i,1)}.

[0267] In this embodiment, it is also used Figure 6b The instruction configuration table shown includes the vector instructions veadd_mm, veadd_mv_dimh, veadd_mv_dimw, and veadd_mf.

[0268] For the vector instruction veadd_mm:

[0269] veadd_mm has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0270] RowTable:{max,max,max} / / C,A,B

[0271] ColTable:{1,1,1} / / C,A,B

[0272] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [max, 1].

[0273] Therefore, the mapping rules for C, A, and B are all:

[0274] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0275] Based on the set `axises`, the loop iteration variable of output C is mapped. Here, the loop iteration variable used by C is `i`. The stride of the loop iteration variable `i` is 1, which can be mapped to `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {(i,1)}.

[0276] Map the loop iteration variables of input A based on the sets dst_row_axises and dst_col_axises. Here, the loop iteration variable used by A is i. The stride of the loop iteration variable i is 1, which can be mapped to col in A. The set of src_row_axises of A is {}, and the set of src_col_axises is {(i,1)}.

[0277] Map the loop iteration variables of input B based on the sets dst_row_axises and dst_col_axises. Here, the loop iteration variable used by B is i. The stride of the loop iteration variable i is 1, which can be mapped to col in B. The set of src_row_axises of B is {}, and the set of src_col_axises is {(i,1)}.

[0278] Similarly, for the vector instruction veadd_mv_dimh:

[0279] veadd_mv_dimh has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0280] RowTable:{max,max,0} / / C,A,B

[0281] ColTable:{1,1,1} / / C,A,B

[0282] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [0, 1].

[0283] Therefore, the mapping rules for C and A are both:

[0284] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0285] The mapping rule for B is:

[0286] Row dimensions do not map to loop iteration variables, while column dimensions map to loop iteration variables with a step size of 1.

[0287] Based on the set `axises`, the loop iteration variable of output C is mapped. Here, the loop iteration variable used by C is `i`. The stride of the loop iteration variable `i` is 1, which can be mapped to `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {(i,1)}.

[0288] Map the loop iteration variables of input A based on the sets dst_row_axises and dst_col_axises. Here, the loop iteration variable used by A is i. The stride of the loop iteration variable i is 1, which can be mapped to col in A. The set of src_row_axises of A is {}, and the set of src_col_axises is {(i,1)}.

[0289] Map the loop iteration variables of input B based on the sets dst_row_axises and dst_col_axises. Here, the loop iteration variable used by B is i. The stride of the loop iteration variable i is 1, which can be mapped to col in B. The set of src_row_axises of B is {}, and the set of src_col_axises is {(i,1)}.

[0290] For the vector instruction veadd_mv_dimw:

[0291] veadd_mv_dimw has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0292] RowTable:{max,max,1} / / C,A,B

[0293] ColTable:{1,1,0} / / C,A,B

[0294] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [1, 0].

[0295] Therefore, the mapping rules for C and A are both:

[0296] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0297] The mapping rule for B is:

[0298] Row dimensions map to loop iteration variables with a step size of 1, while column dimensions do not map to loop iteration variables.

[0299] Based on the set `axises`, the loop iteration variable of output C is mapped. Here, the loop iteration variable used by C is `i`. The stride of the loop iteration variable `i` is 1, which can be mapped to `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {(i,1)}.

[0300] Map the loop iteration variables of input A based on the sets dst_row_axises and dst_col_axises. Here, the loop iteration variable used by A is i. The stride of the loop iteration variable i is 1, which can be mapped to col in A. The set of src_row_axises of A is {}, and the set of src_col_axises is {(i,1)}.

[0301] Map the loop iteration variables of input B based on the sets dst_row_axises and dst_col_axises. The loop iteration variable used by B is i. The stride of the loop iteration variable i is 1, and it cannot be mapped to the row and col directions of B. The set of src_row_axises for B is {}, and the set of src_col_axises is {}.

[0302] For the vector instruction veadd_mv_mf:

[0303] veadd_mv_mf has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0304] RowTable:{max,max,0} / / C,A,B

[0305] ColTable:{1,1,0} / / C,A,B

[0306] The output parameter C is of type [RowTable[0], ColTable[0]], which is [max, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [0, 0].

[0307] Therefore, the mapping rules for C and A are both:

[0308] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0309] The mapping rule for B is:

[0310] Row dimensions do not map to loop iteration variables, and column dimensions do not map to loop iteration variables.

[0311] Based on the set `axises`, the loop iteration variable of output C is mapped. Here, the loop iteration variable used by C is `i`. The stride of the loop iteration variable `i` is 1, which can be mapped to `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {(i,1)}.

[0312] Map the loop iteration variables of input A based on the sets dst_row_axises and dst_col_axises. Here, the loop iteration variable used by A is i. The stride of the loop iteration variable i is 1, which can be mapped to col in A. The set of src_row_axises of A is {}, and the set of src_col_axises is {(i,1)}.

[0313] Map the loop iteration variables of input B according to the set `axises`. Here, the loop iteration variable used by B is `j`. The stride of the loop iteration variable `i` is 1, and it cannot be mapped to the `row` and `col` directions of B. The set of `src_row_axises` for B is: {}, and the set of `src_col_axises` is: {}.

[0314] Optionally, for the reduce instruction, step S302 includes:

[0315] Step S901: Generate a set of loop iteration variables based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0316] Step S902: Obtain the vector instruction dimension mapping rule for the input parameter corresponding to the data type according to the data type of the input parameter of the vector instruction;

[0317] Step S903: Select the loop iteration variable of the input parameter from the set of loop iteration variables;

[0318] Step S904: Map the selected loop iteration variables of the input parameters to the row dimension and column dimension of the input parameters according to the vector instruction dimension mapping rule of the input parameters to obtain the set of loop iteration variables of the input parameters of the vector instruction.

[0319] Step S905: Merge the sets of loop iteration variables of all input parameters to obtain the joint set of loop iteration variables of input parameters;

[0320] Step S906: Obtain the vector instruction dimension mapping rule of the output parameter corresponding to the data type according to the data type of the output parameter of the vector instruction;

[0321] Step S907: Select the loop iteration variable of the output parameter from the joint set of loop iteration variables of the input parameters;

[0322] Step S908: Map the selected loop iteration variables of the output parameters to the row dimension and column dimension of the output parameters according to the vector instruction dimension mapping rule of the output parameters to obtain the set of loop iteration variables of the output parameters of the vector instruction.

[0323] In steps S901-S908 above, loop iteration variables are first mapped onto the input parameters. Then, the union of all the output parameter loop iteration variable sets is used as the set of output parameter selected loop iteration variables. Finally, the selected loop iteration variables are mapped onto the output parameters.

[0324] like Figure 10a The following is an example of another scalar code block. It includes the instruction veemacc, whose loop iteration variables include i and k, where the step size of k is 1 and the step size of i is 10; then the set of loop iteration variables generated based on the obtained loop iteration variables is axeses:{(i,10),(k,1)}.

[0325] In this embodiment, using, for example Figure 10b The instruction configuration table shown includes the vector instructions veemacc_mm, veemacc_mm_dimh, veemacc_mm_dimw, veemacc_mv_dimh, veemacc_mv_dimw, veemacc_mf_dimh, and veemacc_mf_dimw.

[0326] For the vector instruction veemacc_mm:

[0327] veemacc_mm includes 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0328] RowTable:{0,max,max} / / C,A,B

[0329] ColTable:{0,1,1} / / C,A,B

[0330] The output parameter C is of type [RowTable[0], ColTable[0]], which is [0,0]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max,1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [max,1].

[0331] Therefore, the mapping rules for A and B are both:

[0332] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0333] Therefore, the mapping rule for C can be obtained as follows:

[0334] Row dimensions do not map to loop iteration variables, and column dimensions do not map to loop iteration variables.

[0335] Based on the set `axises`, map the loop iteration variables of input A. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in A; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(k, 1)}.

[0336] Based on the set `axises`, map the loop iteration variables of input B. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in B; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in B. The set of `src_row_axises` for B is {(i, 10)}, and the set of `src_col_axises` is {(k, 1)}.

[0337] Obtain the union of the sets of loop iteration variables for all input parameters in the row and col directions, and take the maximum stride for the same loop iteration variable. Therefore, union_row_axises is {(i,10)} and union_col_axises is {(k,1)}.

[0338] Based on the sets `union_row_axises` and `union_col_axises`, map the loop iteration variables of output C. The loop iteration variable used by C is `k`. The stride of the loop iteration variable `k` is 1, and it cannot be mapped to `row` or `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {}.

[0339] For the vector instruction veemacc_mm_dimh:

[0340] veemacc_mm_dimh has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0341] RowTable:{0,max,max} / / C,A,B

[0342] ColTable:{1,1,1} / / C,A,B

[0343] The output parameter C is of type [RowTable[0], ColTable[0]], which is [0, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [max, 1].

[0344] Therefore, the mapping rules for A and B are both:

[0345] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0346] Therefore, the mapping rule for C can be obtained as follows:

[0347] Row dimensions do not map to loop iteration variables, while column dimensions map to loop iteration variables with a step size of 1.

[0348] Based on the set `axises`, map the loop iteration variables of input A. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in A; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(k, 1)}.

[0349] Based on the set `axises`, map the loop iteration variables of input B. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in B; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in B. The set of `src_row_axises` for B is {(i, 10)}, and the set of `src_col_axises` is {(k, 1)}.

[0350] Obtain the union of the sets of loop iteration variables for all input parameters in the row and col directions, and take the maximum stride for the same loop iteration variable. Therefore, union_row_axises is {(i,10)} and union_col_axises is {(k,1)}.

[0351] Based on the sets `union_row_axises` and `union_col_axises`, the loop iteration variables of output C are mapped. Here, the loop iteration variable used by C is `k`. The stride of the loop iteration variable `k` is 1, which can be mapped to `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {(k,1)}.

[0352] For the vector instruction veemacc_mm_dimw:

[0353] veemacc_mm_dimw includes 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0354] RowTable:{1,max,max} / / C,A,B

[0355] ColTable:{0,1,1} / / C,A,B

[0356] The output parameter C is of type [RowTable[0], ColTable[0]], which is [1, 0]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [max, 1].

[0357] Therefore, the mapping rules for A and B are both:

[0358] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0359] Therefore, the mapping rule for C can be obtained as follows:

[0360] Row dimensions map to loop iteration variables with a step size of 1, while column dimensions do not map to loop iteration variables.

[0361] Based on the set `axises`, map the loop iteration variables of input A. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in A; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(k, 1)}.

[0362] Based on the set `axises`, map the loop iteration variables of input B. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in B; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in B. The set of `src_row_axises` for B is {(i, 10)}, and the set of `src_col_axises` is {(k, 1)}.

[0363] Obtain the union of the sets of loop iteration variables for all input parameters in the row and col directions, and take the maximum stride for the same loop iteration variable. Therefore, union_row_axises is {(i,10)} and union_col_axises is {(k,1)}.

[0364] Based on the sets `union_row_axises` and `union_col_axises`, map the loop iteration variables of output C. The loop iteration variable used by C is `k`. The stride of the loop iteration variable `k` is 1, and it cannot be mapped to `row` or `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {}.

[0365] For the vector instruction veemacc_mv_dimh:

[0366] veemacc_mv_dimh has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0367] RowTable:{0,max,1} / / C,A,B

[0368] ColTable:{1,1,0} / / C,A,B

[0369] The output parameter C is of type [RowTable[0], ColTable[0]], which is [0, 1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [1, 0].

[0370] Therefore, the mapping rule for A can be obtained as follows:

[0371] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0372] Therefore, the mapping rule for B can be obtained as follows:

[0373] Row dimensions map to loop iteration variables with a step size of 1, while column dimensions do not map to loop iteration variables.

[0374] Therefore, the mapping rule for C can be obtained as follows:

[0375] Row dimensions do not map to loop iteration variables, while column dimensions map to loop iteration variables with a step size of 1.

[0376] Based on the set `axises`, map the loop iteration variables of input A. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in A; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(k, 1)}.

[0377] Based on the set `axises`, map the loop iteration variables of input B. The loop iteration variable `i` has a stride of 10, which can be mapped to `row` in B. The set `src_row_axises` of B is: `{(i,10)}`, and the set `src_col_axises` is: `{}`.

[0378] Obtain the union of the sets of loop iteration variables for all input parameters in the row and col directions, and take the maximum stride for the same loop iteration variable. Therefore, union_row_axises is {(i,10)} and union_col_axises is {(k,1)}.

[0379] Based on the sets `union_row_axises` and `union_col_axises`, the loop iteration variables of output C are mapped. Here, the loop iteration variable used by C is `k`. The stride of the loop iteration variable `k` is 1, which can be mapped to `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {(k,1)}.

[0380] For the vector instruction veemacc_mv_dimw:

[0381] veemacc_mv_dimw has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0382] RowTable:{1,max,0} / / C,A,B

[0383] ColTable:{0,1,1} / / C,A,B

[0384] The output parameter C is of type [RowTable[0], ColTable[0]], which is [1, 0]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max, 1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [0, 1].

[0385] Therefore, the mapping rule for A can be obtained as follows:

[0386] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0387] Therefore, the mapping rule for B can be obtained as follows:

[0388] Row dimensions do not map to loop iteration variables, while column dimensions map to loop iteration variables with a step size of 1.

[0389] Therefore, the mapping rule for C can be obtained as follows:

[0390] Row dimensions map to loop iteration variables with a step size of 1, while column dimensions do not map to loop iteration variables.

[0391] Based on the set `axises`, map the loop iteration variables of input A. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in A; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(k, 1)}.

[0392] Based on the set `axises`, map the loop iteration variables of input B. The stride of the loop iteration variable k is 1, which can be mapped to `col` in B. The set of `src_row_axises` of B is: {}, and the set of `src_col_axises` is: {(k,1)}.

[0393] Obtain the union of the sets of loop iteration variables for all input parameters in the row and col directions, and take the maximum stride for the same loop iteration variable. Therefore, union_row_axises is {(i,10)} and union_col_axises is {(k,1)}.

[0394] Based on the sets `union_row_axises` and `union_col_axises`, map the loop iteration variables of output C. The loop iteration variable used by C is `k`. The stride of the loop iteration variable `k` is 1, and it cannot be mapped to `row` or `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {}.

[0395] For the vector instruction veemacc_mf_dimh:

[0396] veemacc_mf_dimh has 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0397] RowTable:{0,max,0} / / C,A,B

[0398] ColTable:{1,1,0} / / C,A,B

[0399] The output parameter C is of type [RowTable[0], ColTable[0]], which is [0,1]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max,1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [0,0].

[0400] Therefore, the mapping rule for A can be obtained as follows:

[0401] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0402] Therefore, the mapping rule for B can be obtained as follows:

[0403] Row dimensions do not map to loop iteration variables, and column dimensions do not map to loop iteration variables.

[0404] Therefore, the mapping rule for C can be obtained as follows:

[0405] Row dimensions do not map to loop iteration variables, while column dimensions map to loop iteration variables with a step size of 1.

[0406] Based on the set `axises`, map the loop iteration variables of input A. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in A; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(k, 1)}.

[0407] Map the loop iteration variables of input B based on the set `axises`. Loop iteration variables cannot be mapped to rows or columns of B. The set `src_row_axises` of B is {}, and the set `src_col_axises` is {}.

[0408] Obtain the union of the sets of loop iteration variables for all input parameters in the row and col directions, and take the maximum stride for the same loop iteration variable. Therefore, union_row_axises is {(i,10)} and union_col_axises is {(k,1)}.

[0409] Based on the sets `union_row_axises` and `union_col_axises`, the loop iteration variables of output C are mapped. Here, the loop iteration variable used by C is `k`. The stride of the loop iteration variable `k` is 1, which can be mapped to `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {(k,1)}.

[0410] For the vector instruction veemacc_mf_dimw:

[0411] veemacc_mf_dimw includes 2 inputs and 1 output, and the parameter types in its instruction configuration table are:

[0412] RowTable:{1,max,0} / / C,A,B

[0413] ColTable:{0,1,0} / / C,A,B

[0414] The output parameter C is of type [RowTable[0], ColTable[0]], which is [1,0]. The input parameter A is of type [RowTable[1], ColTable[1]], which is [max,1]. The input parameter B is of type [RowTable[2], ColTable[2]], which is [0,0].

[0415] Therefore, the mapping rule for A can be obtained as follows:

[0416] The loop iteration variable with a row dimension mapping step size of not 1, and the loop iteration variable with a column dimension mapping step size of 1.

[0417] Therefore, the mapping rule for B can be obtained as follows:

[0418] Row dimensions do not map to loop iteration variables, and column dimensions do not map to loop iteration variables.

[0419] Therefore, the mapping rule for C can be obtained as follows:

[0420] Row dimensions map to loop iteration variables with a step size of 1, while column dimensions do not map to loop iteration variables.

[0421] Based on the set `axises`, map the loop iteration variables of input A. The loop iteration variable `i` with a stride of 10 can be mapped to `row` in A; the loop iteration variable `k` with a stride of 1 can be mapped to `col` in A. The set of `src_row_axises` for A is: {(i, 10)}, and the set of `src_col_axises` is: {(k, 1)}.

[0422] Map the loop iteration variables of input B based on the set axes. The stride of the loop iteration variable k is 1, so it cannot be mapped to row and col in B. The set of src_row_axises of B is {}, and the set of src_col_axises is {}.

[0423] Obtain the union of the sets of loop iteration variables for all input parameters in the row and col directions, and take the maximum stride for the same loop iteration variable. Therefore, union_row_axises is {(i,10)} and union_col_axises is {(k,1)}.

[0424] Based on the sets `union_row_axises` and `union_col_axises`, map the loop iteration variables of output C. The loop iteration variable used by C is `k`. The stride of the loop iteration variable `k` is 1, and it cannot be mapped to `row` or `col` in C. The set of `dst_row_axises` for C is: {}, and the set of `dst_col_axises` is: {}.

[0425] By using the different mapping methods described above for reduce instructions and non-reduce instructions, we obtain the result of mapping scalar instructions to vector instructions.

[0426] return Figure 3 The method for recognizing the vector command further includes:

[0427] Step S303: Determine the validity of the vector instruction according to the vector instruction dimension validity rules; wherein, the vector instruction dimension validity rules include rules for verifying the validity of the instruction mapping result; if the vector instruction is valid, then the vector instruction is successfully recognized.

[0428] After mapping scalar instructions to vector instructions in the instruction configuration table, it is impossible to determine whether the mapped vector instructions are valid. Therefore, in this step, the validity rules of the vector instruction dimension are used to further determine which vector instructions are valid.

[0429] Optionally, step S303 includes:

[0430] The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables of the parameters; or,

[0431] The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables of the output parameters and the dimension and step size of the loop iteration variables in the set of loop iteration variables of the input parameters.

[0432] Optionally, the validity rules for vector instruction dimensions may differ for different types of data.

[0433] When the data type is 1*1, there are no constraints on the mapping loop iteration variables of the row dimension and column dimension;

[0434] When the data type is 1*n, there are no constraints on the row dimension mapping loop iteration variable, but the column dimension must have a mapping loop iteration variable.

[0435] When the data type is m*1, the row dimension must have a mapping loop iteration variable, while the column dimension has no constraint on the mapping loop iteration variable.

[0436] When the data type is m*n, there are no constraints on the row dimension mapping loop iteration variable, but the column dimension must have a mapping loop iteration variable.

[0437] In addition, the rules for judging the validity of row / column dimensions in input parameters also include:

[0438] When all input parameters (row / column dimension mapping loop iteration variables) are not empty, the intersection of the row / column dimension mapping loop iteration variables is not empty.

[0439] For reduce-type instructions, the following validity rules also need to be met:

[0440] The loop iteration variables used in the input parameters that are processed by reduce must be successfully mapped to either the row or column dimension.

[0441] The dimension mapped to the loop iteration variable processed by reduce in the input parameters cannot be mapped to the loop iteration variable in the output parameters.

[0442] Therefore, based on the above rules, it can be determined that among the vector instructions in the examples of steps S501-S504, veadd_mv_dimw is an invalid vector instruction. This is because B is an m*1 type data, and its validity rule is: the row dimension must have a mapping loop iteration variable, while the column dimension has no constraint on the mapping loop iteration variable. However, the row dimension of the set B does not have a mapping loop iteration variable, therefore veadd_mv_dimw is invalid. After applying the validity rule, all other vector instructions conform to the validity rule and are therefore valid.

[0443] Similarly, based on the above rules, it can be determined that among the vector instructions in the examples of steps S701-S707, veadd_mv_dimw is an invalid vector instruction because B is an m*1 type data, and its validity rule is: the row dimension must have a mapping loop iteration variable, while the column dimension has no constraint on the mapping loop iteration variable. The src_row_axises set of B is {}, and the src_col_axises set is {}, meaning that the row dimension of B does not have a mapping loop iteration variable, therefore it does not meet the validity rule, and veadd_mv_dimw is invalid. After applying the validity rule, all other vector instructions meet the validity rule and are therefore valid.

[0444] Therefore, based on the above rules, it can be determined that among the vector instructions in the examples of steps S901-S908, veemacc_mm_dimw is an invalid instruction because C is an m*1 type data, and its validity rule is: the row dimension must have a mapping loop iteration variable, while the column dimension has no constraint on the mapping loop iteration variable. The dst_row_axises set of C is {}, and the dst_col_axises set is {}. Since the row dimension of C does not have a mapping loop iteration variable, it does not meet the validity rule; therefore, veemacc_mm_dimw is invalid.

[0445] `veemacc_mv_dimw` is an invalid instruction because `C` is an m*1 type data, and its validity rule is: row dimensions must have mapping loop iteration variables, while column dimensions have no constraints on mapping loop iteration variables. The `dst_row_axises` set of `C` is `{}`, and the `dst_col_axises` set is `{}`. Since `C`'s row dimensions do not have mapping loop iteration variables, it does not meet the validity rule; therefore, `veemacc_mm_dimw` is invalid.

[0446] `veemacc_mf_dimh` is an invalid instruction because B uses the loop iteration variable `i` from the reduce function. The validity rule for this instruction is that the loop iteration variable used in the input parameters must be successfully mapped to either the row or column dimension. However, B's `src_row_axises` set is `{}`, and its `src_col_axises` set is `{}`. Neither `row` nor `col` in B has a mapped axis, violating the validity rule. Therefore, `veemacc_mf_dimh` is invalid.

[0447] `veemacc_mf_dimw` is an invalid instruction because `C` is an m*1 type data, and its validity rule is: row dimensions must have mapped loop iteration variables, while column dimensions have no such constraint. However, the `dst_row_axises` set of `C` is `{}`, and the `dst_col_axises` set is `{}`, meaning `C`'s row dimensions do not have mapped loop iteration variables. Furthermore, because `B` uses the `i` loop iteration variable from the `reduce` function, its validity rule is: the loop iteration variable used in the input parameters that is processed by `reduce` must be successfully mapped to either the row or column dimensions. However, `B`'s `src_row_axises` set is `{}`, and the `src_col_axises` set is `{}`, meaning neither `row` nor `col` in `B` has mapped axes, violating the validity rules. Therefore, `veemacc_mf_dimw` is an invalid instruction.

[0448] All other vector instructions conform to the validity rules.

[0449] Finally, valid vector instructions are retained as those for successful recognition. In the above embodiment, veadd_mm, veadd_mv_dimh, and veadd_mf are the vector instructions for successful recognition; that is, the scalar instruction veadd can be converted into any one of veadd_mm, veadd_mv_dimh, and veadd_mf. Similarly, veemacc_mm, veemacc_mm_dimh, and veemacc_mv_dimh are the vector instructions for successful recognition; that is, the scalar instruction veemacc can be converted into any one of veemacc_mm, veemacc_mm_dimh, and veemacc_mv_dimh.

[0450] The above method can convert scalar instructions into corresponding vector instructions, improving the efficiency of data processing in hardware chips. Furthermore, the vector instructions supported by the above recognition method can be expanded through instruction configuration files.

[0451] This disclosure provides a method for identifying vector instructions. The method includes: acquiring scalar instructions; mapping the scalar instructions to vector instructions according to vector instruction dimension mapping rules and an instruction configuration table; wherein the vector instruction dimension mapping rules include rules for mapping scalar instructions to vector instructions; the instruction configuration table includes a set of vector instructions; determining the validity of the vector instructions according to vector instruction dimension validity rules; wherein the vector instruction dimension validity rules include rules for verifying the validity of the instruction mapping result; if the vector instructions are valid, the vector instructions are successfully identified. This method identifies vector instructions through vector instruction dimension mapping rules, an instruction configuration table, and vector instruction dimension validity rules, solving the technical problems in the prior art where converting scalar instructions to vector instructions is complex, lacks versatility, and cannot distinguish between vector instructions.

[0452] This disclosure provides a vector instruction recognition device, comprising: an instruction acquisition module for acquiring scalar instructions; a mapping module for mapping the scalar instructions to vector instructions according to vector instruction dimension mapping rules and an instruction configuration table; wherein the vector instruction dimension mapping rules include rules for mapping scalar instructions to vector instructions; the instruction configuration table includes a set of vector instructions; and an identification verification module for determining the validity of the vector instructions according to vector instruction dimension validity rules; wherein the vector instruction dimension validity rules include rules for verifying the validity of the instruction mapping results; if the vector instructions are valid, the vector instructions are successfully recognized.

[0453] Furthermore, the vector instruction dimension mapping rule includes:

[0454] The data type of the parameters in a vector command;

[0455] The rule for mapping loop iteration variables in scalar instructions to parameters in vector instructions.

[0456] Furthermore, when the data type of the parameter is 1*1 type data, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter does not map to the loop iteration variable.

[0457] When the data type of the parameter is 1*n, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter maps to the loop iteration variable with a step size of 1.

[0458] When the data type of the parameter is m*1, the mapping rule is that the row dimension of the parameter maps to the loop iteration variable with a step size of not 1, and the column dimension of the parameter does not map to the loop iteration variable.

[0459] When the data type of the parameter is m*n type, the mapping rule is that the row dimension mapping step of the parameter is not 1 and the column dimension mapping step of the parameter is 1.

[0460] Furthermore, the vector instruction dimension validity rules include:

[0461] When the data type of the parameter is 1*1, there are no constraints on the mapping of the loop iteration variable in the row and column dimensions;

[0462] When the data type of the parameter is 1*n, the parameter has no constraint on mapping the loop iteration variable in the row dimension, and the parameter has a mapping loop iteration variable in the column dimension;

[0463] When the data type of the parameter is m*1, the parameter has a mapping loop iteration variable in the row dimension, and the parameter has no constraint on the mapping loop iteration variable in the column dimension;

[0464] When the data type of the parameter is m*n type, the parameter has no constraint on mapping the loop iteration variable in the row dimension, and the parameter has a mapping loop iteration variable in the column dimension;

[0465] When the vector instruction is an instruction to eliminate loop iteration variables, the parameter has a mapping loop iteration variable in the row dimension or the parameter has a mapping loop iteration variable in the column dimension.

[0466] Furthermore, the instruction configuration table includes:

[0467] The data types of all vector instructions to be identified and the parameters in each vector instruction.

[0468] Furthermore, the data type of the parameters in the vector instruction is constrained by the step size of the data type; wherein,

[0469] When the data type is 1*1, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 0.

[0470] When the data type is 1*n, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 1.

[0471] When the data type is m*1, its step size constraint is that the step size in the row dimension is 1 and the step size in the column dimension is 0.

[0472] When the data type is m*n, its step size constraint is that the step size in the row dimension is max and the step size in the column dimension is 1; where max represents the maximum value that the register can represent.

[0473] Furthermore, the mapping module is also used for:

[0474] Retrieve vector instructions from the instruction configuration table;

[0475] Determine the data type of the parameters of the vector instruction;

[0476] Retrieve the loop iteration variable from the scalar instruction;

[0477] The loop iteration variable is mapped to the parameter of the vector instruction according to the data type of the parameter of the vector instruction.

[0478] Furthermore, the mapping module is also used for:

[0479] A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0480] The vector instruction dimension mapping rule corresponding to the data type of the parameter of the vector instruction is obtained.

[0481] The loop iteration variable used to select the parameters of the vector instruction from the set of loop iteration variables;

[0482] The selected loop iteration variables are mapped to the row and column dimensions of the parameters according to the vector instruction dimension mapping rules to obtain the set of loop iteration variables of the vector instruction parameters.

[0483] Furthermore, when the vector instruction is not an instruction to eliminate loop iteration variables, the mapping module is also used to:

[0484] A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0485] Based on the data type of the output parameter of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the output parameter;

[0486] Select the loop iteration variable used for the output parameter from the set of loop iteration variables;

[0487] The loop iteration variables used by the selected output parameters are mapped to the row dimension and column dimension of the output parameters according to the vector instruction dimension mapping rule of the output parameters to obtain the set of loop iteration variables of the output parameters of the vector instruction;

[0488] Based on the data type of the input parameters of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the input parameters;

[0489] Select the loop iteration variable used for the input parameter from the set of loop iteration variables of the output parameter;

[0490] The loop iteration variables used by the selected input parameters are mapped to the row and column dimensions of the input parameters according to the vector instruction dimension mapping rules of the input parameters, respectively, to obtain the set of loop iteration variables of the input parameters of the vector instruction.

[0491] Furthermore, when the vector instruction is an instruction to eliminate loop iteration variables, the mapping module is also used to:

[0492] A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables;

[0493] Based on the data type of the input parameters of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the input parameters;

[0494] Select the loop iteration variable used for the input parameter from the set of loop iteration variables;

[0495] The loop iteration variables used by the selected input parameters are mapped to the row dimension and column dimension of the input parameters according to the vector instruction dimension mapping rule of the input parameters to obtain the set of loop iteration variables of the input parameters of the vector instruction.

[0496] The set of iterative variables for all input parameters is merged to obtain the joint set of iterative variables for the input parameters;

[0497] Based on the data type of the output parameter of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the output parameter;

[0498] Select the loop iteration variable used by the output parameter from the joint set of loop iteration variables of the input parameters;

[0499] The loop iteration variables used by the selected output parameters are mapped to the row and column dimensions of the output parameters according to the vector instruction dimension mapping rules of the output parameters to obtain the set of loop iteration variables of the output parameters of the vector instruction.

[0500] Furthermore, the identification and verification module is also used for:

[0501] The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables of the parameters; or,

[0502] The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables of the output parameters and the dimension and step size of the loop iteration variables in the set of loop iteration variables of the input parameters.

[0503] This disclosure also provides an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions such that the processors, when running, implement any of the methods described in the embodiments.

[0504] This disclosure also provides a non-transitory computer-readable storage medium that stores computer instructions for causing a computer to perform any of the methods described in the foregoing embodiments.

[0505] This disclosure also provides a computer program product, which includes computer instructions that, when executed by a computing device, can perform any of the methods described in the foregoing embodiments.

[0506] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0507] The units described in the embodiments of this disclosure can be implemented in software or in hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0508] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0509] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Claims

1. A method for recognizing vector commands, characterized in that, include: Obtain scalar instruction; The scalar instructions are mapped to vector instructions according to the vector instruction dimension mapping rules and the instruction configuration table; wherein, the vector instruction dimension mapping rules include rules for mapping scalar instructions to vector instructions; the instruction configuration table includes a set of vector instructions; the vector instruction dimension mapping rules include: the data type of the parameters in the vector instructions, and the data type corresponding to different parameters, and rules for mapping the loop iteration variables in the scalar instructions to the row dimension and / or column dimension in the parameters of the vector instructions; The validity of the vector instruction is determined according to the vector instruction dimension validity rules; wherein, the vector instruction dimension validity rules include rules for verifying the validity of the instruction mapping results; If the vector instruction is valid, then the vector instruction was successfully recognized; Wherein, when the data type of the parameter is 1*1 type data, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter does not map to the loop iteration variable; When the data type of the parameter is 1*n, the mapping rule is that the row dimension of the parameter does not map to the loop iteration variable and the column dimension of the parameter maps to the loop iteration variable with a step size of 1. When the data type of the parameter is m*1, the mapping rule is that the row dimension of the parameter maps to the loop iteration variable with a step size of not 1, and the column dimension of the parameter does not map to the loop iteration variable. When the data type of the parameter is m*n type, the mapping rule is that the row dimension of the parameter is mapped to the loop iteration variable with a step size of not 1 and the column dimension of the parameter is mapped to the loop iteration variable with a step size of 1.

2. The vector instruction recognition method as described in claim 1, characterized in that, The vector instruction dimension validity rules include: When the data type of the parameter is 1*1, there are no constraints on the mapping of the loop iteration variable in the row and column dimensions; When the data type of the parameter is 1*n, the parameter has no constraint on mapping loop iteration variables in the row dimension, and the parameter has a mapping loop iteration variable in the column dimension; When the data type of the parameter is m*1, the parameter has a mapping loop iteration variable in the row dimension, and the parameter has no constraint on the mapping loop iteration variable in the column dimension; When the data type of the parameter is m*n type, the parameter has no constraint on mapping the loop iteration variable in the row dimension, and the parameter has a loop iteration variable mapped in the column dimension; When the vector instruction is an instruction to eliminate loop iteration variables, the parameter has a mapping loop iteration variable in the row dimension or the parameter has a mapping loop iteration variable in the column dimension.

3. The vector instruction recognition method as described in claim 1, characterized in that, The instruction configuration table includes: The data types of all vector instructions to be identified and the parameters in each vector instruction.

4. The vector instruction recognition method as described in claim 3, characterized in that: The data type of the parameters in the vector instruction is constrained by the step size of the data type; wherein, When the data type is 1*1, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 0. When the data type is 1*n, its step size constraint is that the step size in the row dimension is 0 and the step size in the column dimension is 1. When the data type is m*1, its step size constraint is that the step size in the row dimension is 1 and the step size in the column dimension is 0. When the data type is m*n, its step size constraint is that the step size in the row dimension is max and the step size in the column dimension is 1; where max represents the maximum value that the register can represent.

5. The vector instruction recognition method as described in claim 1, characterized in that, The step of mapping the scalar instruction to a vector instruction according to the vector instruction dimension mapping rule and the instruction configuration table includes: Retrieve vector instructions from the instruction configuration table; Determine the data type of the parameters of the vector instruction; Retrieve the loop iteration variable from the scalar instruction; The loop iteration variable is mapped to the parameter of the vector instruction according to the data type of the parameter of the vector instruction.

6. The vector instruction recognition method as described in claim 5, characterized in that, The step of mapping the loop iteration variable to the parameters of the vector instruction according to the data type of the parameters of the vector instruction includes: A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables; The vector instruction dimension mapping rule corresponding to the data type of the parameter of the vector instruction is obtained. The loop iteration variable used to select the parameters of the vector instruction from the set of loop iteration variables; The selected loop iteration variables are mapped to the row and column dimensions of the parameters according to the vector instruction dimension mapping rules to obtain the set of loop iteration variables of the vector instruction parameters.

7. The vector instruction recognition method as described in claim 5, characterized in that, When the vector instruction is an instruction to eliminate loop iteration variables, mapping the loop iteration variables to the parameters of the vector instruction according to the data type of the parameters of the vector instruction includes: A set of loop iteration variables is generated based on the loop iteration variables in the scalar instruction and the step size of the loop iteration variables; Based on the data type of the input parameters of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the input parameters; Select the loop iteration variable used for the input parameter from the set of loop iteration variables; The loop iteration variables used by the selected input parameters are mapped to the row dimension and column dimension of the input parameters according to the vector instruction dimension mapping rule of the input parameters to obtain the set of loop iteration variables of the input parameters of the vector instruction. The set of iterative variables for all input parameters is merged to obtain the joint set of iterative variables for the input parameters; Based on the data type of the output parameter of the vector instruction, obtain the vector instruction dimension mapping rule corresponding to the data type of the output parameter; Select the loop iteration variable used by the output parameter from the joint set of loop iteration variables of the input parameters; The loop iteration variables used by the selected output parameters are mapped to the row and column dimensions of the output parameters according to the vector instruction dimension mapping rules of the output parameters, respectively, to obtain the set of loop iteration variables of the output parameters of the vector instruction.

8. The vector instruction recognition method as described in claim 6 or 7, characterized in that, The step of determining the validity of the vector instruction according to the vector instruction dimension validity rule includes: The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables of the parameters; or, The validity of the vector instruction is determined based on the dimension and step size of the loop iteration variables in the set of loop iteration variables for the output parameters and the dimension and step size of the loop iteration variables in the set of loop iteration variables for the input parameters.

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