Display panel and display device

Abstract

The present invention provides a display panel and a display device, which relate to the field of display technology. The display panel includes a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element; the pixel driving circuit includes a driving transistor and a first reset module; the driving transistor controls the driving current; the first reset module is connected to a first node, and the first reset module is used to provide a first reset voltage to the first node; the light-emitting element is connected to the first node; the display panel includes a first driving mode, and the display frame of the first driving mode includes a valid frame and an invalid frame; in the first driving mode, the first reset voltage of the valid frame is different from the first reset voltage of the invalid frame. The present invention provides a display panel and a display device to reduce the difference between the display brightness of the display panel at a low refresh rate and the display brightness at a high refresh rate, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Display panels use different refresh rates in different application scenarios. For example, a higher refresh rate is used to display dynamic images (such as sports events or gaming scenes) to ensure smooth display, while a lower refresh rate is used to display slow-motion images or static images to reduce power consumption. Switching between different refresh rates, such as switching from a higher refresh rate to a lower refresh rate or vice versa, can meet different display requirements.

[0003] However, there are differences in display brightness between different refresh rates, which causes the display brightness to be perceptible to the human eye when switching between different refresh rates, affecting the normal display of the display device and the user experience. Summary of the Invention

[0004] The present invention provides a display panel and a display device, so as to reduce the difference between the display brightness of the display panel at a low refresh rate and the display brightness at a high refresh rate, thereby improving the display effect of the display panel.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, comprising a light-emitting element and a pixel driving circuit electrically connected to the light-emitting element;

[0006] The pixel driving circuit includes a driving transistor and a first reset module;

[0007] The driving transistor controls the driving current;

[0008] The first reset module is connected to the first node, and the first reset module is used to provide a first reset voltage to the first node;

[0009] The light emitting element is connected to the first node;

[0010] The display panel includes a first driving mode, and the display frame of the first driving mode includes a valid frame and an invalid frame;

[0011] In the first driving mode, a first reset voltage of the valid frame is different from a first reset voltage of the invalid frame.

[0012] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel as described in the first aspect.

[0013] An embodiment of the present invention provides a display panel in which, in a first driving mode, a first reset voltage in an active frame differs from a first reset voltage in an inactive frame. That is, an electrode of a light-emitting element connected to a first node receives a different voltage in an active frame than in an inactive frame. Consequently, the embodiment of the present invention reduces the difference in brightness between the display panel at a low refresh rate and at a high refresh rate, thereby improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 A circuit diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0016] Figure 3 A timing diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0017] Figure 4 This is a data table of variable brightness at 16 gray levels;

[0018] Figure 5 This is a data table of variable brightness at 255 grayscale;

[0019] Figure 6 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0020] Figure 7 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0021] Figure 8 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0022] Figure 9 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0023] Figure 10 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0024] Figure 11 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0025] Figure 12 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0026] Figure 13 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0027] Figure 14A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0028] Figure 15 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0029] Figure 16 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0030] Figure 17 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0031] Figure 18 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0032] Figure 19 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0033] Figure 20 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0034] Figure 21 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0035] Figure 22 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0036] Figure 23 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0037] Figure 24 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0038] Figure 25 It is a timing brightness waveform diagram in the known technology;

[0039] Figure 26 A timing brightness waveform diagram after compensation provided by an embodiment of the present invention;

[0040] Figure 27 A circuit diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0041] Figure 28 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0042] Figure 29 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0044] When the display panel displays an image, there is leakage current in the transistors of the pixel driving circuit. As time accumulates, the brightness of the light-emitting diodes driven by the pixel driving circuit changes more and more, resulting in a difference between the display brightness of the display panel at a low refresh rate and the display brightness at a high refresh rate. When the display panel switches between low refresh rate and high refresh rate, the user can perceive the difference in display brightness of the display panel, affecting the visual effect of the display.

[0045] Figure 1 A schematic diagram of a display panel provided by an embodiment of the present invention is shown. Figure 2 A circuit diagram of a pixel driving circuit provided by an embodiment of the present invention is shown. Figure 3 A timing diagram of a pixel driving circuit provided by an embodiment of the present invention, referring to Figure 1 、 Figure 2 and Figure 3 , the display panel includes a light-emitting element 20 and a pixel driving circuit 10 electrically connected to the light-emitting element 20. The pixel driving circuit 10 includes a driving transistor T1 and a first reset module 11. The driving transistor T1 controls the driving current, which is used to control the luminous brightness of the light-emitting element 20. The first reset module 11 is connected to the first node N1, and the first reset module 11 is used to provide a first reset voltage VREF1 to the first node N1 to reset the first node N1. The light-emitting element 20 is connected to the first node N1, that is, the first reset module 11 is electrically connected to the light-emitting element 20. Among them, the first node N1 can be a physical connection point, or the first node N1 is a virtual connection point. The display panel includes a first driving mode, and the display frame of the first driving mode includes a valid frame and an invalid frame. In the first driving mode, the first reset voltage VREF1 of the valid frame is different from the first reset voltage VREF1 of the invalid frame.

[0046] For example, refer to Figure 2 and Figure 3 The control terminal of the first reset module 11 is electrically connected to the strobe scan signal control terminal sp. The first terminal of the first reset module 11 is connected to the first node N1. The second terminal of the first reset module 11 is electrically connected to the first reset voltage terminal vref1. When the strobe scan signal SP transmitted by the strobe scan signal control terminal sp controls the first reset module 11 to be turned on, the first reset voltage VREF1 of the first reset voltage terminal vref1 is transmitted to the first node N1.

[0047] The inventors of this application discovered that the transistor's performance in leakage current is inconsistent during the period when the pixel driving circuit drives the light-emitting element based on a high-grayscale data signal and during the period when the pixel circuit drives the light-emitting element based on a low-grayscale data signal. As a result, the difference between the display brightness of the pixel driving circuit based on the low-grayscale data signal at a low refresh rate and its display brightness at a high refresh rate is different from the difference between the display brightness of the pixel driving circuit based on the high-grayscale data signal at a low refresh rate and its display brightness at a high refresh rate. The difference between the display brightness of the pixel driving circuit based on the low-grayscale data signal at a low refresh rate and its display brightness at a high refresh rate is greater, resulting in a problem of variable frequency flicker.

[0048] It should be noted that the grayscale is divided based on the brightness of the light-emitting element. The larger the grayscale, the higher the brightness. The low grayscale and high grayscale in this application can be understood as relative concepts. For example, the brightness of the light-emitting element represented by the low grayscale is lower than the brightness of the light-emitting element represented by the high grayscale. The low grayscale and high grayscale in this application can be understood as absolute concepts. For example, taking 256 grayscales as an example, grayscales greater than 127 grayscales are considered high grayscales, and grayscales less than or equal to 127 are considered low grayscales, or grayscales greater than 63 grayscales are considered high grayscales, and grayscales less than or equal to 63 are considered low grayscales.

[0049] The pixel driving circuits in a display panel usually receive similar signals provided by the same signal line in units of an entire row or column. For example, the pixel driving circuits in an entire column are connected to the same data signal line to receive data signals, or the pixel driving circuits in an entire row are connected to the same scanning signal line to receive specific scanning signals, etc. Among the pixel driving circuits in an entire column / row, there may be pixel driving circuits that receive low-grayscale data signals and pixel driving circuits that receive high-grayscale data signals. Therefore, it is difficult to provide a corresponding brightness adjustment solution for a single pixel driving circuit individually and in real time based on whether the received data signal is high-grayscale or low-grayscale.

[0050] The inventors have found that the first reset voltage VREF1 has different effects on regulating the brightness of low grayscale and high grayscale. Therefore, by adjusting the first reset voltage VREF1, the brightness of low grayscale can be adjusted without affecting the brightness of high grayscale.

[0051] Figure 4 and Figure 5 The experimental data obtained by the inventor of this application, Figure 4 This is the data table of variable frequency brightness under 16 gray levels. Figure 5 This is a data table of variable brightness at 255 grayscale. Taking the brightness of 500nit as an example, Figure 4 and Figure 5The data obtained under the condition of 500 nit as the experimental parameter is shown: the corresponding relationship between brightness and grayscale is: 0 nit ~ 500 nit corresponds to 0 grayscale ~ 255 grayscale, Figure 4 The 16 gray levels are the 16 gray levels from 0 gray level to 255 gray levels. Figure 5 The grayscale 255 in the figure is the grayscale 255 among the grayscales 0 to 255, with grayscale 16 being an example of a low grayscale and grayscale 255 being an example of a high grayscale.

[0052] refer to Figure 4 Under 16 grayscales, at each first reset voltage VREF1, the frequency conversion brightness difference caused by the brightness difference at 40 Hz and 120 Hz is large. The frequency conversion brightness difference is 10.83% when VREF1 = -2V, 9.48% when VREF1 = -2.2V, 7.87% when VREF1 = -2.4V, 5.93% when VREF1 = -2.6V, 3.41% when VREF1 = -2.8V, 0.68% when VREF1 = -3V, 2.02% when VREF1 = -3.2V, and 4.54% when VREF1 = -3.4V. The variable frequency brightness difference is significantly affected by the fluctuation of the first reset voltage VREF1, which can bring substantial brightness changes to the brightness of low grayscale. For example, the variable frequency brightness difference corresponding to the flicker that can be perceived by the human eye is adjusted to a variable frequency brightness difference that cannot be perceived by the human eye, that is, adjusted to a compliant variable frequency brightness difference.

[0053] refer to Figure 5 At 255 grayscales, at each first reset voltage VREF1, the frequency conversion brightness difference caused by the brightness difference at 40 Hz and 120 Hz is small. The frequency conversion brightness difference is 0.67% when VREF1 = -2V, 0.63% when VREF1 = -2.2V, 0.61% when VREF1 = -2.4V, 0.55% when VREF1 = -2.6V, 0.52% when VREF1 = -2.8V, 0.5% when VREF1 = -3V, 0.46% when VREF1 = -3.2V, and 0.37% when VREF1 = -3.4V. The variable frequency brightness difference is less affected by the fluctuation of the first reset voltage VREF1. The variable rate brightness difference under each first reset voltage VREF1 is less than 2%. The display brightness difference when switching between different refresh rates is not perceptible to the human eye. Figure 4 Compared with the experimental data of FIG1 , under the same experimental conditions, the first reset voltage VREF1 has a smaller ability to adjust the brightness difference of high gray scale during frequency conversion.

[0054] pass Figure 4 and Figure 5 From the experimental data, it can be found that by adjusting the first reset voltage, the brightness of both low grayscale and high grayscale are affected. The basic brightness value of high grayscale is higher, and the brightness fluctuation caused by the change of the first reset voltage VREF1 is negligible relative to the basic brightness value of high grayscale; the basic brightness value of low grayscale is lower, and the brightness fluctuation caused by the change of the first reset voltage VREF1 is not negligible relative to the basic brightness value of low grayscale.

[0055] An embodiment of the present invention provides a display panel, in which, in a first driving mode, the first reset voltage VREF1 of the valid frame is different from the first reset voltage VREF1 of the invalid frame, that is, the first reset voltage VREF1 received by the light-emitting element 20 in the valid frame is different from the first reset voltage VREF1 received in the invalid frame. By adjusting the first reset voltage VREF1 of the invalid frame to be different from the first reset voltage VREF1 of the valid frame, the charging speed of the light-emitting element 20 is adjusted, the difference between the display brightness of the invalid frame and the display brightness of the valid frame at low grayscale is reduced, the difference between the display brightness of the low refresh rate at low grayscale and the display brightness of the high refresh rate at low grayscale is reduced, and the flicker problem of low grayscale during frequency switching is improved. The difference between the display brightness of the display panel at low refresh rate and the display brightness at high refresh rate is reduced, thereby improving the display effect of the display panel.

[0056] In the embodiment of the present invention, the valid frame includes a process of writing a data signal to the gate of the driving transistor, and the invalid frame does not include a process of writing a data signal to the gate of the driving transistor.

[0057] For example, refer to Figure 3 A display frame can be a valid frame or an invalid frame. A valid frame is a display frame in which a data signal is written, and an invalid frame is a display frame in which no data signal is written. The invalid frame drives the light emitting element 20 to emit light using the data signal written in the valid frame.

[0058] The display panel has a higher driving frequency at a high refresh rate and a lower driving frequency at a low refresh rate. The frequency of valid frames of the display panel at a high refresh rate is higher than the frequency of valid frames at a low refresh rate. One implementation is to reduce the frequency to an integer multiple of the base frequency (i.e., fundamental frequency) based on the fundamental frequency. Display frames at the fundamental frequency include valid frames. Display frames after the frequency is reduced based on the fundamental frequency include valid frames and invalid frames, where the frame duration of the valid frames and the frame duration of the invalid frames can be the same. In other words, the driving frequency is reduced by inserting invalid frames between adjacent valid frames, and the reduction factor of the driving frequency is changed by changing the number of invalid frames inserted between adjacent valid frames. For example, if the fundamental frequency is 120 Hz, the reduced frequency can be 60 Hz, 40 Hz, or 30 Hz, etc. In various embodiments of the present invention, switching between two driving frequencies can be switching between the fundamental frequency and a frequency reduced from the fundamental frequency, or switching between two frequencies reduced from the same fundamental frequency. Another implementation is to change the frame drive duration of the fundamental frequency display frame to achieve different fundamental frequencies. For example, the first base frequency is 120 Hz, and the second base frequency is 90 Hz. The frequency after the first base frequency is reduced can be 60 Hz, 40 Hz, or 30 Hz, and the frequency after the second base frequency is reduced can be 45 Hz, 30 Hz, etc. In various embodiments of the present invention, the switching between the two driving frequencies can also be switching between two base frequencies, or switching between two frequencies after frequency reduction based on two different base frequencies.

[0059] refer to Figure 3 , the first reset voltage VREF1 of the invalid frame is less than the first reset voltage VREF1 of the valid frame. In the embodiment of the present invention, the voltage value of the first reset voltage VREF1 in the invalid frame is lowered, the voltage value of the anode of the light-emitting element 20 (the anode of the light-emitting element 20 is connected to the first node N1, and the cathode of the light-emitting element 20 is connected to the second power supply terminal pvee) is reduced, and the brightness value of the light-emitting element 20 when receiving the first reset voltage VREF1 in the invalid frame is lowered, thereby suppressing the brightness increase of the light-emitting element 20 in the invalid frame, reducing the dark state brightness after frequency cutting, and lowering the display brightness of the low refresh rate at low grayscale, thereby reducing the difference between the display brightness of the high refresh rate at low grayscale and the display brightness of the low refresh rate at low grayscale. Among them, the dark state brightness is the display brightness of the display panel at low grayscale.

[0060] refer to Figure 3 The first reset voltage VREF1 of the valid frame includes a first voltage V100, and the first reset voltage of the invalid frame includes a second voltage V110. The difference between the second voltage V110 and the first voltage V100 is between 0.1V and 1V. That is, 0.1V≤(V110-V100)≤1V.

[0061] Furthermore, the difference between the second voltage V110 and the first voltage V100 can be reduced, and the difference between the second voltage V110 and the first voltage V100 does not exceed 0.2V, so as to limit the extent to which the display brightness at low grayscale and low refresh rate is lowered, and prevent the display brightness at low grayscale and low refresh rate from being excessively lowered.

[0062] Figure 6 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 6 The display frame of the first driving mode includes at least two invalid frames, and the first reset voltage VREF1 of the at least two invalid frames is the same. The two invalid frames with the same first reset voltage VREF1 are assigned the same voltage, thereby reducing the design requirements of the driving circuit in the display panel.

[0063] For example, refer to Figure 6 The at least two invalid frames include a first invalid frame and a second invalid frame. In terms of the driving order, the first invalid frame is located between the valid frame and the second invalid frame. The first reset voltage VREF1 of the first invalid frame is denoted as V111, and the first reset voltage VREF1 of the second invalid frame is denoted as V112, where V111=V112. Here, V111<V100, and V112<V100.

[0064] Optionally, in the first driving mode, the first reset voltages VREF1 of all invalid frames between two adjacent valid frames are the same, thereby reducing the design requirements of the driving circuit in the display panel.

[0065] Figure 7 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 7 The at least two invalid frames include a first invalid frame, a second invalid frame, and a third invalid frame. In terms of the driving order, the first invalid frame is located between the valid frame and the second invalid frame, and the second invalid frame is located between the first invalid frame and the third invalid frame. The first reset voltage VREF1 of the first invalid frame is recorded as V111, the first reset voltage VREF1 of the second invalid frame is recorded as V112, and the first reset voltage VREF1 of the third invalid frame is recorded as V113, where V111 = V112 = V113. Among them, V111 < V100, V112 < V100, and V113 < V100.

[0066] Figure 8 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 8 The display frame of the first driving mode includes at least two invalid frames, and the first reset voltages VREF1 of the at least two invalid frames are different.

[0067] For example, refer to Figure 8The at least two invalid frames include a first invalid frame and a second invalid frame. In terms of the driving order, the first invalid frame is located between the valid frame and the second invalid frame. The first reset voltage VREF1 of the first invalid frame is denoted as V111, and the first reset voltage VREF1 of the second invalid frame is denoted as V112. V111 and V112 are not equal.

[0068] Optionally, refer to Figure 8 , the first reset voltage VREF1 of the first invalid frame is recorded as V111, the first reset voltage VREF1 of the valid frame includes the first voltage V100, and the first reset voltage VREF1 of the second invalid frame is recorded as V112. V111<V100, V112<V111. The invalid frame drives the light-emitting element 20 to emit light using the data signal written in the valid frame, and no data signal is written in the invalid frame. The first invalid frame is the first display frame after the valid frame, and the second invalid frame is the second display frame after the valid frame. The time length from the second invalid frame to the valid frame is greater than the time length from the first invalid frame to the valid frame. As the time length accumulates, the leakage degree of the second invalid frame is greater than the leakage degree of the first invalid frame. For this reason, it is necessary to further lower the first reset voltage VREF1 of the second invalid frame and set the first reset voltage VREF1 of the second invalid frame to be lower than the first reset voltage VREF1 of the first invalid frame.

[0069] Optionally, refer to Figure 8 The difference between the first reset voltage VREF1 of the first invalid frame and the first reset voltage VREF1 of the valid frame is a first difference ΔV1, and the difference between the first reset voltage VREF1 of the second invalid frame and the first reset voltage VREF1 of the first invalid frame is a second difference ΔV2. The first difference ΔV1 and the second difference ΔV2 are equal. The voltage drop from the first reset voltage VREF1 of the valid frame to the first reset voltage VREF1 of the first invalid frame is the same as the voltage drop from the first reset voltage VREF1 of the first invalid frame to the first reset voltage VREF1 of the second invalid frame, thereby reducing the design requirements of the driving circuit in the display panel.

[0070] In other embodiments, as time goes by and as leakage continues, the leakage current of the transistor decreases. The voltage drop from the first reset voltage VREF1 of the valid frame to the first reset voltage VREF1 of the first invalid frame is larger, and the voltage drop from the first reset voltage VREF1 of the first invalid frame to the first reset voltage VREF1 of the second invalid frame is smaller, and the first difference ΔV1 is greater than the second difference ΔV2.

[0071] Figure 9 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 9The display frames of the first driving mode include at least three invalid frames, at least two of which have the same first reset voltage VREF1, and at least two of which have different first reset voltages VREF1. That is, among the invalid frames between two adjacent valid frames, a portion of the invalid frames have the same first reset voltage VREF1, and another portion of the invalid frames have different first reset voltages VREF1.

[0072] For example, refer to Figure 9 The at least three invalid frames include a first invalid frame, a second invalid frame, and a third invalid frame. In terms of the driving order, the first invalid frame is located between the valid frame and the second invalid frame, and the second invalid frame is located between the first invalid frame and the third invalid frame. The first reset voltage VREF1 of the first invalid frame is denoted as V111, the first reset voltage VREF1 of the second invalid frame is denoted as V112, and the first reset voltage VREF1 of the third invalid frame is denoted as V113. V112 < V111, V112 = V113.

[0073] Figure 10 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 10 The display frame of the first driving mode includes at least four invalid frames, at least two adjacent invalid frames form an invalid frame unit, the first reset voltage VREF1 of the invalid frames in the same invalid frame unit is the same, and the first reset voltage VREF1 of the invalid frames in different invalid frame units is different.

[0074] For example, refer to Figure 10 The at least four invalid frames include a first invalid frame, a second invalid frame, a third invalid frame, and a fourth invalid frame. In terms of the driving order, the first invalid frame is located between the valid frame and the second invalid frame, the second invalid frame is located between the first invalid frame and the third invalid frame, and the third invalid frame is located between the second invalid frame and the fourth invalid frame. The first reset voltage VREF1 of the first invalid frame is recorded as V111, the first reset voltage VREF1 of the second invalid frame is recorded as V112, the first reset voltage VREF1 of the third invalid frame is recorded as V113, and the first reset voltage VREF1 of the fourth invalid frame is recorded as V114. V111 = V112, V113 = V114, and V113 < V112. Among them, V111 < V100, V112 < V100, V113 < V100, and V114 < V100.

[0075] Optionally, between two adjacent valid frames, the first reset voltages VREF1 of any two invalid frames are different.

[0076] Figure 11 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 11The first reset voltage VREF1 of the first invalid frame is recorded as V111, the first reset voltage VREF1 of the second invalid frame is recorded as V112, and the first reset voltage VREF1 of the third invalid frame is recorded as V113. Any two of V111, V112 and V113 are different.

[0077] For example, refer to Figure 11 The first invalid frame is the first display frame after the valid frame, the second invalid frame is the second display frame after the valid frame, and the third invalid frame is the third display frame after the valid frame. The time length between the second invalid frame and the valid frame is greater than the time length between the first invalid frame and the valid frame, and the time length between the third invalid frame and the valid frame is greater than the time length between the second invalid frame and the valid frame. The leakage level of the third invalid frame is greater than the leakage level of the second invalid frame, and the leakage level of the second invalid frame is greater than the leakage level of the first invalid frame. Therefore, the first reset voltage VREF1 of the second invalid frame is set to be lower than the first reset voltage VREF1 of the first invalid frame, and the first reset voltage VREF1 of the third invalid frame is set to be lower than the first reset voltage VREF1 of the second invalid frame.

[0078] In some embodiments, the first reset voltage VREF1 of an invalid frame farther from a valid frame may be greater than the first reset voltage VREF1 of an invalid frame closer to a valid frame. In the embodiment of the present invention, the invalid frames compared are located between two adjacent valid frames.

[0079] Figure 12 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 12 The first reset voltage VREF1 of the first invalid frame is recorded as V111, and the first reset voltage VREF1 of the second invalid frame is recorded as V112, V111<V112.

[0080] Figure 13 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 13 , the first driving mode includes a first frequency driving mode and a second frequency driving mode, and the frequency of the valid frame of the first frequency driving mode is higher than the frequency of the valid frame of the second frequency driving mode. In the first frequency driving mode, the number of invalid frames inserted between two adjacent valid frames is small; in the second frequency driving mode, the number of invalid frames inserted between two adjacent valid frames is large. The first reset voltage VREF1 of the invalid frame of the first frequency driving mode is recorded as V120, and the first reset voltage VREF1 of the invalid frame of the second frequency driving mode is recorded as V130, and V120 is the same as V130. The first reset voltage VREF1 of the invalid frame of the first frequency driving mode is the same as the first reset voltage VREF1 of the invalid frame of the second frequency driving mode, thereby reducing the design requirements of the driving circuit in the display panel.

[0081] For example, refer to Figure 13 , the first frequency driving mode and the second frequency driving mode have the same basic frequency. The first frequency driving mode and the second frequency driving mode are achieved by reducing the frequency of the same basic frequency. Take the basic frequency of 120HZ as an example. The first frequency driving mode includes a valid frame, a first invalid frame, and a second invalid frame. Two invalid frames are inserted between two adjacent valid frames to reduce the frequency to one-third of the basic frequency. The driving frequency of the first frequency driving mode is 40HZ. The second frequency driving mode includes a valid frame, a first invalid frame, a second invalid frame, and a third invalid frame. Three invalid frames are inserted between two adjacent valid frames to reduce the frequency to one-quarter of the basic frequency. The driving frequency of the second frequency driving mode is 30HZ.

[0082] For example, refer to Figure 13 , the first reset voltage VREF1 of the first invalid frame of the first frequency driving mode is the same as the first reset voltage VREF1 of the second invalid frame of the first frequency driving mode. The first reset voltage VREF1 of the first invalid frame of the second frequency driving mode, the first reset voltage VREF1 of the second invalid frame of the second frequency driving mode, and the first reset voltage VREF1 of the third invalid frame of the second frequency driving mode are all the same. The first reset voltage VREF1 of the first invalid frame of the first frequency driving mode is the same as the first reset voltage VREF1 of the first invalid frame of the second frequency driving mode.

[0083] In other embodiments, the first frequency driving mode and the second frequency driving mode may have different base frequencies.

[0084] Figure 14 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 14 , V120>V130. The frequency of the valid frame of the first frequency driving mode is higher than the frequency of the valid frame of the second frequency driving mode. The proportion of the invalid frame of the second frequency driving mode is higher than the proportion of the invalid frame of the first frequency driving mode. The invalid frame drives the light-emitting element 20 to emit light using the data signal written in the valid frame, and no data signal is written in the invalid frame. Generally speaking, the leakage degree of the second frequency driving mode is greater than the leakage degree of the first frequency driving mode. For this reason, it is necessary to further lower the first reset voltage VREF1 of the second frequency driving mode, and set the first reset voltage VREF1 of the invalid frame of the first frequency driving mode to be greater than the first reset voltage VREF1 of the invalid frame of the second frequency driving mode.

[0085] For example, refer to Figure 14In the first frequency driving mode, the first reset voltage VREF1 of the first invalid frame and the first reset voltage VREF1 of the second invalid frame are the same. In the second frequency driving mode, the first reset voltage VREF1 of the first invalid frame, the first reset voltage VREF1 of the second invalid frame, and the first reset voltage VREF1 of the third invalid frame are all the same. The first reset voltage VREF1 of the first invalid frame in the first frequency driving mode is greater than the first reset voltage VREF1 of the first invalid frame in the second frequency driving mode.

[0086] In other embodiments, at least two of the invalid frames in the first frequency driving mode have different first reset voltages VREF1. At least two of the invalid frames in the second frequency driving mode have different first reset voltages VREF1.

[0087] Figure 15 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 15 , the first driving mode includes a first frequency driving mode and a second frequency driving mode, the frequency of the valid frame of the first frequency driving mode is higher than the frequency of the valid frame of the second frequency driving mode. The display frame of the first frequency driving mode includes at least one invalid frame, and the at least one invalid frame includes a first invalid frame. In the first frequency driving mode, the first reset voltage VREF1 of the first invalid frame is less than the first reset voltage VREF1 of the valid frame. The display frame of the second frequency driving mode includes at least two invalid frames, and the at least two invalid frames include a first invalid frame and a second invalid frame. In the driving order, the first invalid frame is located between the valid frame and the second invalid frame. In the second frequency driving mode, the first reset voltage VREF1 of the first invalid frame is less than the first reset voltage VREF1 of the valid frame, and the first reset voltage VREF1 of the second invalid frame is less than the first reset voltage VREF1 of the valid frame. The first reset voltage VREF1 of the first invalid frame in the first frequency driving mode is equal to the first reset voltage VREF1 of the first invalid frame in the second frequency driving mode.

[0088] For example, refer to Figure 15 The first reset voltage VREF1 of the active frame of the first frequency drive mode is the same as the first reset voltage VREF1 of the active frame of the second frequency drive mode. The first reset voltage VREF1 of the first inactive frame of the first frequency drive mode is the same as the first reset voltage VREF1 of the first inactive frame of the second frequency drive mode. The voltage drop from the active frame of the first frequency drive mode to the first inactive frame of the first frequency drive mode is the same as the voltage drop from the active frame of the second frequency drive mode to the first inactive frame of the second frequency drive mode, thereby reducing the design requirements of the driving circuit in the display panel.

[0089] For example, refer to Figure 15The display frame of the first frequency driving mode includes a first invalid frame and a second invalid frame, and the display frame of the second frequency driving mode includes a first invalid frame, a second invalid frame, and a third invalid frame. The first reset voltage VREF1 of the first invalid frame of the first frequency driving mode is equal to the first reset voltage VREF1 of the first invalid frame of the second frequency driving mode, and the first reset voltage VREF1 of the second invalid frame of the first frequency driving mode is equal to the first reset voltage VREF1 of the second invalid frame of the second frequency driving mode.

[0090] Figure 16 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 16 The display frame includes a first baseband display frame and a second baseband display frame. The frame drive duration of the first baseband display frame is S1, and the frame drive duration of the second baseband display frame is S2, where S1 < S2. The first reset voltage VREF1 of an inactive frame using the first drive mode of the first baseband display frame is the same as the first reset voltage VREF1 of an inactive frame using the first drive mode of the second baseband display frame. This reduces the design requirements for the driver circuit in the display panel.

[0091] For example, reference Figure 16 The first reset voltage VREF1 of the valid frame of the first driving mode in the first baseband display frame is the same as the first reset voltage VREF1 of the valid frame of the first driving mode in the second baseband display frame, thereby reducing the design requirements of the driving circuit in the display panel.

[0092] Figure 17 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 17 The display frame includes a first baseband display frame and a second baseband display frame. The frame drive duration of the first baseband display frame is S1, and the frame drive duration of the second baseband display frame is S2, where S1 < S2. The first reset voltage VREF1 of an inactive frame using the first drive mode of the first baseband display frame is greater than the first reset voltage VREF1 of an inactive frame using the first drive mode of the second baseband display frame. The frame drive duration of the first baseband display frame is less than the frame drive duration of the second baseband display frame. The frequency of active frames using the first drive mode of the first baseband display frame is greater than the frequency of active frames using the first drive mode of the second baseband display frame. Overall, the leakage level of the first drive mode of the second baseband display frame is greater than the leakage level of the first drive mode of the first baseband display frame. Therefore, it is necessary to further lower the first reset voltage VREF1 of the first drive mode of the second baseband display frame and set the first reset voltage VREF1 of the inactive frame using the first drive mode of the first baseband display frame to be greater than the first reset voltage VREF1 of the inactive frame using the first drive mode of the second baseband display frame.

[0093] Figure 18 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 and Figure 18 , the pixel driving circuit 10 also includes a second reset module 12. The second reset module 12 is connected to the second node N2, and the second reset module 12 is used to provide the second reset voltage VREF2 to the second node N2 to reset the second node N2. The gate of the driving transistor T1 is connected to the second node N2. The second node N2 can be a physical connection point, or the second node N2 is a virtual connection point. The display panel also includes a second driving mode, and the display frame of the second driving mode includes a valid frame. The frequency of the valid frame of the second driving mode is higher than the frequency of the valid frame of the first driving mode. The driving frequency in the second driving mode is the base frequency, and the driving frequency in the first driving mode is the frequency after the base frequency is reduced. The second reset voltage VREF2 of the valid frame of the first driving mode is less than the second reset voltage VREF2 of the valid frame of the second driving mode. In an embodiment of the present invention, the first driving mode includes an invalid frame, and the second driving mode does not include an invalid frame.

[0094] As time accumulates, the problem caused by leakage current becomes more prominent. For the same gray scale, the brightness of the light-emitting element in the first driving mode is lower than the brightness of the light-emitting element in the second driving mode. The brightness of the light-emitting element in the first driving mode needs to be compensated to improve the flicker problem of the display panel during frequency switching.

[0095] In one embodiment, a lower second reset voltage VREF2 can be provided for the first driving mode, the voltage value of the second reset voltage VREF2 in the first driving mode can be lowered, the voltage value of the gate of the driving transistor T1 (connected to the second node N2) can be reduced, the charging speed of writing the data signal to the gate of the driving transistor T1 can be increased, and the luminous brightness of the light-emitting element 20 can be increased to compensate for the display brightness of the display panel at a low refresh rate and reduce the difference between the display brightness at a high refresh rate and the display brightness at a low refresh rate.

[0096] In other embodiments, the second reset voltage VREF2 of the valid frame of the first driving mode is equal to the second reset voltage VREF2 of the valid frame of the second driving mode, and brightness compensation of the light-emitting element in the first driving mode (low refresh rate) can be achieved by other means.

[0097] Because the degree of transistor leakage current varies at different grayscales, for example, the degree of transistor leakage current at high grayscales is greater than that at low grayscales. Without brightness compensation in the first driving mode, the brightness of a light-emitting element driven by a data signal at a low grayscale decreases less, while the brightness of a light-emitting element driven by a data signal at a high grayscale decreases more. Because flicker caused by high grayscales is more likely to deteriorate the display effect, when compensating the brightness of the light-emitting element in the first driving mode, greater attention is paid to improving the brightness of high grayscales than the brightness difference at low grayscales during switching frequencies. If the compensation standard is to meet the brightness compensation for high grayscales, the brightness of low grayscales will often be overcompensated. By setting the first reset voltage VREF1 of the active frame to be different from the first reset voltage VREF1 of the inactive frame in the first driving mode, the brightness of the low grayscales in the first driving mode is "fine-tuned." This ensures that the performance of the light-emitting element at both high and low grayscales meets display requirements, thereby improving the flicker problem of the light-emitting element at both high and low grayscales during switching frequencies.

[0098] Figure 19 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 and Figure 19 , the pixel driving circuit 10 also includes a second reset module 12. The second reset module 12 is connected to the second node N2, and the second reset module 12 is used to provide the second reset voltage VREF2 to the second node N2 to reset the second node N2. The gate of the driving transistor T1 is connected to the second node N2. The display panel also includes a second driving mode, and the display frame of the second driving mode includes a valid frame. The frequency of the valid frame of the second driving mode is higher than the frequency of the valid frame of the first driving mode. The first reset voltage VREF1 of the valid frame of the first driving mode is the same as the first reset voltage VREF1 of the valid frame of the second driving mode. After the second driving mode reduces the driving frequency and switches to the first driving mode, there is no need to change the voltage value of the first reset voltage VREF1 in the valid frame of the first driving mode, thereby reducing the design requirements of the driving circuit in the display panel.

[0099] For example, refer to Figure 2 The control terminal of the second reset module 12 is electrically connected to the first scan signal control terminal sn1. The first terminal of the second reset module 12 is connected to the second node N2, and the gate of the driving transistor T1 is connected to the second node N2. The second terminal of the second reset module 12 is electrically connected to the second reset voltage terminal vref2. When the first scan signal SN1 transmitted by the first scan signal control terminal sn1 controls the second reset module 12 to be turned on, the second reset voltage VREF2 of the second reset voltage terminal vref2 is transmitted to the second node N2.

[0100] Figure 20 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 and Figure 20 The pixel driving circuit 10 further includes a data writing transistor T3, which is connected to a third node N3, and a first electrode of the driving transistor T1 is connected to the third node N3. The third node N3 may be a physical connection point, or the third node N3 may be a virtual connection point. In a valid frame, the data writing transistor T3 provides a data signal DATA to the third node N3, the driving transistor T1 is turned on, and the data voltage corresponding to the data signal DATA is written to the first node N1. In an invalid frame, the data writing transistor T3 provides an adjustment voltage VAJ to the third node N3. In an embodiment of the present invention, by providing the adjustment voltage VAJ to the third node N3 in an invalid frame, the difference between the bias state of the driving transistor T1 in the invalid frame and the bias state of the driving transistor T1 in the valid frame is reduced, the display brightness at a low refresh rate is reduced, the difference between the display brightness of the display panel at a low refresh rate and the display brightness at a high refresh rate is reduced, and the display effect of the display panel is improved.

[0101] For example, the voltage of the data signal DATA is the data voltage required for displaying different grayscales, which is pre-set in the display panel. The lower the grayscale, the larger the corresponding data signal DATA voltage, while the higher the grayscale, the smaller the corresponding data signal DATA voltage. The voltage of the data signal DATA is a positive voltage.

[0102] Figure 21 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 21 The display frame of the first driving mode includes at least two invalid frames, and the adjustment voltage VAJ of the at least two invalid frames is the same. The two invalid frames with the same adjustment voltage VAJ are assigned the same voltage, thereby reducing the design requirements of the driving circuit in the display panel.

[0103] For example, refer to Figure 21 The at least two invalid frames include a first invalid frame and a second invalid frame. In the driving order, the first invalid frame is located between the valid frame and the second invalid frame. The adjustment voltage VAJ of the first invalid frame is recorded as V141, and the adjustment voltage VAJ of the second invalid frame is recorded as V142, where V141=V142.

[0104] Optionally, in the first driving mode, the adjustment voltages VAJ of all invalid frames between two adjacent valid frames are the same, thereby reducing the design requirements of the driving circuit in the display panel.

[0105] Figure 22 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 22The display frame of the first driving mode includes at least two invalid frames, and the at least two invalid frames include a first invalid frame and a second invalid frame. In terms of the driving order, the first invalid frame is located between the valid frame and the second invalid frame. The adjustment voltage VAJ of the first invalid frame is recorded as V141, and the adjustment voltage VAJ of the second invalid frame is recorded as V142, and V141 < V142. The invalid frame drives the light-emitting element 20 to emit light using the data signal written in the valid frame, and no data signal is written in the invalid frame. The first invalid frame is the first display frame after the valid frame, and the second invalid frame is the second display frame after the valid frame. The time length from the second invalid frame to the valid frame is greater than the time length from the first invalid frame to the valid frame. The leakage degree of the second invalid frame is greater than the leakage degree of the first invalid frame. For this reason, it is necessary to further increase the adjustment voltage VAJ of the second invalid frame, and set the adjustment voltage VAJ of the first invalid frame to be less than the adjustment voltage VAJ of the second invalid frame.

[0106] Optionally, in the first driving mode, the adjustment voltages VAJ of any two invalid frames between two adjacent valid frames are different.

[0107] Optionally, refer to Figure 22 , the adjustment voltage VAJ is greater than or equal to the minimum value of the data signal DATA, and the adjustment voltage VAJ provided to the third node N3 in the invalid frame reduces the difference between the bias state of the driving transistor T1 in the invalid frame and the bias state of the driving transistor T1 in the valid frame, thereby reducing the display brightness at a low refresh rate.

[0108] Exemplarily, in one embodiment, the adjustment voltage VAJ is greater than or equal to the minimum value of the data signal DATA, and less than or equal to the maximum value of the data signal DATA.

[0109] Exemplarily, in another embodiment, the adjustment voltage VAJ is greater than or equal to the maximum value of the data signal DATA.

[0110] For example, the adjustment voltage VAJ can be selected to have a constant voltage. By setting the adjustment voltage VAJ to a constant voltage, when the display panel operates in an inactive frame, the driving circuit provides a constant voltage to the data voltage terminal data, which can simplify the working mode of the driving circuit.

[0111] Figure 23 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 2 and Figure 23The pixel driving circuit 10 further includes a compensation transistor T4, which is used to compensate for the threshold voltage of the driving transistor T1. During an active frame, the compensation transistor T4 includes an on-period. During the on-period, when the compensation transistor T4 is on, the gate electrode of the driving transistor T1 is electrically connected to the second electrode of the driving transistor T1. During an inactive frame, the compensation transistor T4 remains off.

[0112] Optionally, refer to Figure 2 The first reset module 11 includes a first reset transistor T7, the gate of which is electrically connected to the strobe scan signal control terminal sp, the first electrode of which is connected to the first node N1, and the second electrode of which is electrically connected to the first reset voltage terminal vref1. The display panel also includes a second reset module 12, a data write transistor T3, a compensation transistor T4, a power write transistor T5, and a light emission control transistor T6. The second reset module 12 includes a second reset transistor T2. The gate of the second reset transistor T2 is electrically connected to the first scan signal control terminal sn1, the first electrode of the second reset transistor T2 is connected to the second node N2, the gate of the driving transistor T1 is connected to the second node N2, and the second electrode of the second reset transistor T2 is electrically connected to the second reset voltage terminal vref2. The gate of the data write transistor T3 is electrically connected to the strobe scan signal control terminal sp, the first electrode of the data write transistor T3 is connected to the third node N3, and the first electrode of the driving transistor T1 is connected to the third node N3. The second electrode of the data write transistor T3 is electrically connected to the data voltage terminal data. The gate of the power write transistor T5 is electrically connected to the emission signal control terminal em. The first electrode of the power write transistor T5 is connected to the third node N3, and the second electrode of the power write transistor T5 is electrically connected to the first power supply terminal pvdd. When the emission signal EM transmitted by the emission signal control terminal em controls the power write transistor T5 to conduct, the first power supply voltage of the first power supply terminal pvdd is transmitted to the third node N3. The gate of the emission control transistor T6 is electrically connected to the emission signal control terminal em. The first electrode of the emission control transistor T6 is electrically connected to the second electrode of the drive transistor T1, and the second electrode of the emission control transistor T6 is connected to the first node N1. The gate of the compensation transistor T4 is electrically connected to the second scan signal control terminal sn2. The first electrode of the compensation transistor T4 is connected to the second node N2, and the second electrode of the compensation transistor T4 is electrically connected to the second electrode of the drive transistor T1. When the second scan signal SN2 transmitted by the second scan signal control terminal sn2 controls the compensation transistor T4 to conduct, the gate of the drive transistor T1 is connected to the second electrode of the drive transistor T1.

[0113] For example, refer to Figure 2The pixel driving circuit 10 further includes a storage capacitor cst, a first plate of the storage capacitor cst is electrically connected to the first power supply terminal pvdd, and a second plate of the storage capacitor cst is connected to the second node N2 for maintaining the voltage of the second node N2.

[0114] For example, refer to Figure 2 and Figure 23 Taking the transistors in the pixel driving circuit 10 as P-type transistors as an example, the working process of the display panel includes a valid frame and an invalid frame.

[0115] During an active frame, the pixel drive circuit executes a first period P1, a second period P2, and a third period P3. The first period P1 precedes the second period P2, which in turn precedes the third period P3. The second period P2 includes a fourth period P4. During the first period P1, the emission signal EM is high, the first scan signal SN1 is low, the second scan signal SN2 is high, and the selection scan signal SP is high. The power write transistor T5 and the emission control transistor T6 are turned off. The second reset transistor T2 is turned on, transmitting the second reset voltage VREF2 from the second reset voltage terminal vref2 to the second node N2, resetting the gate of the drive transistor T1. This ensures that the display panel can write accurate data voltages to the gate of the drive transistor T1 during an active frame. The compensation transistor T4 is turned off. The data write transistor T3 and the first reset transistor T7 are turned off. During the second period P2, the emission signal EM is high, the first scan signal SN1 is high, and the second scan signal SN2 is low. The power write transistor T5 and the emission control transistor T6 are turned off. The second reset transistor T2 is turned off. Compensation transistor T4 is turned on, connecting the gate of drive transistor T1 to the second electrode of drive transistor T1. During a fourth period P4 within second period P2, the strobe scan signal SP is low, the data write transistor T3 is turned on, and the data signal DATA is transmitted to the third node N3. Drive transistor T1 and compensation transistor T4 are turned on, and the data signal DATA at third node N3 is transmitted to second node N2 via drive transistor T1 and compensation transistor T4, whereupon the data voltage is written to second node N2. First reset transistor T7 is turned on, transmitting a first reset voltage VREF1 from a first reset voltage terminal vref1 to first node N1, resetting the anode of light-emitting element 20. First reset voltage VREF1 is the first voltage V100. During third period P3, emission signal EM is low, first scan signal SN1 is high, second scan signal SN2 is high, and strobe scan signal SP is high. Power write transistor T5 and emission control transistor T6 are turned on, supplying the drive current generated by drive transistor T1 to light-emitting element 20, thereby controlling the brightness of light-emitting element 20. Second reset transistor T2 is turned off. The compensation transistor T4 is turned off, and the data writing transistor T3 and the first reset transistor T7 are turned off.

[0116] During the inactive frame, the pixel drive circuit executes the fourth period P4 and the third period P3. The third period P3 follows the fourth period P4. During the fourth period P4, the light-emitting signal EM is at a high level, the first scan signal SN1 is at a high level, and the second scan signal SN2 is at a low level. The selection scan signal SP is at a low level. The power write transistor T5 and the light-emitting control transistor T6 are turned off. The second reset transistor T2 is turned off. The compensation transistor T4 is turned on, connecting the gate of the drive transistor T1 to the second electrode of the drive transistor T1. The data write transistor T3 is turned on, transmitting the adjustment voltage VAJ to the third node N3, reducing the difference between the bias state of the drive transistor T1 in the inactive frame and the bias state of the drive transistor T1 in the active frame. The first reset transistor T7 is turned on, transmitting the first reset voltage VREF1 from the first reset voltage terminal vref1 to the first node N1, resetting the anode of the light-emitting element 20. The first reset voltage is the second voltage V110, which is less than the first voltage V100. The display brightness at low grayscale and low refresh rate is lowered, reducing the difference between the display brightness at low grayscale and high refresh rate and the display brightness at low grayscale and low refresh rate. The operation process of the pixel driving circuit in the third period P3 of the invalid frame is the same as that in the third period P3 of the valid frame, and will not be repeated here.

[0117] For example, refer to Figure 23 Each display frame includes a third period P3, that is, a light-emitting stage. In other embodiments, each display frame may further include multiple third periods P3.

[0118] Figure 24 A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 24 The display panel has a lower display brightness at a low grayscale, also known as a dark state display. In order to improve the uniformity of the display, a plurality of third time periods P3 may be set in each display frame.

[0119] For example, refer to Figure 24 The valid frame includes a first period P1, a second period P2, and three third periods P3. The second period P2 is located after the first period P1, and the three third periods P3 are all located after the second period P2. The second period P2 includes a fourth period P4. The invalid frame includes the fourth period P4 and the three third periods P3. The three third periods P3 are all located after the fourth period P4.

[0120] Figure 25 The timing brightness waveform diagram in the known technology is combined with reference to Figure 24 and Figure 25, the brightness in the vertical axis is the relative brightness value. Each frame (including valid frames and invalid frames, invalid frames include the first invalid frame and the second invalid frame) sets three third time periods P3 to form three brightness peaks. Figure 25 In the figure, in the valid frame, the position pointed to by ① indicates the first brightness valley value of the valid frame. In the first invalid frame, the position pointed to by ② indicates the first brightness valley value of the first invalid frame. In the second invalid frame, the position pointed to by ③ indicates the first brightness valley value of the second invalid frame. The first brightness valley value of the first invalid frame is greater than the first brightness valley value of the valid frame, and the first brightness valley value of the second invalid frame is greater than the first brightness valley value of the valid frame. The first brightness valley value of the invalid frame is significantly increased relative to the brightness valley value of the valid frame, resulting in the display brightness of the high refresh rate at low grayscale being lower than the display brightness of the low refresh rate at low grayscale.

[0121] Figure 26 The compensation time sequence brightness waveform diagram provided by the embodiment of the present invention is shown in FIG. Figure 26 By setting the first reset voltage VREF1 of the valid frame to be different from the first reset voltage VREF1 of the invalid frame, Figure 26 In the example, the first brightness valley value of the first invalid frame is substantially the same as the first brightness valley value of the valid frame, and the first brightness valley value of the second invalid frame is substantially the same as the first brightness valley value of the valid frame. This reduces the difference in display brightness at low grayscale and low refresh rate and at high refresh rate. This reduces the difference in display brightness between the display panel at low refresh rate and high refresh rate, thereby improving the display quality of the display panel.

[0122] For example, refer to Figure 2 , the driving transistor T1 is a P-type transistor.

[0123] In other embodiments, the driving transistor T1 may be an N-type transistor. Accordingly, the voltage fluctuation direction of the first reset voltage VREF1 is opposite to that when the driving transistor T1 is a P-type transistor. The voltage fluctuation direction of the adjustment voltage VAJ is opposite to that when the driving transistor T1 is a P-type transistor. The voltage fluctuation direction of the second reset voltage VREF2 is opposite to that when the driving transistor T1 is a P-type transistor.

[0124] It should be noted that in some timing diagrams, in order to highlight the changing rules of the signals, the schematic diagrams of other signals of the pixel driving circuit are omitted. For details, please refer to Figure 3 、 Figure 23 and Figure 24 Detailed instructions in .

[0125] Figure 27 A circuit diagram of another pixel driving circuit provided by an embodiment of the present invention is shown. Figure 28A timing diagram of another pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 27 and Figure 28 The driving transistor T1 is an N-type transistor, and the first reset voltage VREF1 of the inactive frame is greater than the first reset voltage VREF1 of the active frame. In this embodiment of the present invention, secondary compensation is used to reduce the display brightness at low grayscales and low refresh rates, thereby reducing the difference between the display brightness at low grayscales and high refresh rates and the display brightness at low grayscales and low refresh rates. The dark state brightness refers to the display brightness of the display panel at low grayscales.

[0126] An embodiment of the present invention further provides a display device. Figure 29 A schematic diagram of a display device provided by an embodiment of the present invention, see Figure 29 The display device includes any one of the display panels provided in the embodiments of the present invention. The display device can specifically be a mobile phone, a tablet computer, a smart wearable device, etc.

[0127] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: comprising a light emitting element and a pixel driving circuit electrically connected to the light emitting element; The pixel driving circuit includes a driving transistor and a first reset module; The driving transistor controls the driving current; The first reset module is connected to the first node, and the first reset module is used to provide a first reset voltage to the first node; The light emitting element is connected to the first node; The display panel includes a first driving mode, and the display frame of the first driving mode includes a valid frame and an invalid frame; In the first driving mode, the first reset voltage of the valid frame is different from the first reset voltage of the invalid frame; The pixel driving circuit further includes a second reset module, the second reset module is connected to the second node, and the second reset module is used to provide a second reset voltage to the second node; The gate of the driving transistor is connected to the second node; The display panel further includes a second driving mode, wherein a display frame of the second driving mode consists of the valid frames, and a frequency of the valid frames of the second driving mode is higher than a frequency of the valid frames of the first driving mode; The second reset voltage of the valid frame of the first driving mode is lower than the second reset voltage of the valid frame of the second driving mode.

2. The display panel according to claim 1, wherein: The first reset voltage of the invalid frame is lower than the first reset voltage of the valid frame.

3. The display panel according to claim 1, wherein: The first reset voltage of the valid frame includes a first voltage, and the first reset voltage of the invalid frame includes a second voltage. The difference between the second voltage and the first voltage is between 0.1V and 1V.

4. The display panel according to claim 1, wherein: The display frame of the first driving mode includes at least two invalid frames, and the first reset voltage of at least two invalid frames is the same.

5. The display panel according to claim 1, wherein: The display frame of the first driving mode includes at least two invalid frames, and the first reset voltages of the at least two invalid frames are different.

6. The display panel according to claim 5, wherein: At least two frames of invalid frames include a first invalid frame and a second invalid frame. In terms of driving sequence, the first invalid frame is located between the valid frame and the second invalid frame. The first reset voltage of the first invalid frame is less than the first reset voltage of the valid frame, and the first reset voltage of the second invalid frame is less than the first reset voltage of the first invalid frame.

7. The display panel according to claim 6, wherein: The difference between the first reset voltage of the first invalid frame and the first reset voltage of the valid frame is a first difference, the difference between the first reset voltage of the second invalid frame and the first reset voltage of the first invalid frame is a second difference, the first difference is equal to the second difference, or the first difference is greater than the second difference.

8. The display panel according to claim 1, wherein: The first driving mode includes a first frequency driving mode and a second frequency driving mode, wherein the frequency of the effective frame of the first frequency driving mode is higher than the frequency of the effective frame of the second frequency driving mode; The first reset voltage of the inactive frame of the first frequency driving mode is the same as the first reset voltage of the inactive frame of the second frequency driving mode.

9. The display panel according to claim 1, wherein: The first driving mode includes a first frequency driving mode and a second frequency driving mode, wherein the frequency of the effective frame of the first frequency driving mode is higher than the frequency of the effective frame of the second frequency driving mode; The first reset voltage of the inactive frame of the first frequency driving mode is greater than the first reset voltage of the inactive frame of the second frequency driving mode.

10. The display panel according to claim 1, wherein The first driving mode includes a first frequency driving mode and a second frequency driving mode, wherein the frequency of the effective frame of the first frequency driving mode is higher than the frequency of the effective frame of the second frequency driving mode; The display frame of the first frequency driving mode includes at least one invalid frame, the at least one invalid frame includes a first invalid frame, and in the first frequency driving mode, a first reset voltage of the first invalid frame is lower than a first reset voltage of the valid frame; The display frame of the second frequency driving mode includes at least two invalid frames, the at least two invalid frames include a first invalid frame and a second invalid frame, and in a driving order, the first invalid frame is located between the valid frame and the second invalid frame; in the second frequency driving mode, a first reset voltage of the first invalid frame is lower than a first reset voltage of the valid frame, and a first reset voltage of the second invalid frame is lower than the first reset voltage of the valid frame; The first reset voltage of the first inactive frame of the first frequency driving mode is equal to the first reset voltage of the first inactive frame of the second frequency driving mode.

11. The display panel according to claim 1, wherein The display frame includes a first baseband display frame and a second baseband display frame, wherein a frame driving duration of the first baseband display frame is shorter than a frame driving duration of the second baseband display frame; The first reset voltage of the inactive frame of the first driving mode using the first fundamental frequency display frame is the same as the first reset voltage of the inactive frame of the first driving mode using the second fundamental frequency display frame.

12. The display panel according to claim 1, wherein The display frame includes a first baseband display frame and a second baseband display frame, wherein a frame driving duration of the first baseband display frame is shorter than a frame driving duration of the second baseband display frame; The first reset voltage of the inactive frame of the first driving mode using the first baseband display frame is greater than the first reset voltage of the inactive frame of the first driving mode using the second baseband display frame.

13. The display panel according to claim 1, wherein The pixel driving circuit further includes a data writing transistor, wherein the data writing transistor is connected to a third node, and the first electrode of the driving transistor is connected to the third node; In the valid frame, the data writing transistor provides a data signal to the third node; In the inactive frame, the data write transistor provides a regulated voltage to the third node.

14. The display panel according to claim 13, wherein: The display frame of the first driving mode includes at least two invalid frames, and the adjustment voltages of the at least two invalid frames are the same.

15. The display panel according to claim 13, wherein: The display frame of the first driving mode includes at least two invalid frames, and the at least two invalid frames include a first invalid frame and a second invalid frame. In terms of driving sequence, the first invalid frame is located between the valid frame and the second invalid frame, and the adjustment voltage of the first invalid frame is less than the adjustment voltage of the second invalid frame.

16. The display panel according to claim 13, wherein: The regulated voltage is greater than or equal to a minimum value of the data signal.

17. The display panel according to claim 1, wherein: The pixel driving circuit further includes a compensation transistor, wherein the compensation transistor is used to compensate for the threshold voltage of the driving transistor; In the active frame, the compensation transistor includes a turn-on period, and in the inactive frame, the compensation transistor maintains a turn-off state.

18. The display panel according to claim 1, wherein The first reset module includes a first reset transistor, a gate of the first reset transistor is electrically connected to the strobe scan signal control terminal, a first electrode of the first reset transistor is connected to the first node, and a second electrode of the first reset transistor is electrically connected to the first reset voltage terminal; The second reset module includes a second reset transistor, a gate of the second reset transistor is electrically connected to the first scan signal control terminal, a first electrode of the second reset transistor is connected to the second node, and a second electrode of the second reset transistor is electrically connected to the second reset voltage terminal; The pixel driving circuit further includes: a data writing transistor, wherein a gate of the data writing transistor is electrically connected to the strobe scan signal control terminal, a first electrode of the data writing transistor is connected to a third node, and a first electrode of the driving transistor is connected to the third node; and a second electrode of the data writing transistor is electrically connected to a data voltage terminal; a power write transistor, wherein a gate of the power write transistor is electrically connected to the light emitting signal control terminal, a first electrode of the power write transistor is connected to the third node, and a second electrode of the power write transistor is electrically connected to the first power supply terminal; a light emitting control transistor, wherein a gate of the light emitting control transistor is electrically connected to the light emitting signal control terminal, a first electrode of the light emitting control transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the light emitting control transistor is connected to the first node; A compensation transistor, wherein a gate of the compensation transistor is electrically connected to the second scan signal control terminal, a first electrode of the compensation transistor is connected to the second node, and a second electrode of the compensation transistor is electrically connected to the second electrode of the driving transistor.

19. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 18.

Images