Memory and method of forming the same
By forming alternating stacks of interlayer spacers and sacrificial layers in DRAM memory, and replacing the sacrificial layers with active pillars and word lines, the problems of complex manufacturing processes and low yields are solved, achieving simplified manufacturing and improved performance of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-21
- Publication Date
- 2026-07-24
AI Technical Summary
Existing DRAM memory manufacturing processes are complex and have low yield rates. As the size shrinks, stress increases, leading to greater process difficulty.
The stacking process employs alternating layers of interlayer spacers and sacrificial layers, replacing the sacrificial layers with active pillars and word lines, which simplifies the manufacturing process, reduces internal stress, and improves storage capacity and yield.
It simplifies the memory manufacturing process, improves memory yield and electrical performance, reduces the contact resistance between transistors and capacitors, and enhances memory stability and performance.
Smart Images
Figure CN115188714B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more particularly to a memory and a method for forming the same. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.
[0003] For memory devices such as DRAM, the pursuit has always been for faster response times, lower power consumption, and higher storage density. As the size of memory devices such as DRAM continues to shrink, the difficulty of memory manufacturing processes is constantly increasing, and the stress inside the memory is also constantly increasing, thereby reducing the yield of memory devices.
[0004] Therefore, simplifying the manufacturing process of memory and improving memory yield are urgent technical problems that need to be solved. Summary of the Invention
[0005] This disclosure provides some embodiments of the memory and the method for forming the memory, which are used to simplify the memory manufacturing process and improve the memory yield.
[0006] According to some embodiments, this disclosure provides a method for forming a memory, including the following steps:
[0007] A stacked layer is formed on the surface of a substrate. The stacked layer includes interlayer isolation layers spaced apart along a first direction and a group of sacrificial layers located between adjacent interlayer isolation layers. The group of sacrificial layers includes a first sacrificial layer, a second sacrificial layer and a third sacrificial layer stacked sequentially along the first direction. The stacked layer includes a transistor region. The first direction is a direction perpendicular to the top surface of the substrate.
[0008] Remove the first sacrificial layer in the transistor region to form a first void;
[0009] An active column is formed within the first gap;
[0010] The second and third sacrificial layers in the transistor region are removed to form a second void;
[0011] A word line covering a portion of the active column is formed within the second gap.
[0012] In some embodiments, the first sacrificial layer is made of a low dielectric constant material, the second sacrificial layer is made of undoped polycrystalline silicon, and the third sacrificial layer is made of silicon dioxide.
[0013] In some embodiments, the stacked layer further includes a capacitor region located on one side of the transistor region; before forming the first gap, the following steps are also included:
[0014] Remove the sacrificial layer group in the capacitor region to form a third gap;
[0015] A capacitor is formed within the third gap.
[0016] In some embodiments, the specific steps for forming the third gap include:
[0017] Remove all of the second sacrificial layer, a portion of the first sacrificial layer, and a portion of the third sacrificial layer from the capacitor region to form a first trench between the remaining first sacrificial layer and the remaining third sacrificial layer, and a third gap between adjacent interlayer isolation layers and communicating with the first trench.
[0018] A first isolation layer is formed that fills the first trench.
[0019] In some embodiments, the specific steps of forming a capacitor within the third gap include:
[0020] Remove a portion of the first sacrificial layer below the first isolation layer to form a second trench communicating with the third gap;
[0021] A lower electrode layer is formed that fills the second trench and covers the inner wall of the third gap;
[0022] A dielectric layer is formed covering the surface of the lower electrode layer;
[0023] An upper electrode layer is formed covering the surface of the dielectric layer.
[0024] In some embodiments, the stacked layer further includes bit line regions, the capacitor regions and the bit line regions are distributed on opposite sides of the transistor regions along a second direction, the second direction being a direction parallel to the top surface of the substrate; the specific steps for forming the first gap include:
[0025] The first sacrificial layer of the bit line region and the transistor region is removed to form the first gap.
[0026] In some embodiments, the specific steps of forming an active pillar within the first gap include:
[0027] Depositing metal oxide material within the first void forms the active pillar.
[0028] In some embodiments, the specific steps for forming the second gap include:
[0029] The second sacrificial layer and the third sacrificial layer of the bit line region and the transistor region are removed to form the second void.
[0030] In some embodiments, the active post includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, the drain region being electrically connected to the capacitor; the specific steps of forming a word line covering a portion of the active post within the second gap include:
[0031] A second isolation layer is formed covering the inner wall of the second void;
[0032] An initial word line is formed within the second gap, covering the surface of the second isolation layer;
[0033] The second isolation layer and the initial word line in the bit line region are removed to form a fourth gap between the active pillar and the interlayer isolation layer. The initial word line remaining in the transistor region serves as the word line, and the projection of the word line on the top surface of the substrate covers the projection of the channel region on the top surface of the substrate.
[0034] In some embodiments, after forming a word line covering a portion of the active column within the second gap, the method further includes the following steps:
[0035] A third isolation layer is formed to fill the fourth gap;
[0036] Part of the third isolation layer and the interlayer isolation layer are removed to form a fifth void in the bit line region that exposes the active pillar;
[0037] A bit line is formed within the fifth gap.
[0038] According to other embodiments, this disclosure also provides a memory, including:
[0039] Substrate;
[0040] A stacked structure is located on the top surface of the substrate, the stacked structure including memory cells spaced apart along a first direction, wherein the first direction is perpendicular to the top surface of the substrate;
[0041] The memory cell includes a transistor and a capacitor electrically connected to the transistor. The transistor includes an active post, and the capacitor includes a lower electrode layer. The lower electrode layer includes a terminal portion and a main body portion. The terminal portion protrudes from the main body portion along a second direction and is electrically connected to the active post. The second direction is a direction parallel to the top surface of the substrate.
[0042] In some embodiments, the active pillar includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction, and the terminal portion is electrically connected to the drain region; the stacked structure further includes memory cells spaced apart along a third direction, the third direction being a direction parallel to the top surface of the substrate, and the second direction intersecting the third direction;
[0043] The stacking structure further includes word lines spaced apart along the first direction, the word lines extending along the third direction and continuously covering the channel areas spaced apart along the third direction.
[0044] In some embodiments, the stacking structure further includes:
[0045] A second isolation layer is arranged at intervals along the first direction, the second isolation layer is located on the surface of the active column and covers the word line.
[0046] In some embodiments, the stacking structure further includes:
[0047] Bit lines are spaced apart along the third direction, extending along the first direction and continuously electrically connected to the source regions spaced apart along the first direction.
[0048] In some embodiments, at least a portion of the source region of the active pillar extends into the bit line.
[0049] This disclosure provides a memory and its formation method in some embodiments. First, a stacked layer consisting of alternating interlayer spacers and sacrificial layers is formed on the top surface of a substrate. Then, the first sacrificial layer in the sacrificial layer group is replaced with an active pillar, and at least the second and third sacrificial layers in the sacrificial layer group are replaced with word lines. On one hand, by forming a sacrificial layer group including the first, second, and third sacrificial layers, the stress inside the stacked layer can be reduced, thereby helping to increase the stacking height of the stacked layer and the storage capacity of the memory, thus improving the yield and performance of the memory. On the other hand, by replacing the sacrificial layers to form the active pillars and word lines, the formation of transistors in the memory does not require complex epitaxial growth and doping processes, simplifying the memory manufacturing process and further improving the yield of the memory. Furthermore, the capacitor in the memory provided in some embodiments of this disclosure includes a lower electrode layer, which includes a terminal portion and a main body portion. The terminal portion protrudes from the main body portion along a second direction and is electrically connected to the active pillar, thereby reducing the contact resistance between the transistor and the capacitor, further improving the electrical performance of the memory. Attached Figure Description
[0050] Appendix Figure 1 This is a flowchart of a method for forming a memory according to a specific embodiment of this disclosure;
[0051] Appendix Figure 2 -Appendix Figure 20 This is a schematic diagram of the main process structure in the formation of the memory according to a specific embodiment of the present disclosure;
[0052] Appendix Figures 21-23 This is a schematic diagram of the memory structure in a specific embodiment of this disclosure. Detailed Implementation
[0053] The specific embodiments of the memory and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0054] This specific embodiment provides a method for forming a memory, with appended... Figure 1 This is a flowchart illustrating the method for forming a memory according to a specific embodiment of this disclosure, with appended... Figure 2 -Appendix Figure 20 This is a schematic diagram of the main process structure in the formation of the memory according to a specific embodiment of the present disclosure, wherein, Figure 2 This is a top view schematic diagram of the memory structure formed in one embodiment of this specific implementation method. Figures 3-20 This is a top view schematic diagram of the main processes involved in forming the memory. Figure 2 Cross-sectional diagram of position aa Figure 2Provide one or two of the cross-sectional diagrams at position bb in the diagram to clearly illustrate the formation process of the memory. For example... Figures 1-20 As shown, the method for forming the memory includes the following steps:
[0055] Step S11: A stacked layer is formed on the surface of the substrate 30. The stacked layer 30 includes interlayer isolation layers 20 spaced apart along a first direction D1, and sacrificial layer groups 32 located between adjacent interlayer isolation layers 20. The sacrificial layer groups 32 include a first sacrificial layer 321, a second sacrificial layer 322, and a third sacrificial layer 323 sequentially stacked along the first direction D1. The stacked layer includes a transistor region TP, wherein the first direction D1 is a direction perpendicular to the top surface of the substrate 30. Figure 3 As shown.
[0056] Specifically, the substrate 30 may be, but is not limited to, a silicon substrate. This specific embodiment uses a silicon substrate as an example for illustration. In other embodiments, the substrate 30 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 30 is used to support the device structure thereon. The top surface of the substrate 30 refers to the surface of the substrate 30 facing the stacked layer.
[0057] In one example, the interlayer isolation layer 20, the first sacrificial layer 321, the second sacrificial layer 322, and the third sacrificial layer 323 can be alternately deposited on the top surface of the substrate 30 using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to form an interlayer isolation layer 20 and a sacrificial layer group 32 that are alternately stacked along the first direction D1. The more layers of interlayer isolation layer 20 and sacrificial layer group 32 that are alternately deposited, the larger the storage capacity of the formed memory. A high etch selectivity ratio should be present between any two of the first sacrificial layer 321, the second sacrificial layer 322, the third sacrificial layer 323, and the interlayer isolation layer 20 to facilitate subsequent selective etching. In one example, the etch selectivity ratio between any two of the first sacrificial layer 321, the second sacrificial layer 322, the third sacrificial layer 323, and the interlayer isolation layer 20 should be greater than 3. In one example, the thickness of the sacrificial layer group 32 along the first direction D1 can be 30nm to 60nm, so as to reserve enough space for the formation of transistors and capacitors and help control the overall size of the final formed memory.
[0058] To simplify the formation process of the sacrificial layer group 32 and reduce its cost, in some embodiments, the first sacrificial layer is made of a low dielectric constant material, the second sacrificial layer is made of undoped polycrystalline silicon, and the third sacrificial layer is made of silicon dioxide. The low dielectric constant material refers to a material with a dielectric constant less than 3. For example, the low dielectric constant material can be, but is not limited to, one or more combinations of SiOH, SiOCH, FSG (fluorosilicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass).
[0059] In one embodiment, a substrate isolation layer 31 may be provided between the substrate 30 and the stacked layer to isolate the substrate 30 from the stacked layer and further reduce the stress between the substrate 30 and the stacked layer. The substrate isolation layer 31 may be made of an insulating dielectric material such as an oxide (e.g., silicon dioxide).
[0060] Step S12: Remove the first sacrificial layer 321 of the transistor region TP to form a first gap.
[0061] Step S13, an active column 120 is formed in the first gap, such as Figure 12 As shown.
[0062] In some embodiments, the stacked layer further includes a capacitor region CP located on one side of the transistor region TP; before forming the first gap, the following steps are also included:
[0063] The sacrificial layer group 32 of the capacitor region CP is removed to form a third gap 41, as shown below. Figure 4 As shown;
[0064] A capacitor is formed within the third gap 41.
[0065] In some embodiments, the specific steps for forming the third gap 41 include:
[0066] All of the second sacrificial layer 322, a portion of the first sacrificial layer 321, and a portion of the third sacrificial layer 323 of the capacitor region CP are removed, forming a first trench 40 between the remaining first sacrificial layer 321 and the remaining third sacrificial layer 323, and a third gap 41 between adjacent interlayer isolation layers 20 and communicating with the first trench 40, as shown. Figure 4 As shown;
[0067] Forming a first isolation layer 50 that fills the first trench 40, such as Figure 5 As shown.
[0068] Specifically, after forming the stacked layer on the top surface of the substrate 30, the transistor region TP and the capacitor region CP located outside the transistor region TP along the second direction D2 are defined in the stacked layer. The second direction D2 is parallel to the top surface of the substrate 30. Next, a lateral etching process can be used to etch the first sacrificial layer 321, the second sacrificial layer 322, and the third sacrificial layer 323 of the capacitor region CP. The etching depth of the second sacrificial layer 322 is greater than that of the first sacrificial layer 321 and greater than that of the third sacrificial layer 323, thereby forming the first trench 40 located between the remaining first sacrificial layer 321 and the remaining third sacrificial layer 323, and the third gap 41 located between adjacent interlayer isolation layers 20 and communicating with the first trench 40. Figure 4 As shown. Subsequently, an insulating dielectric material such as an oxide (e.g., silicon dioxide) can be deposited within the first trench 40 to form the first isolation layer 50, filling the first trench 40. In one example, the width of the first isolation layer 50 along the second direction D2 is 30 nm to 60 nm, thereby improving the insulation performance of the first isolation layer 50 while reducing the parasitic capacitance between the capacitor (especially the lower electrode layer in the capacitor) and the gate electrode of the transistor.
[0069] During the etching process, by making the etching amount of the second sacrificial layer 322 greater than that of the first sacrificial layer 321 and greater than that of the third sacrificial layer 323, on the one hand, it is convenient to form the first isolation layer 50 for isolating word lines and capacitors in the first trench 40; on the other hand, it also helps to reduce leakage between word lines and capacitors.
[0070] In some embodiments, the specific steps of forming a capacitor within the third gap 41 include:
[0071] Removing a portion of the first sacrificial layer 321 below the first isolation layer 50 forms a second trench 60 communicating with the third gap 41, such as... Figure 6 As shown;
[0072] A lower electrode layer is formed that fills the second trench 60 and covers the inner wall of the third gap 41;
[0073] A dielectric layer 221 is formed covering the surface of the lower electrode layer;
[0074] An upper electrode layer 222 is formed covering the surface of the dielectric layer 221, such as... Figure 11 As shown.
[0075] Specifically, a portion of the first sacrificial layer 321 in the capacitor region CP is etched again to form the second trench 60 located between the first isolation layer 50 and the interlayer isolation layer 20, such as... Figure 6 As shown. Next, a lower electrode material (e.g., conductive material such as tungsten or TiN) is deposited in the second trench 60 and the inner wall of the third gap 41 to form a terminal portion 70 filling the second trench 60 and simultaneously forming a main body portion 71 covering the inner wall of the third gap 41. The terminal portion 70 and the main body portion 71 together constitute the lower electrode layer of the capacitor, as shown. Figure 7 As shown. The terminal portion 70 is in direct contact with the main body portion 71 and is electrically connected, and the terminal portion 70 protrudes from the main body portion 71 along the second direction D2. Along the first direction D1, the height of the terminal portion 70 is less than the height of the main body portion 71. By forming the terminal portion 70, which electrically connects to the transistor, it not only helps to reduce the contact resistance between the capacitor and the transistor, but also ensures the connection stability between the transistor and the capacitor, thereby further improving the electrical performance of the memory.
[0076] After forming the lower electrode layer, an insulating dielectric material such as an oxide (e.g., silicon dioxide) is deposited within the third void 41 to form a first filling layer 80 that fills the third void 41. Figure 8 As shown. Then, the interlayer isolation layer 20, the first filling layer 80, and the main body 71 of the lower electrode layer of the capacitor region CP are etched to form a capacitor trench 90 that penetrates the stacked layers and exposes the substrate 30, as shown. Figure 9 As shown, the first filling layer 80 is removed along the capacitor trench 90. A plurality of capacitor trenches 90 are arranged at intervals along a third direction D3, wherein the third direction D3 is parallel to the top surface of the substrate 30 and intersects (e.g., orthogonally) the second direction D2. Then, an insulating dielectric material such as an oxide (e.g., silicon dioxide) is filled into the capacitor trenches 90 to form a capacitor isolation layer 101, as shown. Figure 10 As shown, capacitors are arranged at intervals along the third direction for isolation. Then, a high-dielectric-constant material is deposited on the surface of the body portion 71 of the lower electrode layer to form the dielectric layer 221. An upper electrode material (e.g., a conductive material such as tungsten or TiN) is deposited on the surface of the dielectric layer 221 to form the upper electrode layer 222, as shown. Figure 11 As shown.
[0077] In some embodiments, the stacked layer further includes a bit line region BP, the capacitor region CP and the bit line region BP are distributed on opposite sides of the transistor region TP along a second direction D2, the second direction D2 being parallel to the top surface of the substrate 30; the specific steps for forming the first gap include:
[0078] The first sacrificial layer 321 of the bit line region BP and the transistor region TP is removed to form the first gap.
[0079] Specifically, after forming the capacitor, a lateral etching process can be used to remove the first sacrificial layer 321 of the bit line region BP and the transistor region TP, forming the first gap located between the interlayer isolation layer 20 and the second sacrificial layer 322. Next, a lateral atomic layer deposition process can be used to deposit channel material within the first gap, forming an active layer filling the first gap. Afterwards, the interlayer isolation layer 20, the second sacrificial layer 322, the third sacrificial layer 323, and the active layer of the bit line region BP and the transistor region TP are etched to form transistor trenches 130 spaced along the third direction D3, as shown below. Figure 13 As shown. The bottom of the transistor trench 130 exposes the substrate 30 and divides the active layer into active pillars 120 spaced along the third direction D3, as shown. Figure 12 As shown. Then, an insulating dielectric material such as an oxide (e.g., silicon dioxide) is filled into the transistor trench 130 to form a transistor isolation layer 21, as shown. Figure 14 As shown.
[0080] In some embodiments, the specific steps of forming the active column 120 within the first gap include:
[0081] Depositing metal oxide material within the first void forms the active pillar 120, such as... Figure 12 As shown.
[0082] The metal oxide material can be, but is not limited to, IGZO (indium gallium zinc oxide). The metal oxide material can be converted between conductor and insulator. Using a metal oxide material to form the active pillar 120 eliminates the need for complex doping processes, thereby simplifying the formation process of the memory.
[0083] Step S14: Remove the second sacrificial layer 322 and the third sacrificial layer 323 of the transistor region TP to form a second gap 150, as shown. Figure 15 As shown;
[0084] Step S15, form a word line 24 covering part of the active column 120 within the second gap 150, such as Figure 18 As shown.
[0085] In some embodiments, the specific steps for forming the second gap 150 include:
[0086] The second sacrificial layer 322 and the third sacrificial layer 323 of the bit line region BP and the transistor region TP are removed to form the second gap 150, as shown below. Figure 15 As shown.
[0087] In some embodiments, the active pillar 120 includes a channel region, and a source region and a drain region distributed on opposite sides of the channel region along the second direction D2, wherein the drain region is electrically connected to the capacitor; the specific steps of forming a word line 24 covering a portion of the active pillar 120 within the second gap 150 include:
[0088] A second insulating layer 160 is formed covering the inner wall of the second void 150, such as Figure 16 As shown;
[0089] An initial word line 161 is formed within the second gap 150, covering the surface of the second isolation layer 160, such as... Figure 16 As shown;
[0090] The second isolation layer 160 and the initial word line 161 of the bit line region BP are removed to form a fourth gap 180 between the active pillar 120 and the interlayer isolation layer 20. The initial word line 161 remaining in the transistor region TP serves as word line 24, and the projection of word line 24 on the top surface of the substrate 30 covers the projection of the channel region on the top surface of the substrate 30.
[0091] Specifically, a lateral etching process can be used to remove the second sacrificial layer 322 and the third sacrificial layer 323 of the transistor region TP and the capacitor region BP to form the second gap 150, such as... Figure 15 As shown. Then, a lateral atomic layer deposition process can be used to form the second isolation layer 160 and the initial word line 161 covered by the second isolation layer 160 within the second void 150, as shown. Figure 16 As shown. The initial word line 161 extends along the third direction D3 and continuously covers the active pillars 120 spaced apart along the third direction D3. Multiple initial word lines 161 are spaced apart along the first direction D1. The ends of the initial word lines 161 extend out of the transistor region TP along the third direction D3 to facilitate connection with the word line plug 25 (see...). Figure 2 Electrical connection. A stepped structure is formed by etching the end of the initial word line 161 extending from the transistor region TP along the third direction D3, as shown below. Figure 17 As shown. The stepped structure refers to the situation where, along the first direction D1, one of the two adjacent initial word lines 161, closer to the substrate 30, protrudes beyond the other initial word line 161 along the third direction D3. After forming the stepped structure, the second isolation layer 160 and the initial word line 161 of the bit line region BP are etched away to form a fourth gap 180 between the active pillar 150 and the interlayer isolation layer 20, as shown. Figure 18 As shown, the initial word line 161 remaining in the transistor region TP serves as word line 24, and the projection of word line 24 on the top surface of the substrate 30 covers the projection of the channel region on the top surface of the substrate 30.
[0092] In some embodiments, after forming a word line covering a portion of the active post 120 within the second gap 150, the following steps are further included:
[0093] A third isolation layer 190 is formed to fill the fourth void 180, such as Figure 19 As shown;
[0094] By removing portions of the third isolation layer 190 and the interlayer isolation layer 20, a fifth void is formed in the bit line region BP to expose the active pillar 120.
[0095] A bit line 23 is formed within the fifth gap, as follows: Figure 20 As shown.
[0096] Specifically, an insulating dielectric material such as an oxide (e.g., silicon dioxide) can be deposited within the fourth void 180 using a lateral atomic layer deposition process to form the third isolation layer 190 filling the fourth void 180. Subsequently, a photolithography process can be used to etch a portion of the third isolation layer 190 and the interlayer isolation layer 20, forming a fifth void in the bit line region BP that exposes the active pillar 120. A bit line material (e.g., conductive material such as tungsten or TiN) is then deposited within the fifth void to form bit lines 23 spaced along the third direction D3. The bit lines 23 extend along the first direction D1 and continuously cover the surface of the active pillars 120 spaced along the first direction D1. By embedding the active post 120 inside the bit line 23, on the one hand, the active post 120 can support the bit line 23, improving the structural stability of the bit line 23; on the other hand, it can also ensure a stable electrical connection between the active region in the active post 120 and the bit line 23, reducing or even avoiding the problem of poor contact between the bit line 23 and the transistor.
[0097] This specific embodiment also provides a memory, attached... Figures 21-23This is a schematic diagram of the memory structure in a specific embodiment of this disclosure, wherein, Figure 21 This is a top view of the memory structure in this specific embodiment. Figure 22 yes Figure 21 A cross-sectional diagram at position aa. Figure 23 yes Figure 21 A cross-sectional view at position bb. The memory provided in this specific embodiment can be adopted as follows: Figures 1-20 The method for forming the aforementioned memory is described. For example... Figures 21-23 As shown, the memory includes:
[0098] Substrate 30;
[0099] A stacked structure is located on the top surface of the substrate 30. The stacked structure includes memory cells arranged at intervals along a first direction D1, wherein the first direction D1 is a direction perpendicular to the top surface of the substrate 30.
[0100] The memory cell includes a transistor and a capacitor electrically connected to the transistor. The transistor includes an active post 120, and the capacitor includes a lower electrode layer. The lower electrode layer includes a terminal portion 70 and a main body portion 71. The terminal portion 70 protrudes from the main body portion 71 along a second direction D2, and the terminal portion 70 is in contact with and electrically connected to the active post 120. The second direction D2 is a direction parallel to the top surface of the substrate 30.
[0101] Specifically, the terminal portion 70 is in direct electrical contact with the main body portion 71, and the terminal portion 70 protrudes from the main body portion 71 along the second direction D2. Along the first direction D1, the height of the terminal portion 70 is less than the height of the main body portion 71. By forming the terminal portion 70, which electrically connects to the transistor, not only can the contact resistance between the capacitor and the transistor be reduced, but the connection stability between the transistor and the capacitor can also be ensured, thereby further improving the electrical performance of the memory.
[0102] In some embodiments, the active pillar 120 includes a channel region and a source region and a drain region distributed on opposite sides of the channel region along the second direction D2, and the terminal portion 70 is electrically connected to the drain region; the stacked structure further includes memory cells spaced apart along a third direction D3, the third direction D3 being a direction parallel to the top surface of the substrate 30, and the second direction D2 intersecting the third direction D3;
[0103] The stacking structure further includes word lines 24 spaced along the first direction D1, the word lines 24 extending along the third direction D3 and continuously covering the channel areas spaced along the third direction D3.
[0104] For example, such as Figures 21-23 As shown, the stacked structure includes multiple layers of memory cells arranged at intervals along the first direction D1. Each layer of memory cells includes multiple memory cells arranged at intervals along the third direction D3, and an interlayer isolation layer 20 is provided between adjacent layers of memory cells, so that the multiple memory cells form a three-dimensional stacked structure. Each memory cell includes a transistor and a capacitor. The transistor includes an active pillar 120, which includes a channel region and source and drain regions distributed on opposite sides of the channel region along the second direction D2. The capacitor includes a lower electrode layer, a dielectric layer 221 covering the surface of the lower electrode layer, and an upper electrode layer 222 covering the surface of the dielectric layer 221. The lower electrode layer includes a terminal portion 70 electrically connected to the drain region and a body portion 71 electrically connected to the terminal portion 70, with the dielectric layer 221 covering the surface of the body portion 71. In this specific embodiment, "multiple" refers to two or more.
[0105] The stacked structure includes a transistor region and capacitor regions and bit line regions distributed along the second direction D2 on opposite sides of the transistor region. The transistor region is used to form the transistor, and the capacitor region is used to form the capacitor. The stacked structure also includes word lines 24 spaced apart along the first direction D1, the word lines 24 extending along the third direction D3 and continuously covering the channel regions spaced apart along the third direction D3. The word lines 24 and the capacitor are electrically isolated through a first isolation layer 50 and a third sacrificial layer 323 located above the first isolation layer 50. The ends of the word lines 24 extend out of the transistor region along the third direction D3 to be electrically connected to word line plugs 25. Multiple word lines 24 extending out of the transistor region along the third direction D3 form a stepped structure to facilitate the signal extraction of each word line 24. The stepped structure refers to the fact that, along the first direction D1, for any two adjacent word lines 24, the word line 24 closer to the substrate 30 protrudes beyond the other word line 24 along the third direction D3.
[0106] In some embodiments, the stacking structure further includes:
[0107] A second isolation layer 160 is arranged at intervals along the first direction D1. The second isolation layer 160 is located on the surface of the active pillar 120 and covers the word line 24. The second isolation layer 160 located between the word line 24 and the channel region serves as the gate dielectric layer of the transistor.
[0108] In some embodiments, the stacking structure further includes:
[0109] Bit lines 23 are spaced apart along the third direction D3, extending along the first direction D1, and continuously electrically connected to the source regions spaced apart along the first direction D1. The bit lines 23 and the word lines 24 are electrically isolated by a third isolation layer 190.
[0110] In some embodiments, at least a portion of the source region of the active post 120 extends into the bit line 23.
[0111] The memory and its formation method provided in some embodiments of this disclosure first form a stacked layer consisting of alternating interlayer spacers and sacrificial layers on the top surface of a substrate. Then, the first sacrificial layer in the sacrificial layer group is replaced with an active pillar, and at least the second and third sacrificial layers in the sacrificial layer group are replaced with word lines. On the one hand, by forming a sacrificial layer group including the first, second, and third sacrificial layers, the stress inside the stacked layer can be reduced, thereby helping to increase the stacking height of the stacked layer and the storage capacity of the memory, thus improving the yield and performance of the memory. On the other hand, by replacing the sacrificial layers to form the active pillars and word lines, the formation of transistors in the memory does not require complex epitaxial growth and doping processes, simplifying the manufacturing process of the memory and further improving the yield of the memory. Moreover, the capacitor in the memory provided in some embodiments of this disclosure includes a lower electrode layer, which includes a terminal portion and a main body portion. The terminal portion protrudes from the main body portion along a second direction and is electrically connected to the active pillar, thereby reducing the contact resistance between the transistor and the capacitor, thereby further improving the electrical performance of the memory.
[0112] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.
Claims
1. A method for forming a memory, characterized in that, Includes the following steps: A stacked layer is formed on the surface of a substrate. The stacked layer includes interlayer isolation layers spaced apart along a first direction and a group of sacrificial layers located between adjacent interlayer isolation layers. The group of sacrificial layers includes a first sacrificial layer, a second sacrificial layer and a third sacrificial layer stacked sequentially along the first direction. The stacked layer includes a transistor region. The first direction is a direction perpendicular to the top surface of the substrate. Remove the first sacrificial layer in the transistor region to form a first void; An active column is formed within the first gap; The second and third sacrificial layers in the transistor region are removed to form a second void; A word line covering a portion of the active column is formed within the second gap; The stacked layer also includes a capacitor region located on one side of the transistor region; before forming the first gap, the following steps are also included: Remove the sacrificial layer group in the capacitor region to form a third gap; A capacitor is formed within the third gap; The specific steps to form the third gap include: Remove all of the second sacrificial layer, a portion of the first sacrificial layer, and a portion of the third sacrificial layer from the capacitor region to form a first trench between the remaining first sacrificial layer and the remaining third sacrificial layer, and a third gap between adjacent interlayer isolation layers and communicating with the first trench. A first isolation layer is formed, filling the first trench; The specific steps for forming a capacitor within the third gap include: Remove a portion of the first sacrificial layer below the first isolation layer to form a second trench communicating with the third gap; A lower electrode layer is formed that fills the second trench and covers the inner wall of the third gap; A dielectric layer is formed covering the surface of the lower electrode layer; An upper electrode layer is formed covering the surface of the dielectric layer.
2. The method for forming a memory according to claim 1, characterized in that, The first sacrificial layer is made of a low dielectric constant material, the second sacrificial layer is made of undoped polycrystalline silicon, and the third sacrificial layer is made of silicon dioxide.
3. The method for forming a memory according to claim 1, characterized in that, The stacked layer further includes bit line regions, and the capacitor regions and the bit line regions are distributed on opposite sides of the transistor regions along a second direction, which is a direction parallel to the top surface of the substrate; The specific steps for forming the first gap include: The first sacrificial layer of the bit line region and the transistor region is removed to form the first gap.
4. The method for forming a memory according to claim 3, characterized in that, The specific steps for forming an active column within the first gap include: Depositing metal oxide material within the first void forms the active pillar.
5. The method for forming a memory according to claim 3, characterized in that, The specific steps for forming the second void include: The second sacrificial layer and the third sacrificial layer of the bit line region and the transistor region are removed to form the second void.
6. The method for forming a memory according to claim 5, characterized in that, The active post includes a channel region and source and drain regions distributed on opposite sides of the channel region along the second direction, wherein the drain region is electrically connected to the capacitor; the specific steps of forming a word line covering a portion of the active post within the second gap include: A second isolation layer is formed covering the inner wall of the second void; An initial word line is formed within the second gap, covering the surface of the second isolation layer; The second isolation layer and the initial word line in the bit line region are removed to form a fourth gap between the active pillar and the interlayer isolation layer. The initial word line remaining in the transistor region serves as the word line, and the projection of the word line on the top surface of the substrate covers the projection of the channel region on the top surface of the substrate.
7. The method for forming a memory according to claim 6, characterized in that, After forming a word line covering a portion of the active column within the second gap, the method further includes the following steps: A third isolation layer is formed to fill the fourth gap; Part of the third isolation layer and the interlayer isolation layer are removed to form a fifth void in the bit line region that exposes the active pillar; A bit line is formed within the fifth gap.
8. A memory, formed using the memory forming method according to any one of claims 1-7, characterized in that, include: Substrate; A stacked structure is located on the top surface of the substrate, the stacked structure including memory cells spaced apart along a first direction, wherein the first direction is perpendicular to the top surface of the substrate; The memory cell includes a transistor and a capacitor electrically connected to the transistor. The transistor includes an active post, and the capacitor includes a lower electrode layer. The lower electrode layer includes a terminal portion and a main body portion. The terminal portion protrudes from the main body portion along a second direction and is electrically connected to the active post. The second direction is a direction parallel to the top surface of the substrate.
9. The memory according to claim 8, characterized in that, The active pillar includes a channel region and source and drain regions distributed on opposite sides of the channel region along the second direction. The terminal portion is electrically connected to the drain region. The stacked structure also includes memory cells spaced apart along a third direction, which is a direction parallel to the top surface of the substrate, and the second direction intersects the third direction. The stacking structure further includes word lines spaced apart along the first direction, the word lines extending along the third direction and continuously covering the channel areas spaced apart along the third direction.
10. The memory according to claim 9, characterized in that, The stacked structure further includes: A second isolation layer is arranged at intervals along the first direction, the second isolation layer is located on the surface of the active column and covers the word line.
11. The memory according to claim 9, characterized in that, The stacked structure further includes: Bit lines are spaced apart along the third direction, extending along the first direction and continuously electrically connected to the source regions spaced apart along the first direction.
12. The memory according to claim 11, characterized in that, At least a portion of the source region of the active pillar extends into the bit line.