Cache method and integrated circuit

Abstract

The embodiment of the present application provides a caching method and integrated circuit that can avoid false hits. The caching method includes: obtaining a first message, the first message including a destination Internet Protocol (IP) address; searching a cache for a routing prefix that matches the destination IP address; in response to the routing prefix not being stored in the cache, searching a tree structure corresponding to a routing table according to the destination IP address to determine a prefix node that matches the destination IP address; in response to the prefix node not being a leaf node, the processor determining a first prefix matching length, the first prefix matching length being equal to the length between the root node and the tail node of the tree structure; determining a first routing prefix based on the first prefix matching length and the destination IP address; and triggering the cache to store a first corresponding relationship, the first corresponding relationship being the first routing prefix and routing information corresponding to the prefix node.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a caching method and an integrated circuit. Background Art

[0002] When forwarding a message, a network device such as a router or switch can obtain the destination Internet Protocol (IP) address carried in the message and search the routing table for the routing information corresponding to the destination IP address, so that the message can be forwarded based on the found routing information. A routing table is a table that records routing prefixes and routing information and is pre-stored in the network device. The routing prefix is ​​used to determine the routing information that matches the destination IP address. For example, it can be the first n bits of the IP address, where n is the length of the routing prefix. The routing information can also be the identifier of the network interface, indicating which network interface the network device needs to use to forward the message.

[0003] When searching the routing table, determine whether the destination IP address matches the routing prefix. For example, assuming that the length of a routing prefix is ​​m, and the first m bits of the destination IP address are consistent with the routing prefix, it can be considered that the destination IP address matches the routing prefix, and the corresponding routing information is the routing information corresponding to the routing prefix. When the destination IP address matches two or more routing prefixes at the same time, the routing prefix can be determined based on the longest prefix match (LPM) principle. That is, the routing information of the longest routing prefix among the multiple routing prefixes that match the destination IP address can be used as the routing information corresponding to the destination IP address.

[0004] Because a routing table lookup requires comparing the route prefix with the destination IP address to see if it matches, network devices must perform a routing table search. Obviously, the faster the routing table is accessed, the faster the network device can forward packets. Currently, to increase the speed at which network devices access routing tables, some of the correspondence between route prefixes and routing information can be stored in a cache. However, this approach often results in false hits. Summary of the Invention

[0005] The embodiments of the present application provide a caching method and an integrated circuit, which avoid the occurrence of false hits by recording in the cache a correspondence between a first routing prefix and routing information with a length greater than that of the destination IP address in the routing table.

[0006] In a first aspect, an embodiment of the present application provides a caching method that can be applied to a processor in a network device. When executing the caching method, the processor can first obtain a first message and determine the destination IP address carried in the first message. Then, the processor can search the cache for a routing prefix that matches the destination IP address. If the cache does not store a routing prefix that matches the destination IP address, the processor can search the tree structure corresponding to the routing table from other memories based on the destination IP address, thereby determining the prefix node that matches the destination IP address in the tree structure, that is, the node in the tree structure corresponding to the routing table that matches the routing prefix that matches the destination IP address. When the prefix node is not a leaf node in the tree structure, that is, the prefix node has child nodes, the processor can determine the length from the root node to the tail node of the tree structure as the first prefix matching length. The tail node is the last node on the search path in the tree structure. The search path is the path from the root node in the tree structure corresponding to the routing table along the tree structure corresponding to the destination IP address to the leaf node in the tree structure corresponding to the routing table. After obtaining the first prefix matching length, the processor can determine the first routing prefix based on the destination IP address and the first prefix matching length, and trigger the cache to store the first corresponding relationship, which is the corresponding relationship between the first routing prefix and the routing information corresponding to the prefix node. That is, when the prefix node is not a leaf node, the routing prefix in the corresponding relationship is different from the routing prefix recorded in the routing table. That is, when there are other routing prefixes in the routing table that include and are longer than the routing prefix corresponding to the destination IP address, the processor can determine the new first routing prefix based on the first prefix matching length, and store the corresponding relationship between the new routing prefix and the routing information in the cache. In this way, the length of the first routing prefix can be greater than the length of the routing prefix that matches the destination IP address in the memory routing table. In this way, compared with the prior art, it can reduce the probability of false hits.

[0007] In one possible implementation, the length of the first routing prefix can be greater than the first prefix matching length. It is easy to understand that the longer the first routing prefix is, the lower the probability of a false hit. When the length of the first routing prefix is ​​greater than the first prefix matching length, the probability of a false hit is zero.

[0008] In a possible implementation, when the tail node of the destination IP address in the tree structure corresponding to the routing table is a leaf node, the length of the first routing prefix may be equal to the first prefix matching length.

[0009] In one possible implementation, the tree structure corresponding to the routing table can be divided into a virtual tree structure and multiple subtree structures. The processor can determine the prefix node that matches the destination IP address using the virtual tree structure and the subtree structures. The virtual tree structure can include any number of nodes in the tree structure corresponding to the routing table, with the root node of each of the multiple subtree structures corresponding to a node in the virtual tree structure. Specifically, the processor can first search the virtual tree structure corresponding to the routing table based on the destination IP address to determine the virtual prefix that longest matches the destination IP address. Next, the processor can determine, based on the virtual prefix, the subtree structure whose root node corresponds to the routing prefix corresponding to the virtual prefix, and search the subtree structure for the prefix node that matches the destination IP address. Assuming that the first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the length from the virtual prefix to the tail node on the search path of the subtree structure, the sum of the first and second lengths is the aforementioned first prefix matching length. In this way, dividing the tree structure corresponding to the routing table into the virtual tree structure and multiple subtrees can improve the efficiency of routing prefix lookup.

[0010] In some possible implementations, the processor may further store a correspondence between a second routing prefix and routing information. A "nowhere routing prefix" is a routing prefix corresponding to a sole child node on a forwarding path, and a sole child node is a child node that has only a left child node or a right child node. Specifically, when the prefix node matching the destination IP address is not a leaf node, the processor may determine the sole child node on the forwarding path based on the forwarding path of the destination IP address, and determine the second prefix matching length based on the leaf node. The second prefix matching length is equal to the length from the root node to the sole child node. After determining the second prefix matching length, the processor may determine the second routing prefix based on the second prefix matching length, thereby storing the second corresponding relationship.

[0011] In some possible implementations, the processor may further trigger the cache to store the type of the first routing prefix. Then, after the processor receives another message, if the destination IP address of the message matches the first routing prefix, the processor may obtain routing information corresponding to the first routing prefix from the cache according to the first correspondence based on the indication of the type of the first routing prefix.

[0012] In some possible implementations, when the processor determines a prefix node using the virtual tree structure and the subtree structure, the processor may trigger the cache to store a third correspondence between the virtual prefix, the type of the virtual prefix, and the subtree structure information. Similarly, if the destination IP address of the packet matches the virtual prefix, the processor may search the subtree structure information based on the indication of the virtual prefix type to determine the routing information corresponding to the first routing prefix.

[0013] In some possible implementations, considering the maximum length matching principle, the processor may further trigger the cache to store the length of the first routing prefix.

[0014] In some possible implementations, the length of the first routing prefix is ​​equal to the first prefix matching length plus 1.

[0015] In some possible implementations, the length of the first routing prefix is ​​smaller than the length of the destination IP address.

[0016] In some possible implementations, the destination IP address includes the first routing prefix.

[0017] In some possible implementations, the cache includes at least one of the following: a ternary content addressable memory (TCAM), a register, a line card, and a die.

[0018] In a second aspect, an embodiment of the present application provides an integrated circuit, which is applied to a processor and includes an interface circuit and a control circuit; wherein the interface circuit is used to obtain a first message, the first message including a destination Internet Protocol IP address; the control circuit is used to search a routing prefix matching the destination IP address from a cache; in response to the routing prefix not being stored in the cache, searching a tree structure corresponding to a routing table according to the destination IP address, and determining a prefix node matching the destination IP address; in response to the prefix node not being a leaf node, determining a first prefix matching length, the first prefix matching length being equal to the length between the root node and the tail node of the tree structure, the tail node being the last node on the search path of the tree structure; determining a first routing prefix based on the first prefix matching length and the destination IP address; triggering the cache to store a first corresponding relationship, the first corresponding relationship being the first routing prefix and the routing information corresponding to the prefix node.

[0019] In some possible implementations, the length of the first routing prefix is ​​greater than or equal to the first prefix matching length.

[0020] In some possible implementations, the control circuit is used to search the virtual tree structure corresponding to the routing table according to the destination IP address, and determine the virtual prefix that matches the destination IP address for the longest time; search the subtree structure corresponding to the virtual prefix according to the destination IP address, and determine the prefix node that matches the destination IP address, and the virtual prefix is ​​the root node of the subtree structure; the first prefix matching length is equal to the sum of the first length and the second length, the first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the length from the virtual prefix to the tail node, and the tail node is the last node on the search path of the subtree structure.

[0021] In some possible implementations, the control circuit is further used to determine a second prefix matching length in response to the prefix node not being a leaf node, the second prefix matching length being equal to the length between the root node and the only child node of the tree structure, the only child node being a node between the prefix node and the tail node that only has a left child node or only has a right child node; determine a second routing prefix based on the second prefix matching length and the destination IP address, the length of the second routing prefix being greater than the second prefix matching length; and trigger the cache to store a second corresponding relationship, the second corresponding relationship being the routing information corresponding to the second routing prefix and the prefix node.

[0022] In some possible implementations, the control circuit is also used to trigger the cache to store the type of the first routing prefix, and the type of the first routing prefix is ​​used to indicate that when the first routing prefix is ​​hit, the routing information corresponding to the first routing prefix is ​​obtained in the cache according to the first corresponding relationship.

[0023] In some possible implementations, the control circuit is also used to trigger the cache to store a third correspondence, where the third correspondence is a correspondence between the virtual prefix, the type of the virtual prefix, and the information of the subtree structure, and the type of the virtual prefix is ​​used to indicate that when the virtual prefix is ​​hit, the subtree structure is searched according to the information of the subtree structure.

[0024] In some possible implementations, the control circuit is further configured to trigger the cache to store the length of the first routing prefix.

[0025] In some possible implementations, the length of the first routing prefix is ​​equal to the first prefix matching length plus 1.

[0026] In some possible implementations, the length of the first routing prefix is ​​smaller than the length of the destination IP address.

[0027] In some possible implementations, the destination IP address includes the first routing prefix.

[0028] In some possible implementations, the cache includes at least one of the following: a TCAM, a register, a line card, and a die.

[0029] In a third aspect, an embodiment of the present application provides a cache device, which includes an acquisition unit and a processing unit. The acquisition unit is used to acquire a first message, which includes a destination Internet Protocol IP address. The processing unit is used to search the cache for a routing prefix that matches the destination IP address; in response to the routing prefix not being stored in the cache, search the tree structure corresponding to the routing table according to the destination IP address to determine the prefix node that matches the destination IP address; in response to the prefix node not being a leaf node, determine a first prefix matching length, which is equal to the length between the root node and the tail node of the tree structure, and the tail node is the last node on the search path of the tree structure; determine a first routing prefix based on the first prefix matching length and the destination IP address; trigger the cache to store a first corresponding relationship, which is the first routing prefix and the routing information corresponding to the prefix node.

[0030] In a fourth aspect, an embodiment of the present application provides a chip, which includes a memory and a processor, the memory being used to store instructions or program codes, and the processor being used to call and run the instructions or program codes from the memory to execute the caching method as described in the first aspect above.

[0031] In the fifth aspect, an embodiment of the present application provides a device, which includes a processor chip and a memory, the memory is used to store instructions or program codes, and the processor chip is used to call and run the instructions or program codes from the memory to execute the caching method as described in the first aspect above.

[0032] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising instructions, programs or codes, which, when executed on a computer, enables the computer to execute the caching method as described in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a tree structure corresponding to a routing prefix provided in an embodiment of the present application;

[0035] Figure 3-a A schematic diagram of the structure of a network system 300 provided in an embodiment of the present application;

[0036] Figure 3-b A schematic diagram of the structure of a network device 350 provided in an embodiment of the present application;

[0037] Figure 3-c Another structural diagram of the network device 350 provided in an embodiment of the present application;

[0038] Figure 3-d A schematic diagram of another structure of the network device 350 provided in an embodiment of the present application;

[0039] Figure 3-e A schematic diagram of the structure of a network device 360 ​​provided in an embodiment of the present application;

[0040] Figure 3-f A schematic diagram of the structure of a chip 370 of a network device provided in an embodiment of the present application;

[0041] Figure 3-g A schematic diagram of the structure of a virtual router 380 provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of a process flow of a caching method provided in an embodiment of the present application;

[0043] Figure 5 A schematic diagram of a tree structure corresponding to the routing table provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of a subtree structure provided in an embodiment of the present application;

[0045] Figure 7 A schematic diagram of a tree structure corresponding to the routing table provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of the structure of an integrated circuit 800 provided in an embodiment of the present application;

[0047] Figure 9 A schematic diagram of the structure of a cache device 900 provided in an embodiment of the present application;

[0048] Figure 10 A schematic structural diagram of a chip 1000 provided in an embodiment of the present application;

[0049] Figure 11 A schematic diagram of the structure of a device 1100 provided in an embodiment of the present application;

[0050] Figure 12 A schematic diagram of the structure of a device 1200 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The following describes the conventional technology and the caching method provided by the embodiment of the present application in conjunction with the accompanying drawings.

[0052] First, the basic structure of the device including the cache is introduced. Figure 1 , which is a schematic diagram of the structure of device 100. Device 100 includes a processor 110 and a memory 120. Processor 110 includes a processing unit 111 and a cache 112. Cache 112 can be used to load data from memory 120, and processing unit 111 can be used to read data from cache 112 and process the data. Optionally, when processor 110 is packaged as a chip, the chip can be called a central processing unit (CPU).

[0053] Cache, also known as high-speed cache memory, is mostly composed of storage devices with fast data exchange speeds. In the embodiments of this application, cache can also be referred to as temporary memory or temporary storage. Cache is connected to the processing unit inside the processor and the memory outside the processor, respectively, and can store some or all of the data stored in the memory.

[0054] The memory can be divided into external memory and internal memory. The external memory is, for example, a storage device such as a hard disk drive (HDD), and the internal memory is, for example, a storage device such as a synchronous dynamic random-access memory (SDRAM) or a double data rate synchronous dynamic random access memory (DDR). The cache is, for example, a storage device such as a static random access memory (SRAM). In the process of exchanging data with the processor, the data exchange speed of SRAM is greater than the data exchange speed of DDR (or SDRAM), and the data exchange speed of DDR is greater than the data exchange speed of the hard disk. When a network device stores part or all of the routing table through a cache, a routing table with empty content can be created in the cache first. In an embodiment of the present application, the routing table stored in the cache can be referred to as a cache routing table, and the routing table stored in the memory can be referred to as a memory routing table.

[0055] When the processor determines that the destination IP address matches a routing prefix in the memory routing table, the processor can store the routing prefix and routing information in the cache routing table. In this way, when the network device receives a new message, and the destination IP address of the new message matches the routing prefix stored in the cache routing table, the processor can obtain the corresponding routing information from the cache routing table. In this way, since the data exchange speed between the processor and the cache is fast, the search speed of the routing table is improved. When the first n bits of the IP address are consistent with the routing prefix, it can be said that the IP address matches the routing prefix.

[0056] Optionally, the cache routing table may include a cache tag item and a cache data item. The cache tag item may include a routing prefix, and the cache data item may be used to store routing information. Accordingly, the correspondence between the cache tag item and the cache data item may represent the correspondence between the routing prefix and the routing information.

[0057] Considering that network devices need to determine the routing prefix that matches the destination IP address based on the longest match principle, the cache tag item can also include the length of the routing prefix (len). In this way, when the destination IP address matches multiple routing prefixes in the cached routing table at the same time, the processor can determine the routing prefix with the longest length as the routing prefix that matches the destination IP address.

[0058] For example, it is assumed that the network device has network interface A and network interface B, and the memory of the network device records the correspondence between the routing prefix 0001010* and network interface A, and the correspondence between the routing prefix 0* and network interface B.

[0059] If the network device receives message M, and the destination IP address of message M is 0001010010100010, the processor of the network device may first search the memory routing table for a routing prefix and routing information that matches the destination IP address. After determining that the destination IP address 0001010010100010 matches the routing prefix 0001011*, the processor may store the routing prefix 0001010*, the length of the routing prefix 0001010*, and the routing information corresponding to the routing prefix 0001010* (i.e., network interface A) in the cache routing table. The cache routing table may be shown in Table 1.

[0060] Table 1

[0061] Cache tag Cache data 0001010*, len=7 A

[0062] Among them, the first row of Table 1 indicates that the routing prefix 000101101* corresponds to network interface A. Therefore, the message with the first digit of the destination IP address being 0 can be forwarded through network interface A. For example, the message with the destination IP address being 0001010010100010 can be forwarded through network interface A.

[0063] If the network device receives another message N, the destination IP address of message N is 0001011010010001. Since the first 7 bits of the destination IP address are 0001011, which is inconsistent with the routing prefix 0001010*, the processor of the network device can search the memory routing table for a routing prefix that matches the destination IP address 0001011010010001. After determining that the destination IP address 0001011010010001 matches the routing prefix 0*, the processor can store the routing prefix 0*, the length of the routing prefix 0*, and the routing information corresponding to the routing prefix 0* (i.e., network interface A) in the cache routing table. The cache routing table can be shown in Table 2.

[0064] Table 1

[0065] Cache tag Cache data 0001010*, len=7 A 0*, len=1 B

[0066] If the network device receives another message with a destination IP address of 0001011011110100, since the first digit of the destination IP address is consistent with the routing prefix 0*, and the first seven digits of the destination IP address are inconsistent with the routing prefix 0001010*, the processor can determine that the message corresponds to the routing prefix 0* and forward the message through network interface B. Obviously, since the processor can obtain data from the cache quickly, storing the correspondence between some or all routing prefixes and routing information in the cache routing table can improve the speed at which the network device forwards messages.

[0067] However, because the information in the cached routing table gradually increases as packets are forwarded, the cached routing table and the memory routing table become inconsistent during this process. Therefore, if the longer of two highly similar routes has not been stored in the cached routing table, while the shorter one has, the processor may mistakenly identify the shorter one as the matching route prefix for the packet, leading to the forwarding of the packet based on the incorrect routing information. This is called a false hit.

[0068] For example, suppose the destination IP address of a message matches routing prefix X and routing prefix Y, and routing prefix X has been stored in the cache routing table, while routing prefix Y has not been stored in the cache routing table. If the length of routing prefix X is shorter than the length of routing prefix Y, the routing information corresponding to the message should theoretically be the routing information corresponding to routing prefix Y. However, after receiving the message, the processor will preferentially search the cache routing table for the routing prefix that matches the destination IP address. Since the cache routing table includes routing prefix X, the processor can find routing prefix X that matches the destination IP address from the cache routing table, thereby forwarding the message using the routing information corresponding to routing prefix X. It can be seen that since the routing prefixes stored in the cache routing table and the memory routing table are different, a false hit may occur when the network device forwards a message whose destination IP address matches multiple routing prefixes.

[0069] The following example still illustrates the case where a network device receives packets M and N. Assuming that the network device receives packet N first, the cached routing table can be as shown in Table 3:

[0070] Table 3

[0071] Cache tag Cache data 0*, len=1 B

[0072] If the network device receives packet M again, since its destination IP address is 0001010010100010, with the first bit being 0, which matches the routing prefix 0* recorded in the cached routing table, the processor will assume that packet M matches the routing prefix 0* and forward packet M using network interface B. Obviously, the network interface corresponding to packet M should actually be network interface A. Because the cached routing table contains incomplete information, false hits may occur.

[0073] In order to solve the above problem, an embodiment of the present application provides a caching method, which can record in the cache the correspondence between the first routing prefix and the destination IP address in the routing table and the routing information, which is longer than the length of the record, thereby avoiding the occurrence of false hits.

[0074] The following is a brief introduction to the terms used in this application:

[0075] Tree structure: A tree structure is a nonlinear data structure. A tree structure can include multiple nodes, each of which can be used to store data. The connection relationship between the nodes of the tree structure represents the relationship between the data stored in each node, for example, it can represent the order relationship or subordination relationship of the data. The topmost node in the tree structure is called the root node. A tree structure can include multiple subtree structures, and each subtree structure can include one or more subtree structures. The topmost node of each subtree structure can be called the root node of the subtree structure. Typical tree structures can include binary trees, ternary trees, and quadtrees.

[0076] In an embodiment of the present application, a routing prefix can be represented by a tree structure such as a binary tree, and the specific value of each bit of the routing prefix is ​​reflected by the connection relationship between two adjacent layers of nodes in the tree structure. Similarly, a routing table can also be represented by a tree structure using similar rules. For example, each routing prefix in the routing table can be represented by a tree structure, and then the root nodes of these tree structures are superimposed together. The resulting tree structure is the corresponding tree structure of the routing table. In order to distinguish the various routing prefixes in the routing table, the node corresponding to the last bit of each routing prefix can be marked as a prefix node. The tree structure corresponding to the routing table can be used to describe the distribution of prefix nodes in the routing table.

[0077] In an embodiment of the present application, the routing prefix and the routing table can be represented by a binary tree, or by a quadtree or a hexadecimal tree. The binary tree is introduced below. It should be noted that, in order to facilitate understanding, the following text uses the tree structure of the routing table as a binary tree as an example for explanation, which does not mean that the tree structure of the routing table in all embodiments of the present application is a binary tree. When the routing prefix is ​​represented by a quadtree structure, each child node corresponds to two digits in the routing prefix. For example, the four child nodes of the root node can represent "00", "01", "10" and "11" respectively. If the routing table is represented by a tree structure, the tree structure can be split into a virtual tree structure and multiple subtree structures. For an introduction to the virtual tree structure, please refer to the following text and will not be repeated here.

[0078] Binary tree: A binary tree is an ordered tree in which the degree of the nodes in the tree structure is no more than 2. That is, a binary tree has a root node, and any node in the binary tree has at most two child nodes. When a node has two child nodes, the child node on the left can be called the left child node, and the child node on the right can be called the right child node. Any node in the binary tree. A binary tree can include multiple sub-binary trees.

[0079] When a routing prefix is ​​represented by a binary tree, starting from the child nodes of the root node, each bit of the IP address corresponds to a layer of the binary tree. If a bit in the IP address is 0, the binary tree extends to the left at that layer. If a bit in the routing prefix is ​​1, the binary tree extends to the right at that layer. In other words, if the first bit of the routing prefix is ​​0, the root node of the binary tree corresponding to that routing prefix has a left child node and no right child node.

[0080] For example, the tree structure corresponding to the routing prefix 10010* can be as follows Figure 2 As shown in the figure, node 2 is the right child of root node 1, and the connection indicates that the first bit of the IP address is 1; node 3 is the left child of node 2, and the connection indicates that the second bit of the IP address is 0; node 4 is the left child of node 3, and the connection indicates that the third bit of the IP address is 0; node 5 is the right child of node 4, and the connection indicates that the fourth bit of the IP address is 1; node 6 is the left child of node 5, and the connection indicates that the fifth bit of the IP address is 0.

[0081] Similarly, when the routing table is represented by a binary tree, the routing table can be represented as follows Figure 5 As shown in the figure, this part can be found in the following text and will not be elaborated here.

[0082] Single-child node: A single-child node is a node in a binary tree that has only a left child node or only a right child node.

[0083] Leaf node: A leaf node is a node in a tree structure that has no child nodes.

[0084] Prefix node: The prefix node is the node corresponding to the routing prefix in the tree structure corresponding to the routing table.

[0085] Search path: The search path is the path from the root node in the tree structure corresponding to the routing table along the tree structure corresponding to the destination IP address to the leaf node in the tree structure corresponding to the routing table.

[0086] Tail node: The tail node is the last node in the search path.

[0087] The method provided in the embodiment of the present application can be applied to Figure 3-a The system 300 shown includes a network device 310, a network device 320, a network device 330, and a network device 340.

[0088] In the embodiment of the present application, the network device 320 includes a processor 321, a cache 322, and a memory 323. The processor 321 is a unit within the network device 320 that has data processing capabilities, for example, it can be a unit in a processor core for data processing, the cache 322 can be a high-speed storage device such as SRAM, and the memory 323 can include any one or more of internal memory and external memory.

[0089] It should be noted that Figure 3-a The cache 322 is independent of the processor 321, which does not mean that the cache provided in the embodiment of the present application must be encapsulated in the processor. In some possible implementations, the cache can also be a storage device encapsulated inside the processor. Figure 1 In the illustrated embodiment, the network device 320 includes a processor 321 and a cache 322, but this does not mean that the device provided in the embodiments of the present application can only include one processor and one cache. In some possible implementations, the device may include one or more processors, and the processor may include one or more processing units, and one or more caches. Among them, one cache may correspond to one processing unit or multiple processing units, and one processing unit may also correspond to one or more caches. The embodiments of the present application do not limit the specific architecture of the processor.

[0090] In some possible implementations, a network device may have a multi-level cache structure, that is, a plurality of storage media are used to construct caches of different levels. The higher the level of the cache, the faster the data exchange speed and the smaller the size. Then, for a computer with a multi-level cache structure, the cache in the embodiment of the present application may be a first-level cache (the first-level cache is the highest-level cache), and the memory may include other caches with a lower level than the first-level cache, such as a second-level cache, a third-level cache, etc. That is, in the embodiment of the present application, the cache is the storage device with the fastest data exchange speed, and the memory is a general term for all other storage devices with a data exchange speed lower than the cache.

[0091] In the embodiment of the present application, in order to facilitate the rapid lookup of routing table entries, the cache may further include hardware modules such as ternary content addressable memory (TCAM), registers, line card boards, and die.

[0092] The following first introduces some application scenarios of the caching method provided in the embodiment of the present application. It should be noted that the application scenarios provided in the embodiment of the present application are only some typical application scenarios, and do not mean that the caching method provided in the embodiment of the present application can only be used in these application scenarios.

[0093] See also Figure 3-b , which is a schematic diagram of the structure of a network device provided by an embodiment of the present application. Figure 3-b In the illustrated embodiment, network device 350 includes a processor 351, a TCAM 352, and a memory 353. Processor 351 is connected to TCAM 352 and memory 353, respectively. Memory 353 can be used to store a main routing table; TCAM 352 can function as a cache to store a cached routing table or search for corresponding routing information based on a destination IP address; processor 351 can be used to store routing prefixes and routing information in TCAM 352 based on the destination IP address or forward packets based on routing information found by TCAM 352.

[0094] Optionally, when the network device has multiple processors, each processor may correspond to its own TCAM, and multiple processors may correspond to the same memory. Figure 3-c , when the network device 350 also includes a processor 354, the network device 350 may also include a TCAM 355. The processor 351 is connected to the TCAM 355 and the memory 353 respectively. The TCAM 355 can be used as a cache to store the routing table used by the processor 354. Similarly, the TCAM 352 can be used to store the routing table used by the processor 351. In this way, each processor has a relatively independent TCAM for storing the routing table it needs, without having to store all the routing tables. In this way, storage space is saved, and because the content stored in the TCAM is small, the speed of the processor reading the routing table is improved. It should be noted that in Figure 3-c In the embodiment shown, the speed at which the processor 351 reads data from the TCAM 352 may not be faster than the speed at which the processor 351 reads data from the memory 353.

[0095] For the working mode of TCAM352, please refer to the description of the embodiment in Table 7 below, which will not be repeated here.

[0096] Optionally, the role played by the aforementioned TCAM can be achieved by parallel comparison logic circuits and registers. Figure 3-d , Figure 3-b In the illustrated embodiment, the function of TCAM 352 can be implemented by parallel comparison logic circuit 356 and register 357. Specifically, processor 351 is connected to parallel comparison logic circuit 356, which is in turn connected to register 357. Register 357 is used to store a routing table, and the parallel comparison logic circuit is used to determine routing information corresponding to a destination IP address.

[0097] Optionally, in Figure 3-b 、 Figure 3-c and Figure 3-d In the illustrated embodiment, processor 351 and / or processor 354 may be referred to as a processor core.

[0098] See also Figure 3-e , which is a schematic diagram of the structure of a network device provided by an embodiment of the present application. Figure 3-e In the illustrated embodiment, the network device 360 ​​includes a line card 361, a line card 362, a line card 363, a switching fabric board 364, and a switching fabric board 365. The switching fabric board 364 is connected to the line card 361, the line card 362, and the line card 363, respectively, and the switching fabric board 365 is connected to the line card 361, the line card 362, and the line card 363, respectively.

[0099] exist Figure 3-e In the illustrated embodiment, each line card may include a cache for storing the cache routing table required for use by that line card. For example, line card 361 includes cache 361-1 for storing the cache routing table required for use by line card 361; line card 362 includes cache 362-1 for storing the cache routing table required for use by line card 362; and line card 363 includes cache 363-1 for storing the cache routing table required for use by line card 363. The switching fabric board may store a routing table containing all routing information, namely the aforementioned main routing table. The main routing table may be stored in switching fabric board 364 and / or switching fabric board 365, or may be split into two parts and stored separately in switching fabric board 364 and switching fabric board 365. Optionally, the main routing table may be stored in the switching fabric board's cache.

[0100] See also Figure 3-f , which is a schematic diagram of the structure of a chip of a network device provided by an embodiment of the present application. Figure 3-f In the illustrated embodiment, chip 370 includes die 371, die 372, die 373, and die 374. Die 371 is connected to die 372 and die 374, respectively, and die 373 is connected to die 372 and die 374, respectively. Of course, in some other implementations, the dies in the chip can also be connected in other ways.

[0101] Any die in the chip may include a cache. For example, die 371 may include cache 371-1, die 372 may include cache 372-1, die 373 may include cache 373-1, and die 374 may include cache 374-1. Any one or more of caches 371-1, 372-1, 373-1, and 374-1 may be used to store a cache routing table, and any one or more of caches may be used to store a main routing table.

[0102] In actual application scenarios, multiple network devices can act as a virtual router to forward packets. For example, see Figure 3-g , which is a schematic diagram of the structure of a virtual router provided by an embodiment of the present application. Figure 3-g In the illustrated embodiment, virtual router 380 includes network device 381, network device 382, ​​network device 383, network device 384, and network device 385. Network device 383 is connected to network device 381, network device 382, ​​network device 384, and network device 385, respectively. In virtual router 380, network device 385 can be used to store a main routing table, while network device 381, network device 382, ​​network device 384, and network device 385 can each store a cache routing table required by each. Optionally, network device 383 can store the main routing table in its cache.

[0103] See also Figure 4 ,Should Figure 4 A data interaction diagram of a caching method provided in an embodiment of the present application. The caching method provided in an embodiment of the present application includes the following steps:

[0104] S401: The processor obtains a first message.

[0105] In the embodiment of the present application, the processor may be a processor in a network device. For example, the processor may be Figure 3-a The processor 321 in the network device 320 can also be a processing unit in the processor 321 for processing data. The processor can receive the first message sent by other devices through the network interface. For example, when the processor is Figure 3-a When the processor 321 is in the network device, the processor 321 can receive the first message sent by the network device 310. Of course, in some possible implementations, the processor can also receive the first message sent by the terminal device. Of course, the cache described below can be a cache in the network device, for example, Figure 3-a The cache 322 in the network device can be a memory. For example, it can be Figure 3-a Memory 323 in.

[0106] The IP address of the destination device of the first message is called the destination IP address of the first message, indicating which device the first message needs to be sent to. Then, after receiving the first message, the processor can parse the first message to determine the destination IP address of the first message.

[0107] S402: The processor searches the cache for a routing prefix that matches the destination IP address.

[0108] After determining the destination address of the first message, the processor may search the cache for a routing prefix that matches the destination IP address. For example, the processor may search the cache routing table for a routing prefix that matches the destination IP address. When there are multiple routing prefixes that match the destination IP address in the cache routing table, the processor may determine the routing prefix with the longest length as the routing prefix that matches the destination IP address. In some possible implementations, the processor may also convert the cache routing table into a corresponding tree structure such as a binary tree or a multi-branch tree, and determine the routing prefix that matches the destination IP address through the tree structure.

[0109] If the processor can find a routing prefix that matches the destination IP address in the cache, the processor can obtain the routing information corresponding to the destination IP address from the cache, thereby forwarding the first message using the routing information. If the processor cannot find a routing prefix that matches the destination IP address in the cache, it indicates that the routing prefix corresponding to the destination IP address is not stored in the cache routing table. The processor can then search the memory for a routing prefix and routing information that matches the destination IP address, and update the cache routing table based on the found routing prefix and routing information.

[0110] Optionally, before updating the cached routing table, the processor may first determine whether there is storage space in the cached routing table for storing the routing prefix and routing information. If the cached storage space is full, the processor may not update the cached routing table, or may delete the routing prefix and routing information stored in the cache, thereby using new storage space to store the new routing prefix and routing information.

[0111] The following describes a method for the processor to update the cache routing table when the cache does not include a routing prefix that matches the destination IP address.

[0112] S403: In response to the cache not storing the routing prefix, the processor searches for the prefix node and routing information corresponding to the destination IP address from the memory.

[0113] If the routing prefix corresponding to the destination IP address is not stored in the cache, the processor may search the memory for the routing prefix and routing information corresponding to the destination IP address. Alternatively, the processor may determine the routing prefix corresponding to the destination IP address using a tree structure corresponding to the routing table. The processor may then determine the prefix node corresponding to the destination IP address from the tree structure corresponding to the routing table and obtain routing information for the prefix node.

[0114] The following describes how the processor determines the prefix node.

[0115] Assume that the routing table stored in the memory is as shown in Table 4

[0116] Table 5

[0117] Route prefix Routing information 0* Network Interface X 11* Network Interface A 0000* Network Interface B 0001010* Network Interface C 00010111* Network Interface D 0001011111* Network Interface E 00010110000* Network Interface F 00010110010* Network Interface G

[0118] The schematic diagram of the attribute structure corresponding to the routing table can be as follows Figure 5 As shown. Among them, Figure 5 The numbers within each node in the table represent the node number. For example, node 2 is the prefix node for routing prefix 0*; node 2 is the prefix node for routing prefix 11*; node 7 is the prefix node for routing prefix 0000*; node 11 is the prefix node for routing prefix 0001010*; node 14 is the prefix node for routing prefix 00010111*; node 19 is the prefix node for routing prefix 0001011111*; node 20 is the prefix node for routing prefix 00010110000*; and node 21 is the prefix node for routing prefix 00010110010*.

[0119] If the destination IP address of the first message is 0001011010010001, since the destination IP address only matches the routing prefix 0*, the processor can determine that the prefix node corresponding to the destination IP address is node 2, and the corresponding routing information is network interface X. If the destination IP address of the first message is 0001010010100010, since the destination IP matches the routing prefix 0* and the routing prefix 0001010*, and the length of the routing prefix 0001010* is greater than the length of the routing prefix 0*, the processor can determine that the prefix node corresponding to the destination IP address is node 11, and the corresponding routing information is network interface C.

[0120] In actual application scenarios, the number of corresponding relationships stored in the routing table is often large, and the corresponding tree structure is also relatively complex. Therefore, in order to quickly find the prefix node corresponding to the destination IP address, the tree structure corresponding to the routing table can be split into multiple subtree structures. The tree structure composed of the root nodes of these subtree structures is called a virtual tree structure. The root node of each subtree structure corresponds to a virtual prefix. The routing prefix represented by each node in the subtree structure can be determined based on the virtual prefix and the position of the node in the virtual tree structure. For example, assuming that the virtual prefix of a subtree structure is 1000*, then the routing prefix corresponding to the right child node of the root node of the subtree structure is 10001*.

[0121] When searching for a routing prefix corresponding to a destination IP address, the processor may first search the virtual tree structure for the virtual prefix that longest matches the destination IP address, and determine the longest virtual prefix from the virtual prefixes that match the destination IP address. The processor may then determine the prefix node that matches the destination IP address from the subtree structure corresponding to the virtual prefix. If a prefix node that matches the destination IP address does not exist in the subtree corresponding to the virtual prefix, the processor may determine the prefix node corresponding to the virtual prefix as the prefix node of the destination IP address.

[0122] For example. Figure 5 The binary tree shown can be divided into three subtree structures. The root nodes of these three subtree structures are root node 1, node 6 and node 12, and the virtual prefixes are *, 00* and 0001011* respectively. Then, when the virtual tree structure is represented in the form of a table, the table can be shown in Table 6. The three subtrees can be as follows Figure 6 shown.

[0123] Table 6

[0124] Virtual prefix Prefix length Subtree information * 0 Subtree 0 00* 2 Subtree 1 0001011* 7 Subtree 2

[0125] The first row of Table 6 indicates that the virtual prefix * of length 0 corresponds to subtree 0. That is, if the destination IP address does not match any other virtual prefix in Table 6, the processor can determine the prefix node corresponding to the destination IP address from subtree 0. The second row of Table 6 indicates that the virtual prefix 00* of length 2 corresponds to subtree 1. The third row of Table 6 indicates that the virtual prefix 0001011* of length 7 corresponds to subtree 2.

[0126] Upon receiving the first message with a destination IP address of 0001010010100010, since the destination IP address has the longest match with the virtual prefix 00*, the processor can search for a prefix node that matches the destination IP address in subtree 1. Since the routing prefix of node 11 in subtree 1 is 0001010*, which matches the destination IP address, and node 11 is a prefix node, the processor can determine that the routing prefix 0001010* is the routing prefix that matches the destination IP address 0001010010100010, and node 11 is the corresponding prefix node.

[0127] Upon receiving the first packet with a destination IP address of 0001011010010001, since this destination IP address has the longest match with the virtual prefix 00*, the processor can search for a prefix node matching the destination IP address in subtree 1. Since subtree 1 does not contain a prefix node matching the destination IP address, the processor can determine the prefix node corresponding to the virtual prefix 00* as the prefix node corresponding to the destination IP address. The processor can then determine that the prefix node matching the destination IP address 0001011010010001 is node 2, and the matching routing prefix is ​​0*.

[0128] S404: The processor determines a corresponding relationship set according to the prefix node and routing information.

[0129] After determining the prefix node and routing information corresponding to the destination IP address, the processor may determine a correspondence set based on the prefix node and routing information. The correspondence set may include the correspondence between the routing prefix of the prefix node and the routing information, and may also include the correspondence between the first routing prefix and the routing information. In an embodiment of the present application, the correspondence between the first routing prefix and the routing information may be referred to as a first correspondence. Specifically, when the prefix node matching the destination IP address is a leaf node, the correspondence may include the correspondence between the routing prefix of the prefix node and the routing information; when the prefix node matching the destination IP address is not a leaf node, the correspondence may include the first correspondence. For an introduction to the first routing prefix, please refer to below.

[0130] The following describes these two situations respectively.

[0131] In a first possible implementation, the prefix node matching the destination IP address is a leaf node, that is, the tail node of the search path is a prefix node, and the processor can determine the corresponding relationship as the corresponding relationship between the routing prefix of the prefix node and the routing information.

[0132] Since leaf nodes do not have child nodes, the prefix node also does not have child nodes. In other words, among the one or more routing prefixes recorded in the routing table, there is no other routing prefix whose first n bits are the same as the routing prefix and whose length is greater than n, where n is the length of the routing prefix.

[0133] Still Figure 5For example, assuming the destination IP address is 0001010010100010, the prefix node that matches the destination IP address is node 11. Node 11 is a leaf node and has no child nodes. If node 11 has a left child node or a right child node, then the routing prefix corresponding to the left child node of node 11 is 00010100*, and the queue routing prefix corresponding to the right child node of node 11 is 00010101*. Since these two child nodes do not exist, the routing table does not include the two routing prefixes 00010100* and 00010101*, and naturally does not include other routing prefixes whose first 7 digits are 0001010 and whose length is greater than 7.

[0134] It can be seen that since there are no other routing prefixes in the routing table whose first n bits are consistent with the routing prefix of the prefix node and whose length is greater than n (n is the length of the routing prefix). Naturally, the destination IP address that matches the routing prefix of the prefix node cannot match other routing prefixes whose length is greater than n. Therefore, after the routing prefix of the prefix node is stored in the cached routing table, there will be no false hits, that is, there will be no situation where the destination IP address should have matched a routing prefix with a length greater than n, but did not match the routing prefix because the routing prefix stored in the cached routing table is not fully matched.

[0135] Then, the processor may obtain the routing information corresponding to the routing prefix of the prefix node from the memory, so as to store the corresponding relationship between the routing prefix and the routing information in the cache in a subsequent step.

[0136] In a second possible implementation, the prefix node that matches the destination IP address is not a leaf node, that is, the tail node of the search path is not a prefix node, then the correspondence set may include a first correspondence. When determining the first correspondence, the processor may first determine a first routing prefix. The first routing prefix matches the destination IP address, and its length is determined based on a first prefix matching length, which is the length from the root node of the tree structure to the tail node of the search path, that is, the number of nodes between the tail node of the search path and the root node plus 1.

[0137] In the embodiment of the present application, the length of the first routing prefix may be greater than the first prefix matching length, may be equal to the first prefix matching length, or may be less than the first prefix matching length, which will be described below.

[0138] First, the case where the first routing prefix is ​​greater than the first prefix matching length is introduced.

[0139] In the tree structure corresponding to the routing table, since the prefix node corresponding to the destination IP address is not a leaf node, this indicates that the subtree of the prefix node includes other prefix nodes. In other words, there are other routing prefixes in the cached routing table that include the routing prefix corresponding to the destination IP address, and these routing prefixes do not match the destination IP address. Therefore, to avoid false hits, the processor may determine a routing prefix that is outside the tree structure corresponding to the routing table and that matches the destination IP address as the first routing prefix.

[0140] Specifically, the processor can select a portion of the destination IP address that is longer than the first prefix matching length as the first routing prefix. The first prefix matching length is the length of the tail node of the search path from the root node of the tree structure to the destination IP address, i.e., the length of the routing prefix corresponding to the tail node. Since the prefix node corresponding to the destination IP address is not a leaf node, the tail node in the search path is not a prefix node, indicating that the tree structure corresponding to the destination IP address and the tree structure corresponding to the forwarding table differ starting from the position of the tail node. Therefore, selecting a portion of the destination IP address that is longer than the first prefix matching length as the first routing prefix ensures that the tail node corresponding to the first routing prefix is ​​outside the tree structure corresponding to the forwarding table, i.e., the first routing prefix does not overlap with any routing prefix in the tree structure corresponding to the routing table. Thus, since the first routing prefix is ​​not recorded in the routing table, it is naturally impossible to record other routing prefixes that are longer than the first routing prefix and include the first routing prefix. In other words, assuming the length of the first routing prefix is ​​n, there are no other routing prefixes in the routing table whose first n bits match the destination IP address and whose length is greater than n. Naturally, any IP address that includes the first routing prefix cannot match a routing prefix in the destination routing table that is longer than n. Therefore, after the routing prefix of the prefix node is stored in the cache routing table, no false hit will occur, that is, the destination IP address will not match a routing prefix with a length greater than n, but will not be matched to the routing prefix because the routing prefix stored in the cache routing table is not fully matched.

[0141] Still Figure 5 Let's take this as an example. Assume the destination IP address is 0001011010010001, and the routing prefix that matches the destination IP address is 0*. The search path for the destination IP address in the tree structure is "1-2-4-6-8-9-10-12-13". Its tail node is node 13, and the first prefix matching length is 8. The part of the destination IP address outside the routing table is represented by a tree structure, and the resulting tree structure can be as follows: Figure 7 As shown. Figure 5 Based on the embodiment shown, Figure 7The tree structure shown has been newly added with nodes 22, 23, 24, 25, 26, 27, packet node 28, and 29. These nodes correspond to bits 9-16 of the destination IP address, respectively. Because these nodes do not exist in the routing table's corresponding tree structure, they can be referred to as virtual nodes.

[0142] Since the virtual node is located in the part of the tree structure corresponding to the destination IP address outside the tree structure of the routing table, the routing prefix corresponding to the virtual node is greater than the first prefix matching length. Therefore, when determining the first routing prefix, the processor can determine the routing prefix corresponding to any virtual node as the first routing prefix. For example, the processor can determine the routing prefix corresponding to the virtual node directly connected to the tail node as the first routing prefix. Figure 6 In the illustrated embodiment, the processor may determine the routing prefix 000101101* corresponding to node 22 as the first routing prefix, where the length of the first routing prefix is ​​the first prefix matching length plus one. Of course, in some possible implementations, the processor may also determine the routing prefix corresponding to any other virtual node as the first routing prefix. For example, the processor may determine the routing prefix 00010110100* corresponding to node 24 as the first routing prefix.

[0143] As described above, when determining the prefix node that matches the destination IP address, the processor can first determine the virtual prefix and subtree structure corresponding to the destination IP address based on the virtual tree structure, and then determine the prefix node that matches the destination IP address based on the subtree structure. Similarly, the processor can also determine the first routing prefix based on the virtual tree structure.

[0144] Specifically, it is assumed that the first length is the length from the root node of the virtual tree structure to the virtual prefix corresponding to the destination IP address, that is, the length of the virtual prefix matching the destination IP address, and the second length is the length from the virtual prefix to the tail node of the search path, that is, the length from the root node to the tail node in the subtree structure corresponding to the destination IP address. Since the search path of the destination IP address is from the root node of the virtual tree structure to the root node of the subtree structure corresponding to the virtual prefix, and then from the root node to the tail node of the subtree structure, the sum of the first length and the second length is the first prefix matching length. When determining the first routing prefix, the processor can determine the virtual prefix as the first half of the first routing prefix, and then select a portion of the destination IP address whose length is greater than the second length as the second half of the first routing prefix.

[0145] by Figure 6The embodiment shown is used as an example for illustration. Assuming that the destination IP address is 0001011010010001, the virtual prefix that matches the destination IP address is the virtual prefix corresponding to node 12, that is, 0001011*. The processor can determine the first 7 bits of the first routing prefix as 0001011*. Since the tail node of the destination IP address in subtree 2 is node 13, the length from node 12 to node 13 is 1, that is, the second length is 1, the processor can intercept the part with a length greater than 1 starting from the 8th bit of the destination IP address as the second half of the first routing prefix. For example, the processor can use the 8th and 9th bits of the destination IP address as the second half of the first routing prefix, and the obtained first routing prefix is ​​000101101*.

[0146] The following describes a case where the length of the first routing prefix is ​​equal to the first prefix matching length.

[0147] In actual application scenarios, because routing table modifications and tree structure modifications may not be synchronized, leaf nodes in the tree structure may not be prefix nodes. Therefore, when the prefix node corresponding to the destination IP address is not a leaf node, and the tail node of the search path for the destination IP address in the tree structure is a leaf node, the processor can determine the routing prefix corresponding to the leaf node as the first routing prefix. In this way, the length of the first routing prefix can also be equal to the first prefix matching length.

[0148] Specifically, after a routing prefix is ​​deleted from the routing table, the node corresponding to that routing prefix in the tree structure (hereinafter referred to as node A) may not have been deleted. However, because the routing table has been modified, node A is no longer a prefix node. If node A has no child nodes, then node A is a leaf node in the tree structure that is not a prefix node.

[0149] For example, in Figure 5 In the illustrated embodiment, it is assumed that the routing prefix 0000* is deleted from the routing table, but the tree structure may still retain node 7. Then the node 7 is a leaf node of the non-prefix node.

[0150] After receiving the first message, if the destination IP address of the first message is 0000101010101010, the routing prefix that matches the destination IP address is 0*, the corresponding prefix node is node 2, the tail node of the search path is node 7, the routing prefix of node 7 is 0000*, and the first prefix matching length is 4. Therefore, the processor can determine the routing prefix 0000* of node 7 as the first routing prefix. Therefore, in this case, the length of the first routing prefix is ​​consistent with the first prefix matching length.

[0151] The following describes a case where the length of the first routing prefix is ​​less than the first prefix matching length.

[0152] In some possible implementations, the length of the first routing prefix may also be less than the first prefix matching length, and greater than the length of the routing prefix corresponding to the prefix node, that is, the length of the routing prefix that matches the destination IP address in the memory routing table. That is to say, the node corresponding to the first routing prefix in the tree structure is the node below the prefix node and above the tail node in the search path. In this way, although the length of the first routing prefix is ​​less than the first prefix matching length, since the length of the first routing prefix is ​​still greater than the length of the routing prefix that matches the destination IP address in the memory routing table, compared with the prior art, storing the correspondence between the first routing prefix and the routing information in the cache can still play a role in reducing the probability of false hits. It is easy to understand that the longer the length of the first routing prefix, the smaller the probability of a false hit. When the length of the first routing prefix is ​​greater than the first prefix matching length, the probability of a false hit is 0.

[0153] For example, assuming the destination IP address is 0001011010010001, the prefix node that matches the destination IP address is node 2, the corresponding routing prefix length is 1, the tail node is node 12, and the corresponding first prefix matching length is 8. Then, the processor can use the first m bits of the destination IP address as the first routing prefix, where m is a positive integer greater than 1 and less than 8. For example, the processor can determine the routing prefix 00010110* as the first routing prefix.

[0154] The above describes a method for the processor to determine the first routing prefix. After determining the first routing prefix, the processor can search for routing information from the routing table stored in the memory based on the routing prefix matching the destination IP address, and then determine the correspondence between the routing information and the first routing prefix as the first correspondence.

[0155] Optionally, when the processor determines a prefix node matching the destination IP address using a virtual tree structure, the correspondence set may further include a third correspondence. The third correspondence may include information about the virtual prefix, the type of the virtual prefix, and a subtree structure. The virtual prefix is ​​the virtual prefix that matches the destination IP address, and the subtree structure information indicates which subtree the destination IP address corresponds to. The virtual prefix type indicates that when a virtual prefix is ​​matched, the corresponding subtree structure is searched based on the subtree structure information.

[0156] That is to say, after receiving a new message, if the destination IP address of the message matches the virtual prefix stored in the cache, the processor can search the subtree structure corresponding to the virtual prefix according to the type of the virtual prefix, and thus determine the subtree structure corresponding to the virtual prefix according to the third correspondence, and then determine the routing prefix that matches the destination IP address according to the subtree structure.

[0157] To improve search efficiency, in some possible implementations, the correspondence set may further include a second correspondence, which is a correspondence between a second routing prefix and routing information, wherein the routing information is routing information of the routing prefix corresponding to the destination IP address of the first message.

[0158] The following describes a method in which the processor determines the second routing prefix.

[0159] After determining that the prefix node corresponding to the destination IP address is not a leaf node, the processor can determine all single-child nodes after the prefix node in the search path based on the tree structure, that is, nodes that only have left child nodes or right child nodes. The processor can then determine the length of the routing prefix corresponding to the single-child node as the second prefix matching length. That is, the second prefix matching length is equal to the length between the root node of the tree structure and the single-child node. The processor can then determine the second routing prefix based on the second prefix matching length and the destination IP address. Assuming the second prefix matching length is n, the processor can determine the first n digits of the destination IP address as the second routing prefix.

[0160] Since the only child node is the node after the prefix node in the search path of the destination IP address, it means that the routing prefix corresponding to any of the only child nodes is not in the cache routing table, and the prefix nodes corresponding to the messages matching the only child nodes are all prefix nodes of the destination IP address. Therefore, the routing prefixes of the IP addresses matching these only child nodes are all routing prefixes of the prefix nodes. And because the only child node is located on the search path of the destination IP address, the destination IP address includes the routing prefix of each only child node. Therefore, the second prefix matching length is determined based on the only child node, and then the second routing prefix is ​​selected from the destination IP address based on the second prefix matching length. The obtained second routing prefix matches the routing information corresponding to the prefix node of the destination IP address. Therefore, the processor can record the correspondence between the second routing prefix and the routing information as a second correspondence, and add it to the correspondence set for cache storage.

[0161] Still Figure 5The illustrated embodiment is used as an example for explanation. After receiving the first message with a destination IP address of 0001011010010001, the processor can determine that the prefix node is node 2. The tail node is node 13, and the only child nodes between the prefix node and the tail node include node 4, node 8, and node 9. The second prefix matching length corresponding to node 4 is 2, the second prefix matching length of node 8 is 4, and the second prefix matching length of node 9 is 5. Then, the processor can determine the first 2 bits, the first 4 bits, and the first 5 bits of the destination IP address as the second routing prefix, that is, the routing prefix 00*, the routing prefix 0001*, and the routing prefix 00010* are all the second routing prefix. Then, the processor can determine the correspondence between these three routing prefixes and the routing information "network interface X" corresponding to the routing prefix 0* as the second correspondence.

[0162] S405: The processor triggers the cache to store the corresponding relationship set.

[0163] After obtaining the corresponding relationship set, the processor may trigger the cache to store the corresponding relationship set. Optionally, considering the longest prefix match principle, the processor may also trigger the cache to store the length of the first routing prefix.

[0164] In addition, when the correspondence set includes a first correspondence, the processor may also trigger the cache to store the type of the first routing prefix. The type of the first routing prefix is ​​used to instruct the processor to obtain the routing information corresponding to the first routing prefix in the cache according to the first correspondence when the first routing prefix is ​​hit. That is, after receiving a new message, if the destination IP address of the message matches the first routing prefix stored in the cache, the processor may search the cache routing table for the routing information corresponding to the first routing prefix based on the type of the first routing prefix, without having to search the memory for the routing information corresponding to the first routing prefix.

[0165] The following describes the process of searching for the corresponding routing information for a TCAM destination IP address.

[0166] Assume that the TCAM serving as a cache routing table stores the correspondence between routing prefix 000101101* and network interface X, and the correspondence between routing prefix 0001011* and routing prefix 0000* and network interface B. Then, the table entries stored in the TCAM may be as shown in Table 7.

[0167] Table 7

[0168] TCAM key TCAM mask TCAM AD 000101101* 1111111110000000 Network Interface X 0000* 1111000000000000 Network Interface B

[0169] The first item in the header of Table 7 is the TCAM key, which is used to record the routing prefix to be matched. The first item in the header of Table 7 is the TCAM mask, which is used to detect the degree of match between the destination IP address and the TCAM key. The first item in the header of Table 7 is the TCAM associated data (AD), which is used to record the routing information corresponding to the TCAM key.

[0170] The first row in Table 7 indicates that the TCAM can determine whether the destination IP address of the message matches the TCAM keyword 000101101* by using the TCAM mask 11111111100000000, and after determining that the destination IP address and TCAM keyword 000101101* match, the message is sent through network interface X. The second row in Table 7 indicates that the TCAM can determine whether the destination IP address of the message matches the TCAM keyword 0000* by using the TCAM mask 1111000000000000, and after determining that the destination IP address and TCAM keyword 0000* match, the message is sent through network interface B.

[0171] To determine whether a packet's destination IP address matches a TCAM keyword, the TCAM performs a bit-by-bit AND operation on the TCAM mask and the destination IP address. It also performs a bit-by-bit AND operation on the TCAM keyword and the TCAM mask. Finally, the two results are compared bit by bit to ensure they are identical. If they match, the TCAM determines that the destination IP address matches the TCAM keyword and routes the packet according to the routing information stored in the TCAM association data.

[0172] For example, if the network device receives a packet with a destination IP address of 0001011010010001, the processor can perform a bit-by-bit AND operation on the destination IP address 0001011010010001, the TCAM keyword 1111111110000000 and the TCAM mask 1111000000000000.

[0173] When performing a bit-by-bit AND operation, if the value of a bit in both the destination IP address and the TCAM mask is 1, the result is 1; otherwise, the result is 0. For example, if the first bit of the destination IP address is 0 and the first bit of the TCAM mask 1111111110000000 is 1, the result of the AND operation is 0. If the fourth bit of the destination IP address is 1 and the fourth bit of the TCAM mask 1111111110000000 is 1, the result of the AND operation is 1.

[0174] Similarly, the result of a bit-by-bit AND operation of the destination IP address 0001011010010001 and the TCAM mask 1111111110000000 is 0001011010000000. The result of a bit-by-bit AND operation of the destination IP address 0001011010010001 and the TCAM mask 1111000000000000 is 0001000000000000. Similarly, the result of a bit-by-bit AND operation of the TCAM keyword 000101101* and the TCAM mask 11111111100000000 is 00010110100000000. The result of a bit-by-bit AND operation of the TCAM keyword 0000* and the TCAM mask 11111111100000000 is 000000000000000000.

[0175] Then, because the result of the destination IP address operation is exactly the same as the result of the TCAM keyword 000101101* operation, the TCAM can determine that the destination IP address matches the routing prefix 000101101* and thus send the packet through network interface X. Because the result of the destination IP address operation is inconsistent with the result of the TCAM keyword 0000* operation, the TCAM can determine that the destination IP address does not match the routing prefix 0000* and therefore does not send the packet through network interface B.

[0176] See also Figure 8 The present application also provides an integrated circuit 800, which can realize Figure 4 The functions of the processor in the embodiment shown. The integrated circuit includes an interface circuit 801 and a control circuit 802. The control circuit 802 is connected to the interface circuit 801 via a communication line 803. The interface circuit 801 is used to connect the integrated circuit 800 to other devices via a communication link. Figure 4 In the embodiment shown in FIG. 401, S402, S403 and S405, the control circuit 802 is used to implement Figure 4 In the embodiment shown, S402, S403, S404 and S405.

[0177] Specifically, the interface circuit 801 is used to obtain a first message, where the first message includes a destination Internet Protocol (IP) address.

[0178] The control circuit 802 is used to search the cache for a routing prefix that matches the destination IP address; in response to the routing prefix not being stored in the cache, search the tree structure corresponding to the routing table according to the destination IP address, and determine the prefix node that matches the destination IP address; in response to the prefix node not being a leaf node, determine a first prefix matching length, the first prefix matching length being equal to the length from the root node to the tail node of the tree structure, the tail node being the last node on the search path of the tree structure; determine a first routing prefix based on the first prefix matching length and the destination IP address; and trigger the cache to store a first corresponding relationship, the first corresponding relationship being the first routing prefix and the routing information corresponding to the prefix node.

[0179] Please refer to the above for the specific execution process Figure 4 The detailed description of the corresponding steps in the illustrated embodiment will not be repeated here one by one.

[0180] Optionally, the integrated circuit 800 provided in the embodiment of the present application may further include a cache. The interface circuit 801 and the control circuit 802 in the integrated circuit 800 may be one or more.

[0181] Exemplarily, the integrated circuit 600 may be an FPGA, an ASIC, a system on chip (SoC), a CPU, an NP, a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0182] See also Figure 9 The embodiment of the present application further provides a device 900, which can implement Figure 4 The function of the processor in the embodiment shown. The cache device 900 includes an acquisition unit 901 and a processing unit 902. The acquisition unit 901 is used to implement Figure 4 In the embodiment shown in S401, the processing unit 402 is used to implement Figure 4 S402, S403, S404 and S405 in the illustrated embodiment.

[0183] Specifically, the acquiring unit 901 is configured to acquire a first message, where the first message includes a destination Internet Protocol (IP) address.

[0184] Processing unit 902 is used to search for a routing prefix that matches the destination IP address from the cache; in response to the routing prefix not being stored in the cache, search the tree structure corresponding to the routing table according to the destination IP address, and determine the prefix node that matches the destination IP address; in response to the prefix node not being a leaf node, determine a first prefix matching length, the first prefix matching length being equal to the length from the root node to the tail node of the tree structure, the tail node being the last node on the search path of the tree structure; determine a first routing prefix based on the first prefix matching length and the destination IP address; trigger the cache to store a first corresponding relationship, the first corresponding relationship being the first routing prefix and the routing information corresponding to the prefix node.

[0185] Please refer to the above for the specific execution process Figure 4 The detailed description of the corresponding steps in the illustrated embodiment will not be repeated here one by one.

[0186] It should be noted that the division of units in the embodiments of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The functional units in the embodiments of the present application can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. For example, in the above embodiment, the acquisition unit and the processing unit can be the same unit or different units. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0187] See also Figure 10 The present application also provides a chip 1000, which can realize Figure 4 The chip includes a memory 1001 and a processor 1002. The memory 1001 is used to store instructions or program codes, and the processor 1002 is used to call and execute instructions or program codes from the memory 1001 to implement Figure 4 S401, S402, S403, S404 and S405 in the illustrated embodiment.

[0188] Optionally, the processor 1002 may be Figure 8 The integrated circuit 800 shown in FIG. 1 may include a cache memory. When the processor 1002 does not include a cache memory, the memory 1001 may include a cache memory.

[0189] Figure 11 1 is a schematic diagram of the structure of a device 1100 provided in an embodiment of the present application. The device where the processor is located can be located at Figure 11 See the device shown. Figure 11The device 1100 includes at least one processor chip 1101 and at least one memory 1102. Optionally, the device 1100 may further include a communication bus 1103 and at least one network interface 1104.

[0190] The processor chip 1101 can be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits (ICs) for controlling the execution of the program of the present application. The processor chip 1101 can be used to implement the data caching method provided in the embodiments of the present application.

[0191] For example, when Figure 1 The network devices in Figure 11 When implemented by the device shown, the processor can be used to obtain a first message, the first message including a destination Internet Protocol IP address; search a routing prefix matching the destination IP address from a cache; in response to the routing prefix not being stored in the cache, search a tree structure corresponding to a routing table according to the destination IP address, and determine a prefix node matching the destination IP address; in response to the prefix node not being a leaf node, determine a first prefix matching length, the first prefix matching length being equal to the length from a root node to a tail node of the tree structure, the tail node being the last node on the search path of the tree structure; determine a first routing prefix based on the first prefix matching length and the destination IP address; and trigger the cache to store a first corresponding relationship, the first corresponding relationship being the first routing prefix and routing information corresponding to the prefix node.

[0192] Optionally, the processor chip 1101 may be Figure 10 The chip 1000 in the embodiment shown may also be Figure 8 In the embodiment shown, the integrated circuit 800. When the processor chip 1101 does not include a cache, the memory 1102 may include a cache, an internal memory, and an external memory; when the processor chip 1101 includes a cache, the memory 1102 may include an internal memory and an external memory.

[0193] The memory 1102 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions. The memory 1102 may also be a random access memory (RAM) or other type of dynamic storage device that can store information and instructions. It may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1102 may be independent and connected to the processor 1101 via a communication bus 1103. The memory 1102 may also be integrated with the processor 1101. Optionally, the memory 1102 may include a cache.

[0194] Optionally, the memory 1102 is used to store program codes or instructions for executing the solution of the present application, and the execution is controlled by the processor 1101. The processor 1101 is used to execute the program codes or instructions stored in the memory 1102. The program code may include one or more software modules. Optionally, the processor 1101 may also store program codes or instructions for executing the solution of the present application. In this case, the processor 1101 does not need to read the program codes or instructions from the memory 1102.

[0195] Optionally, the memory 1102 may be used to implement Figure 1 The role of the memory 120 in the device shown.

[0196] The communication bus 1103 is used to transmit information between the processor chip 1101 , the network interface 1104 and the memory 1102 .

[0197] The network interface 1104 can be a device such as a transceiver for communicating with other devices or communication networks, and the communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). In an embodiment of the present application, the network interface 904 can be used to receive messages sent by other nodes in the segment routing network, and can also send messages to other nodes in the segment routing network. The network interface 1104 can be an Ethernet interface, a Fast Ethernet (FE) interface, or a Gigabit Ethernet (GE) interface.

[0198] In a specific implementation, as an embodiment, the device 1100 may include multiple processor chips, such as Figure 9 The processor chip 1101 and the processor chip 1105 shown in FIG. Each of these processor chips can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Optionally, Figure 4 Different steps in the illustrated cache method may be performed by different processor chips, where a processor chip may refer to one or more devices, circuits, and / or processing cores for processing data (eg, computer program instructions).

[0199] Figure 12 It is a structural diagram of a device 1200 provided in an embodiment of the present application. Figure 1 The device 100 can be Figure 12 See the device shown. Figure 12As shown in the device structure diagram, device 1200 includes a main control board and one or more interface boards. The main control board is in communication with the interface boards. The main control board, also known as a main processing unit (MPU) or route processor card, includes a CPU and memory. The main control board is responsible for controlling and managing various components in device 1200, including routing calculations, device management, and maintenance. The interface board, also known as a line processing unit (LPU) or line card, is used to receive and send messages. In some embodiments, communication between the main control board and the interface boards, or between the interface boards, occurs via a bus. In some embodiments, communication between the interface boards occurs via a switching fabric board (SFB). In this case, device 1200 also includes a SFB, which is in communication with the main control board and the interface boards. The SFB is used to forward data between the interface boards and is also referred to as a switch fabric unit (SFU). The interface board includes a CPU, memory, a forwarding engine, and an interface card (IC), where the interface card may include one or more network interfaces. The network interface can be an Ethernet interface, a FE interface, or a GE interface. The CPU is communicatively connected to the memory, the forwarding engine, and the interface card. The memory is used to store a forwarding table. The forwarding engine is used to forward received messages based on the forwarding table stored in the memory. If the destination address of the received message is the IP address of device 1200, the message is sent to the CPU of the main control board or interface board for processing. If the destination address of the received message is not the IP address of device 1200, the forwarding table is searched based on the destination address. If the next hop and outgoing interface corresponding to the destination address are found in the forwarding table, the message is forwarded to the outgoing interface corresponding to the destination address. The forwarding engine can be a network processor (NP). The interface card, also known as a daughter card, can be installed on the interface board and is responsible for converting optical signals into data frames, performing a validity check on the data frames, and forwarding them to the forwarding engine or the interface board CPU for processing. In some embodiments, the CPU can also perform the functions of the forwarding engine, such as implementing soft forwarding based on a general-purpose CPU, thereby eliminating the need for a forwarding engine on the interface board. In some embodiments, the forwarding engine can be implemented using an ASIC or a field programmable gate array (FPGA). In some embodiments, the memory storing the forwarding table may also be integrated into the forwarding engine as a part of the forwarding engine.

[0200] Optionally, there may be one or more processors in the chip system. The processor may be implemented by hardware or by software. When implemented by hardware, the processor may be a logic circuit, an integrated circuit, or the like. When implemented by software, the processor may be a general-purpose processor implemented by reading software code stored in a memory. Optionally, there may be one or more memories in the chip system. The memory may be integrated with the processor or may be separately provided from the processor, which is not limited in this application. Exemplarily, the memory may be a non-transient processor, such as a read-only memory ROM, which may be integrated with the processor on the same chip or may be provided on different chips. This application does not specifically limit the type of memory or the manner in which the memory and the processor are provided.

[0201] Exemplarily, the chip system can be an FPGA, an ASIC, a system on chip (SoC), a CPU, an NP, a digital signal processing circuit (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0202] It should be understood that each step in the above method embodiment can be completed by hardware integrated logic circuits in a processor or by software instructions. The method steps disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor, or by a combination of hardware and software modules in a processor.

[0203] An embodiment of the present application also provides a computer-readable storage medium, including instructions, which, when executed on a computer, enables the computer to execute the caching method provided by the above method embodiment and executed by a processor.

[0204] An embodiment of the present application also provides a computer program product containing instructions, which, when executed on a computer, enables the computer to execute the cache method provided by the above method embodiment and executed by a processor.

[0205] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0206] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0207] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical module division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0208] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be obtained based on actual needs to achieve the objectives of this embodiment.

[0209] In addition, each module unit in each embodiment of the present application can be integrated into a processing unit, each unit can exist physically separately, or two or more units can be integrated into a single unit. The above-mentioned integrated units can be implemented in the form of hardware or software module units.

[0210] If the integrated unit is implemented in the form of a software module unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0211] Those skilled in the art will appreciate that in one or more of the above examples, the functions described herein can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0212] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are merely specific implementation methods of the present invention.

[0213] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A caching method, characterized in that: The method comprises: The processor obtains a first message, where the first message includes a destination Internet Protocol (IP) address; The processor searches a cache for a routing prefix that matches the destination IP address; In response to the routing prefix not being stored in the cache, the processor searches a tree structure corresponding to a routing table according to the destination IP address to determine a prefix node that matches the destination IP address; In response to the prefix node not being a leaf node, the processor determines a first prefix matching length, where the first prefix matching length is equal to a length from a root node to a tail node of the tree structure, where the tail node is a last node on a search path of the tree structure; The processor determines a first routing prefix based on the first prefix matching length and the destination IP address; The processor triggers the cache to store a first corresponding relationship, where the first corresponding relationship is the first routing prefix and routing information corresponding to the prefix node.

2. The method according to claim 1, characterized in that The length of the first routing prefix is ​​greater than or equal to the first prefix matching length.

3. The method according to claim 1 or 2, characterized in that The processor searches a tree structure corresponding to the routing table according to the destination IP address, and determines that a prefix node matching the destination IP address includes: The processor searches the virtual tree structure corresponding to the routing table according to the destination IP address and determines the virtual prefix that has the longest match with the destination IP address; The processor searches for a subtree structure corresponding to the virtual prefix according to the destination IP address, and determines a prefix node that matches the destination IP address, where the virtual prefix is ​​a root node of the subtree structure; The first prefix matching length is equal to the sum of a first length and a second length, where the first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the length from the virtual prefix to the tail node, where the tail node is the last node on the search path of the subtree structure.

4. The method according to claim 1 or 2, characterized in that The method further comprises: In response to the prefix node not being a leaf node, the processor determines a second prefix matching length, where the second prefix matching length is equal to a length between a root node and a single child node of the tree structure, where the single child node is a node between the prefix node and the tail node that has only a left child node or only a right child node; The processor determines a second routing prefix according to the second prefix matching length and the destination IP address, where the length of the second routing prefix is ​​greater than the second prefix matching length; The processor triggers the cache to store a second corresponding relationship, where the second corresponding relationship is routing information corresponding to the second routing prefix and the prefix node.

5. The method according to any one of claims 1-2, characterized in that The method further comprises: The processor triggers the cache to store a type of the first routing prefix, where the type of the first routing prefix is ​​used to indicate that when the first routing prefix is ​​hit, routing information corresponding to the first routing prefix is ​​obtained from the cache according to the first corresponding relationship.

6. The method according to claim 3, characterized in that The method further comprises: The processor triggers the cache to store a third correspondence, where the third correspondence is a correspondence between the virtual prefix, the type of the virtual prefix, and the information of the subtree structure, and the type of the virtual prefix is ​​used to indicate that when the virtual prefix is ​​hit, the subtree structure is searched according to the information of the subtree structure.

7. The method according to any one of claims 1-2, characterized in that The method further comprises: The processor triggers the cache to store the length of the first routing prefix.

8. The method according to claim 2, characterized in that The length of the first routing prefix is ​​equal to the first prefix matching length plus 1.

9. The method according to any one of claims 1-2, characterized in that The length of the first routing prefix is ​​smaller than the length of the destination IP address.

10. The method according to any one of claims 1-2, characterized in that The destination IP address includes the first routing prefix.

11. The method according to any one of claims 1 to 2, characterized in that: The cache includes at least one of the following: TCAM, registers, line cards, and dies.

12. An integrated circuit, characterized in that: The integrated circuit includes an interface circuit and a control circuit; The interface circuit is configured to obtain a first message, wherein the first message includes a destination Internet Protocol (IP) address; The control circuit is configured to search a cache for a routing prefix that matches the destination IP address; in response to the routing prefix not being stored in the cache, search a tree structure corresponding to a routing table according to the destination IP address, and determine a prefix node that matches the destination IP address; in response to the prefix node not being a leaf node, determine a first prefix matching length, where the first prefix matching length is equal to the length from a root node to a tail node of the tree structure, where the tail node is the last node on a search path of the tree structure; determine a first routing prefix based on the first prefix matching length and the destination IP address; and trigger the cache to store a first corresponding relationship, where the first corresponding relationship is the first routing prefix and routing information corresponding to the prefix node.

13. The integrated circuit according to claim 12, wherein: The length of the first routing prefix is ​​greater than or equal to the first prefix matching length.

14. The integrated circuit according to claim 12 or 13, characterized in that The control circuit is configured to search a virtual tree structure corresponding to the routing table according to the destination IP address, and determine a virtual prefix that has the longest match with the destination IP address; search a subtree structure corresponding to the virtual prefix according to the destination IP address, and determine a prefix node that matches the destination IP address, wherein the virtual prefix is ​​a root node of the subtree structure; The first prefix matching length is equal to the sum of a first length and a second length, where the first length is the length from the root node of the virtual tree structure to the virtual prefix, and the second length is the length from the virtual prefix to the tail node, where the tail node is the last node on the search path of the subtree structure.

15. The integrated circuit according to claim 12 or 13, characterized in that The control circuit is further configured to, in response to the prefix node not being a leaf node, determine a second prefix matching length, wherein the second prefix matching length is equal to a length between a root node and a single child node of the tree structure, the single child node being a node between the prefix node and the tail node that has only a left child node or only a right child node; Determine a second routing prefix according to the second prefix matching length and the destination IP address, where the length of the second routing prefix is ​​greater than the second prefix matching length; The cache is triggered to store a second corresponding relationship, where the second corresponding relationship is routing information corresponding to the second routing prefix and the prefix node.

16. The integrated circuit according to any one of claims 12 to 13, characterized in that: The control circuit is further used to trigger the cache to store the type of the first routing prefix, where the type of the first routing prefix is ​​used to indicate that when the first routing prefix is ​​hit, routing information corresponding to the first routing prefix is ​​obtained in the cache according to the first corresponding relationship.

17. The integrated circuit according to claim 14, wherein: The control circuit is also used to trigger the cache to store a third correspondence, where the third correspondence is a correspondence between the virtual prefix, the type of the virtual prefix, and the information of the subtree structure, and the type of the virtual prefix is ​​used to indicate that when the virtual prefix is ​​hit, the subtree structure is searched according to the information of the subtree structure.

18. The integrated circuit according to any one of claims 12 to 13, characterized in that: The control circuit is further configured to trigger the cache to store the length of the first routing prefix.

19. The integrated circuit according to claim 13, wherein: The length of the first routing prefix is ​​equal to the first prefix matching length plus 1.

20. The integrated circuit according to any one of claims 12 to 13, characterized in that: The length of the first routing prefix is ​​smaller than the length of the destination IP address.

21. The integrated circuit according to any one of claims 12 to 13, characterized in that: The destination IP address includes the first routing prefix.

22. The integrated circuit according to any one of claims 12 to 13, characterized in that: The cache includes at least one of the following: TCAM, registers, line cards, and dies.

23. A chip, characterized in that: The chip includes a memory and a processor, the memory is used to store instructions or program codes, and the processor is used to call and run the instructions or program codes from the memory to execute the caching method according to any one of claims 1 to 11.

24. A device, characterized in that The device includes a processor chip and a memory, the memory is used to store instructions or program codes, and the processor chip is used to call and run the instructions or program codes from the memory to execute the caching method according to any one of claims 1-11.

25. A computer-readable storage medium, characterized in that The method comprises instructions, programs or codes, which, when executed on a computer, enable the computer to execute the caching method according to any one of claims 1 to 11.

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