Three-dimensional memory and methods of making the same
By employing a single-layer silicon oxide insulating layer and selective etching process in the three-dimensional memory, the problems of large thickness, large volume and complex fabrication of the three-dimensional memory are solved, resulting in cost reduction and process simplification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-05-27
- Publication Date
- 2026-05-22
AI Technical Summary
Existing 3D memory devices have composite multilayer insulating layers, resulting in large device thickness, large size, complex fabrication process, and high cost.
A single-layer insulating layer structure is adopted, including a first insulating layer of silicon oxide material, and the contact and connection layers are formed by processes such as selective etching and chemical mechanical polishing, which simplifies the preparation process.
This reduces the thickness and volume of the 3D memory, lowers the manufacturing cost, and improves the efficiency and yield of the manufacturing process.
Smart Images
Figure CN115206989B_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese patent application No. 202110588023.9, filed on May 27, 2021, entitled "Three-dimensional memory and preparation method thereof". Technical Field
[0002] This invention relates to the field of semiconductor device technology, and in particular to a three-dimensional memory and its fabrication method. Background Technology
[0003] Three-dimensional memory comprises stacked insulating layers, source layers, and stacked structures, with the source layers located between the insulating layers and the stacked structures. However, existing insulating layers are composite multilayers, which not only results in larger thickness and volume of the three-dimensional memory but also complicates the fabrication process and increases costs. Summary of the Invention
[0004] The purpose of this invention is to provide a three-dimensional memory and its fabrication method, so as to solve the technical problems of complex fabrication process and high cost of three-dimensional memory.
[0005] This invention provides a three-dimensional memory, comprising: a stacked first insulating layer, a source layer, and a stacked structure, wherein the source layer is located between the first insulating layer and the stacked structure, and the stacked structure includes alternately stacked conductive layers and interlayer insulating layers; a channel structure passing through the stacked structure; and a connecting layer located on the side of the first insulating layer opposite to the stacked structure, having a protrusion that passes through the first insulating layer and is electrically connected to the source layer; wherein the first insulating layer is a single insulating layer, and the first insulating layer is in contact with both the connecting layer and the source layer.
[0006] The material of the first insulating layer includes silicon oxide.
[0007] It also includes: a grounding structure located on the side of the source layer opposite to the stacked structure, the grounding structure passing through the first insulating layer, and its two ends being electrically connected to the source layer and the connection layer, respectively.
[0008] The grounding structure and the source layer are made of the same material.
[0009] It also includes: a second insulating layer covering the stacked structure and the source layer; and a first contact that passes through the second insulating layer, the source layer and the first insulating layer, and is electrically connected to the connection layer.
[0010] It also includes a second contact that passes through the second insulating layer and is connected to the conductive layer of the stacked structure.
[0011] It also includes: an interconnect structure located on the side of the stacked structure away from the source layer, the interconnect structure being electrically connected to the channel structure.
[0012] It also includes: peripheral circuitry located on the side of the interconnect structure away from the stacked structure and electrically connected to the interconnect structure.
[0013] This invention provides a method for fabricating a three-dimensional memory, comprising: providing a first insulating layer, a source layer, and a stacked structure, wherein the source layer is located between the first insulating layer and the stacked structure, the first insulating layer is a single insulating layer, and the stacked structure includes alternately stacked conductive layers and interlayer insulating layers; forming a channel structure through the stacked structure on the stacked structure; forming a connecting layer on the side of the first insulating layer opposite to the stacked structure, wherein the connecting layer has a protrusion that passes through a second insulating layer and is electrically connected to the source layer; and the first insulating layer is in contact with both the connecting layer and the source layer.
[0014] Wherein, a functional layer is stacked on the side of the first insulating layer away from the source layer. Before forming the connection layer, the preparation method further includes: covering the source layer and the stacked structure with a second insulating layer; forming a first contact in the second insulating layer, the source layer and the first insulating layer, wherein the first contact does not extend into the functional layer.
[0015] The functional layer is a substrate, and the first contact does not extend into the substrate.
[0016] The functional layer includes a substrate and an etch stop layer. The substrate is formed on the side of the first insulating layer away from the source layer. The etch stop layer is formed between the first insulating layer and the substrate. The first contact does not extend into the etch stop layer.
[0017] The functional layer further includes an oxide layer, which is stacked between the etch stop layer and the substrate.
[0018] Wherein, "the first contact does not extend into the functional layer" includes: the first contact is flush with the surface of the first insulating layer facing the functional layer, or there is a preset distance between the first contact and the surface of the first insulating layer facing the functional layer.
[0019] The preset distance is between 30nm and 40nm.
[0020] The phrase "forming a first contact within the second insulating layer, the source layer, and the first insulating layer" includes: selectively etching the second insulating layer, the source layer, and the first insulating layer to form a contact hole, wherein the contact hole does not extend into the functional layer; and forming contact material within the contact hole to form the first contact.
[0021] The method further includes, after forming the first contact, removing a portion of the substrate from the surface of the substrate away from the first insulating layer to form a reference substrate, wherein the thickness of the reference substrate is less than the thickness of the substrate; and removing the reference substrate.
[0022] Wherein, “removing the reference substrate” includes: when removing the reference substrate, removing a portion of the structure of the first contact point, such that the first contact point with the portion of the structure removed does not protrude from the surface of the first insulating layer away from the source layer.
[0023] The "removal of the reference substrate" includes: removing the reference substrate by chemical mechanical polishing.
[0024] Wherein, the source layer has an initial ground structure on the side opposite to the stacked structure, the initial ground structure extends into the functional layer after passing through the first insulating layer; "removing the reference substrate" includes: when removing the reference substrate, removing part of the structure of the initial ground structure to form a ground structure, the ground structure being flush with the first insulating layer.
[0025] The fabrication method further includes, after removing the substrate, forming a via on the first insulating layer, the via exposing the source layer; and forming a connection layer on the side of the first insulating layer away from the stacked structure, which includes forming a protrusion in the via during the formation of the connection layer, the protrusion being connected to the source layer.
[0026] The phrase "forming a first contact within the second insulating layer, the source layer, and the first insulating layer" includes: when forming the first contact, forming a second contact within the second insulating layer, wherein the second contact is connected to the conductive layer of the stacked structure.
[0027] Wherein, the first contact and the second contact are made of tungsten, the connecting layer is made of aluminum, the substrate is made of polycrystalline silicon, the etch stop layer is made of silicon nitride, and the first insulating layer and the second insulating layer are made of homogeneous silicon dioxide.
[0028] The fabrication method further includes, before removing the substrate, forming an interconnect structure on the side of the stacked structure opposite to the source layer, wherein the interconnect structure is electrically connected to the channel structure.
[0029] The fabrication method further includes, after forming the interconnect structure, forming a peripheral circuit on the side of the interconnect structure opposite to the stacked structure, wherein the peripheral circuit is electrically connected to the interconnect structure.
[0030] In summary, this application significantly reduces the thickness and volume of the 3D memory by setting the first insulating layer to a single layer. It also simplifies the fabrication process and lowers costs. This application solves the technical problem that existing multi-layered insulating layers not only result in thicker and larger 3D memories but also complicate the fabrication process and increase costs. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic diagram of a three-dimensional memory provided in an embodiment of the present invention.
[0033] Figure 2 This is a schematic flowchart of a method for fabricating a three-dimensional memory according to an embodiment of the present invention.
[0034] Figure 3 This is a schematic diagram of the initial structure of another type of three-dimensional memory.
[0035] Figure 4 Yes Figure 3 The substrate in the middle is thinned to obtain a schematic diagram of the reference substrate structure.
[0036] Figure 5 It is to remove Figure 4 A schematic diagram of the reference substrate.
[0037] Figure 6 Is Figure 5 A schematic diagram of the structure in which vias are formed on the etch stop layer and oxide layer.
[0038] Figure 7 Is Figure 6 A schematic diagram of a connecting layer formed on the oxide layer.
[0039] Figure 8 yes Figure 1 A schematic diagram of the initial structure of the three-dimensional memory.
[0040] Figure 9 Yes Figure 8 The substrate in the middle is thinned to obtain a schematic diagram of the reference substrate structure.
[0041] Figure 10 It is to remove Figure 9 A schematic diagram of the reference substrate.
[0042] Figure 11 Is Figure 10 A schematic diagram of a via formed on the first insulating layer. Detailed Implementation
[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0044] Please see Figure 1 , Figure 1 This invention provides a three-dimensional memory. By setting the first insulating layer 202 as a single insulating layer, the thickness of the three-dimensional memory is greatly reduced, the volume of the three-dimensional memory is smaller, and the fabrication process of the three-dimensional memory is simplified, thereby reducing costs.
[0045] The three-dimensional memory includes:
[0046] The stacked structure includes a first insulating layer 202, a source layer 101, and a stacked structure. The source layer 101 is located between the first insulating layer 202 and the stacked structure. The stacked structure includes alternately stacked conductive layers 103 and interlayer insulating layers. The material of the interlayer insulating layer can be silicon oxide.
[0047] A channel structure 107 passes through the stacked structure; the channel structure 107 includes a charge storage layer and a channel layer. The charge storage layer includes a barrier insulating layer, a charge trapping layer, and a tunneling insulating layer along the sidewalls of the channel aperture toward the center of the aperture. An exemplary material for the barrier insulating layer and the tunneling insulating layer is silicon oxide, and an exemplary material for the charge trapping layer is silicon nitride. The charge storage layer forms a silicon oxide-silicon nitride-silicon oxide (ONO) stacked structure. An exemplary material for the channel layer is silicon (Si). Other materials may be selected for the barrier insulating layer, the charge trapping layer, and the tunneling insulating layer, and are not limited herein.
[0048] The connecting layer 270 is located on the side of the first insulating layer 202 away from the stacked structure and has a protrusion 280 that passes through the first insulating layer 202 and is electrically connected to the source layer 101. The first insulating layer 202 is a single insulating layer and is in contact with both the connecting layer 270 and the source layer 101. The connecting layer 270 is made of aluminum.
[0049] In this application, by setting the first insulating layer 202 as a single-layer insulating layer, the thickness of the three-dimensional memory is greatly reduced, the volume of the three-dimensional memory is smaller, and the fabrication process of the three-dimensional memory is simplified, thus reducing costs. This application solves the technical problem that existing insulating layers are composite multilayers, which not only result in a larger thickness and volume of the three-dimensional memory, but also complicate the fabrication process and increase costs.
[0050] In one specific embodiment, the material of the first insulating layer 202 includes silicon oxide.
[0051] In one specific embodiment, the three-dimensional memory further includes: a ground structure 240 located on the side of the source layer 101 facing away from the stacked structure, the ground structure 240 passing through the first insulating layer 202, and its two ends being electrically connected to the source layer 101 and the connection layer 270, respectively.
[0052] In this application, the grounding structure 240 is electrically connected to the source layer 101 and the connection layer 270 respectively, and can conduct the charge on the source layer 101 to the outside through the connection layer 270.
[0053] In one specific embodiment, the grounding structure 240 and the source layer 101 are made of the same material. In this application, by making the grounding structure 240 and the source layer 101 the same material, the charge on the source layer 101 can be quickly discharged, preventing charge breakdown of the 3D memory. Optionally, the grounding structure 240 can be formed together with the source layer 101. Both the grounding structure 240 and the source layer 101 can be made of polysilicon.
[0054] In one specific embodiment, the three-dimensional memory further includes:
[0055] A second insulating layer 102 covering the stacked structure and the source layer 101;
[0056] The first contact 40 passes through the second insulating layer 102, the source layer 101, and the first insulating layer 202, and is electrically connected to the connection layer 270. It can be understood that the first contact 40 is flush with the connection layer 270, or that there is a predetermined distance between the first contact 40 and the connection layer 270, with a portion of the connection layer 270 extending into the contact hole 30 where the first contact 40 is located and connecting to the first contact 40. Optionally, the second insulating layer 102 is made of silicon oxide. The first contact 40 can be made of tungsten (W).
[0057] In this application, by setting the first contact 40 to be connected to the connection layer 270, the connection layer 270 can be connected to other structures of the three-dimensional memory through the first contact 40.
[0058] In one specific embodiment, the three-dimensional memory further includes:
[0059] The second contact 104 passes through the second insulating layer 102 and connects to the conductive layer 103 of the stacked structure. It is understood that the conductive layer 103 is stepped, and there are multiple second contacts 104 connected to the stepped conductive layer 103. The material of the second contact 104 can be tungsten (W).
[0060] In this application, by setting the second contact 104 to be connected to the conductive layer 103, the conductive layer 103 can be connected to other structures of the three-dimensional memory through the second contact 104.
[0061] In one specific embodiment, the three-dimensional memory further includes:
[0062] Interconnect structure 290 is located on the side of the stacked structure opposite to the source layer 101, and is electrically connected to the channel structure 107. It is understood that interconnect structure 290 is also formed within the second insulating layer 102. Interconnect structure 290 includes pads 70, conductive channels 80, and wiring 50 connected in sequence. Pads 70 are connected to the channel structure 107, and wiring 50 is electrically connected to other structures of the 3D memory, such as connections to peripheral circuitry described below.
[0063] In this application, by setting up the interconnect structure 290, the channel structure 107 is electrically connected to other structures of the three-dimensional memory, such as the connection with the peripheral circuits described below.
[0064] In one specific embodiment, the three-dimensional memory further includes:
[0065] The peripheral circuit 60 is located on the side of the interconnect structure 290 opposite to the stacked structure and is electrically connected to the interconnect structure 290. In this application, the peripheral circuit 60 supplies power to the channel structure 107 through the interconnect structure 290.
[0066] Please see Figure 2 In addition to the aforementioned three-dimensional memory, embodiments of the present invention also provide a method for fabricating a three-dimensional memory. Both the three-dimensional memory and the method for fabricating the three-dimensional memory of the present invention can achieve the advantages of the present invention; they can be used together or used alone, and the present invention does not particularly limit this. In a specific embodiment, the method for fabricating the three-dimensional memory is as follows.
[0067] Please see Figure 2 , Figure 2 This invention provides a method for fabricating a three-dimensional memory. By setting the first insulating layer 202 as a single-layer insulating layer, the thickness of the three-dimensional memory is significantly reduced, resulting in a smaller volume. Furthermore, the fabrication process is simplified, lowering costs. This invention solves the technical problem that existing insulating layers are composite multilayers, which not only lead to larger thickness and volume of the three-dimensional memory but also complicate the fabrication process and increase costs.
[0068] Methods for fabricating three-dimensional memory Figure 2 As shown in the image. Figure 2 As shown, the method can be roughly summarized as follows: providing a first insulating layer 202, a source layer 101, and a stacked structure (S1); forming a channel structure 107 through the stacked structure on the stacked structure (S2); and forming a connecting layer 270 on the side of the first insulating layer 202 opposite to the stacked structure (S3). These will be described separately below.
[0069] Please see Figure 2 This method first executes operations S1-S3:
[0070] S1, a first insulating layer 202, a source layer 101 and a stacked structure are provided, wherein the source layer 101 is located between the first insulating layer 202 and the stacked structure, the first insulating layer 202 is a single insulating layer, and the stacked structure includes alternately stacked conductive layers 103 and interlayer insulating layers; the material of the first insulating layer 202 and the interlayer insulating layer can both be silicon oxide.
[0071] S2, a channel structure 107 is formed through the stacked structure. The channel structure 107 includes a charge storage layer and a channel layer. The charge storage layer includes a barrier insulating layer, a charge trapping layer, and a tunneling insulating layer along the sidewall of the channel hole towards the center of the hole. An exemplary material for the barrier insulating layer and the tunneling insulating layer is silicon oxide, and an exemplary material for the charge trapping layer is silicon nitride. The charge storage layer forms a silicon oxide-silicon nitride-silicon oxide (ONO) stacked structure. An exemplary material for the channel layer is silicon (Si). Other materials can be selected for the barrier insulating layer, the charge trapping layer, and the tunneling insulating layer, and are not limited herein.
[0072] S3, a connecting layer 270 is formed on the side of the first insulating layer 202 away from the stacked structure, wherein the connecting layer 270 has a protrusion 280, the protrusion 280 passes through the second insulating layer 102 and is electrically connected to the source layer 101; the first insulating layer 202 is in contact with both the connecting layer 270 and the source layer 101. The material of the connecting layer 270 may be aluminum.
[0073] In this application, by setting the first insulating layer 202 as a single-layer insulating layer, the thickness of the three-dimensional memory is greatly reduced, the volume of the three-dimensional memory is smaller, and the fabrication process of the three-dimensional memory is simplified, thus reducing costs. This application solves the technical problem that existing insulating layers are composite multilayers, which not only result in a larger thickness and volume of the three-dimensional memory, but also complicate the fabrication process and increase costs.
[0074] In one specific embodiment, a functional layer is stacked on the side of the first insulating layer 202 facing away from the source layer 101. Before forming the interconnect layer 270, the fabrication method further includes:
[0075] A second insulating layer 102 is covered on the source layer 101 and the stacked structure;
[0076] A first contact 40 is formed within the second insulating layer 102, the source layer 101, and the first insulating layer 202, wherein the first contact 40 does not extend into the functional layer. It is understood that the end of the first contact 40 may be located between two opposing surfaces of the first insulating layer 202, or the first contact 40 may be flush with the surface of the first insulating layer 202 away from the source layer 101. The material of the first contact 40 is typically tungsten (W). The material of the first insulating layer 202 is typically silicon dioxide (SiO2).
[0077] In this application, by setting the first contact 40 not to extend into the functional layer, when the subsequent structure is formed on the first insulating layer 202 after the functional layer is removed, the subsequent structure is flat, the structure of the three-dimensional memory is flat, and the yield of the three-dimensional memory is better.
[0078] In one specific embodiment, "forming a first contact 40 within the second insulating layer 102, the source layer 101, and the first insulating layer 202" includes:
[0079] The second insulating layer 102, the source layer 101, and the first insulating layer 202 are selectively etched to form a contact hole 30, which does not extend into the functional layer.
[0080] Contact material is formed within the contact hole 30 to form the first contact 40.
[0081] It is understandable that the material properties of the first insulating layer 202 and the functional layer are different, so that the contact hole 30 stops extending after penetrating the first insulating layer 202 and does not etch the functional layer. The etching process of the second insulating layer 102, the source layer 101 and the first insulating layer 202 can be anisotropic dry etching process, and selective etchants can be used, such as etching gases, for example SF6, NF3, COS, Cl2, HBr and fluorinated hydrocarbons with low carbon-fluorine ratios (CF4, CHF3), etc.; of course, this application can also use high carbon / fluorine ratio gases (C / F ratio) and / or hydrocarbon gases (CHx) to etch the functional layer, the first insulating layer 202 and the second insulating layer 102 to avoid the etching gas from etching the functional layer. The etching ratio between the first insulating layer 202 and the functional layer can be greater than 5, such as 6, 10, 15, 100, 200, 1000, etc. This application does not specifically limit the etching ratio between the first insulating layer 202 and the functional layer, as long as the etching gas does not etch or substantially etch the functional layer after etching the first insulating layer 202. In this application, since the contact hole 30 does not extend into the functional layer, the first contact 40 also does not extend into the functional layer, that is, there is no first contact 40 in the functional layer. After removing the functional layer, the first contact 40 will not protrude outside the first insulating layer. When subsequent structures are formed on the first insulating layer 202, the subsequent structures are also flat, resulting in a flat 3D memory structure and a better yield of the 3D memory.
[0082] In one specific embodiment, "the first contact 40 does not extend into the functional layer" includes:
[0083] The first contact 40 is flush with the surface of the first insulating layer 202 facing the functional layer, or there is a preset distance between the first contact 40 and the surface of the first insulating layer 202 facing the functional layer.
[0084] Understandably, when the first contact 40 is flush with the surface of the first insulating layer 202 facing the functional layer, the first contact 40 will not protrude from the first insulating layer 202, facilitating the connection between subsequent structures stacked on the first insulating layer 202 and the first contact 40. When there is a preset distance between the first contact 40 and the surface of the first insulating layer 202 facing the functional layer, the preset distance between the first contact 40 and the surface of the first insulating layer 202 away from the source layer 101 is a reserved space for the contact hole 30, which can be filled by subsequent structures. This method not only prevents the first contact 40 from protruding from the first insulating layer 202, but also provides a reserved space, allowing subsequent structures to fill the reserved space as needed. This ensures good contact between subsequent structures and the first contact 40, and makes the structure of the three-dimensional memory more flexible.
[0085] In one specific embodiment, the preset distance is between 30nm and 40nm. The reserved space between 30nm and 40nm allows subsequent structures to fill the reserved space better, and the subsequent structures can make good contact with the first contact 40.
[0086] Please see Figure 3 In one specific embodiment, the functional layer includes a substrate 90 and an etch stop layer 210. The substrate 90 is formed on the side of the first insulating layer 202 away from the source layer 101, and the etch stop layer 210 is formed between the first insulating layer 202 and the substrate 90. The first contact 40 does not extend into the etch stop layer 210.
[0087] Understandably, the material of the etch stop layer 210 is different from that of the first insulating layer 202. When etching to form the contact hole 30 accommodating the first contact 40, the first insulating layer 202 is selectively etched, while the etch stop layer 210 is not etched. After the first contact 40 is formed in the contact hole 30, the first contact 40 does not extend into the etch stop layer 210. After the etch stop layer 210 is subsequently removed, the first contact 40 does not protrude beyond the first insulating layer 202. Therefore, it is unnecessary to separately grind the first contact 40, reducing the fabrication process of the three-dimensional memory, saving steps, and reducing costs. Optionally, the material of the etch stop layer 210 is silicon nitride (SiN).
[0088] In one specific embodiment, the functional layer further includes an oxide layer 220, which is stacked between the etch stop layer 210 and the substrate 90. It is understood that the oxide layer 220 is used to planarize the etch stop layer 210.
[0089] Please see Figure 4 After forming the first contact 40, the preparation method further includes:
[0090] A portion of the substrate 90 is removed from the surface of the substrate 90 away from the first insulating layer 202 to form a reference substrate 110, wherein the thickness of the reference substrate 110 is less than the thickness of the substrate 90.
[0091] Please see Figure 5 Remove reference substrate 110.
[0092] In this embodiment, after removing the substrate 90, the fabrication method further includes:
[0093] Please see Figure 6 A via 20b is formed on the first insulating layer 202, and the via 20b exposes the source layer 101.
[0094] In this embodiment, "forming a connecting layer 270 on the side of the first insulating layer 202 away from the stacked structure" includes:
[0095] Please see Figure 7 "Forming a connecting layer 270 on the side of the first insulating layer 202 away from the stacked structure" includes:
[0096] In forming the connection layer 270, a protrusion 280 is formed within the via 20b, and the protrusion 280 is connected to the source layer 101. It is understood that there can be multiple vias 20b.
[0097] Please see Figure 8 In one specific embodiment, the functional layer is a substrate 90, and the first contact 40 does not extend into the substrate 90. The substrate 90 can be made of polycrystalline silicon.
[0098] Understandably, the substrate 90 is made of a different material than the first insulating layer 202. When etching to form the contact hole 30 accommodating the first contact 40, the first insulating layer 202 is selectively etched, while the substrate 90 is not etched. After the first contact 40 is formed within the contact hole 30, the first contact 40 does not extend into the substrate 90. After the substrate 90 is subsequently removed, the first contact 40 does not protrude beyond the first insulating layer 202. Therefore, it is unnecessary to separately grind the first contact 40, reducing the fabrication process of the three-dimensional memory, saving steps, and reducing costs. Optionally, the substrate 90 is made of polycrystalline silicon.
[0099] In this embodiment, after forming the first contact 40, the preparation method further includes:
[0100] Please see Figure 9 A portion of the substrate 90 is removed from the surface of the substrate 90 away from the first insulating layer 202 to form a reference substrate 110, wherein the thickness of the reference substrate 110 is less than the thickness of the substrate 90.
[0101] Please see Figure 10 Remove the reference substrate 110. Optionally, "removing the reference substrate 110" includes removing the reference substrate 110 using a chemical mechanical polishing (CMP) method.
[0102] It is understood that the formation method of a three-dimensional memory typically involves forming a layer structure of the three-dimensional memory on a substrate 90, and then removing the substrate 90. This application first removes a portion of the substrate 90 from the surface of the substrate 90 facing away from the first insulating layer 202, that is, thinning the substrate 90 from the surface of the substrate 90 facing away from the first insulating layer 202. The method for thinning the substrate 90 can be chemical mechanical polishing. Since the substrate 90 is relatively thick, the process of removing a portion of the substrate 90 can be rapid polishing or coarse polishing, that is, the process from the substrate 90 to the reference substrate 110 is rapid polishing, in order to accelerate the thinning speed of the substrate 90 and save time. After forming the reference substrate 110, the method for removing the reference substrate 110 can also be chemical mechanical polishing. The process of removing the reference substrate 110 can be slow polishing or fine polishing, thereby polishing the reference substrate 110 to the required thickness and avoiding polishing to the first insulating layer 202. In this embodiment, the entire reference substrate 110 is polished away without polishing to the first insulating layer 202. The method for removing the entire substrate 90 can be chemical mechanical polishing.
[0103] In one specific embodiment, "removing the reference substrate 110" includes:
[0104] When removing the reference substrate 110, a portion of the structure of the first contact 40 is removed so that the first contact 40 with the portion of the structure removed does not protrude from the surface of the first insulating layer 202 away from the source layer 101.
[0105] It is understood that chemical mechanical polishing involves adding chemical reagents to react with the workpiece while mechanically polishing it. In this application, the chemical reagents can react with the first contact 40, thereby removing part of the structure of the first contact 40 during chemical mechanical polishing of the substrate 90. For example, part of the structure of the first contact 40 in the contact hole 30 is reacted and removed, so that the first contact 40 does not protrude from the first insulating layer 202 away from the surface of the substrate 90. When subsequent structures are formed on the first insulating layer 202, the subsequent structures can be formed flatly on the first insulating layer 202, resulting in a flat 3D memory structure and a better yield of the 3D memory. This also applies to situations where the first contact 40 extends into the substrate 90; the chemical mechanical polishing method can also remove the structure of the first contact 40 extending into the substrate 90.
[0106] Please see Figures 8-9 In one specific embodiment, the source layer 101 has an initial ground structure 230 on the side facing away from the stacked structure. The initial ground structure 230 extends into the functional layer after passing through the first insulating layer 202.
[0107] Please see Figure 10"Removing the reference substrate 110" includes: when removing the reference substrate 110, removing a portion of the initial ground structure 230 to form a ground structure 240, the ground structure 240 being flush with the first insulating layer 202.
[0108] Understandably, when the substrate 90 is polished using a chemical mechanical polishing method, the initial grounding structure 230 within the substrate 90 is also polished simultaneously, so that the initial grounding structure 230 forms a grounding structure 240. After the substrate 90 is removed, when the connection layer 270 is formed on the first insulating layer 202, the connection layer 270 is connected to the grounding structure 240. Moreover, since the grounding structure 240 is flush with the first insulating layer 202, the connection layer 270 can be formed smoothly on the first insulating layer 202.
[0109] In one specific embodiment, after removing the substrate 90, the fabrication method further includes:
[0110] Please see Figure 11 A via 20b is formed on the first insulating layer 202, and the via 20b exposes the source layer 101.
[0111] "Forming a connecting layer 270 on the side of the first insulating layer 202 away from the stacked structure" includes:
[0112] In forming the connection layer 270, a protrusion 280 is formed within the via 20b, and the protrusion 280 is connected to the source layer 101. It is understood that there can be multiple vias 20b.
[0113] In this application, via 20b is used to expose source layer 101, and via 20b is used to form protrusion 280 to lead out source layer 101. When connecting layer 270 is formed on first insulating layer 202, protrusion 280 can also be flatly accommodated in via 20b.
[0114] In one specific embodiment, "forming a first contact 40 within the second insulating layer 102, the source layer 101, and the first insulating layer 202" includes:
[0115] When forming the first contact 40, a second contact 104 is formed within the second insulating layer 102, wherein the second contact 104 is connected to the conductive layer 103 of the stacked structure. Optionally, the first contact 40 and the second contact 104 are made of tungsten.
[0116] In this application, by setting the second contact 104 to be connected to the conductive layer 103, the connection layer 270 can be connected to other structures of the three-dimensional memory through the second contact 104.
[0117] In one specific embodiment, the fabrication method further includes, prior to removing the substrate 90:
[0118] An interconnect structure 290 is formed on the side of the stacked structure away from the source layer 101, wherein the interconnect structure 290 is electrically connected to the channel structure 107. It is understood that the interconnect structure 290 includes pads 70, conductive channels 80, and wiring 50 connected in sequence. The pads 70 are connected to the channel structure 107, and the wiring 50 is electrically connected to other structures of the 3D memory, such as connections to peripheral circuitry described below.
[0119] In this application, by setting the interconnect structure 290, the electrical connection between the channel structure 107 and other structures of the three-dimensional memory is realized.
[0120] In one specific embodiment, after forming the interconnect structure 290, the fabrication method further includes:
[0121] A peripheral circuit 60 is formed on the side of the interconnect structure 290 away from the stacked structure, wherein the peripheral circuit 60 is electrically connected to the interconnect structure 290.
[0122] In this application, the peripheral circuit 60 supplies power to the channel structure 107 through the interconnection structure 290.
[0123] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the invention. Those skilled in the art will understand that implementing all or part of the above-described embodiments and making equivalent changes in accordance with the claims of the present invention are still within the scope of the invention.
Claims
1. A three-dimensional memory, characterized in that, include: A first insulating layer, a source layer, and a stacked structure, wherein the source layer is located between the first insulating layer and the stacked structure, and the stacked structure includes alternately stacked conductive layers and interlayer insulating layers; Channel structure passing through the stacked structure; A connecting layer is located on the side of the first insulating layer opposite to the stacked structure and has a protrusion that passes through the first insulating layer and is electrically connected to the source layer. The first insulating layer is a single insulating layer, and the first insulating layer is in contact with both the connecting layer and the source layer; A second insulating layer covering the stacked structure and the source layer; And the first contact passes through the second insulating layer, the source layer and the first insulating layer, and is electrically connected to the connection layer.
2. The three-dimensional memory as described in claim 1, characterized in that, The material of the first insulating layer includes silicon oxide.
3. The three-dimensional memory according to claim 1, characterized in that, It also includes a grounding structure located on the side of the source layer facing away from the stacked structure. The grounding structure passes through the first insulating layer and its two ends are electrically connected to the source layer and the connection layer, respectively. The grounding structure is flush with the first insulating layer.
4. The three-dimensional memory as described in claim 3, characterized in that, The grounding structure and the source layer are made of the same material.
5. The three-dimensional memory as described in claim 1, characterized in that, Also includes: The second contact passes through the second insulating layer and connects to the conductive layer of the stacked structure.
6. The three-dimensional memory as described in claim 1, characterized in that, Also includes: An interconnect structure is located on the side of the stacked structure opposite to the source layer, and the interconnect structure is electrically connected to the channel structure.
7. The three-dimensional memory as described in claim 6, characterized in that, Also includes: The peripheral circuit is located on the side of the interconnect structure opposite to the stacked structure and is electrically connected to the interconnect structure.
8. A method for fabricating a three-dimensional memory, characterized in that, include: A first insulating layer, a source layer, and a stacked structure are provided, wherein the source layer is located between the first insulating layer and the stacked structure, the first insulating layer is a single insulating layer, and the stacked structure includes alternately stacked conductive layers and interlayer insulating layers; A channel structure is formed through the stacked structure; A grounding structure is formed on the side of the source layer away from the stacked structure, and the grounding structure is electrically connected to the source layer. A connection layer is formed on the side of the first insulating layer away from the stacked structure, wherein the connection layer is electrically connected to the grounding structure, the connection layer has a protrusion that passes through the first insulating layer and is electrically connected to the source layer; the first insulating layer is in contact with both the connection layer and the source layer.
9. The preparation method according to claim 8, characterized in that, Before forming the connecting layer, the preparation method further includes: A functional layer is formed on the side of the first insulating layer that is away from the source layer; An initial grounding structure is formed on the side of the source layer opposite to the stacked structure, and the initial grounding structure extends into the functional layer after passing through the first insulating layer. A second insulating layer is applied to the source layer and the stacked structure. A first contact is formed within the second insulating layer, the source layer, and the first insulating layer, wherein the first contact does not extend into the functional layer.
10. The preparation method according to claim 9, characterized in that, The functional layer is a substrate, and the first contact does not extend into the substrate.
11. The preparation method according to claim 9, characterized in that, The functional layer includes a substrate and an etch stop layer. The substrate is formed on the side of the first insulating layer away from the source layer. The etch stop layer is formed between the first insulating layer and the substrate. The first contact does not extend into the etch stop layer.
12. The preparation method according to claim 11, characterized in that, The functional layer further includes an oxide layer, which is stacked between the etch stop layer and the substrate.
13. The preparation method according to claim 9, characterized in that, "The first contact does not extend into the functional layer" includes: The first contact point is flush with the surface of the first insulating layer facing the functional layer, or there is a predetermined distance between the first contact point and the surface of the first insulating layer facing the functional layer.
14. The preparation method according to claim 13, characterized in that, The preset distance is between 30nm and 40nm.
15. The preparation method according to claim 9, characterized in that, "Forming a first contact point within the second insulating layer, the source layer, and the first insulating layer" includes: The second insulating layer, the source layer, and the first insulating layer are selectively etched to form a contact hole that does not extend into the functional layer. Contact material is formed within the contact hole to form the first contact.
16. The preparation method according to claim 10, characterized in that, After forming the first contact point, the preparation method further includes: A portion of the substrate is removed from the surface of the substrate opposite to the first insulating layer to form a reference substrate, wherein the thickness of the reference substrate is less than the thickness of the substrate; Remove the reference substrate.
17. The preparation method according to claim 16, characterized in that, "Removing the reference substrate" includes: When removing the reference substrate, a portion of the structure of the first contact is removed so that the first contact with the removed portion of the structure does not protrude from the surface of the first insulating layer away from the source layer.
18. The preparation method according to claim 16, characterized in that, "Removing the reference substrate" includes: removing a portion of the initial grounding structure to form the grounding structure during the removal of the reference substrate, the grounding structure being flush with the first insulating layer.
19. The preparation method according to claim 16, characterized in that, After removing the substrate, the fabrication method further includes: A via is formed on the first insulating layer, the via exposing the source layer; "Forming a bonding layer on the side of the first insulating layer opposite to the stacked structure" includes: When forming the connection layer, a protrusion is formed in the via, and the protrusion is connected to the source layer.
20. The preparation method according to claim 11, characterized in that, "Forming a first contact point within the second insulating layer, the source layer, and the first insulating layer" includes: When the first contact is formed, a second contact is formed within the second insulating layer, wherein the second contact is connected to the conductive layer of the stacked structure.
21. The preparation method according to claim 20, characterized in that, The first and second contacts are made of tungsten, and the connecting layers are made of aluminum; the substrate is made of polycrystalline silicon; the etch stop layer is made of silicon nitride; and the first and second insulating layers are made of homogeneous silicon dioxide.
22. The preparation method according to claim 16, characterized in that, Before removing the substrate, the fabrication method further includes: An interconnect structure is formed on the side of the stacked structure opposite to the source layer, wherein the interconnect structure is electrically connected to the channel structure.
23. The preparation method according to claim 22, characterized in that, After forming the interconnect structure, the fabrication method further includes: A peripheral circuit is formed on the side of the interconnect structure opposite to the stacked structure, wherein the peripheral circuit is electrically connected to the interconnect structure.