Dual-Memory Driving of an Electronic Display

Abstract

A display system may include: a memory storing a first digital data value outside a pixel; a memory storing a second digital data signal inside the pixel, wherein a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration according to the first digital data signal and for a second duration according to the second digital data signal.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application is a non - provisional patent application claiming priority to U.S. Provisional Patent Application 63 / 003,039, entitled "DUAL - MEMORY DRIVING OF AN ELECTRONIC DISPLAY", filed on March 31, 2020, which is hereby incorporated by reference in its entirety for all purposes. SUMMARY OF THE INVENTION

[0003] A summary of certain embodiments disclosed herein is set forth below. It should be understood that presenting these aspects is merely to provide a concise summary of these particular embodiments to the reader and that these aspects are not intended to limit the scope of the disclosure. Indeed, the disclosure may cover aspects not set forth below.

[0004] Methods and systems for reducing the bandwidth or simultaneous throughput of image data that is transmitted and processed to prepare an image for presentation on an electronic display by implementing memory in pixels of the electronic display can provide significant value. This implementation of memory in pixels can allow for the elimination or reduction of the size of the frame buffer associated with the electronic display. Having memory in the pixels can also reduce the design complexity of the electronic display because the less image data that is simultaneously transmitted to the pixel array of the electronic display, the simpler the electronic display can be designed. For example, the pixels can be programmed in smaller groups because the memory in the pixels stores values until the time of image presentation.

[0005] The present disclosure describes an electronic display having one or more pixels that include memory and a driver, which can help reduce the bandwidth associated with transmitting and processing image data for presentation on the electronic display. Including memory in the pixels can enable the storage of image data before outputting the image data to the light - emitting portion of the pixels. Thus, the in - pixel memory can reduce or, in some cases, eliminate the dependence on the frame buffer in the electronic display by acting as a separate frame buffer for the pixels. The in - pixel memory can be used in conjunction with the driver to cause the light - emitting portion of the pixels to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure may be better understood when reading the following detailed description and referring to the accompanying drawings, in which:

[0007] Figure 1 is a schematic block diagram of an electronic device according to an embodiment;

[0008] Figure 2 is a perspective view of a watch, which is an embodiment of an electronic device according to an embodiment Figure 1 of the electronic device according to the embodiment

[0009] Figure 3 Is a representation according to the implementation plan Figure 1 A front view of a tablet device of an embodiment of an electronic device;

[0010] Figure 4 Is a representation according to the implementation plan Figure 1 A front view of a computer of an embodiment of the electronic device;

[0011] Figure 5 According to the implementation plan Figure 1 A block diagram of a display system of an electronic device;

[0012] Figure 6 According to the implementation plan Figure 5 A block diagram of a pixel array of a display system;

[0013] Figure 7 According to the implementation plan Figure 5 A block diagram of another exemplary pixel array of a display system;

[0014] Figure 8 According to the implementation plan Figure 6 a block diagram of a pixel in a pixel array of FIG. 1 , the pixel emitting light according to a single pulse width modulated emission scheme;

[0015] Figure 9 is used for operation according to the implementation scheme Figure 8 The process of pixels;

[0016] Figure 10 is a diagram of exemplary binary sequences according to an embodiment, adjacent to a representation of the relative weight of each bit in each binary sequence to help illustrate Figure 8 The single pulse width modulation scheme described;

[0017] Figure 11A is a bit-plane map corresponding to an implementation without reordering according to an embodiment;

[0018] Figure 11B is an error graph corresponding to an implementation without reordering according to an embodiment;

[0019] Figure 11C is a bit plane map corresponding to two reorderings according to an embodiment;

[0020] Figure 11D is an error graph corresponding to two reorderings according to an embodiment;

[0021] Figure 11E is a bit plane map corresponding to three reorderings according to an embodiment;

[0022] Figure 11F correspond to three reordered error maps according to an embodiment;

[0023] Figure 11G is a bit plane map corresponding to the reordered ideal case according to an embodiment;

[0024] Figure 11H is an error map corresponding to the reordered ideal case according to an embodiment;

[0025] Figure 12 is a block diagram according to an embodiment that compares Figure 5 the display system with a first exemplary display system having an intelligent buffer outside the active area of the electronic display;

[0026] Figure 13 is a block diagram of a second exemplary display system according to an embodiment, which has a memory inside the pixels of the panel and a memory inside the intelligent buffer but allocated to the corresponding pixels of the panel;

[0027] Figure 14 is a block diagram of a third exemplary display system according to an embodiment, which has a memory inside the pixels of the panel and a memory outside the display system but allocated to the corresponding pixels of the panel;

[0028] Figure 15 is an illustration according to an embodiment of how the emphasis controller can use the target gray level to drive Figure 8 the pixels;

[0029] Figure 16 is a graph showing the relationship between the gray level and the pulse width control operation according to an embodiment;

[0030] Figure 17 is according to an embodiment of Figure 8 the exemplary pixel circuit diagram;

[0031] Figure 18 is a timing diagram according to an embodiment that compares the change in count with the state of the emission control signal;

[0032] Figure 19 is a process according to an embodiment for operating Figure 17 the pixels;

[0033] Figure 20 is an illustration according to an embodiment depicting Figure 17 the all - on operation of the pixels and Figure 17 the modulation operation of the pixels;

[0034] Figure 21It is based on the description of the implementation plan Figure 17 A diagram of a full-off operation of pixels of

[0035] Figure 22 Is based on the implementation plan and operation Figure 17 The timing diagram of the pixel-related signals is shown in the figure. Figure 19 process. DETAILED DESCRIPTION

[0036] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of an actual implementation are described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the developer's specific goals, such as meeting system-related and business-related constraints that may vary from one implementation to another. In addition, it should be understood that such development work may be complex and time-consuming, but it will still be a routine task of design, processing, and manufacturing for those of ordinary skill in the art who benefit from this disclosure.

[0037] When introducing elements of various embodiments of the present disclosure, the articles "a / an" and "the / said" are intended to mean that there are one or more of the elements. The terms "including" and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that reference to "some embodiments," "embodiments," "one embodiment," or "an embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the cited features. Also, the phrase A "based on" B is intended to mean that A is at least partially based on B. Moreover, the term "or" is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A "or" B is intended to mean A, B, or both A and B.

[0038] Electronic displays are found in many electronic devices, from mobile phones to computers, televisions, and automobile dashboards. Electronic displays have achieved increasingly higher resolutions by reducing the size of individual pixels. However, increasing resolution can increase difficulties associated with managing the increased amount of image data that processing circuitry must process before displaying the image, for example, due to increased power consumption to process the increased amount of image data. Furthermore, increasing resolution can increase the bandwidth required to transmit image data from the processing circuitry to the pixel array for image presentation, as more image data is used to transmit the same image at higher electronic display resolutions.

[0039] Embodiments of the present disclosure relate to systems and methods for implementing an in-pixel memory circuit that can serve as a separate frame buffer for each pixel. The systems and methods of the present disclosure for implementing an in-pixel memory circuit can reduce the transmission bandwidth for image data to a pixel array because the pixels can store the image data in memory. In this way, the reliance on a frame buffer for temporarily storing image data external to the pixels is reduced because the pixels have their own memory to store their own image data before displaying the image data.

[0040] The memory can be implemented in a pixel circuit including a light-emitting diode (LED). An organic light-emitting diode (OLED) represents one type of LED that can be present in a pixel, but other types of LEDs or light-emitting elements can also be used. Other light-emitting or light-receiving components that can be used in a pixel circuit include components for supporting a liquid crystal display (LCD), a plasma display panel, and / or a dot matrix display.

[0041] In some cases, some memory for each pixel can be included in the pixel circuit, while some memory for each pixel can be included in the driving circuit of the display. When the memory implemented in the pixel is not used in combination with an external memory separately allocated for the pixel, the maximum bit depth of the image data stored in the memory can be defined and limited by the physical occupancy area designated for each pixel. For example, the amount of memory used in each pixel, and thus the number of corresponding bits used to represent the target gray level for each pixel reference when presenting an image, can be limited by the amount of space dedicated to each pixel within the display panel.

[0042] Dividing the memory designated for each pixel into separate portions of the display can increase the amount of memory designated for each pixel and enable an increase in the number of corresponding bits used to represent the target gray level. For example, it should be understood that the same number of memory storage units can be included within the pixel as in other in-pixel memory panels, but additional bits can be used to represent the target gray level, at least in part due to the inclusion of additional memory for the pixel in the driving circuit of the display.

[0043] In addition, in some cases, multiple driving cycles can be used to present one image frame. These multiple driving cycles can be considered "sub-frames", where the same storage unit for a particular pixel can be loaded with data multiple times within the duration allocated for presenting the image frame. When using sub-frames to drive the display to present an entire frame, the sub-frame period can be utilized to divide the target gray level into sub-frame-based blocks. For example, a certain portion of the bits representing the target gray level can be used to drive the display to emit light during a first sub-frame, while another portion of these bits representing the target gray level can be used to drive the display during a second sub-frame, where the light emission over these two sub-frames will emit light that appears as the target gray level of the entire image frame.

[0044] A display using in - pixel memory technology can also implement a memory set in a driver for the display that is allocated to a pixel. Sub - frames can be utilized in combination with the use of the internal memory of the pixel and the external memory of the pixel and / or automatically utilized through the use of these internal and external memories. For example, a pixel can be driven to emit light for a duration corresponding to a first sub - frame according to data stored in the external memory allocated to the pixel, and the pixel can be driven to emit light for at least a portion of a second sub - frame according to data stored in the memory inside the pixel (e.g., in - pixel memory). A target gray level can define how many sub - frames to drive the pixel from the internal memory and how many sub - frames to drive the pixel from the external memory to cause a total light emission that can be perceived as the target gray level. In this way, the combination of the light emitted from the pixel during the first sub - frame and the light emitted from the pixel during the second sub - frame can be perceived by an observer of the display as corresponding to the target gray level of the pixel.

[0045] Dividing the driving of a pixel at a target gray level into multiple driving operations spanning multiple sub - frames can improve the pixel driving method. The division into multiple driving operations can be automatically controlled by a processing circuit (e.g., a display driver, a controller) of an electronic device using a counter - based system of the electronic device.

[0046] When the processing circuit controls the driving operations, each target gray level can be analyzed to determine a combination of driving operations to generate a desired light emission. Operations for driving a pixel to emit light can include: selectively driving the pixel from the memory inside the pixel (e.g., in - pixel memory), driving the pixel from a memory outside the pixel but allocated to the pixel (e.g., allocated external memory), or a combination thereof. Additionally, it should be noted that driving a pixel from a memory outside the pixel can also involve unmodulated and / or continuous light emission instructions (or no - light - emission instructions) during the duration of a sub - frame. For example, a pixel can be driven to emit light during the duration of a sub - frame with no expectation that the light emission stops during the sub - frame, and / or be driven to not emit light during the sub - frame duration with no expectation that the light emission starts during that sub - frame. Combining an unmodulated emission instruction with a modulated emission instruction can mean that the pixel is driven to emit unmodulated light in a first sub - frame, driven to emit modulated light (e.g., fine - tuning the gray level presented during the first sub - frame) for at least a portion of a second sub - frame, and driven to not emit light (e.g., unmodulated zero emission) in a third sub - frame after the target gray level has been presented using the first and second sub - frames. In this way, different combinations of operations can be used when the target gray level is greater than a threshold gray level than when the target gray level is less than the threshold gray level.

[0047] When a counter-based system controls driving operations, a pixel can automatically switch between the above driving operations in response to the result of a comparison between a target gray level and a current count. For example, a subset of binary data representing the current count of the counter can be compared with the same bit positions of the binary representing the target gray level at each count change. While waiting for the subset of binary data representing the target gray level to match the subset of binary data representing the count, the pixel can be driven to emit unmodulated light. When the data stored in the corresponding bit positions match, the pixel is driven according to the remaining binary data representing the target gray level, thereby driving the pixel to emit modulated light. It should be understood that when referred to as modulated light, the light emitted from the pixel can be emitted according to the image data stored in the memory of the pixel rather than the data stored in an external memory allocated for the pixel.

[0048] When driving a pixel to emit modulated light or unmodulated light (or no light), data overwrite and / or memory disable operations can be used. The data stored and transmitted to the memory inside the pixel can be overwritten or disabled by a control signal to avoid affecting the output of the pixel during the duration of a sub-frame. The control signal can disable the memory inside the pixel and can allow the allocated external memory to drive the pixel.

[0049] For example, when the target gray level is between 0 and a first threshold, the memory inside the pixel can be decoupled from at least the light-emitting portion of the sub-pixel, so it can be temporarily not used or can be provided with a "0" value to do so. Disabling or not using the memory inside the pixel can allow the allocated external memory to drive the pixel in a first sub-frame, and the memory inside the pixel can drive the pixel in a second sub-frame. In some cases, the output from the allocated external memory and the output from the counter can be compared by a comparator. The output of this comparator can be used as a control signal to control the coupling or decoupling of the memory inside the pixel and the light-emitting portion of the pixel. However, in some cases, the control signal can be generated by a controller or driver to directly control the operation.

[0050] The use of two or more allocated memories can improve the driving method, for example, by extending the possibility of the driving range beyond the range allowed by the physical boundary of the pixel panel. For example, a memory storing 6-bit data can be included within a pixel. However, different from being limited to 6-bit data (e.g., 64 gray-level options), the pixel can be driven to emit light according to 8-bit data (e.g., 256 gray-level options) without using the occupied area of an 8-bit memory inside the pixel. Additionally, the memory inside the pixel can load data for light emission simultaneously or in parallel with the data stored in the allocated external memory while the pixel emits light during the first sub-frame refresh. As discussed herein, driving the pixel can utilize a single pulse width modulation driving method to improve the perceivable appearance of the display relative to other in-pixel memory driving methods. In fact, using the single pulse width modulation driving method can improve driving methods such as the binary pulse width modulation (BPWM) driving method because other driving methods may introduce visual artifacts, such as visual artifacts caused by the slow charging of light-emitting diodes (LEDs) of pixels driven by binary pulse width modulation.

[0051] For ease of explanation, Figure 1 electronic device 10 is shown. As described in more detail below, electronic device 10 can be any suitable electronic device, such as a computer, a mobile phone, a portable media device, a tablet, a television, a virtual reality headset, a vehicle dashboard, etc. Thus, it should be noted that, Figure 1 this is only one example and is intended to illustrate the types of components that can be present in electronic device 10. Electronic device 10 can include a processing core complex 12, such as a system-on-chip (SoC) and / or one or more processing circuits, one or more storage devices (e.g., storage device 14), one or more communication interfaces (e.g., communication interface 16), one or more electronic displays (e.g., electronic display, display 18), one or more input structures (e.g., input structure 20), and one or more power supplies (e.g., power supply 22). Figure 1 The various components described can include hardware elements (e.g., circuits), software elements (e.g., tangible non-transitory computer-readable media storing instructions), or combinations of hardware elements and software elements. It should be noted that the various depicted components can be combined into fewer components or separated into additional components.

[0052] Using pixels that include light-emitting components (e.g., LEDs, OLEDs), the display 18 can display images generated by the processing core complex 12. The processing core complex 12 can be operatively coupled to the storage device 14. The processing core complex 12 can execute instructions stored in the storage device 14 to perform operations such as generating and / or transmitting image data. Thus, the processing core complex 12 can include one or more general-purpose microprocessors, one or more application-specific integrated circuits (ASICs), one or more field-programmable logic arrays (FPGAs), or any combination thereof.

[0053] In addition to instructions, the storage device 14 can also store data to be processed by the processing core complex 12. Thus, in some embodiments, the storage device 14 can include one or more tangible non-transitory computer-readable media. The storage device 14 can be volatile and / or non-volatile. For example, the storage device 14 can include random access memory (RAM) and / or read-only memory (ROM), rewritable non-volatile memory (such as flash memory, hard disk drive, optical disc, etc.), or any combination thereof.

[0054] As shown, the processing core complex 12 can also be operatively coupled to the communication interface 16. In some embodiments, the communication interface 16 can facilitate data transfer with another electronic device and / or network. For example, the communication interface 16 (e.g., a radio frequency system) can enable the electronic device 10 to be communicatively coupled to a personal area network (PAN) such as a Bluetooth network, a local area network (LAN) such as a 802.11x Wi-Fi network, and / or a wide area network (WAN) such as a 4G or Long-Term Evolution (LTE) cellular network, 5G, etc.

[0055] Additionally, as depicted, the processing core complex 12 can also be operatively coupled to the power supply 22. In some embodiments, the power supply 22 can provide power to one or more components in the electronic device 10 such as the processing core complex 12 and / or the display 18. Thus, the power supply 22 can include any suitable energy source such as a rechargeable lithium polymer (Li-poly) battery and / or an alternating current (AC) power converter.

[0056] As shown, the electronic device 10 is also operatively coupled to the input structure 20. In some embodiments, the input structure 20 can facilitate user interaction with the electronic device 10, for example, by receiving user input. Thus, the input structure 20 can include buttons, a keyboard, a mouse, a touchpad, etc. Additionally, in some embodiments, the input structure 20 can include a touch-sensing component in the display 18. In such embodiments, the touch-sensing component can receive user input by detecting the occurrence and / or location of an object touching the surface of the display 18.

[0057] In addition to implementing user input, the display 18 may include a display panel having one or more display pixels. As described above, the display 18 may control the light emitted from the display pixels to present a visual representation of information, such as a graphical user interface (GUI) of an operating system, an application interface, a static image, or video content, through a display frame based at least in part on corresponding image data. As depicted, the display 18 is operatively coupled to the processing core complex 12. In this manner, the display 18 may display frames based at least in part on image data generated by the processing core complex 12. Additionally or alternatively, the display 18 may display frames based at least in part on image data received via the communication interface 16 and / or the input structure 20.

[0058] As can be appreciated, the electronic device 10 may take on a variety of different forms. As Figure 2 shown, the electronic device 10 may take on the form of a watch 30. For illustrative purposes, the watch 30 may be any Apple model available from Apple Inc. As shown, the watch 30 includes a housing 32 (e.g., a case). In some embodiments, the housing 32 may protect internal components from physical damage and / or shield internal components from electromagnetic interference (e.g., encapsulate components). A strap 34 may enable the watch 30 to be worn on an arm or wrist. The display 18 may display information related to the operation of the watch 30. The input structure 20 may enable a user to activate or deactivate the watch 30, navigate the user interface to a home screen, navigate the user interface to a user-configurable application screen, activate a voice recognition feature, provide volume control, and / or switch between vibrate and ring modes. As shown, the input structure 20 may be accessed through an opening in the housing 32. In some embodiments, the input structure 20 may include, for example, an audio jack for connecting to an external device.

[0059] The electronic device 10 may also take on the form of a tablet device 40, as Figure 3 shown. For illustrative purposes, the tablet device 40 may be any Model. Depending on the size of the tablet device 40, the tablet device 40 can be used as a handheld device such as a mobile phone. The tablet device 40 may include a housing 42, and a plurality of input structures 20 may protrude through the housing. In some examples, the input structure 20 may include a hardware keyboard (not shown). The housing 42 also holds the display 18. The input structure 20 may enable a user to interact with the GUI of the tablet device 40. For example, the input structure 20 may enable a user to type a Rich Communication Services (RCS) text message, a Short Message Service (SMS) text message, or make a phone call. The speaker 44 may output the received audio signal, and the microphone 46 may capture the user's voice. The tablet device 40 may also include a communication interface 16 to enable the tablet device 40 to connect to another electronic device via a wired connection.

[0060] Figure 4 Shown is a computer 48 representing another form that the electronic device 10 may take. For illustrative purposes, the computer 48 may be any or model. It should be understood that the electronic device 10 may also take the form of any other computer, including a desktop computer. Figure 4 The illustrated computer 48 includes a display 18 and an input structure 20 including a keyboard and a touchpad. The communication interface 16 of the computer 48 may include, for example, a Universal Serial Bus (USB) connection.

[0061] In any case, as described above, operating the electronic device 10 to convey information by displaying an image on its display 18 generally consumes power. In addition to this, as described above, the electronic device 10 typically stores a limited amount of electrical energy. Thus, to help improve power consumption efficiency, in some embodiments, the electronic device 10 may include a display 18 that implements in-pixel memory as a method for reducing or eliminating the use of an external frame buffer when displaying an image, and thus reducing the power consumed in using the frame buffer when displaying an image and / or reducing the bandwidth of the image data received into the display 18. In some cases, in addition to or instead of in-pixel memory technology, an internal frame buffer (e.g., located within the display 18, such as within the display driver integrated circuit of the display 18) may be used. By implementing in-pixel memory or related technologies, the display 18 can be programmed with image data of a smaller bandwidth, thereby further achieving power savings. Additionally, compared to a display 18 without in-pixel memory or without an on-board frame buffer, a display 18 using in-pixel memory or an on-board frame buffer may have a less complex design. These benefits can be achieved because a pixel retains the data transmitted to its memory until new image data is written to that memory.

[0062] Similarly, portions of the image data can program a subset of the pixels associated with the display 18, including between sub-pixels. The image to be displayed is typically converted to digital data or image data such that the image can be interpreted by components of the display 18. In this manner, the image data itself can be divided into small "pixel" portions, each of which can correspond to a pixel portion of the display 18 or a pixel portion of the display panel corresponding to the display 18. In some embodiments, the image data is represented by a combination of red-green-blue light such that a pixel that appears to have a single color is actually three sub-pixels that each emit a certain proportion of red, green, and blue light to produce that single color. In this manner, the numerical value or image data that quantifies the combination of red-green-blue light can correspond to a digital luminescence level or gray level that correlates to the luminescence intensity (e.g., brightness) of the color of the image data for those particular sub-pixels. It will be understood that the number of gray levels in an image typically depends on the number of bits used to represent the gray levels in a particular display 18, which can be represented as 2 N to the power of N gray levels, where N corresponds to the number of bits used to represent the gray levels. As an example, in an embodiment where the display 18 uses 8 bits to represent the gray levels, the gray levels range from 0 (the pixel emits black or no light) to 255 (the maximum light and / or all light that the pixel is capable of emitting), for a total of 256 potential gray levels. Similarly, a display 18 that uses 6 bits can represent the luminance intensity of each sub-pixel using 64 gray level increments (e.g., assign a value between no light emission and maximum light emission for each sub-pixel).

[0063] Having memory within the pixels of the display 18 enables the image data to be transferred to the sub-pixels associated with one color without having the image data have to be transferred simultaneously to additional sub-pixels associated with a second color. For the purposes of this disclosure, sub-pixels are discussed in terms of red-green-blue color channels, where a color channel is a layer of image data that includes the gray levels of a single color and that, when combined with additional color channels, produces an image of a true or desired color, and where the image data of the color channel corresponds to the image data transferred to the sub-pixels for the color channel. However, it should be understood that any combination of color channels and / or sub-pixels can be used, such as blue-green-red, cyan-magenta-yellow, and / or cyan-magenta-yellow-black.

[0064] For purposes of illustration, in Figure 5, a display system 50 associated with a display 18 that does not implement in-pixel memory and a display system 52 associated with a display 18 that implements in-pixel memory are shown, which may each be implemented in the electronic device 10. The display system 50 includes a timing controller 54 for receiving image data 56, a frame buffer 58 communicatively coupled to the timing controller 54 via a communication link 64, a row driver 60, and a column driver 62, and a pixel array 66 that receives control signals from the column driver 62 and the row driver 60 to produce an image on the display 18. In addition, the display system 52 includes a timing controller 54 for receiving image data 56, a row driver 60 and a column driver 62 communicatively coupled to the timing controller 54 via a communication link 68, and a pixel array 70 that implements in-pixel memory technology and receives control signals from the column driver 62 and the row driver 60 to produce an image on the display 18.

[0065] In preparation for displaying an image, display system 50 may receive image data 56 at timing controller 54. Timing controller 54 may receive and use image data 56 to determine clock signals and / or control signals to control the provision of image data 56 to pixel array 66 via column drivers 62 and row drivers 60. Additionally or alternatively, in some embodiments, image data 56 is received by frame buffer 58.

[0066] In either case, frame buffer 58 may serve as external memory for timing controller 54 to store image data 56 prior to outputting the image data to column drivers 62 and / or row drivers 60. Timing controller 54 may output image data 56 from frame buffer 58 to column drivers 62 and / or row drivers 60 via communication link 64.

[0067] The communication link 64 is large enough (e.g., determined by the transmission bandwidth of the image data) to simultaneously transmit image data 56 associated with all channels to the row driver 60 and / or column driver 62, for example, image data 56 associated with the red channel, the green channel, and the blue channel. In this way, the communication link 64 simultaneously transmits the image data 56 associated with the corresponding pixels of the red channel, the green channel, and the blue channel of the pixel array 66. The column driver 62 and the row driver 60 can transmit control signals to the pixel array 66 based on the image data 56. In response to the control signals, the pixel array 66 emits light with different luminances, or brightness indicated by gray levels ranging from, for example, 0 to 255, to transmit an image.

[0068] However, the display system 52 receives image data 56 at the timing controller 54. The timing controller 54 may use the image data 56 to determine a clock signal for providing the image data 56 to the pixel-in-memory pixel array 70. The timing controller 54 transfers the image data 56 to the row driver 60 and / or the column driver 62 to program the memory of the pixel array 70 with digital data signals associated with the image data 56, where the digital data signals indicate the emission luminance / gray level of the pixels of the pixel array 70.

[0069] By implementing the pixel-in-memory storage system and method, the display system 52 may reduce the bandwidth of the signals transmitted over the communication link 68, e.g., when compared to the bandwidth of the signals transmitted over the communication link 64. In some cases, a single channel of the image data 56 may be transmitted over the communication link 64 (e.g., the red channel), as opposed to all channels (e.g., the red-green-blue channels) being transmitted simultaneously to the pixel array 66. In this manner, the communication link 68 transmits the image data 56 associated with the respective pixels of the pixel array 66 for the red channel, green channel, and blue channel at different times, resulting in a reduction in the total bandwidth of the signals for transmitting the image data 56. Reducing the total bandwidth of the communication link 68 may result in a reduction in the power consumption of the electronic device 10, as processing smaller data (e.g., a single channel of image data) at a given time may consume fewer processing resources than processing more data (e.g., three channels of image data).

[0070] To elaborate on the operation of the pixel array 70 having pixel-in-memory to display an image, Figure 6 is a block diagram of an exemplary display system 52, a display system 52A implementing pixel-in-memory. The display system 52A includes an L-by-M pixel array 70 having one or more pixels 72. Each pixel 72 may include sub-pixels 74 corresponding to the color channels of the display 18, e.g., a red sub-pixel 74R, a green sub-pixel 74G, and a blue sub-pixel 74B. Each sub-pixel 74 may include a memory 78 storing up to N bits and a driver (DRV) 80 for operating the sub-pixel 74 to emit light. It should be understood that the depicted display system 52A is merely illustrative and not restrictive. For example, in some embodiments, the pixel array 70 may include sub-pixels 74 to emit various amounts of cyan light, yellow light, and magenta light corresponding to cyan-yellow-magenta channels instead of or in addition to the red-green-blue channels.

[0071] In explaining the operation of display system 52A, timing controller 54 receives image data 56 corresponding to the next image to be displayed on display 18 having pixel array 70. When presenting an image frame via display 18, timing controller 54 may receive image data 56. Timing controller 54 may generate control signals and / or timing signals in response to image data 56. These generated control signals and / or clock signals may be related to the rows operating pixels 72 and / or to the columns operating pixels 72, and thus may be transmitted to row driver 60 and / or column driver 62, respectively.

[0072] Row driver 60 responds to signals associated with image data 56 transmitted from timing controller 54 and generates emission control signals 82 and write control signals 84 for each red-green-blue (RGB) channel. Column driver 62 also responds to signals associated with image data 56 transmitted from timing controller 54 and generates image data 86 to be transmitted to memory 78 of each pixel 72. Column driver 62 may generate image data 86 in response to signals associated with image data 56 and / or image data 56. However, in some embodiments, image data 56 is transmitted to each pixel 72 as image data 86. Column driver 62 generates data of size N bits for each subpixel 74, thus matching the size of memory 78 (which is also of size N bits).

[0073] Typically, by transmitting an emission control signal 82, a write control signal 84, and image data 86, the pixel 72 is operated to emit light to generate an image on the display 18. Each pixel 72 receives a corresponding emission control signal 88 of the emission control signal 82 transmitted from the row driver 60, three corresponding write control signals 90 of the write control signal 84, and corresponding image data 92 for the channel of the pixel 72, for example, N-bit image data (image data - R) 92R for the red channel, N-bit image data (image data - G) 92G for the green channel, and N-bit image data (image data - B) 92B for the blue channel. The write control signal 84 may enable the memory 78 of the pixel 72 to be programmed with the image data 86 transmitted by the column driver 62. In addition, the corresponding emission control signal 88 of the emission control signal 82 may control whether the pixel 72 can emit light. The emission control signal 88 is transmitted to the corresponding pixels 72 of the column. The enabled emission control signal 88 may activate the driver 80, causing the digital image data 92 to be transmitted from the memory 78 to the light-emitting portion of the pixel 72, such as a light-emitting diode (LED) associated with the sub-pixel 74, which uses an analog data signal to generate the light emitted from the pixel 72. In the depicted embodiment, the pixels 72 in a column of the pixel 72, for example, the pixels 72R1C1, R2C1, R3C1 to RLC1 in the first column, receive the same emission control signal 88. The image data 92 transmitted to the pixel 72 causes the pixel 72 to emit light of an overall color and / or brightness.

[0074] The perceived color emitted from the pixel 72 changes based on the light emitted from each of the three channels of the pixel 72 (i.e., the light emitted from each corresponding sub-pixel). For example, operating each sub-pixel to output a brightness of 0 causes the pixel 72 to appear off, while operating the red sub-pixel 74R to output 100% brightness, the green sub-pixel 74G to output 50% brightness, and the blue sub-pixel 74B to output 0% brightness may cause the pixel 72 to emit an overall color perceived as orange. Thus, data is rendered and transmitted to each sub-pixel 74 to correspond to the individual color channels of the pixel 72.

[0075] Implementing the memory 78 in the pixel 72 enables the image data 92 to be programmed into the pixel 72 before the desired presentation time of the image. In some embodiments, an enabled write control signal 90 causes the memory 78 to clear (or rewrite) the stored image data 92, and the memory 78 can be caused to hold the programmed image data 92 without the write control signal 90 being enabled. For example, to write new image data, the write control signal -R 90R can cause the memory 78 of the red sub-pixel 74R to be cleared, enabling the new image data to be written that is to be loaded into the memory 78, i.e., the image data -R 92R. In this example, the write control signal -B 90B is not enabled, so the memory 78 of the blue sub-pixel 74B is not cleared and continues to hold its programmed image data, i.e., the image data -B 92B. Having the memory 78 in the pixel 72 is an improvement to display technology and processing technology because the memory 78 enables parts of the image data 86 to be written in one go rather than the entire data frame, resulting in an improved use of the available bandwidth for transmitting the image data for display on the display 18, and an improvement in the power consumption for processing the image data, as explained previously with reference to Figure 5 as explained.

[0076] In the pixel array 70, the image data 86 is transferred from the column driver 62 to the sub-pixels 74 by direct communication coupling (e.g., via the communication coupling 94). In some embodiments, a multiplexing circuit can be used to control the transfer of the image data 86 to the sub-pixels 74 such that the column driver 62 uses a multiplexing control signal to arbitrate the transfer of the image data to the sub-pixels 74, e.g., where in such arbitration, the red sub-pixel 74R may not receive the image data simultaneously with the blue sub-pixel 74B and / or the green sub-pixel 74G.

[0077] Specifically, Figure 7 is a block diagram of a display system 52B associated with another exemplary display system 52, the display 18 implementing in-pixel memory technology. Similar to Figure 6 the display system 52A shown, the display system 52B includes an L-row × M-column pixel array 70, where one or more pixels 72 each have sub-pixels 74, such as a red sub-pixel 74R, a green sub-pixel 74G, and a blue sub-pixel 74B, where each sub-pixel 74 includes a memory 78 for storing up to N bits and a driver (DRV) 80 for operating the sub-pixel 74 to emit light. It should be understood that the depicted display system 52B is merely illustrative and not restrictive. It should be noted that the functionality and / or description of the display system 52 is common to Figure 6 and Figure 7 as relied upon herein.

[0078] In Figure 7In the display system 52B, the pixel array 70 includes a multiplexing circuit 96 that receives image data 98 of size N bits from the column driver 62. The multiplexing circuit 96 responds to corresponding multiplexing control signals (MUX control signals) 100 of the multiplexing control signal 101. The MUX control signal 100 can cause the multiplexing circuit 96 to output data to the sub-pixels 74 of the pixels 72. In this way, by transmitting the MUX control signal 100, the column driver 62 can operate to program the sub-pixels 74 (e.g., one color channel) of the pixels 72 once via, for example, the communication coupling 94. For the pixel array 70, various implementations of the sub-pixel 74 circuit can be used.

[0079] Figure 8 An example of an implementation of the sub-pixel 74 that implements in-pixel memory technology is shown. Figure 8 It is a block diagram of the sub-pixel 74 driven using a single pulse width driving method (e.g., single pulse width modulation emission scheme). The sub-pixel 74 includes a memory 78, a driver 80, a current source 102, a light-emitting component (e.g., a circuit, a light-emitting diode (LED) 104), a switch 106, and a counter 108. The sub-pixel 74 can receive various signals, including a part of the image data 56 corresponding to the operation of the sub-pixel 74 of the current frame to be rendered (e.g., image data 56A), a gray-scale clock 110, a common voltage 112, a first reference voltage 114, a second reference voltage 116, and a data clock 118. It should be understood that the depicted sub-pixel 74 is merely illustrative and not restrictive. For example, the memory 78 can be an 8-bit register or any suitable memory circuit for storing any suitable number of bits. The depicted sub-pixel 74 can emit according to a single pulse width modulation emission scheme. Additionally, as described above, the image data 56A can correspond to the image data 92 transmitted according to a non-multiplexed driving scheme (e.g., as at least partially referenced Figure 6 as described) and / or correspond to the image data 98 transmitted according to a multiplexed driving scheme (e.g., as at least partially referenced Figure 7 as described).

[0080] To explain the operation of sub-pixel 74, image data 56A is transferred from, for example, column driver 62 to memory 78. Additionally or alternatively, image data 92 / image data 56 or any suitable image data may be transferred to memory 78 for storage. Upon receiving image data 56A, memory 78 stores image data 56A timed by data clock 118. Image data 56A may be represented by binary data. Memory 78 may output image data 56A to comparator 120 (e.g., comparator circuit) such that, each time counter 108 is incremented, the total count is checked against image data 56A stored in memory 78 to identify when the total count is greater than or equal to image data 56A.

[0081] When comparator 120 determines that the count is not greater than or equal to image data 56A stored in memory 78, comparator 120 generates a control signal to operate switch 106, causing LED 104 to emit light. The operation of switch 106 occurs in response to a varying emission period (e.g., defined by the magnitude of the number stored as image data 56A in memory 78) as a method of modulating the light emission from LED 104, such that the perceived brightness of sub-pixel 74 changes as the modulation changes. In this way, switch 106 may be considered a driving transistor that is at least partially activated based on digital data signals such as image data 56A and / or the output from comparator 120. Switch 106 or any switch described herein may be any suitable switching device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). In this way, electronic device 10 may include one or more p-type MOSFETs and / or n-type MOSFETs. The control signal level may be adjusted to accommodate the use of different types of switches. For example, a p-type MOSFET may be used as the switch in the figure and so described, but in an actual implementation is an n-type MOSFET and thus may receive a control signal of opposite polarity or adjusted amplitude when operating pixel 72.

[0082] For example, through the relationship between the output of comparator 120 and switch 106, image data 56A equal to "00000000" may cause LED 104 not to emit light, while image data 56A equal to "10101100" or any non-zero number may cause LED 104 to be perceived as brighter. Image data 56A equal to "10101100" may be perceived as brighter because sub-pixel 74 emits light in response to each logical high value "1", through which switch 106 is activated, thus allowing light to be emitted from LED 104.

[0083] The longer the switch 106 is activated during the emission period, the brighter the pixel, because more light is emitted over time. In some cases, the image data 56A may be derived from the desired gray level of the sub-pixel 74 rather than an exact binary representation of the gray level, such as when a ratio is used to represent the target gray level of the pixel. However, it should be noted that there may be cases where the target gray level of the sub-pixel 74 does equal the binary representation transmitted via the image data 56A.

[0084] The depicted sub-pixel 74 with in-pixel memory can emit according to a single pulse width emission scheme. To explain the operation of the sub-pixel 74, the image data 56A is transferred from, for example, the column driver 62 to the memory 78 for storage. Additionally or alternatively, the image data 92 / image data 56 or any suitable image data can be transferred to the memory 78 for storage. In some embodiments, the image data 56A may be clocked into the memory 78 by the data clock 118, such as on the rising edge, falling edge, or both of the data clock 118. The image data 56A transferred to the sub-pixel 74 can correspond to the desired gray level at which the sub-pixel 74 will emit light. Using the image data 56A stored in the memory 78, the comparator 120 determines whether the current number represented by the counter 108 is less than or equal to the image data 56A in the memory 78. In other words, the counter 108 counts up to the number indicated by the image data 56A, and in response to the number represented by the counter 108 satisfying a condition (e.g., being greater than or equal to the number indicated by the image data 56A), the comparator 120 outputs a control signal to turn on the switch 106 when the condition is met. When the condition is not met, the comparator 120 continues to output a control signal to keep the switch 106 closed, thus continuing the light emission of the LED 104. Additionally or alternatively, the comparator 120 can enable a deactivation control signal to cause the opening of the switch 106. For example, if the memory 78 stores the binary sequence 10110101 corresponding to the number 181, the comparator 120 will check whether the counter 108 has counted up to the number 181, and after the counter 108 exceeds the number 181, the comparator 120 transmits a signal to open the switch 106, thereby stopping the light emission of the LED 104.

[0085] When switch 106 is closed, an electrical connection is created between the common voltage 112 and the first reference voltage 114. This can cause current from current source 102 to be transmitted through LED 104, thereby causing light to be emitted from subpixel 74. Thus, by varying the digital value indicated by image data 56A, the emission period of subpixel 74 can be varied to control the perceived light emitted from subpixel 74. Additionally or alternatively, in some embodiments, a second reference voltage 116 is included to vary the total current value used to control the light emitted from LED 104. For example, the second reference voltage 116 can increase the sensitivity of LED 104 to current changes such that a lower current value can be used to cause light to be emitted from LED 104, or to enable LED 104.

[0086] Counter 108 counts from 0 to 255 and increments based on the gray scale clock 110, for example, at the rising edge of the gray scale clock 110. The period of the gray scale clock 110 represents the time difference between increments of the gray scale of display 18, e.g., the emission difference between emission gray scale 100 and emission gray scale 101. In this way, counter 108 counts up to the digital value represented by image data 56A stored in memory 78, thereby subsequently causing emission to occur during the time period corresponding to the desired gray scale. Counter 108 can continue to count beyond the digital value represented by image data 56A stored in memory 78 up to a maximum value (e.g., 255), and may restart counting at a minimum value (e.g., 0). Thus, in some embodiments, the counting range of counter 108 can be defined by the design of counter 108, e.g., by a plurality of registers and / or logic components included in counter 108. By the time counter 108 restarts counting at 0, additional image data 56A can be stored in memory 78 in order to begin comparison during the next emission period for the gray scale associated with the additional image data 56A.

[0087] By following this emission scheme, sub-pixel 74 can follow a single pulse width modulation emission scheme. A representation of the light emission from sub-pixel 74 following the single pulse width modulation emission scheme is shown in graph 122. Graph 122 includes an actual emission period 124 and a total emission period 126. The total emission period 126 corresponds to the total length of the emission represented by the maximum number (e.g., 255) transmitted as image data 56A, and can correspond to the maximum perceived brightness of the light emitted from sub-pixel 74. The actual emission period 124 corresponds to the period during which sub-pixel 74 emits light based on a number less than the maximum value transmitted as image data 56A (e.g., from counter 108). Counter 108 increments from 0 to 255, which takes the amount of time represented by the total emission period 126, while comparator 120 enables the light to be emitted for the amount of time represented by the actual emission period 124. In this way, sub-pixel 74 can emit light with different perceived brightnesses.

[0088] To elaborate Figure 8 on the operation of sub-pixel 74 shown, Figure 9 a process 130 for operating sub-pixel 74 having comparator 120 and memory 78 is described. Generally, process 130 includes: initializing the memory circuit (block 132), pre-charging the common output from the comparator (block 134), incrementing the count of the counting circuit (block 136), causing emission based on an auto-comparator determination stored in the memory circuit (block 138), determining whether the counting circuit has reached a maximum count (block 140). In response to the counting circuit reaching the maximum count, prepare the next image (block 142), and in response to the counting circuit not reaching the maximum count, continue to cause emission based on the auto-comparator determination stored in the memory circuit (block 138). In some embodiments, process 130 can be performed at least in part by: using a processing circuit (such as processing core complex 12) to execute instructions stored in a tangible non-transitory computer-readable medium (such as storage device 14). Additionally or alternatively, process 130 can be implemented at least in part based on circuit connections formed in the display control circuit, such as row driver 60, column driver 62, and / or timing controller 54.

[0089] Thus, in some embodiments, timing controller 54 can initialize memory 78 (block 132). To initialize memory 78, timing controller 54 can enable a control signal to force the nodes of memory 78 to a low voltage value, such as by an instruction to row driver 60 or column driver 62. Figure 8For example, to initialize the memory 78, the row driver 60 can enable a reset signal in response to a control signal received from the timing controller 54 to reset the voltage values of the nodes of the memory 78. Initializing the memory 78 enables the light-emitting circuit (e.g., LED 104) of the sub-pixel 74 to emit light until the comparator 120 outputs a control signal to stop the light emission (e.g., in response to the counter 108 reaching the gray level stored in the memory). In other words, for one or more sub-pixels 74 implementing the comparator 120, the sub-pixels 74 can start light emission simultaneously but stop light emission at different times - where the respective durations of the light emission correspond to the target gray levels of the respective sub-pixels 74.

[0090] After initializing the memory 78, the timing controller 54 can pre-charge the common output from the comparator 120 (block 134). The timing controller 54 can enable a pre-charge signal (e.g., via the row driver 60, via the column driver 62) to cause a voltage that boosts the circuit of the sub-pixel 74, thereby improving the responsiveness of the sub-pixel 74 to changes in the output from the comparator 120. It should be understood that any suitable circuit arrangement can be used to facilitate pre-charging of the sub-pixel 74.

[0091] After pre-charging the comparator 120, the timing controller 54 can increment the count of the counter 108 (block 136). The timing controller 54 can increment the counter 108 by using the gray level clock 110. After incrementing the counter 108, the sub-pixel 74 can automatically determine whether the count of the counter 108 is greater than or equal to the value represented by the image data 56A. This is because the respective bits of the count and the respective bits of the image data 56A are respectively transmitted to the comparator 120. The comparator 120 can output a logic high value when no bits match, or can output a logic low value when each bit matches or when a bit changes to indicate that the image data 56A has been counted beyond.

[0092] After incrementing the count of the counting circuit, the timing controller 54 can cause light emission based on the output of the comparator 120 (block 138). The value transmitted from the comparator 120 can activate or deactivate the switch circuit (e.g., switch 106) of the LED driver and the LED 104 responsible for emitting light.

[0093] The timing controller 54 can determine whether the count of the counter 108 is the maximum count (block 140). The counter 108 can count from a minimum value to a maximum value, e.g., from 0 to 255. Thus, when the counting circuit reaches the maximum value or the maximum count, the timing controller 54 can perform certain process steps to restart the count. It should be noted that in some embodiments, the timing controller 54 can count down instead of up, and thus, the timing controller 54 can determine whether the minimum count has been reached.

[0094] In response to not reaching the maximum count, the timing controller 54 may continue to cause light emission from the sub-pixels 74 (block 138). However, in response to reaching the maximum count, the timing controller 54 may prepare to present the next image frame (block 142). To this end, the timing controller 54 may prepare to receive new image data 56A corresponding to the target gray level of the sub-pixels 74 for transmitting the next image frame.

[0095] In some cases, the timing controller 54 may operate the sub-pixels 74 to emit light according to the binary order represented by the image data 56A. Sometimes, the row driver 60 may rearrange the bit order of the image data 56A to improve the driving efficiency of the sub-pixels 74, such as may occur when the image data 56A is thermally encoded. For example, if the image data 56A is equal to 0010, the row driver 60 may operate according to image data equal to 1-0-0-0 such that the emission time of the "1" appears first and no emission occurs after the period corresponding to "00". This rearrangement may improve the appearance of visual artifacts on the display 18 while still causing the same gray level (e.g., gray level = 2) indicated by "0010" to be emitted from the sub-pixels 74 rather than the gray level represented by the reordered image data (e.g., gray level = 8). When the row driver 60 reorders the image data 56A, it should be noted that the relative emission period of each bit may remain the same. For example, when data representing a gray level of 20 is reordered to effectively drive the sub-pixels 74, the reordering does not cause a change in the gray level of the image data 56A (e.g., gray level before reordering = 20 and gray level after reordering = 20).

[0096] Figure 10 is an illustration of an exemplary binary sequence 150, which is adjacent to the representation of the relative weights of each bit in each binary sequence 150. Each binary sequence may correspond to the image data 56A at some point in the operation of the display 18. Relative weights may be assigned to each bit position of each binary sequence 150 (e.g., summarized in Table 152). The bit plane illustration 154 may show the relative impact of each bit position on the overall gray level when using the bits to drive the sub-pixels 74 to emit light.

[0097] For example, bit position 0 may correspond to 1 relative impact unit on the light emission from the sub-pixels 74 (e.g., 2 0 = 1), and bit position 3 may correspond to 8 impact units (e.g., 2 3=8, which is 4 times the effect of bit position 0 on the overall grayscale.) For example, row 156 may correspond to the binary sequence "0001," row 158 may correspond to the binary sequence "0100," and row 160 may correspond to the binary sequence "1111." Bit plane diagram 154 visually illustrates a bit plane representation of each binary combination of binary sequence 150. In some cases, a corresponding binary sequence in binary sequence 150 corresponding to image data 56A may be used to drive subpixels 74, such as when the corresponding binary sequence is used as Figure 8 When the image data 56A is stored in the memory 78 (for example, when the memory 78 stores 4 bits).

[0098] The corresponding binary sequence in the binary sequence 150 can be hot-encoded to show how the binary sequence corresponds to the natural number representation of the number. Hot encoding can change the sequence 162A having a numerical value based on the binary number into a sequence 162B having a numerical value based on multiple consecutive values (e.g., consecutive "1" or "0" values). In this example, the value of the sequence 162B can be interpreted as having a numerical value equal to "11" (e.g., eleven) because there are eleven consecutive "1"s after the sequence 162A is hot-encoded. To illustrate it differently, the sequence 162A corresponds to the binary number "1011", which is represented by the sequence 162B "1111111111110000" when it is hot-encoded. Figure 10 Another one-hot encoding example is also shown. The binary number "1101" can be one-hot encoded to be equal to "1111111111111100".

[0099] As can be seen from the bit plane diagram 154, the binary sequence 150 can be represented according to a pattern in the bit plane representation. For example, the bit in bit position 3 can change the gray levels represented by the binary sequence from the numbers 0-7 to the gray levels representing the binary sequence of numbers 8-15. In this way, the bit in bit position 3 can be considered to have a relatively high impact on the perceived final value gray level of the light emitted by the sub-pixel 74.

[0100] To further elaborate on the bit plane diagram 154, Figure 11A A bit plane diagram 170 is shown, Figure 11B An error graph 172 is shown, Figure 11C A bit plane diagram 174 is shown, Figure 11D An error graph 176 is shown, Figure 11E A bit plane diagram 178 is shown, Figure 11F An error graph 180 is shown, Figure 11G A bit plane diagram 182 is shown, Figure 11H An error graph 184 is shown, with FIG. 11 as a whole illustrating the effect of reordering on the total error. Figures 11A to 11HRepresents the simulated performance of display 18 implementing the emission scheme, where the six-bit binary numbers representing the target gray levels of sub-pixels and / or pixels are and are not reordered.

[0101] Bit plane diagram 170 shows the original sequence of the emission scheme without any reordering of the gray levels represented by six bits, where all bit plane diagrams 170, 174, 178, and 182 have a bright portion 186 corresponding to light emission and a dark portion 188 corresponding to no light emission. In this first example, sub-pixel 74 can be driven to emit light at each indicated light portion 186 and not be driven to emit light at each indicated dark portion 188. Since the human eye can integrate the emitted light over time, the light emitted in a modulated, discontinuous manner can be perceived as smooth. However, since no reordering occurs in the first bit plane diagram 170, the light emission according to the indicated light portion 186 may be perceived as imperfect and have visual artifacts because sometimes the modulation is perceivable. The modulation can additionally or alternatively cause dynamic false contour (DFC) artifacts, which may or may not worsen when the observer of display 18 adjusts the viewing position (e.g., turns the head, moves the body).

[0102] When sub-pixel 74 is operated to emit light following an emission scheme without reordering (e.g., according to bit plane diagram 170), the total error count is high (e.g., error count = 322, and the errors can be perceived as visual artifacts such as DFC), as shown in error map 172. It may be desirable to reduce the total error count through reordering because these errors can appear on the electronic screen of display 18 as, for example, dynamic false contours, color splitting, and / or flickering of the light emitted from one or more pixels.

[0103] Since reordering occurs and the most significant bits are reordered to be emitted first to cause the gray levels of the bit plane diagrams, as shown in bit plane diagram 174 and bit plane diagram 178, the bit plane patterns tend to look like the ideal bit plane shown in bit plane diagram 182. Additionally, as shown in error map 172, error map 176, error map 180, and error map 184, when reordering occurs, the errors are reduced. Through the reordering of the bit planes, the perceived image quality can be improved by reducing the error count.

[0104] The ideal case (e.g., bit plane diagram 182) shows how the bit plane diagram 182 tends to gradually change in the bit plane as the gray level increases, and how the total error tends to approach the total number of states represented by the bit plane by increasing the number of reorderings (e.g., 6 bits correspond to a total of 64 states, following the relationship: number of states = 2 z, where z is the number of bits). Additionally, it should be noted that driving the sub-pixels 74 of the display 18 using single pulse width modulation techniques can be similar to the above-described ideal case (e.g., the bit plane diagram 182), and thus the occurrence of perceivable visual artifacts that occur when presenting an image frame can be reduced. It should be noted that the systems and methods described herein are described in terms of using these single pulse width modulation techniques to drive the sub-pixels 74. However, it should be understood that using the allocated external memory in combination with the memory within the pixel can provide similar benefits for each driving technique. For example, some binary pulse width modulation display systems can benefit from driving the sub-pixels partially from a combined portion of the memory allocated to the sub-pixels.

[0105] To further illustrate the in-pixel memory architecture, the in-pixel memory panel can implement memory within the active area and / or an intelligent buffer for the display 18. For example, Figure 12 is a block diagram showing an in-pixel memory architecture display 210 and an intelligent buffer architecture display 212. As shown, the in-pixel memory structure display 210 includes a memory 78 in each sub-pixel 74 located in the active area 214 of the display 18, where the active area 214 includes the light-emitting components of the display 18 and a communication coupling for supporting data transmission to the light-emitting components. In the in-pixel memory architecture display 210, digital data can be transmitted from the memory 216 to each corresponding sub-pixel 74 for local buffering in the memory 78. In some embodiments, the digital data is transmitted from the memory 216 to a source area (SA) 218 for local buffering (e.g., buffering within the sub-pixel 74) before being transmitted to the memory 78. However, a memory that is substantially similar to the memory 78 can be included in the intelligent buffer 220 of the intelligent buffer architecture display 212 to eliminate or at least reduce the dependence on the frame buffer and to remove the memory 78 from the active area 214. By moving the memory 78 into the intelligent buffer 220, the line driver 60 can use the input latch 222 and the output latch 224 to arbitrate the light emission from each sub-pixel 74 via an analog output circuit (such as the driver (DRV) 80). Here, the intelligent buffer 220 can represent any suitable buffer memory disposed within the integrated circuit of the display 18 but outside the active area of the display 18. It should be noted that although not specifically depicted, a readout circuit can be included between the memory 78 and the interface circuit to enable signal transmission from and / or to the memory 78.

[0106] Additionally, in some cases, some of the memory 78 can be included in the sub-pixels 74 and some of the memory 78 can be included in the intelligent buffer 220. Figure 13It is a block diagram showing another exemplary in-pixel memory architecture display 236. In the in-pixel memory architecture display 236, the sub-pixel 74 includes some of the total memory 78 allocated to the sub-pixel 74 (e.g., memory 78A), and the intelligent buffer 220 includes the remaining memory 78 allocated to the sub-pixel 74 (e.g., memory 78B). It should be noted that in these cases where the memory 78 is roughly divided into two parts (e.g., memory 78A and memory 78B), Figure 8 the content included in the sub-pixel 74 can be simplified. For example, the memory 78A can be included in the sub-pixel 74, while the memory 78B can be set outside the sub-pixel 74, such as in the intelligent buffer 220 or another memory, as Figure 14 shown. Referring back to Figure 8 , for clarity, the driver (DRV) 80 of the sub-pixel 74 can include a current source 102, a comparator 120, a switch 106, a circuit for transmitting the output from the memory 78A and / or the memory 78B to the sub-pixel 74 for processing, etc. In some cases, the comparator 120 can also be set outside the sub-pixel 74, and thus be set in the intelligent buffer 220, the row driver 60, the column driver 62, the timing controller 54, etc.

[0107] Figure 14 It is a block diagram showing yet another example of the in-pixel memory architecture display 238. In the in-pixel memory architecture display 238, the sub-pixel 74 includes some of the total memory 78 allocated to the sub-pixel 74 (e.g., memory 78A) and a memory 216 (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), including the remaining memory 78 allocated to the sub-pixel 74 (e.g., memory 78B). It should be noted that although not specifically depicted in Figure 13 and Figure 14 , the source region 218 can be additionally coupled between the intelligent buffer 220 and the active region 214 and / or coupled between the memory 216 and the active region 214, similar to Figure 12 shown.

[0108] Smart buffer 220 and / or a controller associated with memory 216 may perform a hot encoding operation on received image data 56A before sending a portion of the image data 56A to memory 78A. The hot encoding operation may help convert a target grayscale level into a feasible operation and / or generate control signals to time the activation of certain switches. In some cases, a switch that controls whether memory 78A or memory 78B affects the light emission of subpixels 74 may receive a control signal generated based on the data in memory 78B that has been hot encoded. For example, when memory 78B stores the most significant bit of "1010," when counting from the number 0 (the first binary state allowed as a 4-bit binary sequence), the most significant bit is equal to the number 7, and the switch may be controlled by a control signal equal to "1111 1110 0000 0000." The control signal may be toggled at a time substantially similar to when the counter is expected to reach the number 7.

[0109] In detail, Figure 15 is a diagram highlighting how the electronic device 10 (e.g., a controller or processor of the electronic device 10) may convert a target gray level into an action. For example, the electronic device 10 may drive the sub-pixels 74 based on control signals generated by the timing controller 54, the row driver 60, the column driver 62, the smart buffer 220, the controller of the memory 216, the processing core complex 12, etc. As described herein, the timing controller 54 is described as converting the target gray level into an actionable action, but it should be understood that any suitable processing circuitry of the electronic device 10 may perform some or all of the conversion operations. In some cases, a hot encoding operation may help convert the target gray level into a control signal and / or an actionable action for the sub-pixel 74, such as to identify how many sub-frames to use to cause the sub-pixel 74 to emit light at the target gray level.

[0110] The timing controller 54 can use the overwrite memory 78A and perform an all-on operation that causes the sub-pixels 74 to emit light throughout the sub-frame duration regardless of the data stored in the memory 78A (e.g., according to the data stored in the memory 78B), an all-off operation that overwrites the memory 78A and causes the sub-pixels 74 not to emit light throughout the sub-frame duration regardless of the data stored in the memory 78A, and / or a modulation operation that does not overwrite the memory 78A and causes the sub-pixels 74 to emit light according to the data stored in the memory 78A (as a way to cause the sub-pixels 74 to emit light at a target gray level). Thus, the timing controller 54 can control the light emission of the sub-pixels 74 by sometimes overwriting the memory 78A and by sometimes driving the sub-pixels 74 from the memory 78A. This dual driving (e.g., dual control) of the sub-pixels 74 can improve the efficiency associated with presenting and / or processing the image data of an input image frame. Thus, the sub-pixels 74 can be driven to emit light for a first duration according to (e.g., based on) a first digital data signal (e.g., the data stored in the memory 78B), and to emit light at a target gray level for a second duration according to a second digital data signal (e.g., the data stored in the memory 78A).

[0111] To control the light emission of the sub-pixels 74, each image frame display duration (e.g., each frame duration, each frame) can be considered to be divided into sub-frame display durations. The number of sub-frames used to form a complete image frame display duration can depend on the particular configuration of the memory 78 and thus on the binary arithmetic associated with the configuration of the memory 78. For example, the memory 78 can be divided into a memory 78A and a memory 78B. The ratio of the size of the depth of the memory 78A to the total size of the memory 78 can define the number of sub-frames. For the depicted example, the total size of the memory 78 corresponds to 256 bits (a total of 2 8 ^8 = 256 bits = 0 - 255), and the size of the memory 78A corresponds to 64 bits (e.g., a total of 2 6 ^6 = 64 bits = 0 - 63). Thus, four sub-frames can equal one frame (e.g., 256 / 64 = 4), and each sub-frame will emit one quarter of the target gray level assigned to the sub-pixels. It should be noted that the duration of each corresponding sub-frame can correspond to the duration for which the counter 108 is used to increment from count = 0 to count = 2 M (where 2 M represents the number of bits represented by the data stored in the memory 78A), as will be understood.

[0112] To help illustrate in detail, the timing controller 54 may receive a binary sequence for a target gray level equal to 255 (e.g., arrow 246), where 255 / 255 is represented by the natural number 248 shown. In this way, the timing controller 54 may drive the sub-pixels 74 from the memory 78B to cause 100% light emission for three sub-frames (e.g., all-on operation), and may drive the sub-pixels from the memory 78 to cause modulated light emission for one sub-frame (e.g., modulate but cause the sub-pixels 74 to emit light similar to the all-on operation). For an example where the target gray level is equal to 0 (e.g., arrow 250), the timing controller 54 may drive the sub-pixels 74 from the memory 78B and cause 0% light emission for each sub-frame (e.g., all-off operation) to convey the target gray level of 0.

[0113] In addition, for an example where the target gray level is equal to 120 (e.g., arrow 252), the timing controller 54 may drive the sub-pixels from the memory 78B to perform an all-on operation for the first sub-frame (e.g., arrow 254) to emit light at a gray level substantially similar to or equal to 63 / 63, drive the sub-pixels from the memory 78A to perform a modulation operation for the second sub-frame (e.g., arrow 256) to emit light at a gray level substantially similar to or equal to 55 / 63, and drive the sub-pixels from the memory 78B to perform an all-off operation for the third and fourth sub-frames (e.g., arrow 258A, arrow 258B) to emit light at a gray level substantially similar to or equal to 0 / 63 for the two sub-frames. Thus, when the operator of the display 18 perceives the light emission over four sub-frames, the sub-pixels 74 are perceived to emit light according to the target gray level of 119 (e.g., 119 / 2556 shown by the natural number 260).

[0114] Then, the timing controller 54 may allocate the emission operations for each sub-pixel 74 to each sub-frame. Sometimes, the sub-pixels 74 are instructed to emit light regardless of the data stored in the memory 78A (e.g., all-on operation, all-off operation), and sometimes the sub-pixels 74 are instructed to emit light according to the data stored in the memory 78A. For example, the modulation operation may allow the sub-pixels 74 to emit light according to the data (e.g., binary data) stored in the memory 78A.

[0115] The data stored in memory 78B may correspond to relatively higher significant bit positions than the bit positions represented by the data stored in memory 78A, enabling memory 78B to drive continuous light emission or unmodulated light emission (no light or unmodulated light). In this way, when sub-pixel 74 accumulates to emit at a target gray level, higher significant bits that have a greater impact on the final gray level can be used to drive sub-pixel 74, regardless of the lower significant bits. This emission can continue until it is time to use the lower significant bits in the light emission to fine-tune the total amount of light emitted so that it is perceived as the target gray level.

[0116] Figure 16 is a graph showing the γ relationship between the gray level (e.g., x-axis) and the pulse width control operation (e.g., y-axis). The dashed line 276 shows how the sub-frames and the binary data range supported by memory 78 can conform to the dual-memory drive technique. Each sub-frame may correspond to a range of 2 M gray levels. In this way, the gray levels in the first sub-frame may correspond to the gray levels between 0 and 2 M - 1, the second sub-frame may correspond to the numbers between 2 M - and 2 * 2 M - 1, the third sub-frame may correspond to the numbers between 2 * 2 M and 3 * 2 M - 1, and the fourth sub-frame may correspond to the numbers between 3 * 2 M and 4 * 2 M - 1. When driving sub-pixel 74 to emit light at the target gray level 278, sub-pixel 74 can be operated to emit unmodulated light during the first sub-frame, modulated light during the second sub-frame, and no light during the third and fourth sub-frames.

[0117] The most significant bits that control the modulation operation of sub-pixel 74 can be updated between sub-frames, such as in response to direct control signals from the timing controller 54, row driver 60, column driver 62, etc., and / or in response to a counter incrementing through a binary counting sequence until it equals the target gray level. In this way, the bits that control whether sub-pixel 74 emits unmodulated light, no light, or modulated light can be updated between sub-frames. Updating this bit between sub-frames enables the emission behavior to be changed from sub-pixel 74. It should be noted that in some cases, the display 18 can be a linear display, which can change the relationship between the gray level and the pulse width control operation (e.g., the pulse width used to control light emission does not necessarily increase exponentially over time and may increase at a constant rate as the gray level increases).

[0118] Figure 17 is a circuit diagram of sub-pixel 74 including an in-pixel memory circuit. As at least referenced Figure 8As described, using in-pixel memory technology and comparator 120 enables the row driver to create a single pulse-width modulation emission scheme. Thus, Figure 17 An example of sub-pixel 74 including comparator 120, memory 78A, and memory 78B is shown in Figure 17 . It should be understood that sub-pixel 74 is intended to be illustrative and not limiting. For example, although comparator 120 is shown coupled to the LED driver circuit and the light-emitting circuit of sub-pixel 74, comparator 120 can be coupled to any suitable light-emitting circuit and / or driver circuit.

[0119] In the depicted sub-pixel 74, image data 56A is used to generate data 284 to be stored in memory 78A and data 286 to be stored in memory 78A. Writing data 284 to memory 78 may involve row driver 60 causing control signal 288 (e.g., write_en control signal) to cause data 284 to be transmitted into inverter pair 290. In some embodiments, row driver 60 operates in series with column driver 62 to cause all bits associated with data 284 to be transmitted in parallel into inverter pair 290 by simultaneously enabling control signal 288. Additionally or alternatively, by selectively enabling control signal 288, e.g., by selectively enabling control signal 288A to cause the first bit of data 284 to be transmitted to load a bit into inverter pair 290A, row driver 60 can cause bit-by-bit transmission of the bits associated with data 284.

[0120] Data 286 stored in inverter pair 292 may correspond to a control signal generated by row driver 60, column driver 62, timing controller 54, etc. that causes sub-pixel 74 to emit light according to an all-on operation. Additionally or alternatively, data 286 stored in inverter pair 292 may correspond to a comparison result (e.g., a comparison result).

[0121] The row driver 60, column driver 62, timing controller 54, etc. can generate a comparison result by comparing the most significant bit stored in the memory 78B with the corresponding most significant bit (e.g., a part of the current count) of the current count of the counter 108. While waiting for the most significant bit stored in the memory 78B to match the corresponding most significant bit of the current state of the count, the sub-pixel 74 emits light according to the all-on operation because the light emission will be performed regardless of the bit value stored in the memory 78. When the most significant bit stored in the memory 78B matches the corresponding most significant bit of the count, the comparison result can be switched and cause the switched value to be stored in the inverter pair 292. In some cases, the comparison result stored in the inverter pair 292 can be equal to a logic high value (e.g., a voltage value interpreted as a logic high value by the circuitry of the electronic device 10). The comparison result can be applied to the switch 294 and cause the switch 294 to decouple the comparator 120 from the inverter pair 296 in response to the matched comparison result having a logic high value.

[0122] Once the data 284 is stored in the inverter pair 290 and once the data 286 stored in the inverter pair 292 permits the modulation driving of the sub-pixel 74 (e.g., the match has occurred and the data 286 produces a comparison result indicating that the count at least matches the corresponding bit of the image data 56A), the light emission can continue according to the modulation operation. During the modulation output, the comparator 120 uses the stored bits of the data 284 and the count bits (e.g., CNT) indicating the current count received from the counter 108 at the switch 298 (e.g., a transistor) to perform a comparison between these two sets of bits.

[0123] As a reminder, in the single-pulse width modulation emission scheme, the counter 108 may increment to the maximum gray level in response to a transition of a clock signal (such as the gray-level clock 110), where light emission occurs from the sub-pixel 74 until the counter 108 is counting up to and / or exceeding the number represented by the stored data 284. The counter 108 may include nodes, where the signals of the nodes can be transmitted as values of binary numbers that can be interpreted as counting by the circuit. For example, when counting 1 out of 15, the counter 108 may generate a signal representing "0001" because the largest number represented by 4 bits is 15. Each switch 298 may receive a signal representing the count or a signal represented by the reverse count (e.g., CNTn<0:4>, inverse). When each signal representing the count matches each signal representing the data 284 (e.g., when each bit matches each bit), the comparator 120 may output a logic high signal (e.g., MTCH = 1). When the count does not match the data 284, the comparator 120 may output a logic low signal (e.g., MTCH = 0) because at least one signal combination may cause at least one switch 298 to be coupled to ground (e.g., a logic low reference voltage, a system low voltage, a voltage equal to 0 volts, the first reference voltage 114) without coupling the logic high output from the corresponding inverter in the inverter pair 290 to the switch 294. In this way, the comparator 120 compresses all the bits of the data 284 into a single bit, which indicates whether the data 284 is the same as the count transmitted from the counter 108. Therefore, the comparator 120 performs a bitwise exclusive-NOR (XNOR) function compression on a single bit, where the output of the comparator 120 is a logic low (e.g., "0") value unless each bit matches.

[0124] The output from the comparator 120 may be stored in the inverter pair 296. The inverter pair 296 may retain the value until the row driver 60 uses the reset signal 300 to reset the voltage stored by the inverter pair 296. The reset signal 300 may activate the switch 301 (e.g., initialize the transistor). When the switch 301 is "on" (e.g., activated), the inverter pair 296 may be coupled to ground.

[0125] In addition, switch 302 may be included in sub-pixel 74 to provide energy-saving benefits by pre-charging the common output node (e.g., MTCH) of comparator 120, thereby enabling the circuit to better respond to changes in the output of comparator 120. Pre-charging the common output node may involve timing controller 54 and / or line driver 60 generating and transmitting a pre-charge signal 304 (PCH) to cause switch 294 to couple the common output node to a system logic high reference voltage. Pre-charging one or more parts of sub-pixel 74 before driving sub-pixel 74 may allow for smaller voltage changes to alter the operation of sub-pixel 74, such as by bringing the voltage levels of components closer to the voltage level that separates logic low from logic high in the system. It should be noted that the output from the depicted circuit is output as an emission control (EM) signal 306 that drives the emission of LED 104 from sub-pixel 74 until the output from comparator 120 stops the emission (e.g., MTCH = 1). Inverter pair 296 may receive a value for storage in response to switch 307 being activated, thereby completing the circuit path to inverter pair 296. Thus, timing controller 54 may drive sub-pixel 74 to first determine whether the count of counter 108 matches image data 56A, and then activate switch 307 to lock in the result of the determination (e.g., comparison) in the circuit of inverter pair 296.

[0126] It should be understood that the described in-pixel memory technology may be applied in a variety of effective embodiments, and thus, in some embodiments, the counting circuit may decrement. In this way, if each bit matches, comparator 120 may output a logic low value, and / or switch 302 may be excluded from sub-pixel 74.

[0127] To further illustrate the operation, Figure 18 is a timing diagram comparing the change in the count 308 of counter 108 with the state of EM signal 306. The gray-scale clock 110 may monotonically increase, thereby causing an increase in the duration between changes in count 308. The duration corresponding to each sub-frame is depicted by a line similar to line 310. In this way, the first sub-frame of this example corresponds to an all-on operation (e.g., symbol 312), the second sub-frame of this example corresponds to an all-on operation (e.g., symbol 314), the third sub-frame of this example corresponds to an all-on operation (e.g., symbol 316), and the fourth sub-frame of this example corresponds to an all-on operation (e.g., symbol 318).

[0128] During a specified write period 320 between a first sub-frame and a second sub-frame, such as between transitions in count 308 (and thus also between transitions in gray-scale clock 110), bits stored in memory 78B (e.g., the most significant bit (MSB)) may not be updated, and thus the sub-pixel 74 continues to be driven from memory 78B. Between the second sub-frame and the third sub-frame (e.g., during write time duration 322), memory 78B may be updated to store data equal to 0. This switches which memory drives sub-pixel 74 from memory 78B to memory 78A. Thus, during the third sub-frame (e.g., sub-frame duration 324), memory 78A drives sub-pixel 74 to emit light. Sub-pixel 74 emits light according to a modulation operation because it is expected that light emission stops at some time during the third sub-frame duration 324. In this case, light emission stops at time 326, and the total amount of light emitted by sub-pixel 74 before time 326 is perceived as the target gray-scale or substantially similar to the target gray-scale.

[0129] Figure 19 A process 340 for operating sub-pixel 74 according to a dual-control drive scheme is shown. Generally, process 340 includes initializing a memory circuit for a current frame (e.g., the frame) (block 342), pre-charging a common output from a comparator (block 344), causing emission based on dual-control operation (block 346), and preparing for the next frame (block 350). In some embodiments, process 340 may be performed at least in part by: using a processing circuit (such as processing core complex 12) to execute instructions stored in a tangible non-transitory computer-readable medium (such as storage device 14). Additionally or alternatively, process 340 may be implemented at least in part based on circuit connections formed in a display control circuit, such as row driver 60, column driver 62, and / or timing controller 54. As described herein, process 340 is performed by timing controller 54.

[0130] Thus, in some embodiments, the timing controller 54 may initialize the memory 78 to prepare for presenting a frame (e.g., the current frame, the current frame to be presented) (block 342). To initialize the memory 78, the timing controller 54 may use the row driver 60 and / or the column driver 62 to generate control signals to force one or more nodes of the memory 78 to a low voltage value to reset and / or clear the memory 78. The timing controller 54 may enable the reset signal 300 (e.g., via the row driver 60) to reset the voltage value stored in the inverter pair 296. In some cases, the memory 78 is instructed by the timing controller 54 to write the image data 56A into the memory 78 for initialization. Initializing the memory 78 may enable the light-emitting circuit of the subpixel 74 (e.g., LED 104) to emit light until the comparator 120 outputs a control signal to stop the light emission (e.g., in response to the counter 108 reaching the gray level stored in the memory). In other words, for one or more subpixels 74 implementing the comparator 120, the subpixels 74 may start light emission simultaneously but stop light emission at different times, where the corresponding durations of the light emission correspond to the target gray levels of the respective subpixels 74.

[0131] The row driver 60 may pre-charge the subpixels 74 after initializing the memory 78 (block 344). To pre-charge the subpixels 74, the row driver 60 may enable a pre-charge signal to cause a voltage that boosts the node that couples the output of the comparator 120 to the input of the inverter pair 296. Boosting the node may result in the subpixels 74 responding better to changes from the output of the comparator 120.

[0132] After pre-charging one or more portions of the subpixels 74, the timing controller 54 causes light emission from the subpixels 74 based on a dual control operation (block 346). For example, the timing controller 54 may change the count of the counter 108 (e.g., increment, decrement). The timing controller 54 may increment the counter 108 by using the gray-level clock 110 such that the count represented by the output from the counter 108 changes in response to the rising or falling edge of the gray-level clock 110. Once the count of the counter 108 exceeds the image data 56A, the light emission from the LED 104 may stop. After changing the count of the counter 108, the subpixels 74 may automatically determine whether the count of the counter 108 is greater than or equal to the value represented by the image data 56A. This is because a subset of the bits of the count and a subset of the bits of the image data 56A are transmitted to the comparator 120 for comparison. The comparator 120 may output a logic high value when there is no bit match, or may output a logic low value when each bit matches or when a bit changes to indicate that the image data 56A has been counted past. This output from the comparator 120 may stop the light emission from the subpixels 74.

[0133] Once the sub-pixels 74 emit light at the target gray level, or an amount of light substantially similar to the target gray level, the timing controller 54 may prepare to present the next frame or a portion of the next frame (as may be the case in a partial frame presentation operation) (block 350). In this manner, the timing controller 54 may repeat the operations of process 340 to present subsequent frames, where the subsequent frames may include one or more repeated gray levels from the initial frame. When the gray levels assigned to the sub-pixels 74 do not change between frames, the data stored in the memory 78 may not be changed or may be overwritten. In some cases, each sub-pixel 74 receives image data 56A for a subsequent frame, regardless of whether a portion of the initial frame is repeated in the subsequent frame, or whether a portion of the subsequent frame is to be presented using a sub-pixel 74 that emits light at a repeated gray level relative to the initial frame.

[0134] For further explanation refer to Figure 19 The dual control operation discussed (e.g., block 346), Figure 20 is a diagram depicting the full on operation of subpixel 74 (e.g., as represented over time as in box 360) and the modulated operation of subpixel 74 (e.g., as represented over time as in box 362) in response to the count of counter 108 (e.g., as represented over time as in box 364), Figure 21 is a diagram depicting the total shut-down operation of the sub-pixel 74 (e.g., as represented over time as in box 366) in response to the count of the counter 108 (e.g., as represented over time as in box 364). Figure 20 and Figure 21 Describe together. Figure 20 and Figure 21 The example memory system shown in FIG corresponds to memory 78 having a total size of 8 bits, with memory 78A storing 6 bits and memory 78B storing 2 bits. Block 364 shows a representation of the count maintained by counter 108 over time. In this manner, counter 108 may include a plurality of serially coupled flip-flops or state-holding devices that operate in response to a clock (e.g., grayscale clock 110) to cause outputs to transition between binary states (e.g., outputs representing voltage levels at nodes between the serially coupled flip-flops or devices).

[0135] For this exemplary memory configuration where the memory 78 has a total size of 8 bits, there can be a total range of 256 gray levels. "00000000" can represent the lowest gray level among the 256 gray levels, and "11111111" can represent the highest gray level among the 256 gray levels. The drivable sub-pixel 74 can emit light according to the data stored in the memory 78, where the stored data can indicate a target gray level outside of this total gray level range. For example, the target gray level in this example can correspond to 140 from the 256 total options for gray levels (e.g., 54.7% brightness relative to the maximum brightness). The gray level 140 can be represented by the binary data "10001100". In this example, the memory 78B stores the relatively higher significant bits of the target gray level (e.g., the binary data "10"), and the memory 78A stores the remaining bits (e.g., the binary data "001100").

[0136] When controlling the light emission from the sub-pixel 74, the generally described comparison operation can be divided into two operations (e.g., dual control). The first operation can cause light emission until the higher significant bits match, and then once the higher significant bits match, the second operation can cause light emission until the remaining bits (e.g., the lower significant bits) match (e.g., to fine-tune the gray level). During the first operation, light emission is caused based on the comparison between the bits stored in the memory 78B and the corresponding bits of the count (e.g., bit 368). In this example, whenever the count is incremented, the corresponding bit of the count is compared with the bit stored in the memory 78B. Since the image data 56A cannot be equal to the count when the first few bits do not match, the drivable sub-pixel 74 can be made to emit light without having to concern whether the remaining bits match via an all-on operation (e.g., block 360) while waiting for the first few bits of the count to match the image data 56A.

[0137] When driven according to the all-on operation (e.g., block 360), the sub-pixel 74 emits light regardless of the data stored in the memory 78A. When the first two bits of the count do not match the data stored in the memory 78B, the data 286 is equal to the logical high value (e.g., "1"), and the switch 294 is operated to be open. When the switch 294 is open, the output of the comparator 120 can be stopped so that it cannot drive the sub-pixel 74 to emit light. Once the first two bits of the count match the data stored in the memory 78B, the data 286 can change to be equal to the logical low value (e.g., "0"). The write control signal 291 (write_enX control signal) can be enabled during the all-on operation (e.g., block 360) such that the change is captured relatively quickly in the inverter pair 292 after the change occurs.

[0138] To illustrate the change, a subset 370 of the represented count states corresponds to the case where the first two bits of the count do not match the data stored in memory 78B (e.g., "00000000" to "01111111"), and a subset 372 of the represented count states corresponds to the case where the count matches the data stored in memory 78B (e.g., "10000000" to "10111111"). When the data 286 changes to a logic low value (e.g., "0"), the switch 294 is activated, allowing the output from the comparator 120 (e.g., MTCH) to drive the light emission of the sub-pixel 74.

[0139] When the data 286 changes to a logic low value (e.g., "0"), the sub-pixel 74 can be driven to emit light according to the data stored in the memory 78B via a modulation operation (e.g., block 362), where any remaining bits of the image data 56A are used to fine-tune the amount of light emitted by the sub-pixel 74 during an all-on operation (e.g., block 360). The sub-pixel 74 can emit light until the remaining bits of the count are greater than or equal to the image data 56A. When the count is greater than the image data 56A (e.g., once the last six bits of the count exceed the six bits of the image data 56A stored in the memory 78A), the output from the comparator 120 can be a logic high level, and thus the light emission from the sub-pixel 74 can be stopped as part of an all-off operation (e.g., block 366). This transition between the modulation operation (e.g., block 362) and the all-off operation (e.g., block 366) can occur in response to the count changing from count 374 to count 376.

[0140] When driven according to the all-off operation (e.g., block 366), the sub-pixel 74 may not emit light and / or can be driven not to emit light. The transition to the all-off operation (e.g., block 366) can lock the logic high value generated by the comparator 120 into the inverter pair 296 and / or can disable the precharge signal 304, thereby preventing the output of the comparator 120 from adjusting the value stored in the inverter pair 296. In this way, new image data 56A can be loaded into the memory 78A after the transition to the all-off operation (e.g., block 366) to prepare for the next frame without interrupting the presentation of the ongoing frame. When the count completes the transition on the remaining states corresponding to the subset 378 of the count states, the all-off operation (e.g., block 366) can continue (e.g., "10001101" to "11111111"). The sub-pixel 74 may not be driven to emit light again until the inverter pair 296 is reset and stores a logic low value (e.g., "0"). In this way, when preparing to start presenting a subsequent frame, the timing controller 54 can transmit a reset signal 300 (e.g., from Figure 17). It should be noted that because the inverter pair 292 is operated to store the comparison result in response to the write control signal 291, the value stored in the inverter pair 292 may not change during the all-off operation (e.g., block 366) because the write control signal 291 is not transmitted during the all-off operation (e.g., block 366). It should be noted that although the term "all" is used to describe "all-on operation" or "all-off operation", it should be understood that these operations may be applied to one subpixel 74, one pixel 70, a region of the pixel array 70, a region of a subpixel 74, the entire display 18, or any combination thereof.

[0141] Using dual controls (e.g., memory 78A and memory 78B) to drive subpixels 74 can help reduce the power consumed by driver circuitry (e.g., inverter pair 290, comparator 120) by reducing the amount of time the driver circuitry drives subpixels 74 to emit light because the driver circuitry can be decoupled from the power supply when subpixels 74 are not being driven. Dual-control driving can additionally or alternatively improve the driving flexibility of display 18 by increasing the number of options for loading image data and / or driving subpixels 74 to emit light. Furthermore, dual-control driving of subpixels 74 can enable single pulse-width modulation drive techniques to be used with pixels that include memory.

[0142] Figure 22 is a timing diagram of exemplary operations of sub-pixels 74 according to various operations of process 340. For example, timing controller 54 may drive sub-pixels 74 according to an initialization operation (e.g., block 342), a pre-charge operation (e.g., block 344), an increment and evaluation operation (e.g., block 346), a write-back operation, and finally a preparation operation (e.g., block 350) to prepare for the next frame after performing one or more interactions of the pre-charge operation, the write operation, and / or the increment and evaluation operation. Various combinations of control signals generated in response to instructions from timing controller 54 may be used in Figure 22 shown in and described herein.

[0143] For example, to initialize the subpixel 74, the timing controller 54 may cause the reset signal 300 to be activated. Initialization may cause the value stored by the inverter pair 296 (e.g., signal 392) to be reset to a logic low value (e.g., "0"). Activation of the reset signal 300 may correspond to resetting the clock used to transition the count (e.g., signal 394) maintained by the counter 108 and received at the switch 298 of the comparator 120. Signal 394 may have a sufficiently high value after the initialization period 396 and the precharge period 398 so that the first instance of a count change (e.g., from 0 to 1) occurs once the subpixel 74 is ready to continue emitting.

[0144] To precharge subpixels 74 , timing controller 54 may toggle precharge signal 304 (eg, signal 400 ). Image data 56A may be loaded into some or both of memories 78 (eg, memory 78A, memory 78B) during initialization period 396 .

[0145] During the increment and evaluation period 404, the precharge signal 304 may switch to a state opposite to the state during a portion of the precharge period 398. The count may be incremented in response to the state of the clock (e.g., signal 394), wherein the portion of the signal 394 labeled "4'h0" corresponds to the duration between count changes, such as the duration that drives the counter 108 to update its count. The portion of the signal 394 labeled "4'hn ... 4'h1 ... 4'hF" may correspond to the duration associated with the count of the counter 108 being read as indicated by the number "4'hb," "4'h1," etc.

[0146] The count may be automatically evaluated for a match with the image data 56A stored in memory 78. If the count matches the image data 56A stored in memory 78B, the value of the output from comparator 120 may change (e.g., as indicated by a toggle of signal 406). It should be noted that signal 406 may be briefly driven high during precharge period 398 to reset the value of the output from comparator 120, thereby precharging the node coupling comparator 120 to switch 294, and the evaluation may be performed after precharge period 398 (and any subsequent precharge periods). The output of comparator 120 may be precharged one or more times per frame so that a relatively low voltage change can cause a change in the state of switch 294, thereby causing a temporary toggle of signal 406 during precharge period 398.

[0147] Once signal 406 goes high during the precharge period 398, subsequent high levels of signal 406 during the increment and evaluation period 404 may cause the output from the inverter pair 296 to go high during the writeback period 408. The switch 307 can be controlled in response to a logic high level of a control signal (e.g., signal 410). During the writeback period 408, the switch 307 can be activated in response to signal 410 switching to the logic high level, so that the output from the comparator 120 is stored as signal 392 in the inverter pair 296. The light emission from the subpixel 74 stops in response to signal 392 going high. Signal 392 can remain high until the subsequent initialization period 396 corresponding to a subsequent frame, thus until the next frame. Additionally, once signal 392 goes high and remains high, signal 406 can stop charging to the high level and thus can remain at the logic low value until the subsequent initialization period 396. In this way, it can be considered that signal 406 (e.g., the output from the comparator 120) and signal 392 (e.g., the output from the inverter pair 296) can be reset at substantially similar times during the initialization period 396 and / or in response to the reset signal 300.

[0148] Considering the foregoing, the timing controller 54 can reload data for each subpixel 74 between sub - frames. This may mean that sometimes the data stored in the memory 78A changes between sub - frames such that the memory 78A can be loaded independently of the loading operation of the memory 78B. For example, the data stored in the memory 78A during the first sub - frame of the first frame can correspond to the previous frame until the timing controller 54 updates the data stored in the memory 78 for the current frame. This can improve the driving operation by increasing the parallel driving and / or parallel image frame processing capabilities of the display 18 (e.g., being able to load one image frame when the rendering of the second image frame is completed). Consider the case where the first image frame is rendered before the second image frame. The first image frame can be displayed during a set of four sub - frame driving periods, and the second image frame can be displayed during a set of four sub - frame driving periods. The timing controller 54 can drive the subpixel 74 to emit light from the memory 78A for the last sub - frame corresponding to the rendering of the first image frame while loading data into the memory 78B for the rendering of the first sub - frame corresponding to the rendering of the second image frame.

[0149] Furthermore, in some cases, data can be stored in the memory 78A during a loading operation similar to that of the memory 78B, so that the memory 78A is pre - loaded before the emission operation (e.g., modulation operation 362) according to the memory 78A. When driving the display 18 using separate loading sequences for the memory 78A and the memory 78B, the loading of each part of the memory 78 can occur when it is relatively optimal for the display 18, such as when a refresh has occurred, which can improve the efficiency of the display 18.

[0150] As discussed throughout this disclosure, it should be understood that in-pixel memory technology is effective for various embodiments and display technologies. It should also be understood that for each reference voltage discussed or disclosed in the figures, additional or alternative reference voltages may be used. Additionally or alternatively, it should be noted that although described as reducing or eliminating the reliance on using a frame buffer, in some embodiments, the in-pixel memory technology may be used in series with a frame buffer. Furthermore, although the memory circuit has been described as storing 6 bits and / or 8 bits, it should be understood that any suitable memory structure may be used to store any suitable number of bits, such as 12 bits or 16 bits. It should also be noted that any of the systems or methods described may be used in combination with each other. For example, a memory shared between sub-pixels may benefit from a driving method that also uses memory externally allocated to the sub-pixels when driving the corresponding sub-pixels to emit light.

[0151] Accordingly, the technical effects of this disclosure include techniques for implementing memory in one or more pixels of a display to improve the processing techniques for image data for presentation, e.g., by representing a target gray level using a bit depth that is relatively higher than the bit depth that can be stored by a single memory storing data corresponding to the target gray level. These techniques include systems and methods for receiving image data, storing the image data in memory allocated to the pixels (e.g., in memory internal to the pixels and allocated external memory), and transmitting the image data to a driver circuit to operate the light-emitting elements of the pixels to emit light. By driving the pixels according to the image data stored in the memory allocated to the pixels, the driving operation can be improved, for example, by increasing the flexibility of the options for loading or storing the image data of the pixels and / or by increasing the bit depth that can be used for loading or saving the image data to exceed the capabilities provided by the in-pixel memory (e.g., the memory internal to the pixels). For example, storing the image data in the in-pixel memory can be loaded at a different time than the image data to be loaded into the external memory allocated to the pixels. Additionally, using dual control driving of the sub-pixels can help reduce the power consumed by the driving circuit of the sub-pixels and / or the sub-pixels by reducing the amount of time for the circuit (e.g., the driving circuit) of the sub-pixels to transmit an electrical signal to drive the sub-pixel 74. The duration of transmitting the electrical signal using the circuit of the sub-pixels can reduce time and / or reduce the number of power-consuming components because some of the circuits of the sub-pixels can be decoupled from the power supply when not used to drive the sub-pixel 74. Furthermore, the dual control of the sub-pixel 74 enables the single pulse width modulation driving technique to be used with pixels including memory.

[0152] The techniques described herein can be applied to and integrated with various display technologies and should not be limited to the specific embodiments depicted and / or described herein. For example, pixels with memory are shown with light-emitting diodes as light-modulating devices, however, the in-pixel memory technology can generally be applied to different pixel circuits to support various display technologies using various light-modulating devices. In this way, suitable pixel circuits that support light emission via light-emitting diodes, digital mirror displays, organic light-emitting diodes, or circuits that support liquid crystal displays, plasma displays, or dot matrix displays can each have memory in the pixel to achieve at least improvements in data transmission bandwidth and ease of pixel programming.

[0153] The above specific embodiments have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should also be understood that the claims are not intended to be limited to the specific forms disclosed, but are intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the present disclosure.

[0154] The technology described and claimed herein is cited and applied to specific examples of a tangible and practical nature that significantly advance the art and is therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [the function]..." or "a step for [performing] [the function]...", then those elements will be construed under 35 U.S.C. § 112(f). However, for any claim containing elements designated in any other manner, those elements will not be construed under 35 U.S.C. § 112(f).

Claims

1. A display system, comprising: A display driver, the display driver comprising: A first memory configured to store only a first digital data signal of a frame generated by a controller, the first digital data signal for causing light to be emitted from a portion of a display of the display system at a target gray level, wherein the target gray level is represented by a value within a data range, and wherein the value is configured to be represented partially by the first digital data signal and partially by a second digital data signal generated by the controller; and A pixel circuit communicatively coupled to the display driver, wherein the pixel circuit comprises: A second memory configured to store only the second digital data signal of the frame received from the controller; and A light emitting diode configured to emit light at a luminance corresponding to the target gray level at least in part by: Emitting light according to the first digital data signal during a first duration; and Emitting light according to the second digital data signal during a second duration.

2. The display system according to claim 1, comprising: A counter; And A first comparator that compares the first digital data signal with a first subset of bits of a binary output from the counter to determine that the first subset of bits of the binary output from the counter matches the first digital data signal.

3. The display system according to claim 2, wherein the pixel circuit is configured to drive the light emitting diode to emit light according to the first digital data signal during the first duration in response to the first comparator determining that the binary output from the counter matches the first digital data signal.

4. The display system according to claim 2, wherein the first comparator determines that the binary output from the counter matches the first digital data signal at least in part by comparing a most significant bit of a count represented by the binary output from the counter with the first digital data signal, wherein the first digital data signal is configured to represent a most significant bit of a plurality of bits representing the value within the data range.

5. The display system according to claim 4, wherein the pixel circuit comprises a second comparator that compares the second digital data signal with a second subset of the binary output from the counter to determine that the second subset of the binary output from the counter matches the second digital data signal.

6. The display system according to claim 1, wherein the pixel circuit comprises: An initialization transistor configured to initialize the pixel circuit before the light emitting diode emits light; And A driving transistor configured to be activated at least in part based on the second digital data signal.

7. The display system according to claim 6, wherein the driving transistor is configured as a metal-oxide-semiconductor field-effect transistor (MOSFET), and wherein the pixel circuit includes a plurality of p-type or n-type MOSFETs configured to cause the light-emitting diode to emit light in response to a control signal.

8. The display system according to claim 1, wherein the second memory includes a register and a comparator, the register is configured to store the second digital data signal, the comparator is configured to compare the second digital data signal with an output generated by a counter, and wherein the second memory is configured to transmit the output from the comparator to cause the light-emitting diode to emit light.

9. An electronic device, comprising: a first memory configured to store only a first digital data signal of a frame; and a display panel including a plurality of pixels, the plurality of pixels including a first pixel, wherein the first pixel includes a second memory configured to store only a second digital data signal of the frame, wherein the display panel is configured to emit light from the first pixel at a target gray level during a first duration corresponding to the frame, wherein the target gray level is represented by emitting light using the first digital data signal during a second duration of a first sub-frame corresponding to the frame and by emitting light using the second digital data signal during a third duration of a second sub-frame corresponding to the frame.

10. The electronic device according to claim 9, wherein the first pixel is configured to emit light based on the first digital data signal when the second memory is loaded with the second digital data signal.

11. The electronic device according to claim 9, wherein the first pixel includes a light-emitting diode, an organic light-emitting diode, or a circuit supporting a liquid crystal display, a plasma display panel, a dot matrix display, a digital mirror drive display, or any combination thereof.

12. A method, comprising: storing only a first binary value of a frame in a first memory and storing only a second binary value of the frame in a second memory via a controller associated with a display, the display including a first pixel that emits light according to a target gray level, the second memory being disposed in the first pixel, wherein the target gray level is represented by a binary sequence that represents the first binary value before the second binary value in the binary sequence; driving the first pixel via the controller to emit light at least in part based on the first binary value in the first memory at least in part by: incrementing a count maintained by a counter of the display via the controller; and comparing, via the controller, a first portion of a binary output from the counter with the first binary value to determine that the count is greater than or equal to the first binary value, wherein the binary output from the counter is configured to identify a current state of the count. In response to determining that the count is greater than or equal to the second binary value, driving, via the controller, the first pixel to emit light at least partially based on the second binary value in the second memory, at least in part by: Incrementing, via the controller, the count held by the counter; And Comparing, via the controller, the second part of the binary output with the second binary value to determine that the count is greater than or equal to the second binary value; And In response to determining that the count is greater than or equal to the second binary value, driving, via the controller, the first pixel to stop light emission during the remaining duration allocated for presenting an image frame.

13. The method according to claim 12, the method comprising: Initializing, via the controller, the first pixel before driving the first pixel to emit light at least partially based on the first binary value; And Pre-charging, via the controller, the nodes of the first pixel before incrementing the count held by the counter.

14. The method according to claim 12, wherein the first part of the binary output corresponds to the most significant bit position of the binary sequence, and wherein the second part of the binary output corresponds to any remaining bit positions of the binary sequence.

15. The method according to claim 12, comprising resetting, via the controller, the first pixel and a comparator circuit for performing the comparison to a reset voltage to prepare for a subsequent image frame.

16. The method according to claim 12, the method comprising: Driving, via the controller, the first pixel to emit light at least partially based on the first binary value, at least in part by: Disabling, via the controller, a switch disposed between the second memory and the first pixel in response to a first comparison result configured to indicate that the count is less than or equal to the first binary value; And Enabling, via the controller, the switch in response to determining that the count is greater than the first binary value.

17. A system, comprising: Means for storing only a first part of a binary value corresponding to a target gray level of a frame in a first pixel; Means for storing only a second part of the binary value corresponding to the target gray level of the frame outside the first pixel; And Means for driving the first pixel to emit light at the target gray level at least partially based on the first part of the binary value and the second part of the binary value.

18. The system according to claim 17, wherein the means for driving the first pixel to emit light at the target gray level comprises: Means for comparing the first part of the binary value with a count corresponding to an amount of time; And Means for driving the first pixel to emit light at least partially based on the comparison.

19. The system according to claim 17, wherein the means for driving the first pixel to emit light at the target gray level comprises: Apparatus for maintaining a count of a bit depth corresponding to the first part of the binary value; and Apparatus for driving the first pixel to emit light throughout the count when the second part of the binary value corresponds to a first state and for driving the first pixel to emit light at least partially based on the first part of the binary value when the second part of the binary value corresponds to a second state.

20. A system, comprising: A display driver integrated circuit, the display driver integrated circuit including a first memory configured to store only the most significant bits of digital data corresponding to a target gray level of a first pixel; and A display panel, the display panel including the first pixel, wherein the display panel includes: A second memory configured to store a plurality of least significant bits of the digital data corresponding to the target gray level of the first pixel, the second memory being disposed in the first pixel; A plurality of counter values corresponding to a count having a bit depth equal to the plurality of least significant bits of the digital data; A plurality of comparators configured to respectively compare the plurality of least significant bits of the digital data with the plurality of counter values; A driver circuit configured to drive the first pixel: To emit light continuously when the most significant bit of the digital data has a first state; and To emit light modulated based on the comparison of the plurality of comparators when the most significant bit of the digital data has a second state.

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