A loongson 2K-based vpX management control arbitration device and method

Abstract

This invention relates to a VPX management and control arbitration device and method based on the Loongson 2K chip, belonging to the field of intelligent management and control and its localization technology. This invention, through a multi-bus, multi-redundancy mechanism, can achieve real-time decoding output of B-code timing information, multi-channel switching output of video and control functions, and interconnection of gigabit Ethernet networks. The core chip adopts an independently controllable domestic design, unaffected by bans. In unattended operation, the arbitration device can monitor the heartbeat of external host modules in real time, performing real-time monitoring, management, and control, achieving hot backup from modules to applications and rapid response intelligent management and control. All external display and control outputs are implemented by the arbitration device; the external host module only needs to focus on control calculations, while the management tasks are centralized in the arbitration device, and tasks are distributed among modules, reducing the failure rate.

Description

Technical Field

[0001] This invention belongs to the field of intelligent management and control and its localization technology, specifically relating to a VPX management and control arbitration device and method based on Loongson 2K. Background Technology

[0002] If a control system or control method can effectively overcome the high complexity and uncertainty of the controlled object (or process) and environment, and achieve the desired goal, then this control method is called an intelligent control method. Intelligent management control is a type of automatic control that can independently drive intelligent machines to achieve their goals without human intervention. With the continuous improvement of VPX architecture technology, intelligent management control technology also needs to be introduced in some unattended application scenarios. Furthermore, with external factors such as chip restrictions, finding a domestically developed solution to integrate intelligent management control technology with the VPX architecture has become increasingly urgent.

[0003] To meet the needs of domestic production and realize intelligent management and control of VPX architecture devices, it is urgent to design a VPX management and control arbitration device. Summary of the Invention

[0004] (a) Technical problems to be solved

[0005] The technical problem to be solved by this invention is to overcome the shortcomings of existing domestic intelligent management and control technologies based on the VPX architecture, specifically the problem that the core hardware chip cannot be domestically produced, or that the performance is too low after domestic production and cannot meet the system requirements. On the basis of ensuring the realization of intelligent management and control, this invention designs a domestically produced VPX architecture management and control arbitration device.

[0006] (II) Technical Solution

[0007] To address the aforementioned technical issues, this invention provides a VPX management and control arbitration device based on the Loongson 2K chip. This device interconnects with external host devices via the VPX bus, enabling arbitration management of these devices. Specifically, the video and control switching section employs a multi-bus, multi-redundancy scheme to switch the video and control outputs of the external host devices, thereby achieving display and control output. Dual-redundant control decodes and outputs B-code time synchronization signals, ensuring unified time synchronization for the external host devices. A gigabit network switching chip is used as the network interconnection component, enabling high-speed data interaction between the CPU, FPGA, and BMC, and external communication, thus achieving high-speed communication with external host devices.

[0008] Preferably, the device includes a CPU, an FPGA, and a BMC, which interact with each other. The FPGA communicates with the CPU via UART and PCIe, and the CPU communicates with the BMC via UART and SPI. In addition, the three communicate with each other through a gigabit network switching chip. All three can send switching control commands to the video and control switching section to switch the output of video signals and USB control signals input from the external host device. Furthermore, the FPGA and BMC can decode the input B-code timing information and distribute it to the external host device.

[0009] Preferably, the device uses a Loongson 2K1000 CPU, and the network interconnection part is implemented through a gigabit network switching chip 88E6185, which also enables the interconnection between the CPU and the BMC chip GD32F450. The device detects the working status of the external host device by receiving the GPIO heartbeat signal; it receives the video signal and USB control signal from the external host device, and switches the display and control outputs based on the determination of the working status.

[0010] Preferably, the video and control switching section comprises two parts. One part is implemented using an 8-to-1 video switching chip MAX4617, which can switch between 8 VGA video signal inputs and 1 VGA video signal output. The other part is implemented using two 8-to-1 USB signal switching chips MAX4999, which can switch between 8 differential USB control signal inputs and 1 differential USB control signal output. In addition, the arbitration device also uses a video switching chip LT8511A-M set between the 8-to-1 video switching chip MAX4617 and the VPX bus to switch 4 HDMI / DVI video signals to VGA video signals.

[0011] Preferably, the CPU is connected to one port of the Gigabit network switch chip 88E6185 via a PCIe network card and a PHY controller; the FPGA is connected to the Gigabit network switch chip 88E6185 via a PHY controller; and the BMC is connected to the Gigabit network switch chip 88E6185 via a 100Mbps PHY controller. In addition to these three interfaces, the Gigabit network switch chip 88E6185 also outputs seven Gigabit Ethernet ports to the VPX bus for connecting external host devices.

[0012] Preferably, the Loongson 2K1000 CPU chip uses a 40nm process, integrates two GS264 processor cores with a clock speed of 1GHz, integrates a shared 1MB L2 cache, a 64-bit 533MHz DDR3 controller, two x4 PCIe 2.0 interfaces, and two RGMII gigabit network interfaces.

[0013] Preferably, the device uses the SMQ7K325T FPGA chip from Guowei Company, which contains 840 digital signal processors, 445 36Kb BRAMs, 326080 logic units, 10 CMTs, 1 PCIe 2.1, and 16 GTXs, which are programmable resources.

[0014] Preferably, the device also uses GigaDevice's ARM chip GD32F450, which employs an ARM Cortex-M4 32-bit processor core and integrates 3072KB of FLASH storage and 512KB of SRAM storage on-chip.

[0015] The present invention also provides a method for managing arbitration using the aforementioned device.

[0016] Preferably, it includes the following steps:

[0017] Step 1. Power on the equipment; the arbitration device and all external host devices are powered on and started.

[0018] Step 2. During the startup process of the arbitration device, the firmware defaults to outputting the video and control data of the first external host device.

[0019] Step 3. The arbitration device uses Gigabit Ethernet and GPIO to determine whether the first external host device has a heartbeat;

[0020] Step 4. If step 3 determines that the first external host device has a heartbeat, then start the main application of the first external host device and notify the second external host device to start the same main application through the network interconnection part;

[0021] Step 5. The arbitration device records and monitors the application status of the two external host devices in real time;

[0022] Step 6. The arbitration device ensures that the two external host devices maintain time consistency by decoding and distributing the B-code time information;

[0023] Step 7. If step 3 determines that the first external host device has no heartbeat, the arbitration device will switch the video and control to the second external host device;

[0024] Step 8. The BMC of the arbitration device resets the first external host device via the VPX bus, and the second external host device starts the main application;

[0025] Step 9. The arbitration device monitors the heartbeat of the two host modules in real time. If one of them fails, the video, control, and application are switched to the other host module.

[0026] (III) Beneficial Effects

[0027] This invention discloses a VPX management and control arbitration device and method based on the Loongson 2K chip. Through a multi-bus, multi-redundancy mechanism, it can achieve real-time decoding output of B-code timing information, multi-channel switching output of video and control functions, and interconnection of gigabit Ethernet networks. The core chip adopts an independently controllable domestic design, unaffected by bans. In unattended operation, the arbitration device can monitor the heartbeat of external host modules in real time, performing real-time monitoring, management, and control, achieving hot backup from modules to applications and rapid response intelligent management and control. All external display and control outputs are implemented by the arbitration device. External host modules only need to focus on control calculations, while management tasks are centralized in the arbitration device, and tasks are distributed among modules, reducing the failure rate. Attached Figure Description

[0028] Figure 1 This is a block diagram illustrating the principle of the management control arbitration device upon which the method of this embodiment of the invention is based;

[0029] Figure 2 This is a block diagram illustrating the video and control switching principle upon which the method of this embodiment is based;

[0030] Figure 3 This is a block diagram illustrating the network interconnection principle upon which the method of this embodiment of the invention is based. Detailed Implementation

[0031] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0032] The following is combined with Figure 1 The diagram shown illustrates the principle of the management control arbitration device. Figure 2 The diagram showing the video and control switching principle and Figure 3 The network interconnection principle block diagram shown further describes the apparatus and method of the present invention.

[0033] like Figure 1 As shown, the present invention provides a VPX management and control arbitration device based on Loongson 2K that communicates with external host devices via the VPX bus, thereby realizing arbitration management of external host devices.

[0034] This arbitration device adopts a CPU+FPGA+BMC architecture. Through the video and control switching section, a multi-bus, multi-redundancy scheme is used to achieve video and control switching output. Dual-redundant control is employed to decode and output B-code timing signals. A gigabit network switch chip is used for network interconnection, enabling high-speed data interaction between the CPU, FPGA, and BMC, as well as external communication. The entire device uses a VPX architecture bus for interconnection, supporting B-code timing, USB control, serial port, PCIe bus, GPIO, VGA video, and 1000BASE-T interfaces. All core chips are domestically designed.

[0035] Information exchange exists between the CPU, FPGA, and BMC. With the CPU at its core, the FPGA communicates with the CPU via UART and PCIe, while the CPU communicates with the BMC via UART and SPI. Furthermore, they communicate with each other through a gigabit network switch (88E6185). All three can send control commands to switch the output of video VGA signals and USB control signals input from external host devices. In addition, the FPGA and BMC can decode the input B-code timing information and distribute it to the external host device. In summary, through a gigabit Ethernet network, the arbitration device achieves high-speed communication with external host devices, realizes display and control output from external host devices through video and control switching, and achieves unified time synchronization for external host devices through B-code parsing, thereby realizing arbitration management of external host devices.

[0036] The system employs a Loongson 2K1000 CPU, interconnected with the GD32F450 BMC module via an 88E6185 network switch. The arbitration device receives GPIO heartbeat signals from external host devices to detect their operational status; it also receives HDMI / DVI video signals and USB control signals from the external host devices, using these status indicators to switch between display and control outputs; and it achieves arbitration management of the external host devices through a UART serial port and a 1000BASE-T gigabit Ethernet network.

[0037] like Figure 2As shown, the video and control switching section mainly consists of two parts. One part is based on the MAX4617 8-to-1 video switching chip, which can switch between 8 VGA video signal inputs and 1 VGA video signal output. The other part is based on two MAX4999 8-to-1 USB signal switching chips, which can switch between 8 differential USB control signal inputs and 1 differential USB control signal output. In addition, the arbitration device can also switch 4 HDMI / DVI video signals to VGA video signals through the LT8511A-M video switching chip set between the MAX4617 8-to-1 video switching chip and the VPX bus. Moreover, the CPU, FPGA, and BMC can all send switching control commands to control the switching process.

[0038] like Figure 3 As shown, the network interconnection is mainly implemented using the Gigabit network switch chip 88E6185. The CPU connects to one port of the Gigabit network switch chip 88E6185 via a PCIe network card and a PHY controller; the FPGA connects to the Gigabit network switch chip 88E6185 via the PHY controller; and the BMC connects to the Gigabit network switch chip 88E6185 via a 100Mbps PHY controller. In addition to these three interfaces, the Gigabit network switch chip 88E6185 can also output seven Gigabit Ethernet ports to the VPX bus for connecting external host devices.

[0039] Loongson's 2K1000 CPU chip uses a 40nm process and integrates two GS264 processor cores with a clock speed of 1GHz. It also integrates a shared 1MB L2 cache, a 64-bit 533MHz DDR3 controller, two x4 PCIe 2.0 interfaces, and two RGMII gigabit network interfaces.

[0040] The SMQ7K325T FPGA chip from Guowei Company contains 840 digital signal processors, 445 36Kb BRAMs, 326,080 logic units, 10 CMTs, 1 PCIe 2.1, 16 GTXs, and other programmable resources. It can realize high-performance digital signal processing, large-capacity logic operations, and other applications, and has high bandwidth data throughput. It is fully compatible with Xilinx's XQ7K325T-FFG900.

[0041] GigaDevice's ARM chip GD32F450 uses an ARM Cortex-M4 32-bit processor core, integrates 3072KB of FLASH storage and 512KB of SRAM storage on-chip, and has abundant I / O resources and peripheral interfaces, which can meet both standard and advanced communication needs.

[0042] The specific management arbitration steps implemented using this device are as follows:

[0043] Step 1. Power on the equipment; all devices are powered on and started.

[0044] Step 2. During the startup process of the arbitration device, the firmware defaults to outputting the video and control functions of the external host device 1.

[0045] Step 3. The arbitration device uses Gigabit Ethernet and GPIO to determine whether the external host device 1 has a heartbeat;

[0046] Step 4. If step 3 determines that external host device 1 has a heartbeat, then start the main application of external host device 1 and notify external host device 2 to start the same main application through the network interconnection part;

[0047] Step 5. The arbitration device records and monitors the application status of the two external host devices in real time;

[0048] Step 6. The arbitration device ensures that the two external host devices maintain time consistency by decoding and distributing the B-code time information;

[0049] Step 7. If step 3 determines that external host device 1 has no heartbeat, the arbitration device will switch the video and control to external host device 2;

[0050] Step 8. The BMC of the arbitration device resets external host device 1 via the VPX bus, and external host device 2 starts the main application;

[0051] Step 9. The arbitration device monitors the heartbeat of the two external host devices in real time. If one of them fails, the video, control, and application need to be switched to the other external host device.

[0052] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for implementing management arbitration by using a Loongson 2K-based VPX management control arbitration device, characterized in that, This device communicates with external host devices via the VPX bus, enabling arbitration management of these devices. Specifically, the video and control switching section employs a multi-bus, multi-redundancy scheme to switch the video and control outputs of the external host devices, thus achieving display and control output. Dual redundancy control decodes and outputs B-code time synchronization signals, ensuring unified time synchronization for the external host devices. A gigabit network switching chip is used for network interconnection, enabling high-speed data exchange between the CPU, FPGA, and BMC, and external communication, thereby achieving high-speed communication with external host devices. The device includes a CPU, FPGA, and BMC, which interact with each other. The FPGA communicates with the CPU via UART and PCIe, and the CPU communicates with the BMC via UART and SPI. In addition, the three communicate with each other through a gigabit network switching chip. All three can send switching control commands to the video and control switching section to switch the output of video signals and USB control signals input from external host devices. Furthermore, the FPGA and BMC can decode the input B-code timing information and distribute it to the external host devices. The device uses a Loongson 2K1000 CPU, and the network interconnection part is implemented through a gigabit network switch chip 88E6185, which also enables the interconnection between the CPU and the BMC chip GD32F450. The device detects the working status of the external host device by receiving GPIO heartbeat signals; it also receives video signals and USB control signals from the external host device, and switches between display and control outputs based on the determination of the working status. The video and control switching section comprises two parts. One part is implemented using an 8-to-1 video switching chip MAX4617, which can switch between 8 VGA video signal inputs and 1 VGA video signal output. The other part is implemented using two 8-to-1 USB signal switching chips MAX4999, which can switch between 8 differential USB control signal inputs and 1 differential USB control signal output. In addition, the arbitration device also uses a video switching chip LT8511A-M set between the 8-to-1 video switching chip MAX4617 and the VPX bus to switch 4 HDMI / DVI video signals to VGA video signals. The CPU connects to one port of the 88E6185 gigabit network switch chip via a PCIe network card and a PHY controller; the FPGA connects to the 88E6185 gigabit network switch chip via a PHY controller; the BMC connects to the 88E6185 gigabit network switch chip via a 100 Mbps PHY controller. In addition to these three interfaces, the 88E6185 gigabit network switch chip also outputs seven gigabit Ethernet ports to the VPX bus for connecting external host devices. The method includes the following steps: Step 1. Power on the equipment; the arbitration device and all external host devices are powered on and started. Step 2. During the startup process of the arbitration device, the firmware defaults to outputting the video and control signals from the first external host device; Step 3. The arbitration device uses Gigabit Ethernet and GPIO to determine whether the first external host device has a heartbeat; Step 4. If step 3 determines that the first external host device has a heartbeat, then start the main application of the first external host device and notify the second external host device to start the same main application through the network interconnection part; Step 5. The arbitration device records and monitors the application status of the two external host devices in real time; Step 6. The arbitration device ensures that the two external host devices maintain time consistency by decoding and distributing the B-code time information; Step 7. If step 3 determines that the first external host device has no heartbeat, the arbitration device will switch the video and control to the second external host device; Step 8. The BMC of the arbitration device resets the first external host device via the VPX bus, and the second external host device starts the main application; Step 9. The arbitration device monitors the heartbeat of the two host modules in real time. If one of them fails, the video, control, and application are switched to the other host module.

Images