Space accelerator performance evaluation method, electronic device, and computer storage medium
By introducing a layout factor and utilizing a graph neural network model in the performance evaluation of space accelerators, the inaccuracy and inefficiency of evaluation caused by relying solely on the number of clock cycles in existing technologies are solved, achieving faster and more efficient performance evaluation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ALIBABA (CHINA) CO LTD
- Filing Date
- 2022-08-16
- Publication Date
- 2026-05-19
AI Technical Summary
Existing methods for evaluating the performance of space accelerators only consider the number of clock cycles, which cannot accurately assess their performance, resulting in inaccurate and inefficient evaluation results.
The layout factor is used as an evaluation parameter. The layout factor of the space accelerator is quickly obtained through a graph neural network model, and the performance is evaluated in combination with the number of clock cycles.
This has enabled more accurate and efficient performance evaluation of space accelerators, improving evaluation efficiency and reducing evaluation costs.
Smart Images
Figure CN115238594B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of intelligent chip design technology, and in particular to a method for evaluating the performance of space accelerators in space exploration, an electronic device, and a computer storage medium. Background Technology
[0002] A chip accelerator is a hardware circuit that can perform various functions. It can achieve higher performance or better energy efficiency than a general-purpose microprocessor when executing a set of instructions. Among chip accelerators, the spatial accelerator (SA) is an important type.
[0003] Space accelerators are characterized by parallel execution units, which are arranged in space as pulsating arrays or as parallel vector units. An exemplary space accelerator structure is shown below. Figure 1 As shown in the figure, spatial accelerators are typically organized into a hierarchical array structure, initially composed of sliced tiles connected by explicit pipe registers. Each tile can be further decomposed into a set of processing elements (PEs), each PE performing one or a set of multiplication-accumulation operations per cycle. Due to the regular structure of spatial accelerators, which facilitates linear algebra operations such as matrix multiplication and convolution, many existing accelerators, such as deep neural network (DNN) accelerators, adopt the spatial accelerator form.
[0004] For space accelerators, taking DNN accelerators as an example, there are many variable parameters in their hierarchical array structure design, resulting in a huge design space. To select the best design from this vast space, a common approach is to evaluate the accelerator's performance by assessing the number of clock cycles under different designs. However, when a space accelerator executes operations or instructions, fewer clock cycles do not necessarily mean faster execution speed. This method, which only considers the number of clock cycles, cannot accurately evaluate the performance of a space accelerator. Summary of the Invention
[0005] In view of this, embodiments of this application provide a performance evaluation scheme for space accelerators in space exploration to at least partially solve the above-mentioned problems.
[0006] According to a first aspect of the present application, a method for evaluating the performance of a space accelerator in space exploration is provided, comprising: acquiring hierarchical array structure information of the space accelerator to be evaluated; determining the number of clock cycles and a layout factor corresponding to the space accelerator based on the hierarchical array structure information, wherein the layout factor is used to characterize the degree of influence of the hierarchical array structure indicated by the hierarchical array structure information on the frequency of the space accelerator; and evaluating the performance of the space accelerator based on the number of clock cycles and the layout factor.
[0007] According to a second aspect of the present application, an electronic device is provided, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform an operation corresponding to the method described in the first aspect.
[0008] According to a third aspect of the embodiments of this application, a computer storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the first aspect.
[0009] According to a fourth aspect of the embodiments of this application, a computer program product is provided, including computer instructions that instruct a computing device to perform an operation corresponding to the method described in the first aspect.
[0010] According to the solution provided in the embodiments of this application, when evaluating the performance of a space accelerator, both the clock cycle count and the layout factor are considered simultaneously to achieve a more accurate and efficient performance evaluation. This is because the performance of a space accelerator is actually related not only to the clock cycle count but also to the frequency. For the same task, a lower clock cycle count may correspond to a lower operating frequency, resulting in poor overall performance; conversely, a higher clock cycle count may correspond to a higher operating frequency, making the space accelerator perform better than one with a lower clock cycle count. However, while considering both clock cycle count and operating frequency provides a more accurate assessment of the space accelerator's performance, the operating frequency acquisition cycle is long, typically requiring several hours. This makes the performance evaluation process too time-consuming and costly. In the embodiments of this application, a layout factor is used. The layout factor can characterize the influence of the hierarchical array structure (or layout of the space accelerator) on the operating frequency. Since the corresponding operating frequency can be evaluated and determined when the hierarchical array structure of the space accelerator is determined, and the layout factor is easier and more efficient to obtain than the operating frequency, using the layout factor instead of the operating frequency to evaluate the performance of the space accelerator can accurately evaluate the relative performance of the space accelerator and obtain the performance evaluation results quickly and efficiently. This improves the overall performance evaluation efficiency of the space accelerator and reduces the performance evaluation cost. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0012] Figure 1 This is a schematic diagram of the structure of a space accelerator;
[0013] Figure 2 A schematic diagram of an exemplary system for evaluating the performance of a space accelerator according to embodiments of this application;
[0014] Figure 3A This is a flowchart illustrating the steps of a space accelerator performance evaluation method according to an embodiment of this application.
[0015] Figure 3B for Figure 3A A schematic diagram of the prediction process of a layout factor predictor in the illustrated embodiment;
[0016] Figure 3C for Figure 3B The diagram shows the process of obtaining training samples for the layout factor predictor.
[0017] Figure 3D for Figure 3A A schematic diagram illustrating a specific scenario example of the embodiment shown;
[0018] Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation
[0019] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.
[0020] The specific implementation of the embodiments of this application will be further described below with reference to the accompanying drawings.
[0021] As mentioned earlier, existing space accelerators exhibit considerable variability in their hierarchical array structure design. For example, in Figure 1 As shown in the spatial hierarchy array structure, different numbers of tiles can create different space accelerators; even with the same number of tiles, different tile arrangements will also create different space accelerators; even with the same number and arrangement of tiles, different numbers and / or arrangements of physical components (PEs) within a particular tile or tiles will also create different space accelerators; and so on, different numbers and arrangements of components within PEs will also create different space accelerators. These different space accelerators have different performance characteristics. When evaluating space accelerator performance using clock cycles as a parameter, space accelerators with fewer clock cycles tend to have better performance, while those with more clock cycles tend to have worse performance. However, this evaluation method cannot accurately assess the performance of space accelerators.
[0022] For example, as shown in the table below:
[0023]
[0024] As can be seen, for space accelerators 1 and 2 with different hierarchical array structures, if only the number of clock cycles is considered, the performance of space accelerator 2 is better than that of space accelerator 1. However, because the frequency of space accelerator 1 is higher than that of space accelerator 2, space accelerator 1 actually has better performance. Therefore, considering both clock cycles and frequency can yield a more accurate performance evaluation result compared to considering only the number of clock cycles. However, the frequency needs to be obtained based on the processing and calculation of various layout information of the space accelerators, which is a complex and lengthy process, typically taking more than ten hours. Therefore, this application provides a scheme that uses a layout factor as a parameter to compare the relative performance of space accelerators with different layouts, in order to select the space accelerator layout with superior performance. In this application embodiment, the layout factor can be obtained within seconds, greatly improving the efficiency and speed of space accelerator performance evaluation.
[0025] The performance evaluation scheme of the space accelerator of this application will be described below through several embodiments.
[0026] Figure 2 An exemplary system applicable to embodiments of this application is shown. For example... Figure 2 As shown, the system 100 may include a cloud server 102, a communication network 104, and / or one or more user devices 106. Figure 2 The example in the text refers to multiple user devices. It should be noted that the space accelerator performance evaluation method in this application embodiment can be implemented independently on the cloud server 102, independently on the user device 106, or jointly by the cloud server 102 and the user device 106.
[0027] The cloud server 102 can be any suitable device for storing information, data, programs, and / or any other suitable type of content, including but not limited to distributed storage system devices, server clusters, computing cloud server clusters, etc. In some embodiments, the cloud server 102 can perform any suitable function. When the cloud server 102 performs a space accelerator performance evaluation independently, the cloud server 102 can determine the clock cycle number and layout factor corresponding to the space accelerator based on the hierarchical array structure information of the space accelerator to be evaluated, and then perform the space accelerator performance evaluation based on the clock cycle number and layout factor.
[0028] User equipment 106 may include any one or more user devices for storing information, data, programs, and / or any other suitable type of content. When performing space accelerator performance evaluation independently by user equipment 106, user equipment 106 may determine the clock cycle number and layout factor corresponding to the space accelerator based on the hierarchical array structure information of the space accelerator to be evaluated, and then perform the space accelerator performance evaluation based on the clock cycle and layout factor. In some embodiments, user equipment 106 may include any suitable type of device. For example, in some embodiments, user equipment 106 may include mobile devices, tablet computers, laptop computers, desktop computers, and / or any other suitable type of user equipment.
[0029] When the performance evaluation of a space accelerator is jointly performed by the cloud server 102 and the user equipment 106, the user equipment 106 can send information about at least one space accelerator to be evaluated to the cloud server 102, or send hierarchical array structure information of at least one space accelerator to be evaluated to the cloud server 102. Then, the cloud server 102 obtains the hierarchical array structure information corresponding to the space accelerator based on the space accelerator information, or directly determines the clock cycle count and layout factor corresponding to the space accelerator based on the hierarchical array structure information, and then performs the performance evaluation of the space accelerator based on the clock cycle count and layout factor. After obtaining the performance data of the space accelerator, the cloud server 102 can return the data or information corresponding to the performance data of the space accelerator to the user equipment 106.
[0030] In some embodiments, communication network 104 may be any suitable combination of one or more wired and / or wireless networks. For example, communication network 104 may include any one or more of the following: the Internet, intranet, wide area network (WAN), local area network (LAN), wireless network, digital subscriber line (DSL) network, frame relay network, asynchronous transfer mode (ATM) network, virtual private network (VPN), and / or any other suitable communication network. User equipment 106 may be connected to communication network 104 via one or more communication links (e.g., communication link 112), and communication network 104 may be linked to cloud server 102 via one or more communication links (e.g., communication link 114). Communication links may be any communication link suitable for transmitting data between user equipment 106 and cloud server 102, such as network links, dial-up links, wireless links, hardwired links, any other suitable communication links, or any suitable combination of such links.
[0031] Based on the above system, this application provides a method for evaluating the performance of space accelerators in space exploration, which will be described below through examples.
[0032] Reference Figure 3A This document illustrates a flowchart of the steps involved in evaluating the performance of a space accelerator during design space exploration, according to an embodiment of this application. In chip design, design space exploration (DSE) refers to the systematic analysis and pruning of unwanted design points based on parameters of interest. These parameters may vary depending on the system, and commonly used parameters include power, performance, and cost. Applying the solution of this embodiment to design space exploration can help chip designers select chip designs that meet their needs and standards, especially for the layout and structural design of space accelerators, thereby effectively improving the design efficiency of space accelerators.
[0033] Based on this, the space accelerator performance evaluation method of this embodiment includes the following steps:
[0034] Step S202: Obtain the hierarchical array structure information of the space accelerator to be evaluated.
[0035] like Figure 1 As shown, the space accelerator has a hierarchical array structure, consisting of TILEs, PEs, and various elements within the PEs, such as registers and caches. Differences in the number of TILEs, their arrangement on the silicon wafer, the number and arrangement of PEs within each TILE, and the number and arrangement of each element within the PEs will result in different layouts of the space accelerator. The hierarchical array structure information of the space accelerator effectively describes its layout, corresponding to the specific settings of each layer.
[0036] In practical applications, hierarchical array structure information can be implemented as any appropriate information that can represent the hierarchy and the layout of each hierarchy. For example, {space accelerator identifier, [(TILE identifier 1, TILE position 1), (TILE identifier 2, TILE position 2) ... (TILE identifier n, TILE position n)], [(TILE identifier 1, PE identifier 1, PE position 1), (TILE identifier 1, PE identifier 2, PE position 2), ... (TILE identifier 1, PE identifier n, PE position n), ... (TILE identifier n, PE identifier 1, PE position 1), (TILE identifier n, PE identifier 2, PE position 2), ... (TILE identifier n, PE identifier n, PE position n)]}, etc.
[0037] The space accelerator to be evaluated can be one or more space accelerators specified by the user, or it can be a space accelerator within the design space formed during the chip design process using chip design automation tools. For example, a design space formed based on the BOOM (Berkeley Out-of-Order Machine) microarchitecture specification, etc. In this case, the space accelerator to be evaluated can be provided by the design space. It should be noted that this embodiment uses the performance evaluation of a single space accelerator as an example, but those skilled in the art should understand that when the solution of this application embodiment is applied to the design space scenario, all space accelerators in the design space can be traversed and their performance evaluated to select the space accelerator that meets the requirements and has a better layout.
[0038] In other words, in this case, this step can be implemented as follows: According to preset rules, select one space accelerator from multiple space accelerators already designed in a preset design space as the space accelerator to be evaluated. The design space is used for the hierarchical array structure layout design of the space accelerator. Obtain the hierarchical array structure information of the space accelerator to be evaluated. Further, based on the performance evaluation results corresponding to multiple space accelerators, select a space accelerator that meets preset criteria from among the multiple space accelerators. The preset rules can be appropriately set by those skilled in the art according to actual needs, such as random selection rules, sequential selection rules, etc., and this application embodiment does not limit this. In addition, the preset criteria can also be appropriately set by those skilled in the art according to actual needs, for example, selecting the space accelerator with the highest performance evaluation score, or selecting the top N space accelerators in performance evaluation score ranking, etc. In this way, the solution of this application embodiment can be effectively integrated into traditional chip design automation tools to improve the chip design automation tools, increase the speed and efficiency of chip performance evaluation, and reduce performance evaluation costs.
[0039] Step S204: Determine the number of clock cycles and the layout factor corresponding to the space accelerator based on the hierarchical array structure information.
[0040] The number of clock cycles for a space accelerator can be obtained in a conventional way. For example, based on the hierarchical array structure of the space accelerator, the number of clock cycles can be obtained by calculating the memory access ratio through analysis operators, such as a ceiling model or analytical model.
[0041] The layout factor characterizes the influence of the hierarchical array structure indicated by the hierarchical array structure information on the frequency of the space accelerator. As mentioned earlier, once the layout of the space accelerator, i.e., the hierarchical array structure, is determined, its corresponding operating frequency can also be largely determined. However, under existing methods, obtaining the operating frequency typically takes several or even tens of hours. In this embodiment, a layout factor is used, which can be presented as any one or more of the following: bus length, line congestion data, and signal delay data corresponding to the hierarchical array structure information. Compared to the operating frequency of the space accelerator, these layout factors can be obtained more quickly and efficiently.
[0042] However, in order to control the acquisition time of the layout factor to be on the same order of magnitude as the acquisition time of the clock cycle number, a feasible approach is to use a graph neural network model. Therefore, this embodiment further includes: constructing a structure graph corresponding to the hierarchical array structure information using a pre-trained graph neural network model for predicting the layout factor; and obtaining the layout factor corresponding to the hierarchical array structure information based on the structure graph. The graph neural network can employ a lightweight graph neural network structure to simplify model implementation and improve model processing efficiency.
[0043] Furthermore, since the hierarchical array structure information has a corresponding hierarchical structure, it can be described in the form of a graph, which also facilitates subsequent processing by the graph neural network model. Therefore, when constructing a structure graph corresponding to the hierarchical array structure information using a pre-trained graph neural network model for predicting layout factors, the hierarchical array structure information can be input into the pre-trained graph neural network model for predicting layout factors; through the first vector layer of the graph neural network model, the information corresponding to the computational elements within each TILE in the hierarchical array structure information is constructed into corresponding TILE node information; through the second vector layer of the graph neural network model, the corresponding structure graph is generated based on the constructed TILE node information.
[0044] After generating the structure graph, obtaining the layout factors corresponding to the hierarchical array structure information based on the structure graph can be achieved by using a classification network of a graph neural network model to obtain the layout factors corresponding to the hierarchical array structure information based on the structure graph. By using a classification network, the layout factors corresponding to the structure graph can be determined quickly and effectively, thus allowing for a faster and more efficient determination of the layout factors corresponding to the hierarchical array structure information.
[0045] An exemplary graph neural network model and its process for predicting layout factors are as follows: Figure 3B As shown, since this graph neural network model is mainly used for layout factor prediction, it is also referred to as a layout factor predictor in this embodiment of the application.
[0046] Figure 3B In this context, it is assumed that the space accelerator is located in the TILE layer (shown in the diagram). Four tiles are arranged, as shown in the figure: TILE0, TILE1, TILE2, and TILE3. TILE0 is connected to both TILE1 and TILE2, TILE1 is connected to TILE3, and TILE2 is also connected to TILE3. Each tile contains a certain number of physical components (PEs), and each PE contains corresponding components. Figure 3B In this diagram, the PE and its components are simply represented as multiple cubes of different sizes. These layouts can be indicated and described in the form of hierarchical array structure information; that is, the corresponding hierarchical array structure information can be obtained based on the layout of each space accelerator.
[0047] After the hierarchical array structure information is input into the layout factor predictor, it is first processed through its first vector layer (Layer 1 embedding). In one feasible approach, this first vector layer can be implemented as an encoder structure. This first vector layer first obtains the information corresponding to each TILE from the hierarchical array structure information, including the layout information of each element within the TILE, such as the layout information of PEs within each TILE, and the layout information of computational elements within each PE. For the layout information of each TILE, it is encoded into TILE node information. For example, such as... Figure 3B The one shown corresponds to TILE0. Node, corresponding to TILE1 Node, corresponding to TILE2 Node, corresponding to TILE3 node. Figure 3B In the diagram, this part that forms the node is illustrated as follows: .
[0048] Taking TILE3 as an example, because Figure 3B Assuming each TILE has three elements in its layout, and the indices are arranged in order, then the three elements in TILE3 are illustrated as follows: and ,Right now The elements with layer indices of 9, 10, and 11 are as follows: Figure 3B As shown within the dashed box. The elements in TILE3 are processed through the first vector layer, requiring the generation of... The corresponding node in the layer ,Right now The element with index 3 in the layer. Represented as follows: and If the corresponding If a node succeeds, it is assigned a value of 1; otherwise, it is assigned a value of 0. Therefore, Figure 3B In the example shown, .
[0049] Furthermore, processing is performed through a second vector layer (Layer 2 embedding). In one feasible approach, this second vector layer can also be implemented as an encoder structure. Based on the information from each TILE node, this second vector layer generates a higher-level structural graph, such as... Figure 3B The solid dots in the diagram represent this higher level. .
[0050] In one example, the second vector layer includes multiple hidden layers, and the output of each hidden layer can be represented as:
[0051]
[0052] in, Indicates the first The output feature vector of the layer; Indicates based on the first The first layer generated Layered graph structure; Indicates the first The adjacency matrix of the layer, Indicates the first The adjacency matrix of the layer; Indicates the first The input feature vector of the layer; For activation function, Indicates the first Layer aggregator; Indicates the first Layer weight parameters.
[0053] in:
[0054]
[0055] Indicates the first The first layer The node is assigned to the first The In each group; Represents a node The degree of departure.
[0056] Through the above process, a structure diagram corresponding to the hierarchical array structure information will be constructed.
[0057] Next, the structure diagram can be input into the classification network in the layout factor predictor for classification. Through the classification processing of the classification network, the layout factor corresponding to the hierarchical array structure information will be obtained.
[0058] This layout factor predictor can quickly and efficiently determine the corresponding layout factor for any type of spatial accelerator.
[0059] However, to ensure that the layout factor predictor can quickly and accurately predict layout factors, it needs to be pre-trained to acquire the aforementioned functionalities. Therefore, before using the layout factor predictor, training samples need to be obtained. These training samples include: hierarchical array structure sample information of the space accelerator, and the layout factor annotation information corresponding to this hierarchical array structure sample information. Based on the training samples, the graph neural network model (layout factor predictor) is iteratively trained to obtain a graph neural network model (layout factor predictor) for predicting layout factors.
[0060] Optionally, the layout factor annotation information corresponding to the hierarchical array structure sample information can be achieved through manual annotation. However, to make the annotation more accurate and reduce the annotation cost, an automatic annotation method can be adopted in one feasible approach. Specifically, the hierarchical array structure sample information can be logically synthesized to obtain the corresponding gate-level netlist sample information; based on the gate-level netlist sample information, array regularization can be performed to impose layout constraints on the hierarchical array structure corresponding to the hierarchical array structure sample information; based on the gate-level netlist sample information and the hierarchical array structure information corresponding to the hierarchical array structure after layout constraints, layout rules can be extracted; and the layout factor information obtained according to the layout rule extraction results can be used as the layout factor annotation information corresponding to the hierarchical array structure sample information.
[0061] In chip design, the process of converting Register Transfer Level (RTL) code into a gate-level netlist, while meeting constraints such as functionality, speed, and area, is called logic synthesis. RTL code is an ideal description of circuit logic, but real circuits have gate delays, trace delays, signal transition times, and varying clock arrival times at different flip-flops. Therefore, to achieve a balance between timing and area, and between power consumption and timing, RTL code needs to be converted into a gate-level netlist. A netlist is a text file that describes the interconnections between circuit elements, following a specific syntax. "Gate-level" refers to the synthesis level described by the netlist; therefore, a gate-level netlist describes the connections between circuit elements that are essentially gates or elements at the same level.
[0062] Therefore, by logically synthesizing the sample information of the hierarchical array structure, the corresponding gate-level netlist sample information can be obtained. Based on this, array regularization processing can be performed to apply layout constraints of the hierarchical array structure, such as the coordinates of each component, thereby preparing for mitigation of potential line congestion.
[0063] Furthermore, layout rules can be extracted based on the gate-level netlist sample information and the hierarchical array structure information corresponding to the hierarchical array structure after layout constraints. For example, the number of components, the connection relationships between components, and their positional relationships. Based on this, layout factor information such as bus length, line congestion data, and signal delay data can be further obtained. The obtained layout factor information can then be used as the layout factor annotation information corresponding to the hierarchical array structure sample information.
[0064] An exemplary process for obtaining training samples for a layout factor predictor is as follows: Figure 3C As shown in the figure, the hierarchical array structure sample information undergoes logic synthesis, array normalization, and layout rule extraction processes in sequence to obtain layout factor information. Taking the layout factor as the bus length as an example, assuming that the calculation is as follows... Figure 3C The bus length of the hierarchical array structure P (including the hierarchical array structure of net1, net2, and net3) shown in the figure is used to obtain the corresponding layout factor. P is represented as: Assume the weights corresponding to each net are as follows: , The corresponding line lengths are as follows: Then the layout factor for:
[0065] In this example, the layout factor annotation information corresponding to the hierarchical array structure sample information is the bus length 17.
[0066] Step S206: Evaluate the performance of the space accelerator based on the number of clock cycles and the layout factor.
[0067] Once the clock cycle count and placement factor are obtained, the performance of the space accelerator can be evaluated. In one feasible approach, the performance of the space accelerator can be evaluated based on a cost function that takes the clock cycle count and placement factor as parameters. For example, this cost function can be expressed as: In one feasible implementation, the performance of the space accelerator can be evaluated based on the result of dividing the number of clock cycles by the layout factor. For example, .in, The number of clock cycles. This is the layout factor.
[0068] It should be noted that the above example only demonstrates the performance evaluation of a single space accelerator. In practical applications, the number of space accelerator layouts designed using chip design automation tools is enormous and can be stored in the design space. The search module of the chip design automation tool retrieves one space accelerator layout from the design space each time, evaluates its performance, and compares it with the performance of the previously evaluated space accelerators, retaining the superior one. This process is repeated until all space accelerators in the design space have completed their performance evaluations. The layout of the space accelerator with the best performance is then selected as the final choice.
[0069] The following example, using a specific scenario described above, illustrates the space accelerator performance evaluation method of this application. Figure 3D As shown.
[0070] Figure 3D In this process, chip design automation tools perform space accelerator placement design based on preset architecture models (such as RISC-V, BOOM, etc.) for space accelerators, forming a design space. Then, based on requests from the search module, this design space selects completed space accelerator designs and submits them to the search module. The search module uses the placement design of this space accelerator as the target design, and then passes it to the analysis model for analysis to obtain the clock cycle count. Typically, the acquisition time is on the order of seconds. On the other hand, the target design is delegated to a layout factor predictor. This predictor does not directly output the operating frequency of the space accelerator, but rather outputs the layout factors of the space accelerator that affect the operating frequency, such as bus length, line congestion data, and signal delay data. The layout factor predictor can also acquire the layout factor in the order of seconds. Therefore, both the acquisition of the layout factor and the acquisition of the clock cycle count are on the same order of time, i.e., seconds.
[0071] Furthermore, the number of clock cycles and the layout factor will be based on the cost function. Perform calculations, for example... The calculation results can then be used as performance evaluation results for space accelerators.
[0072] It should be noted that the search module obtains information about space accelerators from the design space and executes it repeatedly until all space accelerators have obtained performance evaluation results. From these results, the TOP1 or TOPN results are selected, and the layout of the space accelerator corresponding to the result is used as the final selected layout.
[0073] As can be seen, this embodiment considers both the clock cycle count and layout factor of the space accelerator when evaluating its performance, resulting in a more accurate and efficient performance assessment. Since the performance of a space accelerator is actually related not only to the clock cycle count but also to its frequency, for the same task, a lower clock cycle count may correspond to a lower operating frequency, leading to poor overall performance; conversely, a higher clock cycle count may correspond to a higher operating frequency, making the space accelerator perform better than one with a lower clock cycle count. However, while considering both clock cycle count and operating frequency provides a more accurate assessment of the space accelerator's performance, the time required to obtain the operating frequency is long, typically several hours, making the performance evaluation process too time-consuming and costly. In the embodiments of this application, a layout factor is used. The layout factor can characterize the influence of the hierarchical array structure (or layout of the space accelerator) on the operating frequency. Since the corresponding operating frequency can be evaluated and determined when the hierarchical array structure of the space accelerator is determined, and the layout factor is easier and more efficient to obtain than the operating frequency, using the layout factor instead of the operating frequency to evaluate the performance of the space accelerator can accurately evaluate the relative performance of the space accelerator and obtain the performance evaluation results quickly and efficiently. This improves the overall performance evaluation efficiency of the space accelerator and reduces the performance evaluation cost.
[0074] Reference Figure 4This document illustrates a schematic diagram of an electronic device according to an embodiment of this application. The electronic device can be implemented as a cloud server device or a user device. The specific embodiments of this application do not limit the specific implementation of the electronic device.
[0075] like Figure 4 As shown, the electronic device may include: a processor 402, a communications interface 404, a memory 406, and a communications bus 408.
[0076] in:
[0077] The processor 402, communication interface 404, and memory 406 communicate with each other via communication bus 408.
[0078] Communication interface 404 is used to communicate with other electronic devices or servers.
[0079] The processor 402 is used to execute program 410, specifically the relevant steps in the above method embodiments.
[0080] Specifically, program 410 may include program code that includes computer operation instructions.
[0081] Processor 402 may be a CPU, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.
[0082] Memory 406 is used to store program 410. Memory 406 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.
[0083] Specifically, program 410 can be used to cause processor 402 to perform the operation corresponding to the method described in any of the foregoing multiple method embodiments.
[0084] The specific implementation of each step in procedure 410 can be found in the corresponding descriptions of the steps and units in the above method embodiments, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.
[0085] This application also provides a computer program product, including computer instructions that instruct a computing device to perform the operation corresponding to the method described in any of the above-described method embodiments.
[0086] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.
[0087] The methods described in the embodiments of this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.
[0088] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.
[0089] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.
Claims
1. A method for evaluating the performance of space accelerators in space exploration, comprising: Obtain the hierarchical array structure information of the space accelerator to be evaluated. The hierarchical array structure information includes the number and arrangement of TILEs, the number and arrangement of processing units (PEs) set in the TILEs, and the number and arrangement of each computing element in the processing unit (PE). Based on the hierarchical array structure information, determine the number of clock cycles corresponding to the space accelerator; A layout factor is obtained based on the hierarchical array structure information using a pre-trained graph neural network model. The layout factor is used to characterize the degree of influence of the hierarchical array structure indicated by the hierarchical array structure information on the frequency of the space accelerator. The performance of the space accelerator is evaluated based on the number of clock cycles and the layout factor.
2. The method according to claim 1, wherein, Before determining the number of clock cycles and the layout factor corresponding to the space accelerator based on the hierarchical array structure information, the method further includes: A structural graph corresponding to the hierarchical array structure information is constructed by using a pre-trained graph neural network model for predicting layout factors. Furthermore, the layout factor corresponding to the hierarchical array structure information is obtained based on the structure diagram.
3. The method according to claim 2, wherein, The construction of a structure graph corresponding to the hierarchical array structure information using a pre-trained graph neural network model for predicting layout factors includes: The hierarchical array structure information is input into a pre-trained graph neural network model for predicting layout factors; Through the first vector layer of the graph neural network model, the information of the computing elements corresponding to each TILE segment in the hierarchical array structure information is constructed into the corresponding TILE node information. The structure graph is generated based on the information of each TILE node through the second vector layer of the graph neural network model.
4. The method according to claim 3, wherein, The step of obtaining the layout factor corresponding to the hierarchical array structure information based on the structure diagram includes: The layout factor corresponding to the hierarchical array structure information is obtained based on the structure graph through the classification network of the graph neural network model.
5. The method according to any one of claims 2-4, wherein, The graph neural network model is pre-trained in the following manner: Acquire training samples, wherein the training samples include: hierarchical array structure sample information of space accelerators, and layout factor annotation information corresponding to the hierarchical array structure sample information; Based on the training samples, the graph neural network model is iteratively trained to obtain a graph neural network model for predicting layout factors.
6. The method according to claim 5, wherein, The layout factor annotation information corresponding to the hierarchical array structure sample information is obtained through the following methods: Logical synthesis is performed on the hierarchical array structure sample information to obtain the corresponding gate-level netlist sample information; Based on the gate-level netlist sample information, array regularization is performed to constrain the layout of the hierarchical array structure corresponding to the hierarchical array structure sample information. Based on the gate-level netlist sample information and the hierarchical array structure information corresponding to the hierarchical array structure after layout constraints, layout rules are extracted. The layout factor information obtained from the extraction results based on the layout rules will be used as the layout factor annotation information corresponding to the hierarchical array structure sample information.
7. The method according to any one of claims 1-4, wherein, The acquisition of the hierarchical array structure information of the space accelerator to be evaluated includes: According to preset rules, one space accelerator is selected from multiple space accelerators that have been designed in the preset design space as the space accelerator to be evaluated. The design space is used to design the hierarchical array structure layout of the space accelerator. Obtain the hierarchical array structure information of the space accelerator to be evaluated.
8. The method according to claim 7, wherein, The method further includes: Based on the performance evaluation results of the multiple space accelerators, space accelerators that meet the preset standards are selected from the multiple space accelerators.
9. The method according to any one of claims 1-4, wherein, The evaluation of the space accelerator's performance based on the clock cycle number and the layout factor includes: The performance of the space accelerator is evaluated based on a cost function that takes the number of clock cycles and the layout factor as parameters.
10. The method according to claim 9, wherein, The evaluation of the space accelerator's performance based on a cost function with parameters of the number of clock cycles and the layout factor includes: The performance of the space accelerator is evaluated based on the result of dividing the number of clock cycles by the layout factor.
11. An electronic device, comprising: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform an operation corresponding to the method as described in any one of claims 1-10.
12. A computer storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described in any one of claims 1-10.
13. A computer program product comprising computer instructions that instruct a computing device to perform an operation corresponding to any one of the methods described in claims 1-10.