OTP memory and manufacturing method thereof, OTP circuit

Abstract

The present application provides an OTP memory, a manufacturing method thereof, and an OTP circuit. By using two series-connected diodes as a fuse structure in the storage cell of the OTP memory, the volume of the storage cell and the volume of the entire OTP memory are reduced, thereby improving the integration of the storage cell and the OTP memory.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a one-time programmable (OTP) memory, a manufacturing method thereof, and an OTP circuit. Background Art

[0002] OTP is a type of memory implemented using a semiconductor structure. Once data is written, it no longer needs to be written to again, and it supports multiple subsequent reads. Because of its write-once nature, it is used in data processing applications such as immutable encryption keys, chip storage, redundancy design, and radio frequency identification.

[0003] In the prior art, OTP includes a memory cell that uses a gate oxide structure as a fuse circuit. Each memory cell has an active region on a substrate, an N-type diffusion region on the active region, and two separate gate structures, forming two transistors: a fuse transistor and a control transistor. When a high level is connected between the word line and the bit line, the gate oxide layer of the fuse transistor is broken down, and the gate and drain are connected, which is considered to be blown. The two states of the fuse transistor, blown and unblown, are judged to represent data 1 and data 0, respectively.

[0004] With the existing technology, in the two gate structures set on each storage cell in the OTP memory, the fuse gate corresponds to the thin gate oxide layer, and the control gate corresponds to the thick gate oxide layer. Due to the requirements of the design rule (DRC), the distance between the two gates is large, resulting in a larger overall volume of the storage cell. In turn, the overall volume of the OTP memory is large and the integration is small, which is not conducive to the promotion and application of the OTP memory in various fields. Summary of the Invention

[0005] The present application provides an OTP memory and a manufacturing method thereof, and an OTP circuit, which are used to solve the technical problem in the prior art that a memory cell with a gate structure has a large volume and low integration due to design rule requirements.

[0006] In a first aspect, the present application provides an OTP memory, comprising:

[0007] A first active region, a second active region, and an isolation region disposed between the first active region and the second active region; the first active region and the second active region have different conductivity types;

[0008] A first diffusion region is provided on the first active region for connecting to a first connection line; the first active region and the first diffusion region have different conductivity types;

[0009] A second diffusion region is provided on the second active region for connecting to a second connection line;

[0010] In an embodiment of the first aspect of the present application, the first active region is a P-type well; and the second active region is an N-type well.

[0011] In an embodiment of the first aspect of the present application, the first diffusion region is an N-type diffusion region; and the second diffusion region is an N-type diffusion region.

[0012] In an embodiment of the first aspect of the present application, the first active region and the first diffusion region constitute a first diode; the first active region and the second active region constitute a second diode.

[0013] In an embodiment of the first aspect of the present application, a breakdown voltage of the first diode is smaller than a breakdown voltage of the second diode.

[0014] In an embodiment of the first aspect of the present application, the first connecting line is a word line; and the second connecting line is a bit line.

[0015] A second aspect of the present application provides a method for manufacturing an OTP memory, comprising:

[0016] providing a semiconductor substrate;

[0017] forming a semiconductor layer on the substrate; the semiconductor layer comprising a first active region and a second active region, wherein the first active region and the second active region have different conductivity types;

[0018] forming an isolation region on the semiconductor layer; the isolation region is disposed between the first active region and the second active region;

[0019] forming a first diffusion region on the first active region; the first active region and the first diffusion region have different conductivity types;

[0020] forming a second diffusion region on the second active region;

[0021] connecting the first diffusion region to a first connecting line;

[0022] The second diffusion region is connected to a second connection line.

[0023] In an embodiment of the second aspect of the present application, the first active region is a P-type well; and the second active region is an N-type well.

[0024] In an embodiment of the second aspect of the present application, the first diffusion region is an N-type diffusion region; and the second diffusion region is an N-type diffusion region.

[0025] In an embodiment of the second aspect of the present application, the first active region and the first diffusion region constitute a first diode; the first active region and the second active region constitute a second diode.

[0026] In an embodiment of the second aspect of the present application, a breakdown voltage of the first diode is smaller than a breakdown voltage of the second diode.

[0027] In an embodiment of the second aspect of the present application, the first connecting line is a word line; and the second connecting line is a bit line.

[0028] A third aspect of the present application provides an OTP circuit, including:

[0029] a plurality of first connection lines, a plurality of second connection lines, and a plurality of storage structures;

[0030] Each of the second connection lines is connected to at least one storage structure, and each of the second connection lines is connected to the plurality of first connection lines through the at least one storage unit;

[0031] The storage unit includes: a first diode and a second diode;

[0032] The cathode of the first diode is connected to the first connection line, the anode of the first diode is connected to the anode of the second diode, and the cathode of the second diode is connected to the second connection line.

[0033] In an embodiment of the third aspect of the present application, a breakdown voltage of the first diode is less than a breakdown voltage of the second diode.

[0034] In an embodiment of the third aspect of the present application, the first connecting line is a word line; and the second connecting line is a bit line.

[0035] In summary, the OTP memory, its manufacturing method, and OTP circuit provided by this application use two diodes in series as a breakdown structure in each memory cell. This allows each memory cell to determine whether it stores data "1" or "0" based on whether the diode is broken down. Compared to memory cells that use a gate oxide structure as a fuse circuit, the absence of gate structure and corresponding design rule (DRC) restrictions reduces the size of the memory cell / OTP memory, thereby relatively improving the integration of the memory cell / OTP memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0037] Figure 1 Schematic diagram of the equivalent circuit structure of the OTP memory array;

[0038] Figure 2 Schematic diagram of an equivalent circuit structure of a memory cell based on a gate oxide structure in the prior art;

[0039] Figure 3 A schematic diagram of the structure of a memory cell based on a gate oxide structure in the prior art;

[0040] Figure 4 This is a schematic diagram of an equivalent circuit structure of an embodiment of a memory cell provided in this application;

[0041] Figure 5 A schematic structural diagram of an embodiment of a storage unit provided in this application;

[0042] Figure 6 This is a schematic diagram of an equivalent circuit structure of an embodiment of a memory cell provided in this application;

[0043] Figure 7 This is a schematic diagram of the equivalent circuit structure of an OTP memory array in one embodiment provided in this application;

[0044] Figure 8 A schematic diagram of a process for manufacturing a storage unit in an OTP memory provided by this application;

[0045] Figure 9 This is a structural diagram of each process of the storage unit manufacturing method in the OTP memory provided by this application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0047] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the numbers used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] Before formally introducing the embodiments of the present application, the application scenarios of the present application and the problems existing in the prior art are first introduced in conjunction with the accompanying drawings. Specifically, the present application can be applied to a one-time programmable (OTP) memory. The present application specifically provides an implementation method of a storage unit in an OTP memory, and each storage unit can provide the data writing and data reading functions of the OTP memory. Among them, due to the characteristic that each storage unit can only be written once, it is widely used in fields with high data security requirements such as data-unchanging keys, chip storage, redundant design, and radio frequency identification. After writing data in the memory, it cannot be written again, which can protect the uniqueness and accuracy of the data in the memory.

[0049] In some embodiments, Figure 1 The equivalent circuit structure diagram of the OTP memory array is as follows: Figure 1 The OTP memory array shown includes multiple memory cells, each of which can be used to store a data "0" or a data "1". All multiple memory cells can be distributed in rows and columns. According to their row and column distribution pattern, the multiple memory cells are marked as P11, P12, P13... At the same time, the multiple memory cells are distributed in rows and columns and connected to multiple word lines (WordLines, abbreviated: WL) and bit lines (Bit Lines, abbreviated: BL) distributed in the same rows and columns.

[0050] For example, in Figure 1In the OTP memory array shown, multiple word lines are arranged in rows, labeled WL1, WL2, WL3, etc., and multiple bit lines are arranged in columns, labeled BL1, BL2, BL3, etc. Multiple memory cells are arranged in a matrix between the word lines and bit lines. The memory cells in the first row are all connected to word line WL1, the memory cells in the second row are all connected to word line WL2, and so on. The memory cells in the first column are all connected to bit line BL1, the memory cells in the second row are all connected to bit line BL2, and so on, so that each memory cell is connected to a word line and a bit line.

[0051] In some embodiments, the word lines and bit lines provided in the embodiments of the present application may also be other connection lines or other names, and the specific implementation of the above connection lines is not limited. Figure 1 The multiple word lines in the diagram are recorded as multiple first connection lines, the multiple bit lines are recorded as second connection lines, and the connection lines can be used to implement the corresponding functions of the word lines or the bit lines.

[0052] In some embodiments, Figure 2 is a schematic diagram of an equivalent circuit of a memory cell based on a gate oxide structure in the prior art, wherein Figure 1 In the OTP memory array shown, the memory cell P11 in the first row and the first column is taken as an example. Figure 2 As shown, the memory cell includes: a first transistor M1 and a second transistor M2. The gates of the first transistor M1 and the second transistor M2 are both connected to WL1. At the same time, the drain of the first transistor M1 is connected to the bit line BL1, and the source is connected to the drain of the second transistor M2. The source of the second transistor M2 is a floating gate.

[0053] In some embodiments, as Figure 2 The memory cell shown in the figure can also be referred to as a gate oxide fuse memory cell due to its gate structure. The first transistor M1 and the second transistor M2 are two separate structures within the memory cell, forming a fuse path between the word line WL1 and the bit line BL1 to which they are connected. The first transistor M1 can be used for fuse operation and is a fuse transistor, with its gate being referred to as a fuse gate. The second transistor M2 can be used for read and write control and is a control transistor, with its gate being referred to as a control gate. Each memory cell can store data "1" or "0" depending on whether the first transistor M1 is blown.

[0054] In some embodiments, for Figure 2In the memory cell P11 shown, when data "1" needs to be written, a high level is applied to word line WL1 and a low level is applied to bit line BL1, causing the fuse gate of first transistor M1 to break down. That is, after programming, the gate and drain of first transistor M1 are conductive. Subsequently, when reading data from memory cell P11, a high level is applied to word line WL1 and current data is read on bit line BL1. If a large current is read from word line WL1 through memory cell P11, it indicates that the fuse gate in memory cell P11 is blown, and it is determined that data "1" is stored in memory cell P11. If no current is read from word line WL1 through memory cell P11, it indicates that the fuse gate in memory cell P11 is not blown, and it is determined that data "0" is stored in memory cell P11.

[0055] In some embodiments, to achieve Figure 2 The circuit structure shown, Figure 3 This is a schematic diagram of a memory cell structure based on a gate oxide structure in the prior art, which can be used to implement Figure 2 The circuit of the memory structure shown in the figure. The bottom of the semiconductor of the memory cell is an N-type well (Deep N-Well), and above the N-type well is a P-type well (P-Well in Deep N-Well). An N-type diffusion region is set on the P-type well. The N-type diffusion region is connected to the bit line BL, the first Poly Gate, the second Poly Gate, and the floating gate. The first Poly Gate and the second Poly Gate are connected to the word line WLr and the word line WLp.

[0056] In such Figure 3 In the memory cell shown, although fusing and control are achieved through the gate oxide structure of the two transistors, since two separate gate structures are introduced into the two transistors, and when the two transistors correspond to gate oxide layers of different thicknesses, due to the requirements of design and engineering rules such as mask alignment and etching process errors, the gate structures of the two transistors in each memory cell need to be separated by a sufficiently large distance, resulting in a larger volume occupied by each memory cell, which in turn leads to a larger overall volume of the OTP memory, relatively reducing the integration of the memory cell / OTP memory, and making it inconvenient to promote and apply the OTP memory in various fields.

[0057] Therefore, the present application provides an OTP memory and a manufacturing method thereof, and an OTP circuit. Through the design of the storage cell in the OTP memory, two diodes, N+ / PW and PW / NW, are used in series in the storage cell as a fuse structure, avoiding the use of a gate oxide structure as a fuse path, thereby reducing the volume of the storage cell and the volume of the entire OTP memory, thereby relatively improving the integration of the storage cell / OTP memory.

[0058] The following specific embodiments are used to describe the technical solution of the present application in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0059] It should be noted that the diode storage unit structure of the present application can also be applied to other integrated circuit products based on CMOS process and related semiconductor products. In the subsequent embodiments of the present application, the application of the storage unit structure in OTP memory is only used as an example, not as a limitation.

[0060] Figure 4 This is a schematic diagram of an equivalent circuit structure of an embodiment of a memory cell provided in this application, as shown in FIG. Figure 4 The memory cell shown can be applied to Figure 1 The OTP memory array shown in Figure 4 In Figure 1 The circuit structure of the memory cell in this embodiment is described by taking the memory structure P11 in FIG. 1 as an example.

[0061] In some embodiments, as Figure 4 The memory cell P11 shown includes: a first diode D1 and a second diode D2, wherein the cathode of the first diode D1 is connected to the word line WL1, the anode of the first diode D1 is connected to the anode of the second diode D2, and the cathode of the second diode D2 is connected to the bit line BL1. It should be noted that in the specific implementation structure of the second diode D2, the active region constituting the cathode can be connected to the bit line BL1 through a diffusion region. The specific structure can be referred to Figure 5 The structural diagram shown.

[0062] In some embodiments, a breakdown voltage V1 of the first diode D1 is less than a breakdown voltage V2 of the second diode D2 .

[0063] In some embodiments, for Figure 4 For the memory cell P11 shown, when data "1" needs to be written, a high level V3 is applied to the word line WL1 and a low level 0V is applied to the bit line BL1, V1<V3<V2, then the voltages on both sides of the memory cell P11 cause the first diode D1 to break down.

[0064] Subsequently, when reading the data in the memory cell P11, a high level is applied to the word line WL1, and the current data is read on the bit line BL1. When the current read from the word line WL1 through the memory cell P11 is greater than the preset value, it indicates that the first diode D1 in the memory cell P11 is broken down, causing the resistance of the memory cell P11 to decrease and the current to increase, and it is judged that the data "1" is stored in the memory cell P11. When the current from the word line WL1 through the memory cell P11 is not read, it indicates that the first diode D1 in the memory cell P11 is not broken down, and it is judged that the data "0" is stored in the memory cell P11.

[0065] In some embodiments, Figure 5 This is a structural diagram of an embodiment of a storage unit provided by this application, as shown in FIG. Figure 5 The structure of the memory cell shown can be used to implement Figure 4 The circuit shown, Figure 5 Also taking the storage unit P11 as an example, the storage unit includes:

[0066] A first active region 101 , a second active region 102 and an isolation region 103 , wherein the first active region 101 and the second active region 102 have different conductivity types.

[0067] In a specific implementation, different ion implantation types can be used in the first active region 101 and the second active region 102 to set the first active region 101 as a P-type well (PW) and the second active region 102 as an N-type well (NW), thereby achieving different conductivity types in the first active region 101 and the second active region 102.

[0068] Figure 6 This is a schematic diagram of an equivalent circuit structure of an embodiment of a memory cell provided in this application, as shown in FIG. Figure 6 Shown in Figure 5 Based on this, an equivalent second diode D2 can be formed between the first active region 101 of the P-type well and the second active region 102 of the N-type well, depending on the conductivity type. The anode of the second diode D2 is on the side of the first active region 101, and the cathode is on the side of the second active region 102.

[0069] In some embodiments, the isolation region 103 may be implemented by shallow trench isolation (STI) technology.

[0070] A first diffusion region 201 is provided on the first active region 101 for connecting to the word line WL1 , and a second diffusion region 202 is provided on the second active region 201 for connecting to the bit line BL1 . The first active region 101 and the first diffusion region 201 have different conductivity types.

[0071] In a specific implementation, the first diffusion region 201 may be an N-type diffusion region (N+), and the second diffusion region 202 may also be an N-type diffusion region (N+). Figure 6 As shown, an equivalent first diode D1 can be formed between the N-type first diffusion region 201 and the P-type well first active region 101 according to different conductivity types. The anode of the first diode D1 is on the first active region 101 side, and the cathode is on the first diffusion region 201 side.

[0072] Figure 7 This is a schematic diagram of an equivalent circuit structure of an OTP memory array according to an embodiment of the present application, as shown in FIG. Figure 7 Shown Figure 1 The OTP memory array shown uses Figure 4-6 The specific circuit structure of the OTP memory array is shown in the storage structure shown in FIG. Each storage unit includes a first diode and a second diode connected in series, and the connection relationship between the two diodes is the same as Figure 4 The circuit structure of the memory cell P11 shown is the same.

[0073] Then for Figure 7 The OTP memory shown, when writing data to each memory cell, applies a corresponding voltage level to the word line and bit line connected to the memory cell, controls the first diode of the memory cell to be in a breakdown or non-breakdown state, and controls the memory cell to specifically store data "1" or store data "0".

[0074] In some embodiments, V3 can be 6V, then V1<6V<V2. Figure 7 When data is written to the memory cell P11 shown, a voltage of 6V is applied to the word line WL1 connected to the memory cell P11, and a voltage of 0V is applied to the bit line BL1 connected to the memory cell P11, so that the first diode D1 of the memory cell P11 is broken down.

[0075] At the same time, in order to prevent the 6V voltage applied to the word line WL1 from accidentally breaking down the diodes in other memory cells on the word line, when a voltage of 6V is applied to the word line WL1, except for the bit line BL1 connected to the memory cell P11 to be written with data, which is applied with a voltage of 0V, the other bit lines BL2, BL3, etc. are all applied with a voltage V4, where 0<V4<6V. V4 can be designed according to the design window, for example, Figure 7 In the example shown, V4 may be 3 V, or, in other specific implementations, may be 2 V or 4 V, etc. At the same time, a voltage of 0 V is applied to the other word lines WL2 , WL3 . . . .

[0076] In summary, the OTP memory provided by the embodiments of the present application uses a diode as a breakdown structure in each memory cell. This allows each memory cell to determine whether it stores data "1" or "0" based on whether the diode is broken down. Compared to memory cells that use a gate oxide structure as a fuse path, the reduced gate structure eliminates the corresponding design rule (DRC) restrictions, thereby reducing the size of each memory cell and, by extension, the entire OTP memory. This results in a relatively higher density of memory cells and / or OTP memory.

[0077] In some embodiments, the present application also provides a method for making Figure 5 The semiconductor structure of the memory cell is shown in the method. Figure 8 This is a flow chart of a method for manufacturing a storage unit in an OTP memory provided by this application, as shown in FIG. Figure 8 The methods shown include:

[0078] S1: Provide a semiconductor substrate. The semiconductor substrate may be a Si substrate, a Ge substrate, a SiGe substrate, a SOI substrate, or a GOI substrate; or a substrate comprising other semiconductors or compound semiconductors, such as GaAs, InP, or SiC; or a stacked structure, such as Si / SiGe, or another epitaxial structure, such as SGOI.

[0079] S2: forming a semiconductor layer on the substrate; Figure 9 , Figure 9 The schematic diagram of the structure of each process of the method for manufacturing a storage unit in the OTP memory provided by this application is as follows: Figure 9 As shown in state ①, the formed semiconductor layer includes a first active region PW and a second active region NW, and the first active region and the second active region have different conductivity types. In some embodiments, the first active region PW and the second active region NW can be formed in the substrate respectively by different ion implantation types.

[0080] S3: forming an isolation region STI on the semiconductor layer; Figure 9 As shown in state ①, the isolation region is provided between the first active region and the second active region. In some embodiments, the isolation region STI may be formed after the first active region PW and the second active region NW are formed, and a trench is filled therebetween to form isolation.

[0081] S4: forming a first diffusion region N+ on the first active region PW; Figure 9 As shown in state ②, the conductivity types of the first active region (P type) and the first diffusion region (N type) are different.

[0082] S5: forming a second diffusion region on the second active region NW; the order of S4 and S5 is not limited.

[0083] S6: Connect the first diffusion region N+ to the first connection line WL.

[0084] S7: Connect the second diffusion region N+ to the second connection line BL; the order of S6 and S7 is not limited.

[0085] related Figure 9 The specific structure and principle of the memory cell produced by the manufacturing method shown can be referred to as Figure 4-6 The embodiments shown will not be described in detail.

[0086] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An OTP memory, characterized in that: include: a first active region, a second active region, and an isolation region disposed between the first active region and the second active region; The first active region is a P-type well, and the second active region is an N-type well; A first diffusion region is provided on the first active region for connecting to a first connection line; the first diffusion region is an N-type diffusion region; A second diffusion region is provided on the second active region for connecting to a second connection line; the second diffusion region is an N-type diffusion region; The first active region and the first diffusion region constitute a first diode; the first active region and the second active region constitute a second diode; The breakdown voltage of the first diode is lower than the breakdown voltage of the second diode.

2. The OTP memory according to claim 1, wherein: The first connection line is a word line; the second connection line is a bit line.

3. A method for manufacturing an OTP memory, characterized in that: include: providing a semiconductor substrate; forming a semiconductor layer on the substrate; The semiconductor layer includes a first active region and a second active region; The first active region is a P-type well; The second active region is an N-type well; forming an isolation region on the semiconductor layer; the isolation region is disposed between the first active region and the second active region; forming a first diffusion region on the first active region; the first diffusion region is an N-type diffusion region; forming a second diffusion region on the second active region; the second diffusion region is an N-type diffusion region; connecting the first diffusion region to a first connecting line; connecting the second diffusion region to a second connecting line; The first active region and the first diffusion region constitute a first diode; the first active region and the second active region constitute a second diode; The breakdown voltage of the first diode is lower than the breakdown voltage of the second diode.

4. The method for manufacturing an OTP memory according to claim 3, wherein: The first connection line is a word line; the second connection line is a bit line.

5. An OTP circuit, characterized in that: include: a plurality of first connection lines, a plurality of second connection lines, and a plurality of storage structures; Each of the second connection lines is connected to at least one storage structure, and each of the second connection lines is connected to the plurality of first connection lines through the at least one storage unit; The storage unit comprises: the first diode and the second diode according to claim 1 or 3; The cathode of the first diode is connected to the first connection line, the anode of the first diode is connected to the anode of the second diode, and the cathode of the second diode is connected to the second connection line.

6. The circuit according to claim 5, characterized in that The first connection line is a word line; the second connection line is a bit line.

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