Method and apparatus for controlling a clock signal

Abstract

This disclosure relates to methods and apparatus for controlling clock signals. An integrated circuit includes a clock transistor, a first enable transistor, a second enable transistor, a branch-1 transistor, a branch-2 transistor, and a clock gating circuit. The first enable transistor is coupled between the clock transistor and a first node. The second enable transistor is coupled between the clock transistor and a second node. The branch-1 transistor is coupled between a first power supply and the first node. The gate terminal of the branch-1 transistor is electrically connected to the second node. The branch-2 transistor is coupled between the first power supply and the second node. The gate terminal of the branch-2 transistor is electrically connected to the first node. The clock gating circuit for generating a gated clock signal receives a latched output signal, which is latched to a logic level of either a first node signal or a second node signal.

Description

Technical Field

[0001] This disclosure relates to methods and apparatus for controlling clock signals. Background Technology

[0002] The latest trend in integrated circuit (IC) miniaturization has resulted in smaller devices that consume less power but offer more functionality at higher speeds. Miniaturization processes have also led to more stringent design and manufacturing specifications and reliability challenges. Various electronic design automation (EDA) tools generate, optimize, and verify standard cell layout designs for ICs, while ensuring that standard cell layout design and manufacturing specifications are met. Summary of the Invention

[0003] According to one embodiment of this disclosure, an integrated circuit is provided, comprising: a clock transistor having a gate terminal configured to receive a first clock signal; a first enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a first node, wherein the first enable transistor has a gate terminal configured to receive a first enable signal; a second enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a second node, wherein the second enable transistor has a gate terminal configured to receive a second enable signal, the second enable signal being a logical inverse of the first enable signal; a branch transistor having a semiconductor channel electrically connected between a first power source and the first node, and having a gate terminal electrically connected to the second node; a branch transistor having a semiconductor channel electrically connected between the first power source and the second node, and having a gate terminal electrically connected to the first node; and a clock gating circuit having an output terminal configured to generate a gated clock signal, and a first input terminal configured to receive a latched output signal latched to a logic level of a first node signal at the first node or a second node signal at the second node.

[0004] According to another embodiment of this disclosure, a method for controlling a clock signal is provided, comprising: receiving a first clock signal at the gate terminal of a clock transistor in an enable latch circuit; receiving a first enable signal at the gate terminal of the first enable transistor in the enable latch circuit; receiving a second enable signal at the gate terminal of a second enable transistor in the enable latch circuit, wherein the second enable signal is a logical inverse of the first enable signal; generating a latch output signal, wherein when the latch output signal is latched, the latch output signal has the same logic level as a first node signal at the gate terminal of a branch-two transistor or has the same logic level as a second node signal at the gate terminal of a branch-one transistor; generating a selected clock signal from the second clock signal by using the latch output signal to select a second clock signal; and wherein the gate terminal of the branch-one transistor is electrically connected to both the drain terminal of the branch-two transistor and the drain terminal of the second enable transistor, and wherein the gate terminal of the branch-two transistor is electrically connected to both the drain terminal of the branch-one transistor and the drain terminal of the first enable transistor.

[0005] According to another embodiment of this disclosure, an integrated circuit is provided, comprising: a clock transistor having a gate terminal configured to receive a first clock signal; a first enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a first node, wherein the first enable transistor has a gate terminal configured to receive a first enable signal; a second enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a second node, wherein the second enable transistor has a gate terminal configured to receive a second enable signal, the second enable signal being a logical inverse of the first enable signal; a plurality of branch-one transistors having a semiconductor channel connected in series between a first power source and the first node, wherein each branch-one transistor has a gate terminal electrically connected to the second node; and a plurality of branch-two transistors having a semiconductor channel connected in series between the first power source and the second node, wherein each branch-two transistor has a gate terminal electrically connected to the first node. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 This is a circuit diagram of an integrated circuit with an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0008] Figure 2 Based on some embodiments Figure 1 The waveforms of signals at each terminal in an integrated circuit.

[0009] Figures 3A-3C This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0010] Figure 4 This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0011] Figures 5A-5C This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0012] Figure 6 This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0013] Figure 7 Based on some embodiments Figure 6 The waveforms of signals at each terminal in an integrated circuit.

[0014] Figures 8A-8C This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0015] Figure 9 This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0016] Figures 10A-10C This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latch output signal.

[0017] Figure 11 This is a flowchart of a method for generating a gated clock signal according to some embodiments.

[0018] Figure 12A-12B This is a circuit diagram of an integrated circuit according to some embodiments, in which a strobed clock signal is used as a clock signal for synchronizing synchronous logic circuits. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components, values, operations, materials, arrangements, etc., are described below. These are, of course, merely examples and not intended to be limiting. Other components, values, operations, materials, arrangements, etc., are contemplated. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, this document may use spatially relevant terms (e.g., "below," "below," "below," "above," "upper," etc.) to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0021] In some embodiments, an integrated circuit with an enable latch circuit is used to generate a latched output signal from an enable signal and a clock signal. The latched output signal is used to gating the clock signal to generate a gated clock signal. The gated clock signal is coupled to the clock input of a synchronous logic circuit. When the latched output signal is at a first logic level, the synchronous logic circuit operates in normal operation mode and is synchronized using the gated clock signal. However, when the latched output signal is at a second logic level, the synchronous logic circuit operates in idle operation mode. The logic level of the latched output signal varies depending on the enable signal and the clock signal. In some embodiments, the latched output signal is latched to the logic level of the enable signal on the rising edge of the clock signal and continues until the next falling edge of the clock signal. In some embodiments, the latched output signal is latched to the logic level of the enable signal on the falling edge of the clock signal and continues until the next rising edge of the clock signal. The latching of the latched output signal is provided by the enable latch circuit. Some transistors in the enable latch circuit are clock-coupled transistors whose gate terminals are set to a logic level controlled by the clock signal. In some embodiments, the power consumption of an integrated circuit having an enable latch circuit is reduced when the number of clock-coupled transistors in the enable latch circuit is reduced.

[0022] Figure 1This is a circuit diagram of an integrated circuit having an enable latch circuit 100 according to some embodiments, the enable latch circuit 100 being configured to generate a latch output signal. Figure 1 In this configuration, the enable latch circuit 100 is configured to generate a latched output signal L-EN at output 109. The clock gating circuit 190 receives the latched output signal L-EN at a first input terminal 191. The clock gating circuit 190 has a second input terminal 192 configured to receive a clock signal CP. By gating the clock signal CP using the latched output signal L-EN, a gated clock signal G-CP is generated from the clock signal CP at output terminal 199 of the clock gating circuit 190. In some embodiments, when the latched output signal L-EN is logic high, the gated clock signal G-CP changes with the clock signal CP; however, when the latched output signal L-EN is logic low, the gated clock signal G-CP remains logic low. In some embodiments, the clock signal CP is a global clock signal, and the gated clock signal G-CP is a gated global clock signal. The clock gating circuit 190 includes a NAND gate 194 and an inverter 196, and the output of the NAND gate 194 is coupled to the input of the inverter 196. The two input terminals of the NAND gate 194 correspond to the first input terminal 191 and the second input terminal 192 of the clock gating circuit 190. Figure 1 The circuit implementation of the clock gating circuit 190 in this disclosure is merely an example, and other embodiments of the clock gating circuit 190 are within the scope of this disclosure.

[0023] exist Figure 1 In this circuit, a latched output signal L-EN is generated at the output 109 of the enable latch circuit 100 based on the clock signal and enable signal received by the enable latch circuit 100. The clock signals clkb and clkbb received by the enable latch circuit 100 are generated by the clock logic circuit 60. The clock logic circuit 60 includes a first inverter 62 and a second inverter 64, and the output of the first inverter 62 is coupled to the input of the second inverter 64. The clock logic circuit 60 receives the clock signal CP at the input of the first inverter 62. The clock signal clkb generated at the output of the first inverter 62 is transmitted to the input of the second inverter 64, and the clock signal clkbb is generated at the output of the second inverter 64.

[0024] exist Figure 1In this circuit, the enable signals enb and enbb received by the enable latch circuit 100 are generated by the enable logic circuit 80. The enable logic circuit 80 includes a NOR gate 82 and an inverter 84, with the output of the NOR gate 82 coupled to the input of the inverter 84. The first and second inputs of the NOR gate 82 respectively receive enable signals TE and E. The enable signal enb generated at the output of the NOR gate 82 is transmitted to the input of the inverter 84, and the enable signal enbb is generated at the output of the inverter 84. Figure 1 In this configuration, when either the enable signal TE or the enable signal E is logic high, the enable signal enb is logic low, and the enable signal enbb is logic high. When both the enable signals TE and E are logic low, the enable signal enb is logic high, and the enable signal enbb is logic low. In some embodiments, the enable signal TE is an enable signal that enables all clock signals of synchronous logic circuits in a portion of the integrated circuit, while the enable signal E is an enable signal that enables the clock signals of a single block of synchronous logic circuits in a portion of the integrated circuit.

[0025] exist Figure 1 In the clock logic circuit 60, the enable latch circuit 100 includes a clock transistor TK3, an enable transistor TE1, an enable transistor TE2, a branch-one transistor TA1, a branch-two transistor TB1, and a coupling circuit 180. The semiconductor channel of the enable transistor TE1 is electrically connected between the drain terminal of the clock transistor TK3 and the first node no1. In other words, the source terminal of the enable transistor TE1 is electrically connected to the drain terminal of the clock transistor TK3, and the drain terminal of the enable transistor TE1 is electrically connected to the first node no1. The semiconductor channel of the enable transistor TE2 is electrically connected between the drain terminal of the clock transistor TK3 and the second node no2. In other words, the source terminal of the enable transistor TE2 is electrically connected to the drain terminal of the clock transistor TK3, and the drain terminal of the enable transistor TE2 is electrically connected to the second node no2. The source terminal of the clock transistor TK3 is electrically connected to the power supply VSS. The gate terminal of the clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62 in the clock logic circuit 60. The gate terminal of enable transistor TE1 receives the enable signal enbb from the output of inverter 84 in enable logic circuit 80. The gate terminal of enable transistor TE2 receives the enable signal enb from the output of NOR gate 82 in enable logic circuit 80.

[0026] Branch transistor TA1 has a semiconductor channel electrically connected between power supply VDD and first node no1, and the gate terminal of branch transistor TA1 is electrically connected to second node no2. Branch transistor TB1 has a semiconductor channel electrically connected between power supply VDD and second node no2, and the gate terminal of branch transistor TB1 is electrically connected to first node no1.

[0027] First node no1 and second node no2 are electrically connected to coupling circuit 180. Coupling circuit 180 has an output terminal 189 that provides a latched output signal L-EN from a first node signal at first node no1 and / or a second node signal at second node no2. In some embodiments, during latching, the latched output signal L-EN generated by coupling circuit 180 is latched to the logic level of the first node signal received by coupling circuit 180 from first node no1. During latching, the latched output signal L-EN generated by coupling circuit 180 is latched to the logic level of the second node signal received by coupling circuit 180 from second node no2.

[0028] exist Figure 1 In the circuit 180, coupling circuit 180 includes coupling transistors TC1, TC2, and TC3. The gate terminal of coupling transistor TC1 is electrically connected to the second node no2, and the drain terminal of coupling transistor TC1 is electrically connected to the first node no1. The gate terminal of the second coupling transistor TC2 is electrically connected to the first node no1, and the drain terminal of the second coupling transistor TC2 is electrically connected to the second node no2. The source terminals of the first coupling transistor TC1 and the second coupling transistor TC2 are electrically connected to the drain terminal of the third coupling transistor TC3. The source terminal of the third coupling transistor TC3 is electrically connected to the power supply VSS. The gate terminal of the third coupling transistor TC3 receives the clock signal clkbb from the output of the second inverter 64 in the clock logic circuit 60.

[0029] In operation, the clock signal CP is received at the input of the first inverter 62 and the second input terminal 192 of the clock gating circuit 190. Enable signals TE and E are received at the input of the NOR gate 82. A gated clock signal G-CP is generated at the output terminal 199 of the clock gating circuit 190. When the enable signal TE remains low, the enable signals enb at the output of the NOR gate 82 and enbb at the output of the inverter 84 are determined by the logic level of the enable signal E.

[0030] When the clock signal CP is logic low, the logic high of the clock signal clkb at the gate terminal of clock transistor TK3 drives clock transistor TK3 into a conducting state, and the logic low of the clock signal clkbb at the gate terminal of coupling transistor TC3 drives coupling transistor TC3 into a non-conducting state. When clock transistor TK3 is in the conducting state, each of the first node signal at the first node no1 and the second node signal at the second node no2 changes with the enable signal E. If the enable signal E is logic low, the enable transistor TE1 is turned off by the logic low of the enable signal enbb, and the enable transistor TE2 is turned on by the logic high of the enable signal enb. That is, when the enable signal E is logic low, the first node no1 is logic high, and the second node no2 is logic low. On the other hand, if the enable signal E is logic high, the enable transistor TE1 is turned on by the logic high of the enable signal enbb, and the enable transistor TE2 is turned off by the logic low of the enable signal enb. That is, when the enable signal E is logic high, the first node no1 is logic low, and the second node no2 is logic high. Furthermore, when the clock signal CP is logic low, except for the operation where the second node signal at the second node no2 changes with the enable signal E, the latched output signal L-EN at the output 189 of the coupling circuit 180 follows the second node signal because the coupling transistor TC3 is in a non-conducting state when the clock signal CP is logic low. Therefore, during the period when the clock signal CP is logic low, the logic value of the latched output signal L-EN follows the logic value of the enable signal E.

[0031] When the clock signal CP is logic high, the low logic value of the clock signal clkb at the gate terminal of clock transistor TK3 drives clock transistor TK3 into a non-conducting state, and the high logic value of the clock signal clkbb at the gate terminal of coupling transistor TC3 drives coupling transistor TC3 into a conducting state. If clock transistor TK3 is in a non-conducting state, the first node signal at the first node no1 and the second node signal at the second node no2 do not change with the enable signal E, because branch transistor TA1 and branch transistor TB1 are interconnected as a cross-latch circuit. Furthermore, when the clock signal CP changes from logic low to logic high, if coupling transistor TC3 is in a conducting state, the latched output signal L-EN at the output 189 of coupling circuit 180 is latched to the same logic value as the second node signal (at the second node no2). Here, before the clock signal CP changes from logic low to logic high, the logic value of the second node signal follows the logic value of the enable signal E. Therefore, the latched output signal L-EN is latched during the period when the clock signal CP is at logic high, and the latched logic value of the output signal L-EN is determined by the logic value of the enable signal E at the rising edge of the clock signal CP.

[0032] In the following text, see references Figure 2 To illustrate using the waveforms in the image Figure 1 The operation of integrated circuits. Figure 2 This is a waveform diagram of the clock signal, enable signal E, latched output signal L-EN, and strobed clock signal according to some embodiments. In some embodiments, for example in Figure 2 In the example waveform, the clock signal CP is the global clock signal, and the gated clock signal G-CP is the gated global clock signal.

[0033] Figure 2 Including by Figure 1 Example waveforms generated by integrated circuits, in Figure 1 In the integrated circuit, the enable latch circuit 100 is latched by the rising edge of the clock signal CP. The latched logic value of the latched output signal L-EN at the output 109 of the enable latch circuit 100 depends on the logic value of the enable signal E at the rising edge of the clock signal CP. Figure 2 During the transition from time t+ to time t-, the enable signal E is at logic high. Figure 2In this context, each of the times t0, t2, t4, t6, and t8 corresponds to the rising edge of the clock signal CP. Each of the times t1, t3, t5, t7, and t9 corresponds to the falling edge of the clock signal CP. When the clock signal CP is logic high from time t0 to time t1, the logic value of the latched output signal L-EN is latched low because the enable signal E at time t0 (as the rising edge of the clock signal CP) is logic low. When the clock signal CP is logic low from time t1 to time t2, the logic value of the latched output signal L-EN follows the enable signal E from time t1 to time t2. That is, from time t1 to time t+, the logic value of the latched output signal L-EN is logic low, and from time t+ to time 2, the logic value of the latched output signal L-EN is logic high. From time t2 to time t3, when the clock signal CP is logic high, the logic value of the latched output signal L-EN is latched high. The logic value of the latched output signal L-EN is logic high from time t3 to time t4 because, from time t3 to time t4, when the clock signal CP is logic low, the latched output signal L-EN follows the enable signal E. From time t4 to time t5, when the clock signal CP is logic high, the logic value of the latched output signal L-EN is latched as logic high. From time t5 to time t6, when the clock signal CP is logic low, the logic value of the latched output signal L-EN is logic high because the latched output signal L-EN follows the enable signal E. From time t6 to time t7, when the clock signal CP is logic high, the logic value of the latched output signal L-EN is latched as logic high.

[0034] like Figure 1 As shown, when the latched output signal L-EN is received at the first input terminal 191 of the clock gating circuit 190, and the clock signal CP is received at the second input terminal 192 of the clock gating circuit 190, the clock gating circuit 190 is gated by the latched output signal L-EN. Figure 2 In the clock selection circuit 190, the clock signal CP is sent as a strobed clock signal G-CP to the output terminal 199 during the time window from time t+ to t7 (when the latched output signal L-EN is logic high). During the time periods from time t0 to time t+ and from time t7 to time t9 (when the latched output signal L-EN is logic low), the logic value of the strobed clock signal G-CP remains logic low.

[0035] exist Figure 2Even if the enable signal E changes from logic high to logic low at time t- and remains logic low from time t- to time t7, the latched output signal L-EN will not follow the enable signal E from time t- to time t7 to become logic low, because the latched output signal L-EN is latched until time t7. The latching of the latched output signal L-EN until the next falling edge of the clock signal CP (e.g., time t7) allows the gated clock signal G-CP to maintain the same duty cycle as the original clock signal CP. The latching of the latched output signal L-EN until the next falling edge of the clock signal CP ensures that the positive pulse of the clock signal CP passes through the enable latch circuit 100 as a complete pulse. In contrast, in some alternative designs, if the enable signal E is directly coupled to the first input terminal 191 of the clock gating circuit 190, the final positive pulse will be truncated by the falling edge of the enable signal E. For example, in an alternative design, if the enable signal E is used directly for gating... Figure 2 In the clock signal G-CP, the first part of the final positive pulse from time t6 to t- will pass through the clock gating circuit as a narrowed positive pulse with logic high, but the second part of the final positive pulse from time t- to t7 will be set to logic low by the clock gating circuit. As the relative time difference between the falling edge of the enable signal E (e.g., t-) and the rising edge of the final positive pulse (e.g., t6) changes, the pulse width of the final positive pulse in the gated clock signal G-CP (the difference between t- and t6) can also change accordingly. In alternative designs, if the gated clock signal G-CP is used as a clock for synchronizing and controlling synchronous logic circuits, the pulse width variation introduces uncertainty into the operation of the synchronous logic circuits and reduces operational reliability. In this disclosure, using the latched output signal L-EN to generate the gated clock signal G-CP eliminates the pulse width variation, thus eliminating the reliability problems caused by the pulse width variation in the gated clock signal G-CP.

[0036] also, Figure 1 The two transistors in the enable latch circuit 100 have gate terminals configured to receive a clock signal from the clock logic circuit 60. The gate terminal of clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62 in the clock logic circuit 60, and the gate terminal of the third coupling transistor TC3 receives the clock signal clkbb from the output of the second inverter 64 in the clock logic circuit 60. Figure 1In this example, the gate terminals of two transistors in the enable latch circuit need to be driven by clock logic circuit 60. Conversely, in some alternative designs, the gate terminals of four transistors in the enable latch circuit need to be driven by clock logic circuit, and these four transistors are clock-coupled transistors. Reducing the number of transistors that need to be driven by clock logic circuit 60 improves the response time of enable latch circuit 100 and also reduces power consumption (if many enable latch circuits are used in the integrated circuit). In some embodiments, the number of transistors that need to be driven by clock logic circuit 60 is further reduced. For example, in Figure 3A In the enable latch circuit 300A, only one transistor has a gate terminal configured to receive a clock signal from the clock logic circuit 60.

[0037] Figure 3A This is a circuit diagram of an integrated circuit having an enable latch circuit 300A according to some embodiments, the enable latch circuit 300A being configured to generate a latch output signal. Figure 3A The enable latch circuit 300A in the middle is Figure 1 A variant of the enable latch circuit 100 in the circuit. The changes include removing... Figure 1 The third coupled transistor TC3 in the enable latch circuit 100 is used to form Figure 3A The enable latch circuit is 300A. Figure 3A The change also includes connecting both the source terminal of the first coupling transistor TC1 and the source terminal of the second coupling transistor TC2 to the power supply voltage VSS.

[0038] exist Figure 3A In the coupling circuit 180, when the source terminals of the first coupling transistor TC1 and the second coupling transistor TC2 are maintained at the power supply voltage VSS, the first coupling transistor TC1 and the second coupling transistor TC2 form a local latch circuit. The logic level at the output 189 of the local latch circuit is controlled by the first node signal at the first node no1 and the second node signal at the second node no2. If the first node no1 is logic low and the second node no2 is logic high during the setting process, the output 189 of the local latch circuit is set to logic high. Alternatively, if the first node no1 is logic high and the second node no2 is logic low during the reset process, the output 189 of the local latch circuit is reset to logic low. That is, during the setting or reset process, the logic level at the output 189 follows the logic level at the second node no2.

[0039] exist Figure 3AIn the circuit, if clock transistor TK3 is turned on by clock signal clkb, the first node signal at the first node no1 and the second node signal at the second node no2 are determined by the enable signal enbb applied to the gate terminal of enable transistor TE1 and the enable signal enb applied to the gate terminal of enable transistor TE2. Therefore, if clock transistor TK3 is turned on by clock signal clkb, when enable signal TE remains low, the latched output signal L-EN at output 109 of enable latch circuit 300A follows enable signal E, and the logic level of latched output signal L-EN reaches the same logic level as enable signal E.

[0040] exist Figure 3A In this circuit, if clock transistor TK3 is turned off by clock signal clkb, the first node signal at first node no1 and the second node signal at second node no2 are unaffected by the enable signal enbb applied to the gate terminal of enable transistor TE1 and the enable signal enb applied to the gate terminal of enable transistor TE2. When clock transistor TK3 changes from the on state to the off state at the falling edge of clock signal clkb, the logic level at output 189 is latched to the logic level at second node no2. Therefore, the logic level of the latched output signal L-EN at output 109 of enable latch circuit 300A is latched to the following logic level: the logic level of output signal L-EN is latched when clock transistor TK3 is turned off at the rising edge of clock signal CP.

[0041] In some embodiments, Figure 1 In the enable latch circuit 100, the branch-1 transistor TA1 and the branch-2 transistor TB1 are respectively replaced by at least two branch-1 transistors and at least two branch-2 transistors. Figure 3B This is a circuit diagram of an integrated circuit having an enable latch circuit 300B according to some embodiments. The enable latch circuit 300B is... Figure 1 A variant of the enable latch circuit 100. In some embodiments, Figure 3A The branch-1 transistor TA1 and branch-2 transistor TB1 in the enable latch circuit 300A are respectively replaced with at least two branch-1 transistors and at least two branch-2 transistors. Figure 3C This is a circuit diagram of an integrated circuit having an enable latch circuit 300C according to some embodiments. The enable latch circuit 300C is... Figure 3A A variant of the 300A enable latch circuit.

[0042] exist Figure 3B In this circuit, the enable latch circuit 300B includes at least two branch-one transistors (labeled TA1 and TA2 to N) and at least two branch-two transistors (labeled TB1 and TB2 to N). Figure 3C In this circuit, the enable latch circuit 300C also includes at least two branch-one transistors (labeled TA1 and TA2 to N) and at least two branch-two transistors (labeled TB1 and TB2 to N). Figure 3B and Figure 3C In this diagram, if the number of branch-one transistors is N (which is a positive integer greater than or equal to 2), then the symbols TA2 to N represent all N-1 branch-one transistors (from the second branch-one transistor to the Nth branch-one transistor) having a semiconductor channel with a series electrical connection between the drain of the first branch-one transistor TA1 and the first node no1. The gate terminals of all branch-one transistors are electrically connected together. Similarly, if the number of branch-two transistors is N, then the symbols TB2 to N represent all N-1 branch-two transistors (from the second branch-two transistor to the Nth branch-two transistor) having a semiconductor channel with a series electrical connection between the drain of the first branch-two transistor TB1 and the second node no2. The gate terminals of all branch-two transistors are electrically connected together.

[0043] exist Figure 3B and Figure 3C In this configuration, the gate terminals of all branch-1 transistors (TA1 and TA2 to N) are electrically connected to the second node no2, while the gate terminals of all branch-2 transistors (TB1 and TB2 to N) are electrically connected to the first node no1. The latching connection is formed through cross-coupling between the branch-1 and branch-2 transistors. Since the semiconductor channels of all branch-1 transistors (TA1 and TA2 to N) are connected in series, and the semiconductor channels of all branch-2 transistors (TB1 and TB2 to N) are connected in series, therefore... Figure 3B The cross-coupling ratio between branch 1 transistor and branch 2 transistor in the circuit Figure 1 The cross-coupling between branch-one transistor TA1 and branch-two transistor TB1 is weaker. For the same reason, Figure 3C The cross-coupling ratio between branch 1 transistor and branch 2 transistor in the circuit Figure 3A The cross-coupling between branch-one transistor TA1 and branch-two transistor TB1 is weaker. Therefore, when clock transistor TK3 is in the on state, the first node signal at the first node no1 and the second node signal at the second node no2 in enable latch circuits 300B or 300C are more responsive to changes in the enable signal E than the first node signal and the second node signal in enable latch circuits 100 or 300A.

[0044] exist Figure 1 and Figures 3A-3CIn some embodiments, each of the enable transistor TE1, enable transistor TE2, and clock transistor TK3 has an enhanced drive strength by increasing the channel width of the respective transistor. In some embodiments, the channel width of each of the enable transistor TE1, enable transistor TE2, and clock transistor TK3 is greater than the channel width of branch transistor TA1, branch transistor TB1, coupling transistor TC1, or coupling transistor TC2. In some embodiments, each of branch transistor TA1, branch transistor TB1, coupling transistor TC1, or coupling transistor TC2 has a default channel width, which is the channel width of a majority of transistors in the integrated circuit having clock logic circuit 60, enable logic circuit 80, and clock gating circuit 190. When the drive strength of the enable transistor TE1, enable transistor TE2, and clock transistor TK3 is enchanted, when the clock transistor TK3 is in the on state, the first node signal at the first node no1 and the second node signal at the second node no2 in the enable latch circuit become more responsive to changes in the enable signal E.

[0045] exist Figure 1 and Figures 3A to 3C In some embodiments, each of the enable transistor TE1, enable transistor TE2, and clock transistor TK3 has a threshold voltage reduced from a default threshold voltage, while each of the branch transistor TA1, branch transistor TB1, coupling transistor TC1, and coupling transistor TC2 has a default threshold voltage. The default threshold voltage is the threshold voltage of most transistors in the integrated circuit having clock logic circuit 60, enable logic circuit 80, and clock gating circuit 190. Alternatively, each of the branch transistor TA1, branch transistor TB1, coupling transistor TC1, and coupling transistor TC2 has a threshold voltage increased from the default threshold voltage, while each of the enable transistor TE1, enable transistor TE2, and clock transistor TK3 has a default threshold voltage. When the threshold voltage in each of the branch transistor TA1, branch transistor TB1, coupling transistor TC1, and coupling transistor TC2 increases, the latching connection formed by the branch transistor TA1 and branch transistor TB1 becomes more robust, and the latching connection formed by the coupling transistor TC1 and coupling transistor TC2 also becomes more robust.

[0046] In enable latch circuits 100, 300A, 300B, and 300C, each of the clock transistor TK3, the first enable transistor TE1, the second enable transistor TE2, the coupling transistor TC1, and the coupling transistor TC2 is a type 1 transistor, while each of the branch-1 transistor TA1 and the branch-2 transistor TB1 is a type 2 transistor. Figure 1and Figures 3A-3C In the illustrated embodiment, the first type of transistor is an NMOS transistor, and the second type of transistor is a PMOS transistor. In alternative embodiments, for example in Figure 4 and Figures 5A-5C In the illustrated embodiment, the first type of transistor is a PMOS transistor, while the second type of transistor is an NMOS transistor.

[0047] Figure 4 This is a circuit diagram of an integrated circuit having an enable latch circuit 400 according to some embodiments, the enable latch circuit 400 being configured to generate a latch output signal. Figure 4 The enable latch circuit 400 in the middle is Figure 1 A variant of the enable latch circuit 100 in the example. Figure 4 The coupling transistors TC1, TC2, and TC3 in the enable latch circuit 400, the enable transistors TE1 and TE2, and the clock transistor TK3 are PMOS transistors. Figure 1 The corresponding transistor in this context is an NMOS transistor. Additionally, Figure 4 In the enable latch circuit 400, branch-one transistor TA1 and branch-two transistor TB1 are NMOS transistors, while Figure 1 The corresponding transistor in this context is a PMOS transistor. Furthermore, Figure 4 The gate terminal of the clock transistor TK3 in the clock logic circuit 60 receives the clock signal clkbb from the output of the second inverter 64, and Figure 4 The gate terminal of the coupling transistor TC3 receives the clock signal clkb from the output of the first inverter 62. Conversely, Figure 1 The gate terminal of the clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62, and Figure 1 The gate terminal of the coupling transistor TC3 receives the clock signal clkbb from the output of the second inverter 64.

[0048] Figure 5A This is a circuit diagram of an integrated circuit having an enable latch circuit 500A according to some embodiments, the enable latch circuit 500A being configured to generate a latch output signal. Figure 5A The enable latch circuit 500A in the middle is Figure 3A A variant of the enable latch circuit 300A in the circuit. Figure 5A The coupling transistors TC1 and TC2, the enable transistors TE1 and TE2, and the clock transistor TK3 in the 500A enable latch circuit are PMOS transistors. Figure 3A The corresponding transistor in this context is an NMOS transistor. Additionally, Figure 5A In the 500A enable latch circuit, branch-one transistor TA1 and branch-two transistor TB1 are NMOS transistors, while Figure 3A The corresponding transistor in this context is a PMOS transistor. Furthermore, Figure 5A The gate terminal of the clock transistor TK3 in the clock logic circuit 60 receives the clock signal clkbb from the output of the second inverter 64. Figure 3A The gate terminal of the clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62.

[0049] Figure 5B This is a circuit diagram of an integrated circuit having an enable latch circuit 500B according to some embodiments, the enable latch circuit 500B being configured to generate a latch output signal. Figure 5B The enable latch circuit 500B in the middle is Figure 3B A variant of the enable latch circuit 300B in the circuit. Figure 5B The coupling transistors TC1, TC2, and TC3 in the enable latch circuit 500B, the enable transistors TE1 and TE2, and the clock transistor TK3 are PMOS transistors. Figure 3B The corresponding transistor in this context is an NMOS transistor. Additionally, Figure 5B In the enable latch circuit 500B, branch-one transistors TA1 and TA2 to N and branch-two transistors TB1 and TB2 to N are NMOS transistors, while Figure 3B The corresponding transistor in this context is a PMOS transistor. Furthermore, Figure 5B The gate terminal of the clock transistor TK3 in the clock logic circuit 60 receives the clock signal clkbb from the output of the second inverter 64, and Figure 5B The gate terminal of the coupling transistor TC3 receives the clock signal clkb from the output of the first inverter 62. Conversely, Figure 3B The gate terminal of the clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62, and Figure 3B The gate terminal of the coupling transistor TC3 receives the clock signal clkbb from the output of the second inverter 64.

[0050] Figure 5C This is a circuit diagram of an integrated circuit having an enable latch circuit 500C according to some embodiments, the enable latch circuit 500C being configured to generate a latch output signal. Figure 5C The enable latch circuit 500C in the middle is Figure 3C A variant of the enable latch circuit 300C in the model. Figure 5C In the enable latch circuit 500C, coupling transistors TC1 and TC2, enable transistors TE1 and TE2, and clock transistor TK3 are PMOS transistors. Figure 3C The corresponding transistor in this context is an NMOS transistor. Additionally, Figure 5CIn the enable latch circuit 500C, branch-one transistors TA1 and TA2 to N and branch-two transistors TB1 and TB2 to N are NMOS transistors, while Figure 3C The corresponding transistor in this context is a PMOS transistor. Furthermore, Figure 5C The gate terminal of the clock transistor TK3 in the clock logic circuit 60 receives the clock signal clkbb from the output of the second inverter 64. Figure 3C The gate terminal of the clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62.

[0051] and Figure 1 The enable latch circuit 100 and Figures 3A-3C The enable latch circuit in the 300A-300C is similar. Figure 4 The enable latch circuit 400 and Figures 5A-5C The enable latch circuits 500A-500C are also triggered by the rising edge of the clock signal CP. Figure 4 and Figures 5A-5C During the clock signal CP, the clock signal clkbb changes from logic low to logic high and turns off the clock transistor TK3. This causes the output signal L-EN to be latched by the enable latch circuits 400, 500A, 500B or 500C.

[0052] exist Figure 1 , Figures 3A-3C , Figure 4 and Figures 5A-5C In this circuit, each of the enable latch circuits 100, 300A-300C, 400, and 500A-500C is used to generate an output signal L-EN by latching the enable signal E at the rising edge of the clock signal CP, and the output signal L-EN is also used to gating the clock signal CP to generate a gated clock signal G-CP. Next, in... Figure 6 , Figures 8A-8C , Figure 9 and Figures 10A-10C In the alternative embodiments described, each of the enable latch circuits 100, 300A-300C, 400, and 500A-500C is used to generate an output signal L-EN by latching an enable signal E at the falling edge of the clock signal CPN, and the output signal L-EN is also used to gating the clock signal CPN to generate a gated clock signal G-CPN. In some embodiments, the phase of the clock signal CPN is 180 degrees different from the phase of the clock signal CP. In some embodiments, when the clock signal CPN is logic high, the clock signal CP is logic low, and conversely, when the clock signal CPN is logic low, the clock signal CP is logic high.

[0053] Figure 6This is a circuit diagram of an integrated circuit having an enable latch circuit 600 according to some embodiments, the enable latch circuit 600 being used to gating a clock signal CPN to generate a gated clock signal G-CPN. Figure 6 Integrated circuits in the middle are Figure 1 A variant of the integrated circuit in [the text]. Figure 6 The clock logic circuit 60 in the circuit receives the clock signal CPN at the input of the first inverter 62. Figure 1 The clock logic circuit 60 receives the clock signal CP at the input of the first inverter 62. Figure 6 The gate terminal of the clock transistor TK3 receives the clock signal clknbb from the output of the second inverter 64, while Figure 1 The gate terminal of the clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62. Figure 6 The latched output signal L-EN at output 109 of the enable latch circuit 600 is coupled to the clock gating circuit 190B to select the clock signal CPN. Figure 1 The latched output signal L-EN at the output 109 of the enable latch circuit 100 is coupled to the clock gating circuit 190 to gating the clock signal CP.

[0054] like Figure 6 As shown, in some embodiments, the clock gating circuit 190B for gating the clock signal CPN includes an inverter 193, a NOR gate 195, and an inverter 197. The inverter 193 has an input configured to receive a latched output signal L-EN from the output 109 of the enable latch circuit 600. The output of the inverter 193 is electrically connected to a first input of the NOR gate 195. The second input of the NOR gate 195 is configured to receive the clock signal CPN. The output of the NOR gate 195 is electrically connected to an input of the inverter 197. The output of the inverter 197 is configured to generate the gated clock signal G-CPN.

[0055] In the following text, see references Figure 7 To illustrate using the waveforms in the image Figure 6 The operation of integrated circuits. Figure 7 This is a waveform diagram of the inverted clock signal, the enable signal E, the latched output signal L-EN, and the gated inverted clock signal according to some embodiments. In some embodiments, for example in Figure 7 In the example waveform, the clock signal CPN is a globally inverted clock signal, and the gated clock signal G-CPN is a gated globally inverted clock signal.

[0056] Figure 7 Including by Figure 6 Example waveforms generated by integrated circuits, in Figure 6In the integrated circuit, the enable latch circuit 600 is latched by the falling edge of the clock signal CPN. The latched logic value of the latched output signal L-EN at output 109 of the enable latch circuit 600 depends on the logic value of the enable signal E at the falling edge of the clock signal CPN. From time t+ to time t-, the enable signal E is at logic high. Figure 7 In this context, each of times t0, t2, t4, t6, and t8 corresponds to the falling edge of the clock signal CPN. Each of times t1, t3, t5, t7, and t9 corresponds to the rising edge of the clock signal CPN. When the clock signal CPN is logic low from time t0 to time t1, the logic value of the latched output signal L-EN is latched low because the enable signal E at time t0 (as the falling edge of the clock signal CPN) is logic low. When the clock signal CPN is logic high from time t1 to time t2, the logic value of the latched output signal L-EN follows the enable signal E from time t1 to time t2. That is, from time t1 to time t+, the logic value of the latched output signal L-EN is logic low, and from time t+ to time t2, the logic value of the latched output signal L-EN is logic high. From time t2 to time t3, when the clock signal CPN is logic low, the logic value of the latched output signal L-EN is latched as logic high. From time t3 to time t4, when the clock signal CPN is logic high, the logic value of the latched output signal L-EN is logic high because the latched output signal L-EN follows the enable signal E from time t3 to time t4. From time t4 to time t5, when the clock signal CPN is logic low, the logic value of the latched output signal L-EN is latched as logic high. From time t5 to time t6, when the clock signal CPN is logic high, the logic value of the latched output signal L-EN is logic high because the latched output signal L-EN follows the enable signal E. From time t6 to time t7, when the clock signal CPN is logic low, the logic value of the latched output signal L-EN is latched as logic high.

[0057] like Figure 6 As shown, when a latched output signal L-EN is received at the first input terminal 191 of the clock gating circuit 190B, and a clock signal CPN is received at the second input terminal 192 of the clock gating circuit 190B, the clock gating circuit 190B uses the latched output signal L-EN to select the clock signal G-CPN. Figure 7During the time window from time t+ to t7 (when the latched output signal L-EN is logic high), the clock signal CPN is sent as a strobed clock signal G-CPN to the output terminal 199 of the clock strobing circuit 190B. During the time periods from time t0 to time t+ and from time t7 to time t9 (when the latched output signal L-EN is logic low), the logic value of the strobed clock signal G-CPN remains logic high.

[0058] exist Figure 7 Even if the enable signal E changes from logic high to logic low at time t- and remains logic low from time t- to time t7, the latched output signal L-EN will not follow the enable signal E from time t- to time t7 to become logic low, because the latched output signal L-EN is latched high until time t7. Latching the latched output signal L-EN high until the next rising edge of the clock signal CPN (e.g., time t7) allows the gated clock signal G-CPN to maintain the same duty cycle as the original clock signal CPN. The latching of the latched output signal L-EN until the next rising edge of the clock signal CPN ensures that the negative pulse of the clock signal CPN passes through the enable latch circuit 100 as a complete pulse. In contrast, in some alternative designs, if the enable signal E is directly coupled to the first input terminal 191 of the clock gating circuit 190B, the final negative pulse will be truncated by the falling edge of the enable signal E. For example, in an alternative design, if the enable signal E is used directly for gating... Figure 7 In the clock signal G-CPN, the first part of the final negative pulse from time t6 to t- will pass through the clock gating circuit as a narrowed negative pulse with logic low, but the second part of the final negative pulse from time t- to t7 will be set to logic high by the clock gating circuit. As the relative time difference between the falling edge of the enable signal E (e.g., t-) and the falling edge of the final negative pulse (e.g., t6) changes, the pulse width of the final negative pulse in the gated clock signal G-CPN (the difference between t- and t6) can also change accordingly. If the gated clock signal G-CPN is used as a clock for synchronizing and controlling synchronous logic circuits, the pulse width variation introduces uncertainty into the operation of the synchronous logic circuits and reduces operational reliability. In this disclosure, using the latched output signal L-EN to generate the gated clock signal G-CPN eliminates the pulse width variation, thus eliminating the reliability problems caused by the pulse width variation in the gated clock signal G-CPN.

[0059] and Figure 6 The enable latch circuit in the 600 is similar. Figures 8A-8C , Figure 9 and Figures 10A-10CThe enable latch circuits 300A-300C, 400, and 500A-500C are also used to generate the strobed clock signal G-CPN from the clock signal CPN. Similar to... Figure 6 Integrated circuits in, such as Figures 8A-8C , Figure 9 and Figures 10A-10C In each of the integrated circuits shown, the input of the first inverter 62 of the clock logic circuit 60 also receives the clock signal CPN, and Figure 6 The latched output signal L-EN at output 109 of the enable latch circuit 600 is coupled to the first input of the clock gating circuit 190B to gating the clock signal CPN. Similar to... Figure 6 Integrated circuits in, such as Figures 8A-8C , Figure 9 and Figures 10A-10C In each of the integrated circuits shown, the second input of the clock gating circuit 190B receives the clock signal CPN.

[0060] Figures 8A to 8C This is a circuit diagram of an integrated circuit with an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latched output signal L-EN for gating a clock signal CPN to generate a gated clock signal G-CPN. Figure 8A Integrated circuits in the middle are Figure 3A A variant of the integrated circuit in [the text]. Figure 8B Integrated circuits in the middle are Figure 3B A variant of the integrated circuit in [the text]. Figure 8C Integrated circuits in the middle are Figure 3C Variations of integrated circuits in [the context]. In, for example... Figures 8A-8C In each integrated circuit shown, the gate terminal of the clock transistor TK3 receives the clock signal clknbb from the output of the second inverter 64 of the clock logic circuit 60. Conversely, in such... Figures 3A-3C In each integrated circuit shown, the gate terminal of the clock transistor TK3 receives the clock signal clkb from the output of the first inverter 62. Additionally, in... Figure 8B In the integrated circuit shown, the gate terminal of the coupling transistor TC3 receives the clock signal clknb from the output of the first inverter 62. Conversely, in... Figure 3B In the integrated circuit shown, the gate terminal of the coupling transistor TC3 receives the clock signal clkbb from the output of the second inverter 64.

[0061] Figure 9 This is a circuit diagram of an integrated circuit with an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latched output signal L-EN for gating a clock signal CPN to generate a gated clock signal G-CPN. Figure 9 Integrated circuits in the middle are Figure 4A variant of the integrated circuit. In Figure 9 In the integrated circuit, the gate terminal of clock transistor TK3 receives the clock signal clknb from the output of the first inverter 62 of clock logic circuit 60, and the gate terminal of coupling transistor TC3 receives the clock signal clknbb from the output of the second inverter 64. Conversely, in Figure 4 In the integrated circuit, the gate terminal of the clock transistor TK3 receives the clock signal clkbb from the output of the second inverter 64, and the gate terminal of the coupling transistor TC3 receives the clock signal clkb from the output of the first inverter 62.

[0062] Figures 10A-10C This is a circuit diagram of an integrated circuit having an enable latch circuit according to some embodiments, the enable latch circuit being configured to generate a latched output signal L-EN for strobing a clock signal CPN to generate a strobed clock signal G-CPN. Figure 10A Integrated circuits in the middle are Figure 5A A variant of the integrated circuit in [the text]. Figure 10B Integrated circuits in the middle are Figure 5B A variant of the integrated circuit in [the text]. Figure 10C Integrated circuits in the middle are Figure 5C A variant of the integrated circuit in [the text].

[0063] In such Figures 10A-10C In each integrated circuit shown, the gate terminal of the clock transistor TK3 receives the clock signal clknb from the output of the first inverter 62 of the clock logic circuit 60. Conversely, in... Figures 5A-5C In each integrated circuit shown, the gate terminal of the clock transistor TK3 receives the clock signal clkbb from the output of the second inverter 64. Additionally, in... Figure 10B In the integrated circuit shown, the gate terminal of the coupling transistor TC3 receives the clock signal clknbb from the output of the second inverter 64. Conversely, in... Figure 5B In the integrated circuit shown, the gate terminal of the coupling transistor TC3 receives the clock signal clkb from the output of the first inverter 62.

[0064] Figure 11 This is a flowchart of a method 1100 for generating a gated clock signal coupled to a clock input of a synchronous logic circuit, according to some embodiments. Method 1100 can be compared with... Figure 1 , Figures 3A-3C , Figure 4 and Figures 5A-5C The enable latch circuits 100, 300A-300C, 400, and 500A-500C are used together. Method 1100 can also be used with... Figure 6 , Figures 8A-8C , Figure 9 and Figures 10A-10CThe enable latch circuits 600, 300A-300C, 400 and 500A-500C are used together.

[0065] Figure 11 The order of operations of method 1100 described herein is for illustrative purposes only; the operations of method 1100 can be performed in conjunction with... Figure 11 The operations described herein are executed in different sequences. In some embodiments, in Figure 11 The operations described in the text are performed before, between, during, and / or after the operations, except for Figure 11 Operations other than those described in the text.

[0066] In operation 1110 of method 1100, a first clock signal is received at the gate terminal of the clock transistor in the enable latch circuit. Figure 1 , Figures 3A-3C , Figure 9 and Figures 10A-10C In an example embodiment, the gate terminal of clock transistor TK3 receives a first clock signal from the output of the first inverter 62 of clock logic circuit 60. Figure 1 and Figures 3A-3C In this circuit, the first clock signal at the output of the first inverter 62 is the clock signal clkb generated from the clock signal CP. Figure 9 and Figures 10A-10C In this circuit, the first clock signal at the output of the first inverter 62 is the clock signal clknb generated from the clock signal CPN. Figure 4 , Figures 5A-5C , Figure 6 and Figures 8A-8C In an example embodiment, the gate terminal of clock transistor TK3 receives a first clock signal from the output of the second inverter 64 of clock logic circuit 60. Figure 4 and Figures 5A-5C In the second inverter 64, the first clock signal at the output is the clock signal clkbb generated from the clock signal CP. Figure 6 and Figures 8A-8C In the second inverter 64, the first clock signal at the output is the clock signal clknbb generated from the clock signal CPN.

[0067] In operation 1120 of method 1100, a first enable signal is received at the gate terminal of the first enable transistor in the enable latch circuit. Figure 1 , Figures 3A-3C , Figure 4 and Figures 5A-5C In the example embodiments and in Figure 6 , Figures 8A-8C , Figure 9 and Figures 10A-10CIn an example embodiment, the gate terminal of the enable transistor TE1 receives the enable signal enbb from the output of the inverter 84 in the enable logic circuit 80.

[0068] In operation 1130 of method 1100, a second enable signal is received at the gate terminal of the second enable transistor in the enable latch circuit. Figure 1 , Figures 3A-3C , Figure 4 and Figures 5A-5C In the example embodiments and in Figure 6 , Figures 8A-8C , Figure 9 and Figures 10A-10C In an example embodiment, the gate terminal of the enable transistor TE2 receives an enable signal enb from the output of the NOR gate 82 in the enable logic circuit 80. The second enable signal for controlling the enable transistor TE2 is the logical inversion of the first enable signal for controlling the enable transistor TE1.

[0069] In operation 1140 of method 1100, an enable latch circuit is used to generate a latch output signal. In some embodiments, the latch output signal is latched to the logic level of a first node signal at the gate terminal of a branch-two transistor. In some embodiments, the latch output signal is latched to the logic level of a second node signal at the gate terminal of a branch-one transistor (TA1). Figure 1 , Figures 3A-3C , Figure 4 and Figures 5A-5C In the example embodiment, at the rising edge of the clock signal CP, the latched output signal L-EN is latched to the logic value of the second node signal on the second node no2. Figure 6 , Figures 8A-8C , Figure 9 and Figures 10A-10C In an example embodiment, at the falling edge of the clock signal CPN, the latched output signal L-EN is latched to the logic value of the second node signal on the second node no2.

[0070] In operation 1150 of method 1100, a second clock signal is generated from the second clock signal by using a latched output signal to select it. Figure 1 , Figures 3A-3C , Figure 4 and Figures 5A-5C In an example embodiment, the clock signal CP is selected using the latched output signal L-EN, and a selected clock signal G-CP is generated at the output terminal 199 of the clock selection circuit 190 from the clock signal CP. Figure 6 , Figures 8A-8C , Figure 9 and Figures 10A-10CIn an example embodiment, the clock signal CPN is selected by using the latched output signal L-EN, and the selected clock signal G-CPN is generated at the output terminal 199 of the clock selection circuit 190B from the clock signal CPN.

[0071] In operation 1160 of method 1100, the strobed clock signal is sent to the clock input of the synchronous logic circuit. Figure 12A-12B The example provided illustrates the use of a strobed clock signal to synchronize synchronous logic circuits. Synchronous logic circuits are digital circuits in which changes in the state of memory elements are synchronized via a clock signal. An example of a memory element is a flip-flop. The output of a flip-flop is constant until a rising or falling edge of the clock signal is received at the flip-flop's clock input, and the logic value at the flip-flop's input is latched into the flip-flop's output and generated as the logic value at the flip-flop's output.

[0072] Figure 12A-12B This is a circuit diagram of an integrated circuit according to some embodiments, in which a strobed clock signal is used as a clock signal for synchronizing synchronous logic circuits. Figure 12A Integrated circuits in the middle are Figure 1 A variant of the integrated circuit. In Figure 12A In the clock selection circuit 190, the selected clock signal G-CP at the output terminal 199 is coupled to the clock input 1250 of the synchronous logic circuit 1200. Figure 12B Integrated circuits in the middle are Figure 6 A variant of the integrated circuit. In Figure 12B In the clock selection circuit 190B, the selected clock signal G-CPN at output terminal 199 is coupled to the clock input 1250 of the synchronous logic circuit 1200. Figure 12A-12B In this circuit, the synchronous logic circuit 1200 is a shift register based on D-type flip-flops. The shift register includes a serial input 1210 and a serial output 1290. The D-type flip-flops are synchronized by a strobed clock signal G-CPN received at clock input 1250. Figure 12A-12B Using the shift register in the example, other types of synchronous logic circuits are also within the scope of this disclosure.

[0073] One aspect of this disclosure relates to an integrated circuit. The integrated circuit includes a clock transistor, a first enable transistor, a second enable transistor, a branch-one transistor, a branch-two transistor, and a clock gating circuit. The clock transistor has a gate terminal configured to receive a first clock signal. The first enable transistor has a semiconductor channel electrically connected between a drain terminal of the clock transistor and a first node. The first enable transistor has a gate terminal configured to receive a first enable signal. The second enable transistor has a semiconductor channel electrically connected between a drain terminal of the clock transistor and a second node. The second enable transistor has a gate terminal configured to receive a second enable signal, which is a logically inverted version of the first enable signal. The branch-one transistor has a semiconductor channel electrically connected between a first power source and a first node, and has a gate terminal electrically connected to a second node. The branch-two transistor has a semiconductor channel electrically connected between a first power source and a second node, and has a gate terminal electrically connected to the first node. The clock gating circuit has an output terminal configured to generate a gated clock signal and a first input terminal configured to receive a latched output signal latched to the logic level of a first node signal at a first node or a second node signal at a second node.

[0074] Another aspect of this disclosure relates to a method. The method includes: receiving a first clock signal at the gate terminal of a clock transistor in an enable latch circuit; receiving a first enable signal at the gate terminal of a first enable transistor in the enable latch circuit; and receiving a second enable signal at the gate terminal of a second enable transistor in the enable latch circuit. The second enable signal is a logical inverse of the first enable signal. The method further includes: generating a latch output signal, which, when latched, generates a latch output signal having the same logic level as a first node signal at the gate terminal of a branch-two transistor or having the same logic level as a second node signal at the gate terminal of a branch-one transistor. The method further includes generating a selected clock signal from the second clock signal by strobing the second clock signal using the latch output signal. In the enable latch circuit, the gate terminal of a branch-one transistor is electrically connected to both the drain terminal of the branch-two transistor and the drain terminal of the second enable transistor. The gate terminal of the branch-two transistor is electrically connected to both the drain terminal of the branch-one transistor and the drain terminal of the first enable transistor.

[0075] Another aspect of this disclosure relates to an integrated circuit. The integrated circuit includes a clock transistor, a first enable transistor, a second enable transistor, a plurality of branch-one transistors, and a plurality of branch-two transistors. The clock transistor has a gate terminal configured to receive a first clock signal. The first enable transistor has a semiconductor channel electrically connected between a drain terminal of the clock transistor and a first node. The first enable transistor has a gate terminal configured to receive a first enable signal. The second enable transistor has a semiconductor channel electrically connected between a drain terminal of the clock transistor and a second node. The second enable transistor has a gate terminal configured to receive a second enable signal, the second enable signal being a logical inverse of the first enable signal. Each branch-one transistor has a semiconductor channel series-connected between a first power source and a first node, and each branch-one transistor has a gate terminal electrically connected to a second node. Each branch-two transistor has a semiconductor channel series-connected between a first power source and a second node, and each branch-two transistor has a gate terminal electrically connected to a first node.

[0076] Those skilled in the art will readily recognize that one or more of the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing specification, those skilled in the art will be able to implement various variations, equivalents, and other embodiments as broadly disclosed herein. Therefore, the protection granted herein is limited only by the definitions contained in the appended claims and their equivalents.

[0077] Example 1 is an integrated circuit comprising: a clock transistor having a gate terminal configured to receive a first clock signal; a first enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a first node, wherein the first enable transistor has a gate terminal configured to receive a first enable signal; a second enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a second node, wherein the second enable transistor has a gate terminal configured to receive a second enable signal, the second enable signal being a logical inverse of the first enable signal; a branch transistor having a semiconductor channel electrically connected between a first power source and the first node, and having a gate terminal electrically connected to the second node; a branch transistor having a semiconductor channel electrically connected between the first power source and the second node, and having a gate terminal electrically connected to the first node; and a clock gating circuit having an output terminal configured to generate a gated clock signal and a first input terminal configured to receive a latched output signal latched to a logic level of a first node signal at the first node or a second node signal at the second node.

[0078] Example 2 is the integrated circuit described in Example 1, further comprising: synchronous logic circuitry having a clock input configured to receive a strobed clock signal generated from the second clock signal by strobing the second clock signal using the latch output signal.

[0079] Example 3 is the integrated circuit described in Example 1, wherein the clock gating circuit has a second input terminal configured to receive a second clock signal, and wherein the second clock signal has the same waveform as the first clock signal or has a waveform that is logically opposite to the first clock signal.

[0080] Example 4 is the integrated circuit described in Example 1, wherein the clock transistor has a source terminal electrically connected to a second power supply.

[0081] Example 5 is the integrated circuit described in Example 1, further comprising: a coupling circuit configured to generate the latch output signal from at least one of a first node signal at the first node or a second node signal at the second node.

[0082] Example 6 is the integrated circuit described in Example 1, further comprising: a first coupling transistor having a gate terminal electrically connected to the second node and a drain terminal electrically connected to the first node; and a second coupling transistor having a gate terminal electrically connected to the first node and a drain terminal electrically connected to the second node.

[0083] Example 7 is the integrated circuit described in Example 6, wherein each of the first coupling transistor and the second coupling transistor has a source terminal configured to have a constant voltage.

[0084] Example 8 is the integrated circuit described in Example 6, further comprising: a third coupling transistor having a source terminal electrically connected to a second power supply and a gate terminal configured to receive a second clock signal, wherein the second clock signal is a logical inverse of the first clock signal; and wherein each of the first coupling transistor and the second coupling transistor has a source terminal electrically connected to a drain terminal of the third coupling transistor.

[0085] Example 9 is the integrated circuit described in Example 1, wherein each of the clock transistor, the first enable transistor, and the second enable transistor is a first type transistor, wherein each of the branch one transistor and the branch two transistor is a second type transistor, and wherein each first type transistor is an NMOS transistor and each second type transistor is a PMOS transistor, or each first type transistor is a PMOS transistor and each second type transistor is an NMOS transistor.

[0086] Example 10 is the integrated circuit described in Example 1, wherein: each of the clock transistor, the first enable transistor, and the second enable transistor is a first type transistor with a reduced threshold; and each of the branch one transistor and the branch two transistor is a second type transistor with a default threshold.

[0087] Example 11 is the integrated circuit described in Example 1, wherein: each of the clock transistor, the first enable transistor, and the second enable transistor is a first type transistor with enhanced drive strength, said enhanced drive strength being greater than the default drive strength of another first type transistor.

[0088] Example 12 is a method for controlling a clock signal, comprising: receiving a first clock signal at the gate terminal of a clock transistor in an enable latch circuit; receiving a first enable signal at the gate terminal of the first enable transistor in the enable latch circuit; receiving a second enable signal at the gate terminal of a second enable transistor in the enable latch circuit, wherein the second enable signal is a logical inverse of the first enable signal; generating a latch output signal, wherein when latched, the latch output signal has the same logic level as a first node signal at the gate terminal of a branch-two transistor or has the same logic level as a second node signal at the gate terminal of a branch-one transistor; generating a selected clock signal from the second clock signal by selecting the second clock signal using the latch output signal; and wherein the gate terminal of the branch-one transistor is electrically connected to both the drain terminal of the branch-two transistor and the drain terminal of the second enable transistor, and wherein the gate terminal of the branch-two transistor is electrically connected to both the drain terminal of the branch-one transistor and the drain terminal of the first enable transistor.

[0089] Example 13 is the method of Example 12, further comprising: maintaining the source terminals of the branch one transistor and the branch two transistor at a first power supply voltage; and maintaining the source terminal of the clock transistor at a second power supply voltage.

[0090] Example 14 is the method of Example 12, further comprising: sending the strobed clock signal to the clock input of the synchronous logic circuit.

[0091] Example 15 is the method of Example 12, wherein generating the latch output signal includes: receiving the first node signal at both the drain terminal of the first coupled transistor and the gate terminal of the second coupled transistor; receiving the second node signal at both the drain terminal of the second coupled transistor and the gate terminal of the first coupled transistor; and generating the latch output signal at the drain terminal of the second coupled transistor.

[0092] Example 16 is the method of Example 15, wherein generating the latched output signal further includes: keeping the source terminals of both the first coupling transistor and the second coupling transistor at a constant voltage.

[0093] Example 17 is the method of Example 15, wherein generating the latched output signal further includes: maintaining the source terminal of the third coupled transistor at a constant voltage, and wherein the drain terminal of the third coupled transistor is electrically connected to the source terminals of both the first coupled transistor and the second coupled transistor at a constant voltage; and receiving a third clock signal at the gate terminal of the third coupled transistor.

[0094] Example 18 is the method described in Example 12, wherein generating the gated clock signal includes: receiving the latched output signal at a first input terminal of the clock gating circuit; receiving a second clock signal at a second input terminal of the clock gating circuit; and sending the second clock signal to the output terminal of the clock gating circuit based on the logic level of the latched output signal.

[0095] Example 19 is an integrated circuit comprising: a clock transistor having a gate terminal configured to receive a first clock signal; a first enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a first node, wherein the first enable transistor has a gate terminal configured to receive a first enable signal; a second enable transistor having a semiconductor channel electrically connected between a drain terminal of the clock transistor and a second node, wherein the second enable transistor has a gate terminal configured to receive a second enable signal, the second enable signal being a logical inverse of the first enable signal; a plurality of branch-one transistors having a semiconductor channel connected in series between a first power source and the first node, wherein each branch-one transistor has a gate terminal electrically connected to the second node; and a plurality of branch-two transistors having a semiconductor channel connected in series between the first power source and the second node, wherein each branch-two transistor has a gate terminal electrically connected to the first node.

[0096] Example 20 is the integrated circuit described in Example 19, further comprising: a coupling circuit configured to receive at least one of a first node signal from the first node or a second node signal from the second node, and further configured to generate a latched output signal latched to a logic level of the first node signal or the second node signal; and a synchronization logic circuit having a clock input configured to receive a strobed clock signal generated from the second clock signal by strobing the second clock signal using the latched output signal.

Claims

1. An integrated circuit, comprising: A clock transistor having a gate terminal configured to receive a first clock signal; A first enabling transistor has a semiconductor channel electrically connected between the drain terminal of the clock transistor and a first node, wherein the first enabling transistor has a gate terminal configured to receive a first enabling signal. The second enable transistor has a semiconductor channel electrically connected between the drain terminal and the second node of the clock transistor, wherein the second enable transistor has a gate terminal configured to receive a second enable signal, the second enable signal being the logical inverse of the first enable signal; A branch transistor has a semiconductor channel electrically connected between a first power supply and a first node, and has a gate terminal electrically connected to a second node, wherein the source terminal of the branch transistor is configured to maintain a constant power supply voltage on the first power supply, and wherein the clock transistor has a source terminal electrically connected to a second power supply. A branched-two transistor having a semiconductor channel electrically connected between a first power supply and a second node, and having a gate terminal electrically connected to the first node, wherein the source terminal of the branched-two transistor is configured to maintain a constant power supply voltage on the first power supply. A clock gating circuit has an output terminal configured to generate a gated clock signal and a first input terminal configured to receive a latched output signal, the latched output signal being latched to the logic level of a first node signal at the first node or a second node signal at the second node; and The coupling circuit is configured to generate the latch output signal from at least one of a first node signal at the first node or a second node signal at the second node.

2. The integrated circuit according to claim 1, further comprising: A synchronous logic circuit having a clock input configured to receive a strobed clock signal generated from a second clock signal by strobing the second clock signal using the latch output signal.

3. The integrated circuit according to claim 1, wherein, The clock gating circuit has a second input terminal configured to receive a second clock signal, wherein the second clock signal has the same waveform as the first clock signal or has a waveform that is logically opposite to the first clock signal.

4. The integrated circuit according to claim 1, wherein, The coupling circuit further includes: A first coupled transistor has a gate terminal electrically connected to the second node and a drain terminal electrically connected to the first node; and The second coupled transistor has a gate terminal electrically connected to the first node and a drain terminal electrically connected to the second node.

5. The integrated circuit according to claim 4, wherein, Each of the first coupling transistor and the second coupling transistor has a source terminal configured to have a constant voltage.

6. The integrated circuit according to claim 4, further comprising: A third coupling transistor has a source terminal electrically connected to a second power supply and a gate terminal configured to receive a second clock signal, wherein the second clock signal is the logical inverse of the first clock signal; and Each of the first coupling transistor and the second coupling transistor has a source terminal electrically connected to the drain terminal of the third coupling transistor.

7. The integrated circuit according to claim 1, wherein, Each of the clock transistor, the first enable transistor, and the second enable transistor is a first type transistor, wherein each of the branch one transistor and the branch two transistor is a second type transistor, and wherein each first type transistor is an NMOS transistor and each second type transistor is a PMOS transistor, or each first type transistor is a PMOS transistor and each second type transistor is an NMOS transistor.

8. The integrated circuit according to claim 1, wherein: Each of the clock transistor, the first enable transistor, and the second enable transistor is a first type transistor with a reduced threshold. as well as Each of the branch one transistor and the branch two transistor is a second type transistor with a default threshold.

9. The integrated circuit according to claim 1, wherein: Each of the clock transistor, the first enable transistor, and the second enable transistor is a first-type transistor with enhanced drive strength, which is greater than the default drive strength of another first-type transistor.

10. A method for controlling a clock signal, comprising: The first clock signal is received at the gate terminal of the clock transistor in the enable latch circuit; The first enable signal is received at the gate terminal of the first enable transistor in the enable latch circuit; A second enable signal is received at the gate terminal of the second enable transistor in the enable latch circuit, wherein the second enable signal is the logical inversion of the first enable signal; Generate a latch output signal. When the latch output signal is latched, the latch output signal has the same logic level as the first node signal at the gate terminal of the branch two transistor or has the same logic level as the second node signal at the gate terminal of the branch one transistor. A selected clock signal is generated from the second clock signal by using the latched output signal to select the second clock signal; The source terminals of the first branch transistor and the second branch transistor are kept at a first power supply voltage, and the source terminal of the clock transistor is kept at a second power supply voltage. Wherein, the gate terminal of the first branch transistor is electrically connected to both the drain terminal of the second branch transistor and the drain terminal of the second enable transistor, and wherein, the gate terminal of the second branch transistor is electrically connected to both the drain terminal of the first branch transistor and the drain terminal of the first enable transistor. The first node signal is received at both the drain terminal of the first coupling transistor and the gate terminal of the second coupling transistor. The second node signal is received at both the drain terminal of the second coupled transistor and the gate terminal of the first coupled transistor.

11. The method of claim 10, further comprising: The selected clock signal is sent to the clock input of the synchronous logic circuit.

12. The method of claim 10, further comprising: The latched output signal is generated at the drain terminal of the second coupled transistor.

13. The method according to claim 10, wherein, Generating the latch output signal further includes: The source terminals of both the first and second coupled transistors are kept at a constant voltage.

14. The method of claim 10, wherein, Generating the latch output signal further includes: The source terminal of the third coupled transistor is kept at a constant voltage, and wherein the drain terminal of the third coupled transistor is electrically connected to the source terminals of both the first coupled transistor and the second coupled transistor, which are at a constant voltage; and A third clock signal is received at the gate terminal of the third coupled transistor.

15. The method according to claim 10, wherein, Generating the strobed clock signal includes: The latched output signal is received at the first input terminal of the clock gating circuit; The second clock signal is received at the second input terminal of the clock gating circuit; and The second clock signal is sent to the output terminal of the clock gating circuit based on the logic level of the latch output signal.

16. An integrated circuit, comprising: A clock transistor having a gate terminal configured to receive a first clock signal; A first enabling transistor has a semiconductor channel electrically connected between the drain terminal of the clock transistor and a first node, wherein the first enabling transistor has a gate terminal configured to receive a first enabling signal. The second enable transistor has a semiconductor channel electrically connected between the drain terminal and the second node of the clock transistor, wherein the second enable transistor has a gate terminal configured to receive a second enable signal, the second enable signal being the logical inverse of the first enable signal; A plurality of branch-one transistors having a semiconductor channel connected in series between a first power supply and a first node, wherein each branch-one transistor has a gate terminal electrically connected to a second node, wherein a source terminal of one of the plurality of branch-one transistors is configured to maintain a constant power supply voltage on the first power supply, wherein a clock transistor has a source terminal electrically connected to a second power supply; and A plurality of branched two-transistors having a semiconductor channel connected in series between a first power supply and a second node, wherein each branched two-transistor has a gate terminal electrically connected to the first node, wherein the source terminal of one of the plurality of branched two-transistors is configured to maintain a constant power supply voltage on the first power supply.

17. The integrated circuit according to claim 16, further comprising: The coupling circuit is configured to receive at least one of a first node signal from the first node or a second node signal from the second node, and is further configured to generate a latched output signal latched to the logic level of the first node signal or the second node signal. as well as A synchronous logic circuit having a clock input configured to receive a strobed clock signal generated from a second clock signal by strobing the second clock signal using the latch output signal.

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