Display devices

Abstract

The present disclosure provides a display device. The display device of the present disclosure includes a light-emitting unit, a current source, a voltage comparator and an emission control unit. The current source is configured to output a supply current. The voltage comparator is configured to receive voltage data and a ramp signal. The emission control unit receives an emission enable signal and is coupled to the light-emitting unit, the current source and the voltage comparator. The voltage comparator outputs a comparison signal to the emission control unit according to the voltage data and the ramp signal. The emission control unit outputs a driving current to the light-emitting unit according to the supply current, the emission enable signal and the comparison signal. The display device of the present disclosure can provide a good display effect.

Description

Technical Field

[0001] The present disclosure relates to a device; in particular, the present disclosure relates to a display device. Background Art

[0002] For general display devices, since each pixel of a general display device can perform data setting operations at the same time, the general display device has the problem of on-peak power consumption, specifically, infrared (IR) drop and no light when shooting a camera. In addition, general display devices with high pixels per inch (PPI) panels also have the disadvantage of too large circuit area. Summary of the invention

[0003] The display device disclosed in the present invention includes a light-emitting unit, a current source, a voltage comparator and an emission control unit. The current source is configured to output a supply current. The voltage comparator is configured to receive voltage data and a ramp signal. The emission control unit is configured to receive an emission enable signal and is coupled to the light-emitting unit, the current source and the voltage comparator. The voltage comparator outputs a comparison signal to the emission control unit according to the voltage data and the ramp signal. The emission control unit outputs a driving current to the light-emitting unit according to the supply current and the comparison signal.

[0004] The display device of the present disclosure includes a pixel array. The pixel array includes a plurality of pixel units. The plurality of pixel units are divided into a plurality of pixel groups. The plurality of pixel groups receive a plurality of emission enable signals, a plurality of voltage data and a common ramp signal respectively. The plurality of pixel groups are illuminated during a plurality of emission cycles and set during a plurality of data setting cycles according to the plurality of emission enable signals, the plurality of voltage data and the common ramp signal respectively. The plurality of data setting cycles corresponding to the plurality of pixel groups do not overlap with each other in time.

[0005] Based on the above, according to the display device disclosed herein, the display device can provide a good display effect.

[0006] In order to make the above contents easier to understand, several embodiments attached with the drawings will be described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0008] Figure 1is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0009] Figure 2 According to the present disclosure Figure 1 A schematic diagram of signals of the illustrated embodiment;

[0010] Figure 3 is a schematic diagram of a display device according to another embodiment of the present disclosure;

[0011] Figure 4 According to the present disclosure Figure 3 A schematic diagram of signals of the illustrated embodiment;

[0012] Figure 5 is a schematic diagram of a display device according to another embodiment of the present disclosure;

[0013] Figure 6 According to the present disclosure Figure 5 A schematic diagram of signals of the illustrated embodiment;

[0014] Figure 7 is a schematic diagram of a current source according to another embodiment of the present disclosure;

[0015] Figure 8 is a schematic diagram of a current source according to yet another embodiment of the present disclosure;

[0016] Fig.9A is a schematic diagram of a signal and a dimming operation according to a first embodiment of the present disclosure;

[0017] Fig. 9B is a schematic diagram of a signal and dimming operation according to a second embodiment of the present disclosure;

[0018] Fig. 9C is a schematic diagram of a signal and dimming operation according to a third embodiment of the present disclosure;

[0019] Fig.9D is a schematic diagram of a signal and dimming operation according to a fourth embodiment of the present disclosure;

[0020] Fig. 10A is a schematic diagram of a signal and dimming operation according to a fourth embodiment of the present disclosure;

[0021] Fig. 10B is a schematic diagram of a signal and dimming operation according to a fifth embodiment of the present disclosure;

[0022] Fig. 10C is a schematic diagram of a signal and dimming operation according to a sixth embodiment of the present disclosure;

[0023] Fig.11 is a schematic diagram of a signal and dimming operation according to a seventh embodiment of the present disclosure;

[0024] Fig.12 is a schematic diagram of signals and dimming operations according to an eighth embodiment of the present disclosure;

[0025] Fig.13 is a schematic diagram of a display device according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like components.

[0027] Throughout the specification and claims of the present disclosure, certain terms are used to refer to specific components. It should be understood by those skilled in the art that electronic device manufacturers may use different names to refer to the same component. It is not intended herein to distinguish between components that have the same function but different names. In the following description and claims, words such as "comprise" and "include" are open-ended terms and should be interpreted as "including but not limited to ..."

[0028] The term "coupling (coupling) (or connection (connection))" used throughout the entire specification of this application (including the attached claims) may refer to any direct or indirect connection mode. For example, if the text states that a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or certain connection modes. The terms "first (first)", "second (second)" and similar terms mentioned throughout the entire specification of this application (including the attached claims) are only used to name discrete elements or to distinguish different embodiments or scopes. Therefore, the terms should not be regarded as limiting the upper or lower limits of the number of elements and should not be used to limit the arrangement order of elements. In addition, whenever possible, the same reference number is used in the drawings and embodiments to represent the same or similar parts. In different embodiments, the same reference number or the same term can be used to refer to the relevant description of the element / component / step.

[0029] The display device of the present disclosure may be an active matrix light emitting diode (AM-LED) display device, but the present disclosure is not limited thereto. In some embodiments of the present disclosure, the display device of the present disclosure may be, for example, applicable to a combination of liquid crystal, a light emitting diode, a quantum dot (QD), fluorescence, a phosphor, other suitable display media or the foregoing materials, but the present disclosure is not limited thereto. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (QLED or QDLED) or other suitable materials. The materials may be arranged and combined arbitrarily, but the present disclosure is not limited thereto. The display device of the present disclosure may include peripheral systems, such as a drive system, a control system, a light source system, a shelf system and similar systems to support the light emitting device.

[0030] It should be noted that in the following embodiments, without departing from the spirit of the present disclosure, the technical features of several different embodiments may be replaced, recombined and mixed to complete other embodiments. As long as the features of each embodiment do not violate the spirit of the present disclosure or conflict with each other, the features may be mixed and used together at will.

[0031] Figure 1 is a schematic diagram of a display device according to an embodiment of the present disclosure. Figure 1 The display device 100 includes a pixel array, and the pixel array includes a plurality of pixel units, wherein each of the plurality of pixel units may include Figure 1The circuit architecture shown in . In an embodiment of the present disclosure, the display device 100 includes a current source 110, a voltage comparator 120, an emission control unit 130 and a light emitting unit 140. The current source 110 is coupled between the operating voltage VDD_LEU and the emission control unit 130. The emission control unit 130 is further coupled to the voltage comparator 120 and the light emitting unit 140, and receives an emission enable signal EM. The light emitting unit 140 is coupled between the emission control unit 130 and the voltage VSS_LEU. The voltage VSS_LEU is lower than the operating voltage VDD_LEU. In an embodiment of the present disclosure, the current source 110 is configured to output a supply current SI to the emission control unit 130. The voltage comparator 120 is configured to receive voltage data VD and a ramp signal SS. The voltage comparator 120 outputs a comparison signal CS to the emission control unit 130 according to the voltage data VD and the ramp signal SS, and the emission control unit 130 outputs a drive current DI to the light emitting unit 140 according to the supply current SI, the emission enable signal EM and the comparison signal CS. In an embodiment of the present disclosure, the emission enable signal EM, the voltage data VD and the ramp signal SS may be provided from a plurality of driving circuits respectively arranged outside or within the plane of the display device 100 through data lines and / or scan lines.

[0032] Figure 2 According to the present disclosure Figure 1 A schematic diagram of the signals of the illustrated embodiment. Figure 1 and Figure 2 , the voltage comparator 120 may receive the voltage data VD and the ramp signal SS. At time t1, the voltage of the ramp signal SS begins to rise to form a ramp waveform. Since the voltage of the ramp signal SS is lower than the voltage of the voltage data VD, the voltage comparator 120 outputs a comparison signal CS having a high voltage level. During the enable period from time t1 to time t3, the emission control unit 130 receives the emission enable signal EM having a high voltage level. After time t2, since the voltage of the ramp signal SS is higher than the voltage of the voltage data VD, the voltage comparator 120 outputs a comparison signal CS having a low voltage level. Therefore, during the emission period EP from time t1 to time t2, the emission control unit 130 outputs a driving current DI to drive the light emitting unit 140.

[0033] In an embodiment of the present disclosure, the voltage comparator 120 may further receive a pulse width modulation (PWM) scanning signal, and perform voltage programming on the voltage data VD according to the pulse width modulation scanning signal. The display device 100 may determine the emission period EP by controlling the voltage level of the voltage data VD. If the voltage level of the voltage data VD is higher, the time length of the emission period EP is longer. If the voltage level of the voltage data VD is lower, the time length of the emission period EP is shorter. The time length of the emission period EP of the drive current DI is determined by the voltage data VD and the ramp signal SS. In other words, the pixel unit can be dimmed by the voltage data VD to determine the time length of the turnlight period of the pixel unit. In addition, in an embodiment of the present disclosure, the ramp signal SS is a ramp-up signal, but the present disclosure is not limited thereto. In one embodiment of the present disclosure, the ramp signal SS may be a ramp-down signal.

[0034] Figure 3 is a schematic diagram of a display device according to another embodiment of the present disclosure. Figure 3 The display device 300 includes a pixel array, and the pixel array includes a plurality of pixel units, wherein each of the plurality of pixel units may include Figure 3 The circuit architecture shown in . In an embodiment of the present disclosure, the display device 300 includes a current source 310, a voltage comparator 320, an emission control unit 330 and a light emitting unit 340. The current source 310 is coupled between the operating voltage VDD_LEU and the emission control unit 330. The emission control unit 330 is further coupled to the voltage comparator 320 and the light emitting unit 340, and receives an emission enable signal EM. The light emitting unit 340 is coupled between the emission control unit 330 and the voltage VSS_LEU. The voltage VSS_LEU is lower than the operating voltage VDD_LEU. In an embodiment of the present disclosure, the current source 330 is configured to output a supply current to the emission control unit 330. The voltage comparator 320 is configured to receive voltage data VD through a data line DL, and to receive a ramp signal SS through a signal line RL. The voltage comparator 320 outputs a comparison signal to the emission control unit 330 according to the voltage data VD and the ramp signal SS, and the emission control unit 330 outputs a driving current to the light emitting unit 340 according to the supply current, the emission enable signal EM and the comparison signal CS. In an embodiment of the present disclosure, the emission enable signal EM, the voltage data VD, and the ramp signal SS may be provided from a plurality of driving circuits respectively arranged outside a plane of the display device 300 or arranged within a plane of the display device 300 .

[0035] In an embodiment of the present disclosure, the current source 310 includes a transistor 311, a transistor 312, and a capacitor 313. A first terminal of the transistor 311 is coupled to the data line DL and receives voltage data VD, and a control terminal of the transistor 311 receives a pulse amplitude modulation scanning signal SPAM. A first terminal of the transistor 312 receives an operation voltage VDD_LEU, a control terminal of the transistor 312 is coupled to a second terminal of the transistor 311, and a second terminal of the transistor 312 is coupled to an emission control unit 330. A first terminal of the capacitor 313 is coupled to a second terminal of the transistor 311, and a second terminal of the capacitor 313 is coupled to a first terminal of the transistor 312. In an embodiment of the present disclosure, the transistors 311 and 312 are P-type transistors. In an embodiment of the present disclosure, the current source 310 receives a pulse amplitude modulation scanning signal SPAM for voltage programming a voltage of a control terminal of the transistor 312, thereby modulating a current of a supply current output through a second terminal of the transistor 312.

[0036] In an embodiment of the present disclosure, the voltage comparator 320 includes a plurality of transistors 321, 322, and 325, a capacitor 323, and an inverter circuit 324. A first terminal of the transistor 321 is coupled to the data line DL and receives voltage data VD, and a control terminal of the transistor 321 receives a pulse width modulation scanning signal SPWM. A first terminal of the transistor 322 receives a ramp signal SS, a control terminal of the transistor 322 receives an emission enable signal EM, and a second terminal of the transistor 322 is coupled to a second terminal of the transistor 321. A first terminal of the capacitor 323 is coupled to a second terminal of the transistor 322 and a second terminal of the transistor 321. An input terminal of the inverter circuit 324 is coupled to a second terminal of the capacitor 323, and an output terminal of the inverter circuit 324 is coupled to the emission control unit 330. A first terminal of the transistor 325 is coupled to an input terminal of the inverter circuit 324, a control terminal of the transistor 325 receives a pulse width modulation scanning signal SPWM, and a second terminal of the transistor 325 is coupled to an output terminal of the inverter circuit 324. In the embodiment of the present disclosure, the transistors 321 , 322 and 325 are P-type transistors. The voltage comparator 320 performs voltage programming on the voltage data VD according to the pulse width modulation scanning signal SPWM, so that the second terminal of the transistor 321 can output the pulse width modulation voltage.

[0037] In an embodiment of the present disclosure, the inverter circuit 324 includes a transistor 3241 and a transistor 3242. A first terminal of the transistor 3241 receives an operating voltage VDD, a control terminal of the transistor 3241 is coupled to an input terminal of the inverter circuit 324, and a second terminal of the transistor 3241 is coupled to an output terminal of the inverter circuit 324. A first terminal of the transistor 3242 receives a voltage VSS, a control terminal of the transistor 3242 is coupled to an input terminal of the inverter circuit 324, and a second terminal of the transistor 3242 is coupled to an output terminal of the inverter circuit 324. The voltage VSS is lower than the operating voltage VDD. In an embodiment of the present disclosure, the transistor 3241 is a P-type transistor, and the transistor 3242 is an N-type transistor.

[0038] In an embodiment of the present disclosure, the emission control unit 330 includes a plurality of transistors 331 to 335. The control terminal of the transistor 331 is coupled to the voltage comparator 320. The first terminal of the transistor 332 is coupled to the operating voltage VDD, the control terminal of the transistor 332 receives the emission enable signal EM, and the second terminal of the transistor 332 is coupled to the first terminal of the transistor 331. The first terminal of the transistor 333 is coupled to the second terminal of the transistor 331, the control terminal of the transistor 333 is coupled to the voltage comparator 320, and the second terminal of the transistor 333 is coupled to the voltage VSS. The voltage VSS is lower than the operating voltage VDD. The first terminal of the transistor 334 is coupled to the second terminal of the transistor 331, the control terminal of the transistor 334 receives the emission enable signal EM, and the second terminal of the transistor 334 is coupled to the voltage VSS. The first terminal of the transistor 335 is coupled to the current source 310, the control terminal of the transistor 335 is coupled to the second terminal of the transistor 331, and the second terminal of the transistor 335 is coupled to the light emitting unit 340. In the embodiment of the present disclosure, transistors 321 and 322 are P-type transistors, and transistors 323 and 324 are N-type transistors.

[0039] Figure 4 According to the present disclosure Figure 3 A schematic diagram of the signals of the illustrated embodiment. Figure 3 and Figure 4During the period from time t0 to time t1, the voltage of the pulse width modulation scanning signal SPWM changes from a high voltage level to a low voltage level, thereby turning on the transistors 321 and 325. The data line DL transmits the voltage data VD having the pulse width modulation data. During the period from time t1 to time t2, the voltage of the pulse amplitude modulation scanning signal SPAM changes from a high voltage level to a low voltage level, thereby turning on the transistor 311. The data line DL transmits the voltage data VD having the pulse amplitude modulation data. During the data setting period from time t0 to time t2, the voltage of the emission enable signal EM changes from a low voltage level to a high voltage level, thereby turning off the transistors 322 and 332, and turning on the transistor 334. During the emission period from time t2 to time t5, the voltage of the emission enable signal EM changes from a high voltage level to a low voltage level, thereby turning on the transistors 322 and 332, and turning off the transistor 334.

[0040] In the first ramp signal type 401, the voltage comparator 320 may receive a ramp signal SS. During the data setting period from time t0 to time t2, the ramp signal SS has a high voltage level, and the node voltage N1 changes from a relatively high voltage level to a threshold voltage (Vth). During the data setting period from time t0 to time t2, since the transistor 334 is turned on, the node voltage N2 is maintained at a low voltage level. At time t2, the ramp signal SS (ramp down signal) begins to decline, and the node voltages N1 and N2 change from the threshold voltage (Vth) to a relatively high voltage level, so that the transistor 335 is turned on to provide a driving current to the light emitting unit 340. At time t2, the light emitting unit 340 is illuminated. During the emission period from time t2 to time t5, the voltage of the ramp signal SS decreases, and the node voltage N1 decreases synchronously. After time t4, since the node voltage N1 is lower than the threshold voltage, after the voltage is inverted, the transistor 331 is turned off and the transistor 333 is turned on. Therefore, the node voltage N2 changes from a high voltage level to a low voltage level, so that the transistor 335 is turned off and the light emitting unit 340 is also turned off. Among them, the display device 300 can implement an effective dimming function for the light emitting unit 340. It should be noted that the light emitting unit 340 is first lit during the on period (lighting period) P1 (all light emitting units are lit), and then the light emitting unit 340 is turned off during the off period (dimming period) P2 to implement data setting (all light emitting units are turned off sequentially or simultaneously).

[0041] In the second ramp signal type 402, the voltage comparator 320 may receive a ramp signal SS'. During the data setting period from time t0 to time t2, the ramp signal SS' has a low voltage level, and the node voltage N1 changes from a relatively low voltage level to a threshold voltage (Vth). During the data setting period from time t0 to time t2, since the transistor 334 is turned on, the node voltage N2 is maintained at a low voltage level. At time t2, the ramp signal SS' (ramp rising signal) starts to rise, and the node voltage N1 changes from the threshold voltage (Vth) to a relatively low voltage level, so that the transistor 335 is turned off and the light emitting unit 340 is also turned off. During the period from time t2 to time t3, the voltage of the ramp signal SS' rises, and the node voltage N1 rises synchronously. After time t3, since the node voltage N1 is higher than the threshold voltage, after the voltage is inverted, the node voltage N2 changes from a low voltage level to a high voltage level, so that the transistor 331 is turned on and the transistor 333 is turned off. Therefore, the transistor 335 is turned on and the light emitting unit 340 is lit. Among them, the display device 300 can implement an effective dimming function for the light emitting unit 340. It should be noted that the light emitting unit 340 is first turned off during the off period (dimming period) P2' to implement data setting (all light emitting units are turned off), and then the light emitting unit 340 is lit during the on period (lighting period) P1' (all light emitting units are lit sequentially or simultaneously).

[0042] Figure 5 is a schematic diagram of a display device according to another embodiment of the present disclosure. Figure 5 The display device 500 includes a pixel array, and the pixel array includes a plurality of pixel units, wherein each of the plurality of pixel units may include Figure 5The circuit architecture shown in . In an embodiment of the present disclosure, the display device 500 includes a current source 510, a voltage comparator 520, an emission control unit 530 and a light emitting unit 540. The current source 510 is coupled between the operating voltage VDD_LEU and the emission control unit 530. The emission control unit 530 is further coupled to the voltage comparator 520 and the light emitting unit 540, and receives an emission enable signal EM. The light emitting unit 540 is coupled between the emission control unit 530 and the voltage VSS_LEU. The voltage VSS_LEU is lower than the operating voltage VDD_LEU. In an embodiment of the present disclosure, the current source 530 is configured to output a supply current to the emission control unit 530. The voltage comparator 520 is configured to receive voltage data VD through a data line DL, and to receive a ramp signal SS through a signal line RL. The voltage comparator 520 outputs a comparison signal CS to the emission control unit 530 according to the voltage data VD and the ramp signal SS, and the emission control unit 530 outputs a driving current to the light emitting unit 540 according to the supply current, the emission enable signal EM and the comparison signal CS. In an embodiment of the present disclosure, the emission enable signal EM, the voltage data VD, and the ramp signal SS may be provided from a plurality of driving circuits respectively arranged outside a plane of the display device 500 or arranged within a plane of the display device 500 .

[0043] In an embodiment of the present disclosure, the current source 510 includes a transistor 511, a transistor 512, and a capacitor 513. A first terminal of the transistor 511 is coupled to the data line DL and receives voltage data VD, and a control terminal of the transistor 511 receives a pulse amplitude modulation scanning signal SPAM. A first terminal of the transistor 512 receives an operating voltage VDD_LEU, a control terminal of the transistor 512 is coupled to a second terminal of the transistor 511, and a second terminal of the transistor 512 is coupled to an emission control unit 530. A first terminal of the capacitor 513 is coupled to a first terminal of the transistor 511, and a second terminal of the capacitor 513 is coupled to a second terminal of the transistor 512. In an embodiment of the present disclosure, the transistors 511 and 512 are P-type transistors. In an embodiment of the present disclosure, the current source 510 receives a pulse amplitude modulation scanning signal SPAM for voltage programming a voltage of a control terminal of the transistor 512, thereby modulating a current of a supply current output through a second terminal of the transistor 512.

[0044] In an embodiment of the present disclosure, the voltage comparator 520 includes a plurality of transistors 521, 522, and 525, a capacitor 523, an inverter circuit 524, and a transistor 525. A first terminal of the transistor 521 is coupled to the data line DL and receives voltage data VD, and a control terminal of the transistor 521 receives a pulse width modulation scanning signal SPWM. A first terminal of the transistor 522 receives a ramp signal SS, a control terminal of the transistor 522 receives an emission enable signal EM, and a second terminal of the transistor 522 is coupled to a second terminal of the transistor 521. A first terminal of the capacitor 523 is coupled to a second terminal of the transistor 522 and a second terminal of the transistor 521. An input terminal of the inverter circuit 524 is coupled to a second terminal of the capacitor 523, and an output terminal of the inverter circuit 524 is coupled to an inverter circuit 526. A first terminal of the transistor 525 is coupled to an input terminal of the inverter circuit 524, a control terminal of the transistor 525 receives a pulse width modulation scanning signal SPWM, and a second terminal of the transistor 525 is coupled to an output terminal of the inverter circuit 524. The input terminal of the inverter circuit 526 is coupled to the output terminal of the inverter circuit 524, and the output terminal of the inverter circuit 526 is coupled to the emission control unit 530. In the embodiment of the present disclosure, the transistors 521, 522 and 525 are P-type transistors. The voltage comparator 520 performs voltage programming on the voltage data VD according to the pulse width modulation scanning signal SPWM, so that the second terminal of the transistor 521 can output the pulse width modulation voltage.

[0045] In an embodiment of the present disclosure, the inverter circuit 524 includes a transistor 5241 and a transistor 5242. A first terminal of the transistor 5241 receives an operating voltage VDD, a control terminal of the transistor 5241 is coupled to an input terminal of the inverter circuit 524, and a second terminal of the transistor 5241 is coupled to an output terminal of the inverter circuit 524. A first terminal of the transistor 5242 receives a voltage VSS, a control terminal of the transistor 5242 is coupled to an input terminal of the inverter circuit 524, and a second terminal of the transistor 5242 is coupled to an output terminal of the inverter circuit 524. The voltage VSS is lower than the operating voltage VDD. In an embodiment of the present disclosure, the transistor 5241 is a P-type transistor, and the transistor 5242 is an N-type transistor.

[0046] In an embodiment of the present disclosure, the inverter circuit 526 includes a transistor 5261 and a transistor 5262. A first terminal of the transistor 5261 receives an operating voltage VDD, a control terminal of the transistor 5261 is coupled to an input terminal of the inverter circuit 526, and a second terminal of the transistor 5261 is coupled to an output terminal of the inverter circuit 526. A first terminal of the transistor 5262 receives a voltage VSS, a control terminal of the transistor 5262 is coupled to an input terminal of the inverter circuit 526, and a second terminal of the transistor 5262 is coupled to an output terminal of the inverter circuit 526. In an embodiment of the present disclosure, the transistor 5261 is a P-type transistor, and the transistor 5262 is an N-type transistor.

[0047] In an embodiment of the present disclosure, the emission control unit 530 includes a plurality of transistors 531 to 535. The control terminal of the transistor 531 is coupled to the voltage comparator 520. The first terminal of the transistor 532 is coupled to the operation voltage VDD, the control terminal of the transistor 532 receives the emission enable signal EM, and the second terminal of the transistor 532 is coupled to the first terminal of the transistor 531. The first terminal of the transistor 533 is coupled to the second terminal of the transistor 531, the control terminal of the transistor 533 is coupled to the voltage comparator 520, and the second terminal of the transistor 533 is coupled to the voltage VSS. The first terminal of the transistor 534 is coupled to the second terminal of the transistor 531, the control terminal of the transistor 534 receives the emission enable signal EM, and the second terminal of the transistor 534 is coupled to the voltage VSS. The first terminal of the transistor 535 is coupled to the current source 510, the control terminal of the transistor 535 is coupled to the second terminal of the transistor 531, and the second terminal of the transistor 535 is coupled to the light emitting unit 540. In an embodiment of the present disclosure, the transistors 521 and 522 are P-type transistors, and the transistors 523 and 524 are N-type transistors.

[0048] Figure 6 According to the present disclosure Figure 5 A schematic diagram of the signals of the illustrated embodiment. Figure 5 and Figure 6During the period from time t0 to time t1, the voltage of the pulse width modulation scanning signal SPWM changes from a high voltage level to a low voltage level, thereby turning on the transistors 521 and 525. The data line DL transmits the voltage data VD having the pulse width modulation data. During the period from time t1 to time t2, the voltage of the pulse amplitude modulation scanning signal SPAM changes from a high voltage level to a low voltage level, thereby turning on the transistor 511. The data line DL transmits the voltage data VD having the pulse amplitude modulation data. During the data setting period from time t0 to time t2, the voltage of the emission enable signal EM changes from a low voltage level to a high voltage level, thereby turning off the transistors 522 and 532, and turning on the transistor 534. During the emission period from time t2 to time t5, the voltage of the emission enable signal EM changes from a high voltage level to a low voltage level, thereby turning on the transistors 522 and 532, and turning off the transistor 534.

[0049] In the first signal type 601, the voltage comparator 520 may receive a ramp signal SS'. During the data setting period from time t0 to time t2, the ramp signal SS' has a high voltage level, and the node voltage N1 changes from a relatively low voltage level to a threshold voltage (Vth). During the data setting period from time t0 to time t2, since the transistor 534 is turned on, the node voltage N2 is maintained at a low voltage level. At time t2, the ramp signal SS' (ramp rising signal) begins to rise, the node voltage N1 changes from the threshold voltage (Vth) to a relatively low voltage level, and the node voltage N2 changes from a low voltage level to a high voltage level, so that the transistor 535 is turned on to provide a driving current to the light emitting unit 540. At time t2, the light emitting unit 540 is lit. During the emission period from time t2 to time t5, the voltage of the ramp signal SS' rises, and the node voltage N1 rises synchronously. After time t4, since the node voltage N1 is higher than the threshold voltage, the transistor 531 is turned off and the transistor 533 is turned on. Therefore, the node voltage N2 changes from a high voltage level to a low voltage level, so that the transistor 535 is turned off and the light-emitting unit 540 is also turned off. Among them, the display device 500 can implement an effective dimming function for the light-emitting unit 540. It should be noted that the light-emitting unit 540 is first lit during the on period (lighting period) P1 from time t2 to time t4 (all light-emitting units are lit), and then the light-emitting unit 540 is turned off during the off period (dimming period) P2 from time t4 to time t5 to implement data setting (all light-emitting units are turned off sequentially or simultaneously). The total time length of the sum of the time lengths of the on period P1 and the off period P2 is equal to the emission period (time t2 to time t5).

[0050] In the first signal type 602, the voltage comparator 520 may receive a ramp signal SS. During the data setting period from time t0 to time t2, the ramp signal SS has a high voltage level, and the node voltage N1 changes from a relatively high voltage level to a threshold voltage (Vth). During the data setting period from time t0 to time t2, since the transistor 534 is turned on, the node voltage N2 is maintained at a low voltage level. At time t2, the ramp signal SS (ramp down signal) starts to decrease, and the node voltage N1 changes from the threshold voltage (Vth) to a relatively high voltage level. The node voltage N2 is maintained at a low voltage level, so that the transistor 535 is turned off and the light emitting unit 540 is also turned off. During the off period (dimming period) P2' from time t2 to time t3, the voltage of the ramp signal SS decreases, and the node voltage N1 decreases synchronously. After time t3, since the node voltage N1 is lower than the threshold voltage, the node voltage N2 changes from a low voltage level to a high voltage level, so after the voltage is inverted, the transistor 531 is turned on and the transistor 533 is turned off. Therefore, the transistor 535 is turned on and the light-emitting unit 540 is lit. Among them, the display device 500 can implement an effective dimming function for the light-emitting unit 540. It should be noted that the light-emitting unit 540 is first turned off during the off period (dimming period) P2' to implement data setting (all light-emitting units are turned off), and then the light-emitting unit 350 is lit during the on period (lighting period) P1' from time t3 to time t5 (all light-emitting units are lit sequentially or simultaneously). The total time length of the sum of the time lengths of the on period P1' and the off period P2' is equal to the emission period (time t2 to time t5).

[0051] Figure 7 is a schematic diagram of a current source according to another embodiment of the present disclosure. Figure 7 , Figure 3 and Figure 5The current source 310 and the current source 510 of the above-mentioned embodiment can be replaced by a current source 710 having a threshold voltage compensation function. In an embodiment of the present disclosure, the current source 710 includes a plurality of transistors 711 to 713, 715 and 716, and a capacitor 714. The first terminal of the transistor 711 is coupled to the data line and receives voltage data, and the control terminal of the transistor 711 receives the pulse amplitude modulation scanning signal SPAM. The first terminal of the transistor 712 receives the operation voltage, the control terminal of the transistor 712 receives the emission enable signal EM, and the second terminal of the transistor 712 is coupled to the second terminal of the transistor 711. The first terminal of the transistor 713 is coupled to the second terminal of the transistor 712, and the second terminal of the transistor 713 is coupled to the emission control unit. The first terminal of the capacitor 714 is coupled to the first terminal of the transistor 712, and the second terminal of the capacitor 714 is coupled to the control terminal of the transistor 713. The first terminal of the transistor 715 is coupled to the second terminal of the transistor 713, the control terminal of the transistor 715 receives the pulse amplitude modulation scanning signal, and the second terminal of the transistor 715 is coupled to the control terminal of the transistor 713. A first terminal of the transistor 716 is coupled to the second terminal of the transistor 715 , a control terminal of the transistor 716 receives the pulse width modulation scanning signal SPWM, and a second terminal of the transistor 716 is coupled to the reset voltage Vrst.

[0052] Figure 8 is a schematic diagram of a current source according to another embodiment of the present disclosure. Figure 8 , Figure 3 and Figure 5The current source 310 and the current source 510 of the above-mentioned embodiment can be replaced by a current source 810 having a threshold voltage compensation function. In the embodiment of the present disclosure, the current source 810 includes a plurality of transistors 811 to 813, and 816 to 818, a capacitor 814, and a capacitor 815. The first terminal of the transistor 811 is coupled to the data line and receives voltage data, and the control terminal of the transistor 811 receives the pulse amplitude modulation scanning signal SPAM. The first terminal of the transistor 812 is coupled to the second terminal of the transistor 811, the control terminal of the transistor 812 receives the emission enable signal EM, and the second terminal of the transistor 812 is coupled to the reference voltage Vref. The first terminal of the transistor 813 is coupled to the second terminal of the transistor 811, the control terminal of the transistor 813 receives the pulse width modulation scanning signal SPWM, and the second terminal of the transistor 813 is coupled to the reference voltage Vref. The first terminal of the capacitor 814 is coupled to the second terminal of the transistor 811. The first terminal of the capacitor 815 is coupled to the second terminal of the capacitor 814, and the second terminal of the capacitor 815 receives the operating voltage. A first terminal of transistor 816 is coupled to the second terminal of capacitor 815 and the operating voltage, and a control terminal of transistor 816 is coupled to the first terminal of capacitor 815. A first terminal of transistor 817 is coupled to the first terminal of capacitor 815, a control terminal of transistor 817 receives the pulse amplitude modulation scanning signal SPAM, and a second terminal of transistor 817 is coupled to the second terminal of transistor 816. A first terminal of transistor 818 is coupled to the first terminal of capacitor 815, a control terminal of transistor 818 receives the pulse width modulation scanning signal SPWM, and a second terminal of transistor 818 is coupled to the reset voltage Vrst.

[0053] Fig.9A is a schematic diagram of the signal and dimming operation according to the first embodiment of the present disclosure. Fig.9A The display device of the embodiment includes a pixel array. The pixel array includes a plurality of pixel units, and the plurality of pixel units are respectively Figure 4 The first ramp signal type 401 of the above embodiment is shown to operate. Figure 3The pixel circuit of the illustrated embodiment implements the plurality of pixel units of the display device of the embodiment. The plurality of pixel units are divided into a plurality of pixel groups for receiving different emission enable signals, and the plurality of pixel groups receive a common ramp signal SS. In the embodiment of the present disclosure, the plurality of pixel units are divided into two pixel groups G1 and G2. The pixel groups G1 and G2 may receive emission enable signals EM1 and EM2, respectively, and receive a common ramp signal SS. The common ramp signal SS includes a plurality of sub-slope falling signals. During the period from time t0 to time t1, corresponding to the emission enable signal EM1 with a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signal EM2 with a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G1 may operate in the data setting mode (the light-emitting unit is turned off), and the pixel group G2 may operate in the dimming mode (the light-emitting unit is lit sequentially or simultaneously). All the light-emitting units of the pixel group G2 are lit simultaneously, and then all the light-emitting units of the pixel group G2 are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t1 to time t2, corresponding to the emission enable signal EM1 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signal EM2 having a high voltage level (corresponding to the data setting period described in the above embodiment), the pixel group G1 may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), and the pixel group G2 may operate in the data setting mode (the light emitting units are turned off). All the light emitting units of the pixel group G1 are lit at the same time, and then all the light emitting units of the pixel group G1 are turned off sequentially or simultaneously after different or the same emission periods.

[0054] It should be noted that the plurality of ramp periods corresponding to the sub-ramp down signals of the common ramp signal SS overlap with the data setting period and the emission period of the emission enable signals EM1 and EM2, respectively. A vertical scanning period VSP of the display device of the embodiment includes a data setting period and an emission period. The pixel groups G1 and G2 are lit during different emission periods, and are set during different data setting periods according to the emission enable signals EM1 and EM2, respectively. The different data setting periods corresponding to the pixel groups G1 and G2 do not overlap with each other in time. In addition, the data setting period corresponding to one of the emission enable signals EM1 and EM2 overlaps with the emission period corresponding to the other of the emission enable signals EM1 and EM2. Therefore, the display device of the embodiment can effectively reduce the peak power consumption. Specifically, if all pixel units are operated in the data setting mode (the light-emitting unit is turned off), the occurrence of IR drop and no light can be avoided.

[0055] Fig. 9Bis a schematic diagram of a signal and dimming operation according to the second embodiment of the present disclosure. Fig. 9B The display device of the embodiment includes a pixel array. The pixel array includes a plurality of pixel units, and the plurality of pixel units are respectively Figure 6 The second ramp signal type 602 of the above embodiment is shown to operate. Figure 5 The pixel circuit of the embodiment shown in the figure implements the plurality of pixel units of the display device of the embodiment. The plurality of pixel units are divided into a plurality of pixel groups for receiving different emission enable signals, and the plurality of pixel groups receive a common ramp signal SS. In the embodiment of the present disclosure, similar to Fig.9A In the above embodiment, the plurality of pixel units are divided into two pixel groups G1 and G2. The pixel groups G1 and G2 can receive emission enable signals EM1 and EM2 respectively, and receive a common ramp signal SS. The common ramp signal SS includes a plurality of sub-ramp down signals.

[0056] and Fig.9A Unlike the above-mentioned embodiments, during the period from time t0 to time t1, all the light-emitting units of the pixel group G2 are first turned off, and then after different or the same data setting cycles, all the light-emitting units of the pixel group G2 are sequentially or simultaneously lit. During the period from time t1 to time t2, all the light-emitting units of the pixel group G1 are first turned off, and then after different or the same data setting cycles, all the light-emitting units of the pixel group G1 are sequentially or simultaneously lit. Therefore, the display device of the embodiment can effectively reduce the peak power consumption. Specifically, if all the pixel units are operated in the data setting mode (the light-emitting units are turned off), the occurrence of IR drop and no light can be avoided.

[0057] Fig. 9C is a schematic diagram of a signal and dimming operation according to the third embodiment of the present disclosure. Fig. 9C The display device of the embodiment includes a pixel array. The pixel array includes a plurality of pixel units, and the plurality of pixel units are respectively Figure 4 The second ramp signal type 402 of the above embodiment is shown to operate. Figure 3 The pixel circuit of the embodiment shown in the figure implements the plurality of pixel units of the display device of the embodiment. The plurality of pixel units are divided into a plurality of pixel groups for receiving different emission enable signals, and the plurality of pixel groups receive a common ramp signal SS'. In the embodiment of the present disclosure, similar to Fig. 9B In the above embodiment, the plurality of pixel units are divided into two pixel groups G1 and G2. The pixel groups G1 and G2 can receive emission enable signals EM1 and EM2 respectively. Fig. 9BDifferent from the above-mentioned embodiment, the pixel groups G1 and G2 can respectively receive a common ramp signal SS'. The common ramp signal SS' includes a plurality of sub-ramp rising signals.

[0058] During the period from time t0 to time t1, all the light emitting units of the pixel group G2 are first turned off, and then after different or the same data setting cycles, all the light emitting units of the pixel group G2 are sequentially or simultaneously lit. During the period from time t1 to time t2, all the light emitting units of the pixel group G1 are first turned off, and then after different or the same data setting cycles, all the light emitting units of the pixel group G1 are sequentially or simultaneously lit.

[0059] Similar to Fig. 9B In the above-mentioned embodiment shown, during the period from time t0 to time t1, all the light-emitting units of the pixel group G2 are first turned off, and then after different or the same data setting cycles, all the light-emitting units of the pixel group G2 are sequentially or simultaneously lit. During the period from time t1 to time t2, all the light-emitting units of the pixel group G1 are simultaneously lit, and then after different or the same emission cycles, all the light-emitting units of the pixel group G1 are sequentially or simultaneously turned off. Therefore, the display device of the embodiment can effectively reduce the peak power consumption. Specifically, if all the pixel units are operated in the data setting mode (the light-emitting units are turned off), the occurrence of IR drop and no light can be avoided.

[0060] Fig.9D is a schematic diagram of a signal and dimming operation according to a fourth embodiment of the present disclosure. Fig.9D The display device of the embodiment includes a pixel array. The pixel array includes a plurality of pixel units, and the plurality of pixel units are respectively Figure 6 The first ramp signal type 601 of the above embodiment is shown to operate. Figure 5 The pixel circuit of the embodiment shown in the figure implements the plurality of pixel units of the display device of the embodiment. The plurality of pixel units are divided into a plurality of pixel groups for receiving different emission enable signals, and the plurality of pixel groups receive a common ramp signal SS'. In the embodiment of the present disclosure, similar to Fig.9A In the above embodiment, the plurality of pixel units are divided into two pixel groups G1 and G2. The pixel groups G1 and G2 can receive emission enable signals EM1 and EM2 respectively. Fig.9A Different from the above-mentioned embodiment, the pixel groups G1 and G2 can respectively receive a common ramp signal SS'. The common ramp signal SS' includes a plurality of sub-ramp rising signals.

[0061] Similar to Fig.9AIn the above-mentioned embodiment shown, during the period from time t0 to time t1, all the light-emitting units of the pixel group G2 are simultaneously lit, and then all the light-emitting units of the pixel group G2 are sequentially or simultaneously turned off after different or the same emission cycles. During the period from time t1 to time t2, all the light-emitting units of the pixel group G1 are simultaneously lit, and then all the light-emitting units of the pixel group G1 are sequentially or simultaneously turned off after different or the same emission cycles. Therefore, the display device of the embodiment can effectively reduce the peak power consumption. Specifically, if all the pixel units are operated in the data setting mode (the light-emitting units are turned off), the occurrence of IR drop and no light can be avoided.

[0062] Fig. 10A is a schematic diagram of a signal and dimming operation according to a fourth embodiment of the present disclosure. Fig. 10A The display device of the embodiment includes a pixel array. The pixel array includes a plurality of pixel units, and the plurality of pixel units are respectively Figure 6 The first ramp signal type 601 of the above embodiment is shown to operate. Figure 5The pixel circuit of the illustrated embodiment implements the plurality of pixel units of the display device of the embodiment. The plurality of pixel units are divided into a plurality of pixel groups for receiving different emission enable signals, and the plurality of pixel groups receive a common ramp signal SS'. In an embodiment of the present disclosure, the plurality of pixel units are divided into four pixel groups G1 to G4. The pixel groups G1 to G4 may receive emission enable signals EM1 to EM4, respectively, and receive a common ramp signal SS'. The common ramp signal SS' includes a plurality of sub-ramp rising signals. During the period from time t0 to time t1, corresponding to the emission enable signal EM1 having a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signal EM2 to EM4 having a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G1 may operate in the data setting mode (the light-emitting unit is turned off), and the pixel groups G2 to G4 may operate in the dimming mode (the light-emitting units are lit sequentially or simultaneously). All the light-emitting units of the pixel groups G2 to G4 are lit at the same time, and then all the light-emitting units of the pixel groups G2 to G4 are turned off sequentially or simultaneously after different or the same emission cycles. During the period from time t1 to time t2, corresponding to the emission enable signal EM2 with a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signals EM1, EM3 and EM4 with a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G2 can be operated in the data setting mode (the light-emitting unit is turned off), and the pixel groups G1, G3 and G4 can be operated in the dimming mode (the light-emitting units are lit sequentially or simultaneously). All the light-emitting units of the pixel group G2 are lit at the same time, and then all the light-emitting units of the pixel group G2 are turned off sequentially or simultaneously after different or the same emission cycles. During the period from time t2 to time t3, corresponding to the emission enable signal EM3 having a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signals EM1, EM2 and EM4 having a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G3 may operate in the data setting mode (the light emitting unit is turned off), and the pixel groups G1, G2 and G4 may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit). All the light emitting units of the pixel group G3 are lit at the same time, and then all the light emitting units of the pixel group G3 are turned off sequentially or simultaneously after different or the same emission periods.During the period from time t3 to time t4, corresponding to the emission enable signal EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signals EM1 to EM3 having a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G4 may operate in the data setting mode (the light emitting unit is turned off), and the pixel groups G1 to G3 may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit). All the light emitting units of the pixel group G4 are lit at the same time, and then all the light emitting units of the pixel group G4 are turned off sequentially or simultaneously after different or the same emission periods.

[0063] It should be noted that the plurality of ramp periods corresponding to the sub-ramp rising signals of the common ramp signal SS' overlap with the data setting period and the emission period of the emission enable signals EM1 to EM4, respectively. One vertical scanning period VSP of the display device of the embodiment includes one data setting period and three emission periods. The pixel groups G1 to G4 are lit during different emission periods, and are set during different data setting periods according to the emission enable signals EM1 to EM4, respectively. The different data setting periods corresponding to the pixel groups G1 to G4 do not overlap with each other in time. In addition, the data setting period corresponding to one of the emission enable signals EM1 to EM4 overlaps with the emission period corresponding to the other three of the emission enable signals EM1 and EM2. Therefore, the display device of the embodiment can effectively reduce the peak power consumption. Specifically, if all pixel units are operated in the data setting mode (the light-emitting unit is turned off), the occurrence of IR drop and no light can be avoided.

[0064] Fig. 10B is a schematic diagram of a signal and dimming operation according to the fifth embodiment of the present disclosure. Fig. 10B In the embodiment of the present disclosure, the plurality of pixel units are divided into four pixel groups G1 to G4. The pixel groups G1 to G4 can receive emission enable signals EM1 to EM4, respectively, and receive a common ramp signal SS'. The common ramp signal SS' includes a plurality of sub-ramp rising signals. Fig. 10AUnlike the embodiment shown, during the period from time t0 to time t1, corresponding to the emission enable signals EM1 to EM3 having a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signal EM4 having a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G1 can operate in the data setting mode (the light-emitting unit is turned off), and the pixel group G4 can operate in the dimming mode (the light-emitting units are sequentially or simultaneously lit), wherein the pixel groups G2 and G3 do not receive, for example, the pulse amplitude modulation scanning signal and / or the pulse width modulation scanning signal as described in the above embodiment. The pixel groups G2 and G3 can operate in the idle mode (no operation state). In other words, even if the pixel groups G2 and G3 receive the emission enable signals EM2 and EM3 having a high voltage level, if there is no pulse amplitude modulation scanning signal and / or pulse width modulation scanning signal, the pixel groups G2 and G3 operate in the idle mode. All the light-emitting units of the pixel group G4 are lit at the same time, and then all the light-emitting units of the pixel group G4 are turned off sequentially or simultaneously after different or the same emission cycles. During the period from time t1 to time t2, corresponding to the emission enable signals EM2 to EM4 with a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signal EM1 with a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G2 can be operated in the data setting mode (the light-emitting unit is turned off), and the pixel group G1 can be operated in the dimming mode (the light-emitting unit is lit sequentially or simultaneously), wherein the pixel groups G3 and G4, for example, do not receive the pulse amplitude modulation scanning signal and / or the pulse width modulation scanning signal as described in the above embodiment. The pixel groups G3 and G4 can operate in the idle mode (no operation state). In other words, even if the pixel groups G3 and G4 receive the emission enable signals EM3 ​​and EM4 with a high voltage level, if there is no pulse amplitude modulation scanning signal and / or pulse width modulation scanning signal, the pixel groups G3 and G4 operate in the idle mode. All the light-emitting units of the pixel group G1 are lit at the same time, and then all the light-emitting units of the pixel group G1 are turned off sequentially or simultaneously after different or the same emission cycles. During the period from time t2 to time t3, corresponding to the emission enable signals EM1, EM3 and EM4 with a high voltage level (corresponding to the data setting period described in the above embodiments) and the emission enable signal EM2 with a low voltage level (corresponding to the enable period described in the above embodiments), the pixel group G3 can be operated in the data setting mode (the light-emitting units are turned off), and the pixel group G2 can be operated in the dimming mode (the light-emitting units are lit sequentially or simultaneously), wherein the pixel groups G1 and G4 do not receive, for example, the pulse amplitude modulation scanning signal and / or the pulse width modulation scanning signal described in the above embodiments.The pixel groups G1 and G4 may operate in an idle mode (no operation state). In other words, even if the pixel groups G1 and G4 receive emission enable signals EM1 and EM4 with a high voltage level, if there is no pulse amplitude modulation scan signal and / or pulse width modulation scan signal, the pixel groups G1 and G4 operate in an idle mode. All light-emitting units of the pixel group G2 are lit at the same time, and then all light-emitting units of the pixel group G2 are turned off sequentially or simultaneously after different or the same emission cycles. During the period from time t3 to time t4, corresponding to the emission enable signals EM1, EM2 and EM4 with a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signal EM3 with a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G4 may operate in the data setting mode (the light-emitting unit is turned off), and the pixel group G3 may operate in the dimming mode (the light-emitting unit is lit sequentially or simultaneously), wherein the pixel groups G1 and G2 do not receive the pulse amplitude modulation scan signal and / or the pulse width modulation scan signal, for example, as described in the above embodiment. The pixel groups G1 and G2 can operate in an idle mode (no operation state). In other words, even if the pixel groups G1 and G2 receive emission enable signals EM1 and EM2 with a high voltage level, if there is no pulse amplitude modulation scanning signal and / or pulse width modulation scanning signal, the pixel groups G1 and G2 operate in an idle mode. All light-emitting units of the pixel group G3 are lit at the same time, and then all light-emitting units of the pixel group G3 are turned off sequentially or simultaneously after different or the same emission cycles. Therefore, the display device of the embodiment can achieve a 1 / 4 duty ratio in time and space by controlling the emission enable signals EM1 to EM4, thereby more effectively reducing peak power consumption. Specifically, if all pixel units are operated in a data setting mode (the light-emitting units are turned off), IR drop and no light can be avoided.

[0065] Fig. 10C is a schematic diagram of a signal and dimming operation according to a sixth embodiment of the present disclosure. Fig. 10C In the embodiment of the present disclosure, the plurality of pixel units are divided into four pixel groups G1 to G4. The pixel groups G1 to G4 can receive emission enable signals EM1 to EM4, respectively, and receive a common ramp signal SS'. The common ramp signal SS' includes a plurality of sub-ramp rising signals. Fig. 10AUnlike the embodiment shown, during the period from time t0 to time t1, corresponding to the emission enable signals EM1 and EM3 having a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signals EM2 and EM4 having a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G1 can operate in the data setting mode (the light-emitting unit is turned off), and the pixel groups G2 and G4 can operate in the dimming mode (the light-emitting units are sequentially or simultaneously lit), wherein the pixel group G3 does not receive, for example, the pulse amplitude modulation scanning signal and / or the pulse width modulation scanning signal as described in the above embodiment. The pixel group G3 can operate in the idle mode (no operation state). In other words, even if the pixel group G3 receives the emission enable signal EM3 having a high voltage level, if there is no pulse amplitude modulation scanning signal and / or pulse width modulation scanning signal, the pixel group G3 operates in the idle mode. All the light-emitting units of the pixel groups G2 and G4 are lit at the same time, and then all the light-emitting units of the pixel groups G2 and G4 are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t1 to time t2, corresponding to the emission enable signals EM2 and EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signals EM1 and EM3 having a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G2 may operate in the data setting mode (the light emitting unit is turned off), and the pixel groups G1 and G3 may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), wherein the pixel group G4 does not receive, for example, a pulse amplitude modulation scanning signal and / or a pulse width modulation scanning signal as described in the above embodiment. The pixel group G4 may operate in the idle mode (no operation state). In other words, even if the pixel group G4 receives the emission enable signal EM4 having a high voltage level, if there is no pulse amplitude modulation scanning signal and / or pulse width modulation scanning signal, the pixel group G4 operates in the idle mode. All the light emitting units of the pixel groups G1 and G3 are lit at the same time, and then all the light emitting units of the pixel groups G1 and G3 are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t2 to time t3, corresponding to the emission enable signals EM1 and EM3 having high voltage levels (corresponding to the data setting period described in the above embodiments) and the emission enable signals EM2 and EM4 having low voltage levels (corresponding to the enable period described in the above embodiments), the pixel group G3 may operate in the data setting mode (the light-emitting unit is turned off), and the pixel groups G2 and G4 may operate in the dimming mode (the light-emitting units are lit sequentially or simultaneously), wherein the pixel group G1 does not receive, for example, a pulse amplitude modulation scanning signal and / or a pulse width modulation scanning signal as described in the above embodiments.The pixel group G1 may be operated in an idle mode (no operation state). In other words, even if the pixel group G1 receives an emission enable signal EM1 having a high voltage level, if there is no pulse amplitude modulation scan signal and / or pulse width modulation scan signal, the pixel group G1 operates in an idle mode. All light-emitting units of the pixel groups G2 and G4 are simultaneously lit, and then all light-emitting units of the pixel groups G2 and G4 are sequentially or simultaneously turned off after different or the same emission cycles. During the period from time t3 to time t4, corresponding to the emission enable signals EM2 and EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment) and the emission enable signals EM1 and EM3 having a low voltage level (corresponding to the enable period described in the above embodiment), the pixel group G4 may be operated in a data setting mode (the light-emitting unit is turned off), and the pixel groups G1 and G3 may be operated in a dimming mode (the light-emitting units are sequentially or simultaneously lit), wherein the pixel group G2 does not receive a pulse amplitude modulation scan signal and / or a pulse width modulation scan signal, for example, as described in the above embodiment. The pixel group G2 can operate in an idle mode (no operation state). In other words, even if the pixel group G2 receives an emission enable signal EM3 having a high voltage level, if there is no pulse amplitude modulation scanning signal and / or pulse width modulation scanning signal, the pixel group G2 operates in an idle mode. All light-emitting units of the pixel groups G1 and G3 are lit at the same time, and then all light-emitting units of the pixel groups G1 and G3 are turned off sequentially or simultaneously after different or the same emission cycles. Therefore, the display device of the embodiment can achieve a 1 / 2 duty cycle in time and space by controlling the emission enable signals EM1 to EM4, thereby more effectively reducing peak power consumption. Specifically, if all pixel units are operated in a data setting mode (the light-emitting units are turned off), IR drop and no light can be avoided.

[0066] Fig.11 is a schematic diagram of a signal and dimming operation according to the seventh embodiment of the present disclosure. Fig.11 The display device of the embodiment includes a pixel array. The pixel array includes a plurality of pixel units, and the plurality of pixel units are respectively Figure 6 The first ramp signal type 601 of the above embodiment is shown to operate. Figure 5The pixel circuit of the illustrated embodiment implements the multiple pixel units of the display device of the embodiment. The multiple pixel units are divided into multiple pixel groups for receiving different emission enable signals, and the multiple pixel groups receive a common ramp signal SS'. In the embodiment of the present disclosure, the multiple pixel units are divided into four pixel groups. It should be noted that the four pixel groups of pixel units correspond to different rows of the pixel array, respectively, and the different rows of the pixel array corresponding to the different pixel groups of pixel units are arranged alternately and sequentially. Fig.11 As shown in , the first pixel group includes the row (4(n-1)+1) of the pixel array, the row (4n+1) of the pixel array, the row (4(n+1)+1) of the pixel array, the row (4(n+2)+1) of the pixel array, etc., where n may be equal to 2 or greater than 2. The second pixel group includes the row (4(n-1)+2) of the pixel array, the row (4n+2) of the pixel array, the row (4(n+1)+2) of the pixel array, etc. The third pixel group includes the row (4(n-1)+3) of the pixel array, the row (4n+3) of the pixel array, the row (4(n+1)+3) of the pixel array, etc. The fourth pixel group includes the row (4(n-2)+4) of the pixel array, the row (4(n-1)+4) of the pixel array, the row (4n+4) of the pixel array, the row (4(n+1)+4) of the pixel array, etc.

[0067] The four pixel groups may receive emission enable signals EM1 to EM4, respectively, and receive a common ramp signal SS'. The common ramp signal SS' includes a plurality of sub-ramp rising signals. During the period from time t1 to time t2, corresponding to the emission enable signal EM4 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM1 to EM3 having a high voltage level (corresponding to the data setting period described in the above embodiment), the fourth pixel group may operate in a dimming mode (the light-emitting units are sequentially or simultaneously lit), and the first pixel group may operate in a data setting mode (the light-emitting units are turned off), wherein the second pixel group and the third pixel group may operate in an idle mode. All light-emitting units of the fourth pixel group are lit at the same time, and then all light-emitting units of the fourth pixel group are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t2 to time t3, corresponding to the emission enable signal EM1 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM2 to EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment), the first pixel group may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), and the second pixel group may operate in the data setting mode (the light emitting units are turned off), wherein the third pixel group and the fourth pixel group may operate in the idle mode. All the light emitting units of the first pixel group are lit at the same time, and then all the light emitting units of the first pixel group are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t3 to time t4, corresponding to the emission enable signal EM2 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM1, EM3 and EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment), the second pixel group may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), and the third pixel group may operate in the data setting mode (the light emitting units are turned off), wherein the first pixel group and the fourth pixel group may operate in the idle mode. All the light emitting units of the second pixel group are lit at the same time, and then all the light emitting units of the second pixel group are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t4 to time t5, corresponding to the emission enable signal EM3 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM1, EM2 and EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment), the third pixel group can be operated in the dimming mode (the light-emitting units are lit sequentially or simultaneously), and the fourth pixel group can be operated in the data setting mode (the light-emitting units are turned off), wherein the first pixel group and the second pixel group can be operated in the idle mode.All the light-emitting units of the third pixel group are lit at the same time, and then all the light-emitting units of the third pixel group are turned off sequentially or simultaneously after different or the same emission cycles. During a vertical scanning period VSP of the display device, each row of the pixel array performs an emission operation during an emission period, and performs a data setting operation during a data setting period. Therefore, the display device of the embodiment can achieve a 1 / 4 duty cycle in time and space by controlling the emission enable signals EM1 to EM4 based on the staggered emission mode of the present embodiment, thereby more effectively reducing the peak power consumption. Specifically, if all pixel units are operated in the data setting mode (the light-emitting unit is turned off), the occurrence of IR drop and no light can be avoided.

[0068] Fig.12 is a schematic diagram of a signal and dimming operation according to the eighth embodiment of the present disclosure. Fig.12 The display device of the embodiment includes a pixel array. The pixel array includes a plurality of pixel units, and the plurality of pixel units are respectively Figure 6 The first ramp signal type 601 of the above embodiment is shown to operate. Figure 5 The pixel circuit of the embodiment shown implements the multiple pixel units of the display device of the embodiment. The multiple pixel units are divided into multiple pixel groups for receiving different emission enable signals, and the multiple pixel groups receive a common ramp signal SS'. In the embodiment of the present disclosure, the multiple pixel units are divided into four pixel groups. It should be noted that the four pixel groups of the pixel unit correspond to different rows of the pixel array, respectively, and the different rows of the pixel array corresponding to the different pixel groups of the pixel unit are arranged alternately but not sequentially.

[0069] In an embodiment of the present disclosure, the four pixel groups may receive emission enable signals EM1 to EM4 respectively, and receive a common ramp signal SS'. The common ramp signal SS' includes a plurality of sub-ramp rising signals. Fig.11Unlike the embodiment shown, during the period from time t1 to time t2, corresponding to the emission enable signal EM4 with a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM1 to EM3 with a high voltage level (corresponding to the data setting period described in the above embodiment), the fourth pixel group can operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), and the first pixel group can operate in the data setting mode (the light emitting units are turned off), wherein the second pixel group and the third pixel group can operate in the idle mode. All the light emitting units of the fourth pixel group are lit at the same time, and then all the light emitting units of the fourth pixel group are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t2 to time t3, corresponding to the emission enable signal EM1 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM2 to EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment), the first pixel group may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), and the third pixel group may operate in the data setting mode (the light emitting units are turned off), wherein the second pixel group and the fourth pixel group may operate in the idle mode. All the light emitting units of the first pixel group are lit at the same time, and then all the light emitting units of the first pixel group are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t3 to time t4, corresponding to the emission enable signal EM3 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM1, EM2 and EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment), the third pixel group may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), and the second pixel group may operate in the data setting mode (the light emitting units are turned off), wherein the first pixel group and the fourth pixel group may operate in the idle mode. All the light emitting units of the third pixel group are lit at the same time, and then all the light emitting units of the third pixel group are turned off sequentially or simultaneously after different or the same emission periods. During the period from time t4 to time t5, corresponding to the emission enable signal EM2 having a low voltage level (corresponding to the enable period described in the above embodiment) and the emission enable signals EM1, EM3 and EM4 having a high voltage level (corresponding to the data setting period described in the above embodiment), the second pixel group may operate in the dimming mode (the light emitting units are sequentially or simultaneously lit), and the fourth pixel group may operate in the data setting mode (the light emitting units are turned off), wherein the first pixel group and the third pixel group may operate in the idle mode. All the light emitting units of the second pixel group are lit at the same time, and then all the light emitting units of the second pixel group are turned off sequentially or simultaneously after different or the same emission periods.During a vertical scanning period VSP of the display device, each row of the pixel array performs an emission operation during an emission period, and performs a data setting operation during a data setting period. Therefore, the display device of the embodiment can achieve a 1 / 4 duty cycle in time and space by controlling the emission enable signals EM1 to EM4 based on the skip emission mode of the present embodiment, thereby more effectively reducing the peak power consumption. Specifically, if all pixel units are operated in the data setting mode (the light-emitting unit is turned off), the occurrence of IR drop and no light can be avoided.

[0070] Fig.13 is a schematic diagram of a display device according to another embodiment of the present disclosure. Fig.13 The display device 1300 includes a pixel array, and the pixel array includes a plurality of pixel units, wherein each of the plurality of pixel units may include Fig.13 In the embodiment of the present disclosure, the display device 1300 includes a current source 1310, a voltage comparator 1320, an emission control unit 1331, an emission control unit 1332, a light emitting unit 1341, and a light emitting unit 1342. The current source 1310 is coupled to the pixel array and is configured to output a supply current SI to the light emitting unit 1341 and the light emitting unit 1342 in the pixel array. Similar to the above embodiment, the current source 1310 can receive a pulse amplitude modulation scanning signal for voltage programming.

[0071] The current source 1310 is coupled between the operating voltage VDD_LEU and the emission control unit 1331, and is coupled between the operating voltage VDD_LEU and the emission control unit 1332. The emission control unit 1331 is further coupled to the voltage comparator 1320 and the light emitting unit 1341, and receives the emission enable signal EM1. The emission control unit 1332 is further coupled to the voltage comparator 1320 and the light emitting unit 1342, and receives the emission enable signal EM2. The light emitting unit 1341 is coupled between the emission control unit 1331 and the voltage VSS_LEU. The voltage VSS_LEU is lower than the operating voltage VDD_LEU. The light emitting unit 1342 is coupled between the emission control unit 1332 and the voltage VSS_LEU. In other words, the plurality of pixel units may be divided into a plurality of pixel groups, and the pixel groups are coupled to the common current source 1310 and the common voltage comparator 1320.

[0072] In an embodiment of the present disclosure, the current source 1310 is configured to output a supply current SI to the emission control unit 1331 and the emission control unit 1332. The voltage comparator 1320 is configured to receive voltage data VD and a ramp signal SS. The voltage comparator 1320 outputs a comparison signal CS to the emission control unit 1331 and the emission control unit 1332 according to the voltage data VD and the ramp signal SS. The emission control unit 1331 may output a driving current DI1 to the light emitting unit 1341 according to the supply current SI, the emission enable signal EM1, and the comparison signal CS. The emission control unit 1332 may output a driving current DI2 to the light emitting unit 1342 according to the supply current S1, the emission enable signal EM2, and the comparison signal CS. In an embodiment of the present disclosure, the emission enable signal EM1, the emission enable signal EM2, the voltage data VD, and the ramp signal SS may be provided from a plurality of driving circuits respectively arranged outside the plane of the display device 1300 or arranged within the plane of the display device 1300 through data lines and / or scan lines.

[0073] It should be noted that, for example, Fig.11 and Fig.12 Each of the odd-numbered rows in the pixel array in the illustrated embodiment can be implemented by the emission control unit 1331 and the light emitting unit 1341, and Fig.11 and Fig.12 Each row of the even rows in the pixel array in the illustrated embodiment that is adjacent to a corresponding odd row can be implemented by the emission control unit 1332 and the light emitting unit 1342. In other words, since the light emitting units of each row of the odd rows and the light emitting units of each row of the even rows that is adjacent to a corresponding odd row share the current source 1310 and the voltage comparator 1320, Fig.11 and Fig.12 The display device of the illustrated embodiment can reduce the circuit area by time-sharing the circuit using pixels on even-numbered rows and odd-numbered rows.

[0074] In summary, the display device of one embodiment of the present disclosure can reduce peak power consumption by time-sharing the data setting operation and dimming operation on different pixel groups of the pixel array for the display device. Specifically, if all pixel units are operated in the data setting operation mode, IR drop and no light can be avoided. In addition, the display device of another embodiment of the present disclosure can reduce the circuit area by time-sharing the circuit using pixels on even rows and odd rows.

[0075] It is obvious to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In view of the above, the present disclosure is intended to cover modifications and changes within the scope of the above claims and their equivalents.

Claims

1. A display device, characterized in that: include: Light emitting unit; a current source configured to output a supply current; a voltage comparator configured to receive voltage data and a ramp signal; as well as a transmission control unit configured to receive a transmission enable signal and coupled to the light emitting unit, the current source and the voltage comparator; wherein the voltage comparator outputs a comparison signal to the emission control unit according to the voltage data and the ramp signal, and the emission control unit outputs a driving current to the light emitting unit according to the supply current, the emission enable signal and the comparison signal, The voltage comparator further receives a pulse width modulation scanning signal and performs voltage programming on the voltage data according to the pulse width modulation scanning signal.

2. The display device according to claim 1, characterized in that The time length of the emission period of the driving current is determined by the voltage data and the ramp signal.

3. The display device according to claim 1, characterized in that The voltage comparator comprises: a first transistor, wherein a first terminal of the first transistor is coupled to a data line and receives the voltage data, and a control terminal of the first transistor receives a pulse width modulated scan signal; a second transistor, wherein a first terminal of the second transistor receives the ramp signal, a control terminal of the second transistor receives the emission enable signal, and a second terminal of the second transistor is coupled to a second terminal of the first transistor; a first capacitor, wherein a first terminal of the first capacitor is coupled to the second terminal of the second transistor and to the second terminal of the first transistor; a first inverter circuit, wherein an input terminal of the first inverter circuit is coupled to the second terminal of the first capacitor and an output terminal of the first inverter circuit is coupled to the transmit control unit; and a third transistor, wherein a first terminal of the third transistor is coupled to the input terminal of the first inverter circuit, a control terminal of the third transistor receives the pulse width modulated scan signal, and a second terminal of the third transistor is coupled to the output terminal of the first inverter circuit.

4. The display device according to claim 3, characterized in that The first inverter circuit comprises: a fourth transistor, wherein a first terminal of the fourth transistor receives an operating voltage, a control terminal of the fourth transistor is coupled to the input terminal of the first inverter circuit, and a second terminal of the fourth transistor is coupled to the output terminal of the first inverter circuit; and a fifth transistor, wherein a first terminal of the fifth transistor receives a voltage, a control terminal of the fifth transistor is coupled to the input terminal of the first inverter circuit, and a second terminal of the fifth transistor is coupled to the output terminal of the first inverter circuit.

5. The display device according to claim 3, characterized in that: The voltage comparator also includes: A second inverter circuit, wherein an input terminal of the second inverter circuit is coupled to the output terminal of the first inverter circuit, and an output terminal of the second inverter circuit is coupled to the transmit control unit.

6. The display device according to claim 1, characterized in that The transmitting control unit comprises: a sixth transistor, wherein a control terminal of the sixth transistor is coupled to the voltage comparator; a seventh transistor, wherein a first terminal of the seventh transistor is coupled to an operating voltage, a control terminal of the seventh transistor receives the transmit enable signal, and a second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor; an eighth transistor, wherein a first terminal of the eighth transistor is coupled to the second terminal of the sixth transistor, a control terminal of the eighth transistor is coupled to the voltage comparator, and a second terminal of the eighth transistor is coupled to a voltage; a ninth transistor, wherein a first terminal of the ninth transistor is coupled to the second terminal of the sixth transistor, a control terminal of the ninth transistor receives the emission enable signal, and a second terminal of the ninth transistor is coupled to the voltage; and A tenth transistor, wherein a first terminal of the tenth transistor is coupled to the current source, a control terminal of the tenth transistor is coupled to the second terminal of the sixth transistor, and a second terminal of the tenth transistor is coupled to the light emitting unit.

7. The display device according to claim 1, characterized in that The current source also receives a pulse amplitude modulated scanning signal for voltage programming.

8. The display device according to claim 7, characterized in that: The current source comprises: an eleventh transistor, wherein a first terminal of the eleventh transistor is coupled to a data line and receives the voltage data, and a control terminal of the eleventh transistor receives the pulse amplitude modulation scanning signal; a twelfth transistor, wherein a first terminal of the twelfth transistor receives an operating voltage, a control terminal of the twelfth transistor is coupled to a second terminal of the eleventh transistor, and a second terminal of the twelfth transistor is coupled to the emission control unit; and a second capacitor, wherein a first terminal of the second capacitor is coupled to the second terminal of the eleventh transistor and a second terminal of the second capacitor is coupled to the second terminal of the twelfth transistor.

9. The display device according to claim 7, characterized in that: The current source comprises: a thirteenth transistor, wherein a first terminal of the thirteenth transistor is coupled to a data line and receives the voltage data, and a control terminal of the thirteenth transistor receives the pulse amplitude modulation scanning signal; a fourteenth transistor, wherein a first terminal of the fourteenth transistor receives an operating voltage, a control terminal of the fourteenth transistor receives the emission enable signal, and a second terminal of the fourteenth transistor is coupled to the second terminal of the thirteenth transistor; a fifteenth transistor, wherein a first terminal of the fifteenth transistor is coupled to the second terminal of the fourteenth transistor, and a second terminal of the fifteenth transistor is coupled to the emission control unit; a third capacitor, wherein a first terminal of the third capacitor is coupled to the first terminal of the fourteenth transistor and a second terminal of the third capacitor is coupled to the control terminal of the fifteenth transistor; a sixteenth transistor, wherein a first terminal of the sixteenth transistor is coupled to the second terminal of the fifteenth transistor, a control terminal of the sixteenth transistor receives the pulse amplitude modulation scanning signal, and a second terminal of the sixteenth transistor is coupled to the control terminal of the fifteenth transistor; and A seventeenth transistor, wherein a first terminal of the seventeenth transistor is coupled to the second terminal of the sixteenth transistor, a control terminal of the seventeenth transistor receives a pulse width modulated scan signal, and a second terminal of the seventeenth transistor is coupled to a reset voltage.

10. The display device according to claim 7, characterized in that: The current source comprises: an eighteenth transistor, wherein a first terminal of the eighteenth transistor is coupled to a data line and receives the voltage data, and a control terminal of the eighteenth transistor receives the pulse amplitude modulation scanning signal; a nineteenth transistor, wherein a first terminal of the nineteenth transistor is coupled to the second terminal of the eighteenth transistor, a control terminal of the nineteenth transistor receives the emission enable signal, and a second terminal of the nineteenth transistor is coupled to a reference voltage; a twentieth transistor, wherein a first terminal of the twentieth transistor is coupled to the second terminal of the eighteenth transistor, a control terminal of the twentieth transistor receives a pulse width modulated scan signal, and a second terminal of the twentieth transistor is coupled to the reference voltage; a fourth capacitor, wherein a first terminal of the fourth capacitor is coupled to the second terminal of the eighteenth transistor; a fifth capacitor, wherein a first terminal of the fifth capacitor is coupled to a second terminal of the fourth capacitor and a second terminal of the fifth capacitor receives an operating voltage; a twenty-first transistor, wherein a first terminal of the twenty-first transistor is coupled to the second terminal of the fifth capacitor and the operating voltage, and a control terminal of the twenty-first transistor is coupled to the first terminal of the fifth capacitor; a twenty-second transistor, wherein a first terminal of the twenty-second transistor is coupled to the first terminal of the fifth capacitor, a control terminal of the twenty-second transistor receives the pulse amplitude modulation scanning signal, and a second terminal of the twenty-second transistor is coupled to the second terminal of the twenty-first transistor; and A twenty-third transistor, wherein a first terminal of the twenty-third transistor is coupled to the first terminal of the fifth capacitor, a control terminal of the twenty-third transistor receives the pulse width modulated scan signal, and a second terminal of the twenty-third transistor is coupled to a reset voltage.

11. The display device according to claim 1, characterized in that The ramp signal is a ramp-up signal or a ramp-down signal.

12. A display device, characterized in that: include: A pixel array, comprising a plurality of pixel units, wherein the plurality of pixel units are divided into a plurality of pixel groups, and the plurality of pixel groups are coupled to a common voltage comparator, wherein the common voltage comparator is configured to receive voltage data and a pulse width modulation scanning signal, and perform voltage programming on the voltage data according to the pulse width modulation scanning signal, wherein the plurality of pixel groups respectively receive a plurality of emission enable signals, a plurality of voltage data and a common ramp signal, and the plurality of pixel groups are respectively illuminated during a plurality of emission cycles and set during a plurality of data setting cycles according to the plurality of emission enable signals, the plurality of voltage data and the common ramp signal, The multiple data setting periods respectively corresponding to the multiple pixel groups do not overlap with each other in time.

13. The display device according to claim 12, characterized in that: A data setting period among the plurality of data setting periods corresponding to one of the plurality of transmit enable signals overlaps with a transmission period among the plurality of transmission periods corresponding to at least another one of the plurality of transmit enable signals.

14. The display device according to claim 12, characterized in that: The common ramp signal includes a plurality of sub-ramp signals, wherein a plurality of ramp periods respectively corresponding to the plurality of sub-ramp signals overlap with a data setting period and a transmission period of one of the plurality of transmission enable signals.

15. The display device according to claim 12, characterized in that: The plurality of pixel groups respectively correspond to different rows of the pixel array, and the different rows of the pixel array corresponding to different pixel groups among the plurality of pixel groups are arranged alternately and sequentially.

16. The display device according to claim 12, characterized in that: Different rows of the pixel array corresponding to different pixel groups among the plurality of pixel groups are arranged alternately but not sequentially.

17. The display device according to claim 12, characterized in that: Also includes: A current source is coupled to the pixel array and configured to supply current to the pixel array output, wherein the current source receives a pulse amplitude modulation scanning signal for voltage programming.

18. The display device according to claim 12, characterized in that: When the plurality of pixel groups are illuminated during the plurality of emission periods, the plurality of pixel groups respectively receive a pulse width modulated scanning signal.

19. The display device according to claim 12, characterized in that: The plurality of pixel groups are coupled to a common current source.

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