Optical network terminal

Abstract

The present application discloses an optical network terminal, comprising: a MAC chip and a PHY chip. The PHY chip comprises: a downlink port and a register, and the register stores the output rate of the PHY chip. The MAC chip is provided with an uplink port, which is connected to the optical line terminal. The interface configuration module is used to obtain the output rate of the PHY chip and the input rate of the PHY chip. When the input rate of the PHY chip is greater than the output rate of the PHY chip, the input rate of the PHY chip is configured to be equal to the output rate of the PHY chip. The QOS function module queues the received data packets, sends the first part of the data packets to the PHY chip, and sends the last part of the data packets to the data cache module, transmits the high-priority data stream to the PHY chip, and discards the low-priority data stream, thereby effectively avoiding the disordered loss of data packets.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an optical network terminal. Background Art

[0002] An optical network terminal (ONT) is a network device that modulates and demodulates optical signals into other protocol signals over optical fiber. It is a relay transmission device for large-scale local area networks (LANs), metropolitan area networks (MANs), and wide area networks (WANs).

[0003] A single-port optical network terminal has a downlink port and an uplink port, where the downlink port is connected to the user terminal and the uplink port is connected to the optical line terminal. Usually, when the rate of the uplink port is higher than the rate of the downlink port, the downstream data flow from the optical line terminal exceeds the rate of the downlink port, which will cause congestion and cause disordered loss of data packets. Summary of the Invention

[0004] The present application provides an optical network terminal to solve the problem of disorderly loss of data packets caused by congestion of downstream data flows from an OLT.

[0005] In order to solve the above technical problems, the embodiments of the present application disclose the following technical solutions:

[0006] The embodiment of the present application discloses an optical network terminal, comprising: a MAC chip and a PHY chip;

[0007] The PHY chip includes:

[0008] Downlink port, connected to the user terminal;

[0009] A register, used to store the output rate of the PHY chip;

[0010] The MAC chip includes:

[0011] Uplink port, connected to the optical line terminal;

[0012] A MAC protocol port connected to the PHY chip; the input rate of the PHY chip is equal to the output rate of the MAC chip;

[0013] an interface configuration module, configured to obtain an output rate of the PHY chip and an input rate of the PHY chip, and when the input rate of the PHY chip is greater than the output rate of the PHY chip, configure the input rate of the PHY chip to be equal to the output rate of the PHY chip;

[0014] Data cache module;

[0015] The QOS function module is used to queue the received data packets, send a portion of the data packets that are sorted first to the PHY chip, and send a portion of the data packets that are sorted later to the data cache module.

[0016] Beneficial effects of this application:

[0017] The present application discloses an optical network terminal, comprising: a MAC chip and a PHY chip. The PHY chip comprises: a downlink port and a register, and the register stores the output rate of the PHY chip. The MAC chip is provided with an uplink port, which is connected to the optical line terminal. The interface configuration module is used to obtain the output rate of the PHY chip and the input rate of the PHY chip. When the input rate of the PHY chip is greater than the output rate of the PHY chip, the input rate of the PHY chip is configured to be equal to the output rate of the PHY chip. The QOS function module queues the received data packets, sends the first part of the data packets to the PHY chip, and sends the last part of the data packets to the data cache module, transmits the high-priority data stream to the PHY chip, and discards the low-priority data stream, thereby effectively avoiding the disordered loss of data packets. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0019] Figure 1 is a connection relationship diagram of an optical network terminal according to some embodiments;

[0020] Figure 2 A connection relationship of an optical network terminal according to some embodiments Figure 2 ;

[0021] Figure 3 is a schematic structural diagram of an optical network terminal according to some embodiments;

[0022] Figure 4 is a communication schematic diagram of an optical network terminal according to some embodiments;

[0023] Figure 5 is a schematic diagram of a PHY chip structure according to some embodiments;

[0024] Figure 6is a schematic diagram of PHY chip communication according to some embodiments;

[0025] Figure 7 is a schematic diagram of a MAC chip structure according to some embodiments;

[0026] Figure 8 is a schematic diagram of MAC chip communication according to some embodiments;

[0027] Figure 9 is a schematic structural diagram of an optical network terminal according to some embodiments;

[0028] Figure 10 A communication diagram of an optical network terminal according to some embodiments is shown. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0030] The main application types of broadband fiber access include FTTH, FTTO, and FTTB. The user-side equipment for each application type also varies. The user-side equipment for FTTH and FTTO is used by a single user and is called an optical network terminal (ONT), commonly known as an optical modem.

[0031] Figure 1 FIG. 1 is a connection diagram of an optical communication system according to some embodiments. Figure 1 As shown, a bidirectional optical communication system is established between the remote server 1000 and the local information processing device 2000 through the optical fiber 101, the optical module 200, the optical network terminal 100 and the network cable 103.

[0032] One end of the optical fiber 101 is connected to the remote server 1000, and the other end is connected to the optical network terminal 100 through the optical module 200. One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the optical network terminal 100.

[0033] The connection between the local information processing device 2000 and the remote server 1000 is completed by the optical fiber 101 and the network cable 103 ; and the connection between the optical fiber 101 and the network cable 103 is completed by the optical module 200 and the optical network terminal 100 .

[0034] In optical module 200, the optical port is configured to connect to optical fiber 101, thereby establishing a bidirectional optical signal connection between optical module 200 and optical fiber 101; the electrical port is configured to connect to optical network terminal 100, thereby establishing a bidirectional electrical signal connection between optical module 200 and optical network terminal 100. Optical module 200 performs mutual conversion between optical and electrical signals, thereby establishing a connection between optical fiber 101 and optical network terminal 100.

[0035] The optical network terminal 100 is provided with an optical module interface 102 and a network cable interface 104. The optical module interface 102 is configured to connect to the optical module 200, thereby establishing a bidirectional electrical signal connection between the optical network terminal 100 and the optical module 200. The network cable interface 104 is configured to connect to the network cable 103, thereby establishing a bidirectional electrical signal connection between the optical network terminal 100 and the network cable 103. The connection between the optical module 200 and the network cable 103 is established through the optical network terminal 100. In addition to the optical network terminal 100, the host computer of the optical module 200 may also include an optical line terminal (OLT) and the like.

[0036] Figure 2 A connection relationship of an optical network terminal according to some embodiments Figure 2 .like Figure 2 As shown in , the optical network terminal of the present application has a downlink port and an uplink port, wherein the downlink port is connected to the user terminal, and the uplink port is connected to the OLT (optical line terminal).

[0037] The data transmission between the optical line terminal and the optical network terminal is bidirectional, and the data transmission between the user terminal and the optical network terminal is bidirectional.

[0038] User terminals include but are not limited to computers, Pads and other terminal products.

[0039] The rate determined by negotiation between the ONT and the user terminal is commonly referred to as the negotiated rate. The transmission rate between the OLT and the ONT is greater than the transmission rate between the user terminal and the ONT. For ease of description, the transmission rate between the OLT and the ONT is referred to as the first transmission rate; the transmission rate between the user terminal and the ONT is referred to as the second transmission rate, also referred to as the second transmission rate.

[0040] Typically, the first transmission rate is 2.5G, and the second transmission rate is one of 10M, 100M, 1000M, or 2.5G. When the first transmission rate is greater than the second transmission rate, such as when the first transmission rate is 2.5G and the second transmission rate is 10M, or when the first transmission rate is 2.5G and the second transmission rate is 100M, or when the first transmission rate is 2.5G and the second transmission rate is 1000M, then when data is transmitted downstream from the optical line terminal to the user terminal via the optical network terminal, congestion may occur between the optical line terminal and the user terminal, resulting in the loss of some data packets.

[0041] Figure 3 This is a schematic diagram of the structure of an optical network terminal according to some embodiments. The optical network terminal provided herein includes a MAC chip and a PHY chip, wherein the PHY chip is connected to a user terminal, and the MAC chip is connected to an optical line terminal. The PHY chip sets a downlink port to connect to the user terminal, negotiates a protocol rate, and stores the protocol rate in a register on the PHY chip.

[0042] Figure 4 This is a communication diagram of an optical network terminal according to some embodiments. A MAC chip receives data packets sent by an optical line terminal and transmits them to a PHY chip. The PHY chip then transmits the data packets to a user terminal. The MAC chip reads the second transmission rate between the PHY chip and the user terminal and the first transmission rate between the MAC chip and the optical line terminal. When the first transmission rate is greater than the second transmission rate, the MAC chip sets a third transmission rate between the MAC chip and the PHY chip to be less than or equal to the second transmission rate. After this setting, the first transmission rate between the optical line terminal and the MAC chip is greater than the communication rate between the MAC chip and the PHY chip, and signal congestion generated between the optical line terminal and the user terminal is localized at the MAC chip. The MAC chip queues received data packets based on the priority tags carried by the data packets, sending the first-ordered packets to the PHY chip and the last-ordered packets to the data buffer module. The total message length of the data packets sent to the PHY chip is less than or equal to the data length threshold corresponding to the second transmission rate. The QoS function module sends the last-ordered packets to the data buffer module, thereby preventing packet loss.

[0043] Based on the above, the MAC chip's input rate is the first transmission rate, and the MAC chip's output rate is the third transmission rate. The PHY chip's input rate is the third transmission rate, and the PHY chip's output rate is the second transmission rate. The MAC chip's output rate is equal to the PHY chip's input rate.

[0044] When it is detected that the input rate of the PHY chip is greater than the output rate of the PHY chip, the output rate of the PHY chip is set to be equal to or less than the output rate of the PHY chip. Because the output rate of the PHY chip is equal to the output rate of the MAC chip, after this setting, the input rate of the MAC chip is greater than the output rate of the MAC chip, and the signal congestion generated between the optical line terminal and the user terminal is located at the MAC chip. The MAC chip queues the received data packets according to the priority tags carried by the data packets, sending the first-ordered data packets to the PHY chip and the last-ordered data packets to the data cache module. The total message length of the data packets sent to the PHY chip is less than or equal to the data length threshold corresponding to the output rate of the MAC chip. The QOS function module sends the last-ordered data packets to the data cache module, thereby preventing data packet loss.

[0045] The MAC chip includes a rate reading module that reads the second transmission rate, i.e., the output rate, stored in a register of the PHY chip. The interface configuration module obtains the MAC chip's input rate, i.e., the first transmission rate. When the first transmission rate is greater than the second transmission rate, the interface configuration module sets the communication rate between the MAC chip and the PHY chip to be less than or equal to the second transmission rate. After this setting, the first transmission rate between the optical line terminal and the MAC chip is greater than the communication rate between the MAC chip and the PHY chip, and signal congestion between the optical line terminal and the user terminal is localized at the MAC chip. The MAC chip also includes a Quality of Service (QoS) function module that queues received data packets based on their priority tags, sending the first-ordered packets to the PHY chip and the last-ordered packets to the data cache module. The total message length of the data packets sent to the PHY chip is less than or equal to the data length threshold corresponding to the second transmission rate. The QoS function module sends the last-ordered packets to the data cache module, thus preventing packet loss.

[0046] The optical network terminal disclosed in this application has both a single uplink port and a single downlink port. The uplink port is the connection port between the optical network terminal and the optical line terminal, while the downlink port is the connection port between the optical network terminal and the user terminal. An optical network terminal with both a single uplink port and a single downlink port has only one uplink port connected to the optical line terminal and only one downlink port connected to the user terminal.

[0047] In this application, the optical network terminal includes: a protocol chip and a physical layer chip. The protocol chip is provided with a first port connected to the optical line terminal, an MDIO interface is set between the protocol chip and the physical layer chip, and the physical layer chip is provided with a first communication interface connected to the user terminal.

[0048] The protocol chip, MAC (Media Access Control) chip, resides in the lower half of the data link layer within the seven-layer OSI protocol. It is primarily responsible for controlling the physical medium connecting to the physical layer. When sending data, the MAC protocol determines whether the data can be sent. If so, it adds some control information to the data and ultimately sends the data and control information to the physical layer in a specified format. When receiving data, the MAC protocol first checks the input information and checks for transmission errors. If there are no errors, it removes the control information and sends it to the LLC layer. Ethernet MAC is defined by the IEEE-802.3 Ethernet standard.

[0049] The physical layer chip, or PHY chip, is a physical interface transceiver that implements the physical layer, including the MII / GMII (Media Independent Interface) sublayer, PCS (Physical Coding Sublayer), PMA (Physical Medium Attachment) sublayer, PMD (Physical Medium Dependent) sublayer, and MDI sublayer. The physical layer defines the electrical and optical signals, line states, clock references, data encoding, and circuits required for data transmission and reception, and provides a standard interface to data link layer devices. The physical layer chip is called a PHY. The data link layer provides addressing mechanisms, data frame construction, data error checking, transmission control, and a standard data interface to the network layer.

[0050] Figure 5 is a schematic diagram of a PHY chip structure according to some embodiments. Figure 6 FIG. 1 is a schematic diagram of a PHY chip communication according to some embodiments. Figure 5 and Figure 6 As shown in , the PHY chip is provided with a downlink port connected to the user terminal. The PHY chip is provided with a network speed negotiation module, which is connected to the user terminal through the downlink port, and obtains the second transmission rate between the PHY chip and the user terminal and stores it in a register. The PHY chip is provided with a second communication port connected to the MAC chip. The MAC chip obtains the second transmission rate stored in the register through the second communication port and sets the transmission rate between the MAC chip and the PHY chip according to the second transmission rate.

[0051] a network speed negotiation module, connected to the downlink port, to obtain a maximum input rate threshold of the user terminal and a maximum output rate threshold of the PHY chip; when the maximum input rate threshold of the user terminal is greater than or equal to the maximum output rate threshold of the PHY chip, configuring the output rate of the PHY chip to be the maximum output rate threshold of the PHY chip; when the maximum input rate threshold of the user terminal is less than the maximum output rate threshold of the PHY chip, configuring the output rate of the PHY chip to be the maximum input rate threshold of the user terminal;

[0052] Specifically, the PHY chip has a first communication interface, namely a downlink port, to which the user terminal is connected. The network rate between the PHY chip and the user terminal is negotiated through a network protocol, which is called the protocol rate. The PHY chip has a register for storing the protocol rate between the PHY chip and the user terminal. The PHY chip also has a network speed negotiation module that is connected to the first communication interface and communicates with the user terminal through the first communication interface. The module is used to obtain the maximum rate of the user terminal and determine the second transmission rate between the PHY chip and the user terminal by comparing it with the maximum rate of the PHY chip.

[0053] The PHY chip is connected to the user terminal device through a first communication interface. The PHY chip and the user terminal will use the lower of the highest rates supported by both parties as the second transmission rate. For example, the PHY chip supports the first network rate at most, such as 1000M, and the user terminal supports the second network rate at most, such as 100M. Then the second transmission rate between the PHY chip and the user terminal is the second network rate. At this time, the second transmission rate between the optical network terminal and the user terminal is the second network rate.

[0054] The PHY chip is connected to the user terminal device via a first communication interface. The PHY chip supports a maximum first network rate, and the user terminal supports a maximum second network rate. When the first network rate is greater than the second network rate, the second transmission rate between the PHY chip and the user terminal is the second network rate. The second transmission rate between the PHY chip and the user terminal is the second transmission rate.

[0055] The PHY chip is provided with a second communication interface connected to the MAC chip. The second communication interface is an MDIO interface. The MAC chip is provided with a rate reading module to read the second transmission rate set in the register of the PHY chip through the second communication interface. The PHY chip is provided with a PHY protocol interface connected to the MAC chip.

[0056] Figure 7 FIG. 1 is a schematic diagram of a MAC chip structure according to some embodiments. Figure 8 FIG. 1 is a schematic diagram of MAC chip communication according to some embodiments. Figure 7 and Figure 8 As shown in , the MAC chip further includes a rate reading module, a MAC protocol interface, a data buffer module, a QOS function module, and an interface configuration module. The interface configuration module is connected to the rate reading module and the MAC protocol interface, respectively, and configures the interface rate of the MAC protocol interface by obtaining the second transmission rate from the rate reading module.

[0057] The MAC chip sets a MAC protocol interface to connect with the PHY chip, and sets an interface configuration module to configure the MAC protocol interface rate according to the read second transmission rate.

[0058] Specifically, the rate reading module of the MAC chip reads the second transmission rate set in the register of the PHY chip through the second communication interface, and the interface configuration module configures the interface rate of the MAC protocol interface and the PHY protocol interface according to the read second transmission rate. If the second transmission rate between the PHY chip and the user terminal is the second network rate, for example, the second network rate is 100M, the interface rate of the MAC protocol interface is set to the second network rate. If the second transmission rate between the PHY chip and the user terminal is the first network rate, for example, the first network rate is 1000M, the interface rate of the MAC protocol interface is set to the first network rate.

[0059] The communication interface between the PHY chip and the MAC chip is adaptively configured based on different rates. For example, the MAC protocol interface can be an SGMII interface, which supports 10M, 100M, and 1000M rates; or a HiSGMII interface, which supports 2.5G rates.

[0060] In this application, the first transmission rate of the uplink port is 2.5G. Each time the network port of the optical network terminal is inserted into the terminal device, the second transmission rate of the network port will be read. When the second transmission rate is one of 10M, 100M, and 1000M, the protocol interface between the PHY chip and the MAC chip is set to the SGMII interface; when the second transmission rate is 2.5G, the protocol interface between the PHY chip and the MAC chip is set to the HiSGMII interface.

[0061] If the maximum interface rate of the MAC chip is lower than the maximum interface rate of the PHY chip, and the maximum interface rate of the MAC chip is lower than the second transmission rate between the optical network terminal and the user terminal, the interface rate of the MAC protocol interface and the PHY protocol interface is set to the maximum interface rate of the MAC chip. For example, if the maximum interface rate of the MAC chip is 100 Mbps, the maximum interface rate of the PHY chip is 1000 Mbps, and the second transmission rate between the optical network terminal and the user terminal is 1000 Mbps, the interface rate of the MAC protocol interface and the PHY protocol interface is the maximum interface rate of the MAC chip, 100 Mbps.

[0062] During the process of transmitting a message from the optical line terminal to the user terminal, which is also called message downlink, the first transmission rate is greater than the interface rate of the MAC protocol interface and the PHY protocol interface. The QOS function module of the MAC chip caches the low-priority data streams in the received data streams into the data cache area.

[0063] Data packets sent from the optical network terminal carry priority tags, including first, second, and third priority tags. According to the protocol, data flows with the first priority tag have a higher priority than packets with the second priority tag. The MAC chip's QOS module queues received data packets based on the priority tags they carry, prioritizing the first-ranked packets for transmission. Congested packets with the last-ranked packets are stored in the data buffer based on the difference between the first transmission rate and the protocol rate.

[0064] Furthermore, when the QOS function module of the MAC chip queues the received data packets according to the priority tags carried by the data packets, the data packets of the same priority are arranged in the order of reception time, with the data packets received earlier being sorted first and the data packets received later being sorted last.

[0065] When the first transmission rate is greater than the interface rate between the MAC protocol interface and the PHY protocol interface, the QOS function module transfers the congested data packets to the data buffer. Specifically, the QOS function module of the MAC chip queues the received data packets according to the priority tags carried by the data packets, and then preferentially transmits the data packets with the highest priority in the queue, with the total traffic volume of the preferentially transmitted data packets being less than or equal to the data length threshold corresponding to the second transmission rate.

[0066] In this application, after the protocol interface of the MAC chip sends a data packet, it feeds back the data packet sending mark to the QOS function module. The QOS function module counts the sent data packets according to the data packet sending mark. When the high-priority data packet is sent, it obtains the data packet stored in the data buffer area and sends it in order of priority.

[0067] IP QoS (Quality of Service) refers to the ability of IP networks to provide the services required by specific services across multiple underlying network technologies (MP, FR, ATM, Ethernet, SDH, MPLS, etc.). Quality of service includes transmission bandwidth, transmission delay and jitter, packet loss rate, and network resource contention.

[0068] When the total length of the data packets sent to the data cache module is greater than the storage threshold of the data cache module, some of the data packets sorted later are discarded.

[0069] If the total amount of data packets stored in the data buffer exceeds the buffer capacity, the excess packets will be discarded based on their priority and reception time. The lowest priority packets are discarded first. For packets of the same priority, packets in the earlier data buffer are discarded first.

[0070] If the total traffic in the data buffer exceeds the buffer capacity, packets are discarded in reverse order of their queue order. The lowest priority packet is discarded first. For packets of the same priority, packets in the earlier buffer are discarded first.

[0071] Figure 9 is a schematic structural diagram of an optical network terminal according to some embodiments, Figure 10 This is a communication diagram of an optical network terminal according to some embodiments. As shown in the figure, a second transmission rate is agreed upon between the PHY chip and the user terminal via a network protocol, and the second transmission rate is stored in a register of the PHY chip. When the transmission rate between the MAC chip and the optical line terminal exceeds the second transmission rate, the interface configuration module of the MAC chip configures the network speed of the MAC protocol interface to the second transmission rate. The MAC chip's QOS function module receives priority-tagged packets, sorts the received packet queues, and sends packets within the second transmission rate range to the PHY chip. Packets outside the second transmission rate range are stored in the data cache module.

[0072] The QoS function module of the MAC chip receives data packets carrying priority tags, sorts the received data packet queue, sends a portion of data packets sorted earlier to the PHY chip, and sends a portion of data packets sorted later to the data cache module. The total message length of the data packets sent to the PHY chip is less than or equal to the data length threshold corresponding to the second transmission rate.

[0073] The data packet carries a priority tag and a packet length tag, and the number of data packets allowed to be sent at the second transmission rate is calculated based on the packet length tag. Based on the packet sorting, the data packets that are ranked first and within the second transmission rate range are sent to the PHY chip. The PHY chip sends the data packet and feeds back a sent flag to the QOS function module of the MAC chip. Upon receiving a flag indicating that the data packet to be sent has been sent, i.e., receiving a sent flag for the last data packet in the data packets to be sent to the PHY chip, the QOS function module reads the data packets cached in the data cache module and forwards them to the PHY chip.

[0074] The optical network terminal disclosed in this application includes a MAC chip and a PHY chip, wherein the PHY chip is connected to a user terminal, and the MAC chip is connected to an optical line terminal. The PHY chip sets a downlink port to connect to the user terminal, negotiates a protocol rate, and stores the protocol rate in a register of the PHY chip. The MAC chip includes a rate reading module that reads a second transmission rate stored in the register of the PHY chip. An interface configuration module obtains a first transmission rate between the optical line terminal and the MAC chip. When the first transmission rate is greater than the second transmission rate, the communication rate between the MAC chip and the PHY chip is set to be less than or equal to the second transmission rate. After the setting, the first transmission rate between the optical line terminal and the MAC chip is greater than the communication rate between the MAC chip and the PHY chip, and signal congestion generated between the optical line terminal and the user terminal is localized at the MAC chip. The MAC chip includes a Quality of Service (QoS) function module that queues received data packets based on the priority tags carried by the data packets, sending the first-ordered packets to the PHY chip and the last-ordered packets to the data buffer module. The total message length of the data packets sent to the PHY chip is less than or equal to the data length threshold corresponding to the second transmission rate. The QOS module sends the last-ordered packets to the data buffer module, preventing packet loss. Furthermore, upon receiving a flag indicating that a packet has been sent, i.e., upon receiving a flag indicating that the last packet in the queue has been sent to the PHY chip, the QOS module reads the packets cached in the data buffer module and forwards them to the PHY chip.

[0075] In this application, for ease of description, the downlink port of a PHY chip is the output port of the PHY chip; the second communication port of a PHY chip is the input port of the PHY chip. The MAC protocol port of a MAC chip is the output port of the MAC chip, and the uplink port is the input port of the MAC chip.

[0076] The adaptive method for an optical network terminal disclosed in this application obtains a first transmission rate for an uplink port and a second transmission rate for a downlink port. When the first transmission rate is greater than the second transmission rate, the interface rate between the MAC chip and the PHY chip is configured to the second transmission rate. The MAC chip includes a Quality of Service (QoS) function module that queues received data packets based on the priority tags carried by the packets, sending the first-ordered packets to the PHY chip and the last-ordered packets to a data cache module. The total message length of the data packets sent to the PHY chip is less than or equal to the data length threshold corresponding to the second transmission rate. The QoS function module sends the last-ordered packets to the data cache module, thereby preventing packet loss.

[0077] The self-adaptation method of an optical network terminal of the present application is applicable to an optical network terminal in which both the uplink port and the downlink port are single ports.

[0078] Furthermore, upon receiving the flag indicating that the data packet to be sent has been sent, that is, receiving the sent flag of the last data packet in the data packets to be sent to the PHY chip, the QOS function module reads the data packets cached in the data cache module and forwards them to the PHY chip.

[0079] Since the above embodiments are all described by reference in combination with other embodiments, different embodiments have the same parts, and the same and similar parts between the various embodiments in this specification can be referred to each other. No further detailed explanation is given here.

[0080] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a circuit structure, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such circuit structure, article or device. In the absence of further restrictions, the presence of an element defined by the phrase "includes a..." does not exclude the presence of other identical elements in the circuit structure, article or device comprising the element.

[0081] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the disclosure of this application. This application is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered merely as exemplary, and the true scope and spirit of the present application are indicated by the claims.

[0082] The above-described embodiments of the present application do not constitute a limitation on the scope of protection of the present application.

Claims

1. An optical network terminal, characterized in that: include: MAC chip and PHY chip; The PHY chip includes: Downlink port, connected to the user terminal; A PHY protocol interface connected to the MAC chip; A register, used to store the output rate of the downlink port; a network speed negotiation module, connected to the downlink port and the register, respectively, for performing rate negotiation between the downlink port and the user terminal, determining an output rate of the downlink port, and storing the output rate of the downlink port in the register; The MAC chip includes: Uplink port, connected to the optical line terminal; A MAC protocol interface connected to the PHY protocol interface; the input rate of the PHY protocol interface is equal to the output rate of the MAC protocol interface; A rate reading module, connected to the MAC protocol interface, for reading the output rate of the downlink port stored in the register of the PHY chip; an interface configuration module connected to the rate reading module, configured to obtain the output rate of the downlink port and the input rate of the uplink port when the message is downlink, and when the input rate of the uplink port is greater than the output rate of the downlink port, configure the interface rate of the MAC protocol interface and the interface rate of the PHY protocol interface at the data link layer to be less than the output rate of the downlink port; A data cache module, configured to store data packets from the optical line terminal; A QOS functional module is connected to the uplink port and is used to queue the received data packets according to the priority tags of the data packets when the messages are downlink, so that the MAC chip sends a portion of the data packets that are sorted first to the PHY chip at the interface rate of the MAC protocol interface after configuration, and sends a portion of the data packets that are sorted later to the data cache module. When the portion of the data packets that are sorted first is sent, the data packets stored in the data cache module are sent to the PHY chip at the interface rate of the MAC protocol interface after configuration; the PHY chip sends the data packets from the MAC chip to the user terminal.

2. The optical network terminal according to claim 1, wherein The QOS function module is further configured to obtain a data length threshold corresponding to an output rate of the downlink port; and the sum of lengths of data packets sent from the MAC chip to the PHY chip is less than the data length threshold.

3. The optical network terminal according to claim 1, wherein The network speed negotiation module is configured to obtain a maximum input rate threshold of the user terminal and a maximum output rate threshold of the downlink port; if the maximum input rate threshold of the user terminal is greater than or equal to the maximum output rate threshold of the downlink port, configure the output rate of the downlink port to be the maximum output rate threshold of the downlink port; If the maximum input rate threshold of the user terminal is less than the maximum output rate threshold of the downlink port, the output rate of the downlink port is configured to be the maximum input rate threshold of the user terminal.

4. The optical network terminal according to claim 1, characterized in that The PHY protocol interface is an MDIO interface.

5. The optical network terminal according to claim 1, characterized in that The PHY chip includes a data forwarding module, one end of the data forwarding module is connected to the PHY protocol interface, and the other end of the data forwarding module is connected to the downlink port.

6. The optical network terminal according to claim 1, characterized in that The QOS function module is further configured to receive a sent flag sent by the PHY protocol interface, obtain a data packet in the data buffer module, and send the data packet to the MAC protocol interface.

7. The optical network terminal according to claim 1, characterized in that The QOS function module is further configured to receive a sent flag sent by the PHY protocol interface, and when the input rate of the MAC chip is less than the output rate of the MAC chip, obtain the data packet in the data cache module and send the data packet to the MAC protocol interface.

8. The optical network terminal according to claim 1, characterized in that The QOS function module is further configured to discard some of the data packets that are sorted later when the total length of the data packets sent to the data cache module is greater than a storage threshold of the data cache module.

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