Page cache circuit and storage device

Abstract

This application provides a page buffer circuit and storage device. The page buffer includes: multiple registers and a page buffer; the multiple registers are respectively connected to peripheral interfaces to sequentially receive input data through the peripheral interfaces; the input data is sequentially converted into at least one data segment; the page buffer is connected to the multiple registers to write the current data segment stored in the multiple registers into the page buffer, thereby writing the input data into the page buffer in the manner of converting it into the at least one data segment. The write speed of the page buffer in this page buffer circuit is not limited by the write speed specified by the peripheral interface protocol of the peripheral interface, and the multiple registers can write the stored data into the page buffer as needed, which reduces the performance requirements for the write speed of the page buffer.

Description

Technical Field

[0001] This invention relates to the field of data caching technology, and in particular to a page cache circuit and storage device. Background Technology

[0002] Memory typically includes a page buffer, on which programming commands need to be written during operation. Generally, data is written to the page buffer through the memory's peripheral interface, such as the SPI (Serial Peripheral Interface). SPI interfaces are typically 1-wire, 2-wire, 4-wire, or 8-wire, and data transmission depends on the corresponding interface protocol. Therefore, the page buffer's write speed is significantly affected by the peripheral interface. For example, writing one byte of input data requires two external clock cycles on a common 4-wire SPI interface, while it takes only one external clock cycle on a common 8-wire SPI interface. Thus, the performance requirements for the page buffer are relatively high, and its write speed must meet the data transfer speed requirements of the peripheral interface. Summary of the Invention

[0003] The page cache circuit and storage device provided in this application aim to solve the problem that existing memory has high performance requirements for page caches, and the write speed of page caches needs to meet the data transfer speed requirements of peripheral interfaces.

[0004] To solve the above-mentioned technical problems, this application adopts the following technical solution: providing a page buffer circuit. The page buffer includes: multiple registers and a page buffer; the multiple registers are respectively connected to peripheral interfaces to sequentially receive input data through the peripheral interfaces; the input data is sequentially converted into at least one data segment; the page buffer is connected to the multiple registers to write the current data segment stored in the multiple registers into the page buffer, thereby writing the input data into the page buffer in the manner of converting it into the at least one data segment.

[0005] In one embodiment, the plurality of registers are arranged sequentially, and the current data segment received by the peripheral interface is sequentially written to the plurality of registers, wherein at least one of the plurality of registers respectively stores a portion of the current data segment.

[0006] In one embodiment, in response to each time the peripheral interface receives a current data segment, the plurality of registers are initialized, and the current data segment is received and stored sequentially; the plurality of registers write the stored current data segment to the page buffer.

[0007] In one embodiment, in response to the current data segment received by the peripheral interface being the starting data segment, any one of the plurality of registers is used as the starting register, and the starting register and the registers arranged after it sequentially receive and store the starting data segment; the plurality of registers write the stored current data segment into the page buffer.

[0008] In one embodiment, in response to the current data segment being the starting data segment, during the process of the plurality of registers writing the current data segment registered to the page buffer, data registered in registers preceding the starting register is masked, and the current data segment is written to the page buffer.

[0009] In one embodiment, in response to the current data segment received by the peripheral interface being an intermediate data segment, the plurality of registers sequentially receive and store the intermediate data segment in their order of arrangement; the plurality of registers write the stored current data segment into the page buffer.

[0010] In one embodiment, in response to the current data segment received by the peripheral interface being a tail data segment, the plurality of registers sequentially receive and register the tail data segment in the order of arrangement, and determine the register that last registers the last part of the tail data segment as the tail register; mask the data registered in the registers arranged after the tail register, and execute the writing of the current data segment to the page buffer.

[0011] In one embodiment, in response to the current data segment received by the peripheral interface being a tail data segment, the plurality of registers sequentially receive and register the tail data segment in order, and determine the register that last registers the last part of the tail data segment as the tail register; in response to the fact that the corresponding address space of the page buffer corresponding to other registers after the tail register has been occupied, the data in the corresponding address space of the page buffer is sequentially read into other registers after the tail register; and the current data segment is written into the page buffer.

[0012] In one embodiment, the write speed of the page cache is not limited by the write speed specified by the data transmission protocol of the peripheral interface.

[0013] In one embodiment, the plurality of registers write the current data segment they register into the page cache in parallel.

[0014] In one embodiment, the peripheral interface is an SPI interface.

[0015] To solve the aforementioned technical problems, another technical solution adopted in this application is to provide a storage device. This storage device includes the page cache circuitry described above.

[0016] The beneficial effects of this application's embodiments, which differ from the prior art, are as follows: The page buffer circuit provided in this application's embodiments, by setting multiple registers and connecting each register to the peripheral interface and the page buffer respectively, allows the registers to receive input data sequentially through the peripheral interface according to the peripheral interface protocol, and to sequentially segment and register the input data, thereby converting the input data into at least one data segment. The page buffer writes the current data segment registered in the multiple registers into the page buffer, thereby writing the input data into the page buffer. Specifically, by adding multiple registers, the input data is first written to multiple registers for segmented registration through the peripheral interface, and then the multiple registers write their current data segments to the page buffer. Instead of the peripheral interface directly writing to the page buffer, the page buffer's write speed is not limited by the write speed specified by the peripheral interface protocol. The peripheral interface can write data to multiple registers for registration according to the write speed (external clock cycle) specified by the peripheral interface protocol, and the multiple registers can write the registered data to the page buffer according to demand (e.g., internal clock cycle), which reduces the performance requirements for the page buffer's write speed. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the architecture of a page cache circuit provided in an embodiment of this application;

[0019] Figure 2 A schematic diagram of the architecture of a page cache circuit provided in a specific embodiment of this application;

[0020] Figure 3 A schematic diagram of the architecture of a page cache circuit provided for another specific embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application.

[0022] Explanation of reference numerals in the attached figures

[0023] Page buffer circuit 10; Register 1; First register 11; Second register 12; Third register 13; Fourth register 14; Page buffer 2; Peripheral interface 3; Write data line 4; Read data line 5. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0026] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Please see Figure 1 , Figure 1 This is a schematic diagram of the architecture of a page cache circuit provided in one embodiment of this application; in this embodiment, a page cache circuit 10 is provided. The page cache circuit 10 includes multiple registers 1 and page caches 2.

[0029] Multiple registers 1 are connected to peripheral interface 3 to receive input data sequentially through peripheral interface 3 according to the peripheral interface protocol. The input data is then segmented and registered sequentially, thereby converting the input data into a sequence consisting of at least one data segment. Peripheral interface 3 can be a Serial Peripheral Interface (SPI). Peripheral interface 3 can also be a parallel peripheral interface.

[0030] Each data segment can include one byte, two bytes, or four bytes, etc. The number of registers 1 can include two, three, four, five, six, seven, or eight, etc. The register width of each register 1 can be one bit, two bits, four bits, eight bits, or two bytes, three bytes, or four bytes, etc. The maximum data length of each data segment depends on the number of registers 1 and the register width of each register 1.

[0031] For example, taking an 8-bit data width for each register 1 as an example. If there are two registers 1, the maximum data length of each data segment can include two bytes; the two registers 1 sequentially receive two-byte data segments from peripheral interface 3 and store the two-byte data segments in these two registers 1. If there are four registers 1, the maximum data length of each data segment can include four bytes; the four registers 1 sequentially receive four-byte data segments from peripheral interface 3 and store the four-byte data segments in these four registers 1.

[0032] Of course, if the register width of each register 1 is 4 bits, then the number of register 1s must be at least two. In this case, if the number of register 1s is two, the maximum data length of each data segment can include one byte; if the number of register 1s is four, the maximum data length of each data segment can include two bytes.

[0033] Page buffer 2 is connected to multiple registers 1, so that the data of the current data segment stored in each of the multiple registers 1 is written in parallel to page buffer 2, thereby writing the input data into page buffer 2 in the form of data segments. Specifically, as shown below... Figure 1 As shown, multiple registers 1 write the data of their respective current data segments in parallel into page buffer 2. For example, if the current data segments registered in four registers 1 each consist of one byte, then all four registers 1 simultaneously write the data segments consisting of those one-byte segments, totaling four bytes, into page buffer 2 in parallel. If the current data segments registered in four registers 1 each consist of four bytes, then all four registers 1 simultaneously write the data segments consisting of those four bytes, totaling sixteen bytes, into page buffer 2 in parallel.

[0034] It should be noted that the process of each of the multiple registers 1 writing the data of the current data segment stored in it to the page buffer 2 can be specifically carried out by using a serial peripheral interface or a parallel peripheral interface to write the data of the current data segment to the page buffer 2.

[0035] Page cache 2 can be static random-access memory (SRAM). This allows the write speed of page cache 2 to be independent of the write speed limit specified by the data transfer protocol of peripheral interface 3. Alternatively, in other embodiments, page cache 2 can be dynamic random-access memory (DRAM).

[0036] In this application, by adding multiple registers 1, input data is first written in segments to multiple registers 1 for storage via peripheral interface 3. Then, the data of the current data segment stored in multiple registers 1 is written in parallel to page buffer 2. Instead of peripheral interface 3 directly writing to page buffer 2, the write speed of page buffer 2 is not limited by the write speed specified by the peripheral interface data transmission protocol of peripheral interface 3. Peripheral interface 3 can write data to multiple registers 1 for storage according to the write speed (external clock cycle) specified by the peripheral interface protocol. Multiple registers 1 can write the stored data to page buffer 2 as needed (e.g., internal clock cycle), which reduces the performance requirements for the write speed of page buffer 2.

[0037] For details, see Figure 2 , Figure 2 This is a schematic diagram of the page buffer circuit architecture provided in a specific embodiment of this application. Multiple registers 1 are arranged in parallel. For example, there are four registers 1, which are connected to the peripheral interface 3 and the page buffer 2 respectively, so that the four registers 1 are configured in parallel. Simultaneously, the four registers 1 are arranged in the order in which data is written, and are respectively referred to as the first register 11, the second register 12, the third register 13, and the fourth register 14 according to the order in which data is written.

[0038] Specifically, the data of the current data segment received by peripheral interface 3 is sequentially written to multiple registers 1. That is, the data of the current data segment received by peripheral interface 3 is sequentially written to multiple registers 1 in the order they are arranged. At least one of the multiple registers 1 stores a portion of the current data segment. For example, ... Figure 2As shown, there are four registers 1, which are arranged sequentially as register 11, register 12, register 13, and register 14. The data of the current data segment received by peripheral interface 3 is written into at least one of the four registers 1 in the order of their arrangement. For example, the data of the current data segment received by peripheral interface 3 is written into register 12, register 13, and register 14 in sequence; or, the data of the current data segment received by peripheral interface 3 is written into register 11, register 12, register 13, and register 14 in sequence.

[0039] In a specific embodiment, such as Figure 2 As shown, after the data of the current data segment received by the peripheral interface 3 is written to the last register 1 in the order of multiple registers 1, the current data segment stored in multiple registers 1 is written to the page buffer 2 in sequence through the write data line 4.

[0040] In a specific embodiment, in response to each time the peripheral interface 3 receives data of the current data segment, multiple registers 1 are initialized, for example, multiple registers 1 are initialized to 0xF...F (F is m bits, m is a natural number greater than 0); and the data of the current data segment written from the peripheral interface 3 is received and stored in sequence; after the data of the current data segment is written, the multiple registers 1 are connected in parallel to write the stored data of the current data segment to the page buffer 2 in sequence.

[0041] When the peripheral interface 3 stores input data into multiple registers 1, it can start from any one of the registers 1. For example, it can start from the second register 12, or from the third register 13, or from the fourth register 14, or from the first register 11, and so on.

[0042] Similarly, due to the inconsistent length of the input data, the last part of the input data is not always stored in the last register 1 (e.g., the fourth register 14 in this embodiment). Therefore, depending on the order in which the data is stored in the multiple registers 1, the input data can be divided into a start data segment, a middle data segment, and a tail data segment. The start data segment refers to the data in the input data corresponding to the first write to page buffer 2; the tail data segment refers to the data in the input data corresponding to the last write to page buffer 2; and the middle data segment refers to all the other data in the input data written to page buffer 2, excluding the start and tail data segments.

[0043] Specifically, in response to the current data segment received by peripheral interface 3 as the starting data segment, any one of the multiple registers 1 serves as the starting register. The starting register and the registers 1 arranged after it sequentially receive and store the data in the starting data segment. The data width of each register 1 is one byte. The multiple registers 1 write the stored current data segment into page buffer 2. It can be understood that if the starting register is the second register 12, then the second register 12, the third register 13, and the fourth register 14 sequentially receive and store the three bytes in the starting data segment in their order. The starting data segment consists of three bytes. Then, the multiple registers 1 write the data of the starting data segment into page buffer 2 in parallel.

[0044] In a specific embodiment, in response to the current data segment being the starting data segment and the starting register not being the first register 11, to prevent excessive data stored in registers 1 before the starting register from occupying too much address space in page buffer 2 during the process of multiple registers 1 writing the data of the current data segment stored in them to page buffer 2, the data stored in registers 1 before the starting register can be masked during the process of multiple registers 1 writing the data of the current data segment stored in them to page buffer 2, and then the data of the current data segment is written to page buffer 2. It should be noted that the method of "masking the data stored in register 1" involved in this application can be to stop supplying power to the write data line connected to register 1, so that the data stored in register 1 cannot be written to the corresponding address space in page buffer 2.

[0045] For example, if the start register is the second register 12, in order to prevent the data (i.e., the initialization data) registered in the first register 11 from occupying too much address space in the page buffer 2 during the process of writing the data of the current data segment registered in the second register 12, the third register 13, and the fourth register 14 to the page buffer 2, the data registered in the first register 11 can be masked during the process of writing the data of the current data segment registered in the second register 12, the third register 13, and the fourth register 14 to the page buffer 2, and then the data of the current data segment is written to the page buffer 2.

[0046] In response to the current data segment received by peripheral interface 3 being an intermediate data segment, multiple registers 1 sequentially receive and store the data of the intermediate data segment according to their arrangement; multiple registers 1 then write the stored data of the current data segment into page buffer 2. That is, after the data of the initial data segment is written into multiple registers 1, in response to the current data segment received by peripheral interface 3 being an intermediate data segment, the data of the intermediate data segment is written sequentially from the first register 11 to the last register 1 according to the arrangement of multiple registers 1. For example, if there are four registers 1, and the intermediate data segment includes four bytes, the four registers 1 receive the four bytes sequentially in the order of the first register 11, the second register 12, the third register 13, and the fourth register 14, with each register 1 receiving one byte and storing it. Then, the four registers 11 to 14 are connected in parallel to write the data of the intermediate data segment into page buffer 2 sequentially.

[0047] In response to the fact that the current data segment received by the peripheral interface 3 is the tail data segment, multiple registers 1 receive the data of the tail data segment in sequence according to the arrangement order and register it, and determine that the last part of the tail data segment is the last part of the tail data segment, that is, the register 1 that registers the last data of the tail data segment is the tail register; then the multiple registers 1 write the data of the tail data segment to the page buffer 2.

[0048] In one specific embodiment, in response to the fact that the corresponding address space of the page buffer 2 corresponding to other registers after the tail register is not occupied, the data of the tail data segment and the data registered in other registers after the tail register (i.e., the initialization data) are written together to the write data line 4, and then written to the page buffer 2 through the write data line 4.

[0049] It should be noted that when multiple registers 1 write the registered tail data segment to page buffer 2, in order to prevent the data registered in register 1 after the tail register from overwriting the data in the corresponding address space in page buffer 2 or excessively occupying the address space in page buffer 2, in one embodiment, during the process of multiple registers 1 writing the data of the current tail data segment to page buffer 2, the data (i.e., initialization data) registered in register 1 after the tail register can be masked, and the step of writing the current tail data segment to page buffer 2 can be performed.

[0050] To facilitate understanding, an example is given below. Assume there are four registers (1), each with a data width of one byte. The input data consists of 256 bytes. The starting register is the second register (12), so the starting data segment consists of three bytes. The middle data segment consists of 63 segments, each consisting of four bytes. The tail data segment consists of one byte. The four registers (1) receive the tail data segment in their order of arrangement; therefore, the tail register is the first register (11).

[0051] During the process of writing data from the tail data segment to page buffer 2, in order to prevent the data (i.e., initialization data) registered in the second register 12, the third register 13, and the fourth register 14 from overwriting the data in the address space corresponding to these three registers 1 in page buffer 2, the data registered in the second register 12, the third register 13, and the fourth register 14 can be masked during the process of writing the data registered in these four registers to page buffer 2.

[0052] Of course, if the tail register is the second register 12, to prevent the data (i.e., initialization data) registered in the third register 13 and the fourth register 14 from overwriting the data in the address space corresponding to these two registers 1 in page buffer 2, the data registered in the third register 13 and the fourth register 14 can be masked during the process of writing the data registered in these four registers to page buffer 2. If the tail register is the third register 13, to prevent the data registered in the fourth register 14 from overwriting the data in the address space corresponding to the fourth register 14 in page buffer 2, the data registered in the fourth register 14 can be masked during the process of writing the data registered in these four registers to page buffer 2. If the tail register is the fourth register 14, then there are no registers arranged after the tail register, and the current data segment registered in these four registers can be directly written to page buffer 2 without data masking.

[0053] In another embodiment, see Figure 3 , Figure 3This is a schematic diagram of the page buffer circuit architecture provided in another specific embodiment of this application. In response to the fact that the corresponding address space of the page buffer 2 corresponding to other registers 1 after the tail register is occupied, i.e., this part of the address space already contains original data, during the writing process of the tail data segment, in order to prevent the data registered in registers 1 after the tail register from masking the original data in the corresponding address space of the page buffer 2, after registering the data of the tail data segment to registers 1, the original data in the corresponding address space of the page buffer 2 is sequentially read to the other multiple registers 1 after the tail register; the step of writing the data registered in these four registers to the page buffer 2 is then performed. In this embodiment, it is not necessary to mask the data in the other registers 1 after the tail register.

[0054] Continuing with the example of register 11 as the tail register, the data stored in register 11 is the tail data segment, while the data stored in registers 12, 13, and 14 are the initialization data. If the corresponding address spaces of page buffer 2 corresponding to registers 12, 13, and 14 are already occupied (i.e., the original data already exists in the corresponding address spaces of page buffer 2), then before writing the tail data segment stored in register 11 to page buffer 2, the data in the corresponding address spaces of page buffer 2 can be read sequentially into registers 12, 13, and 14. Then, the current data stored in registers 11, 12, 13, and 14 is written to page buffer 2 in parallel via write data line 4 to complete the writing of the tail data segment to page buffer 2.

[0055] See Figure 4 , Figure 4 This is a schematic diagram of a storage device provided according to an embodiment of this application. In this embodiment, a storage device is provided, which includes the page cache circuit 10 provided in any of the above embodiments. The specific structure and function of the page cache circuit 10 can be found in the specific structure and function of the page cache circuit 10 provided in the above embodiments, and will not be repeated here.

[0056] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A page buffer circuit, comprising: include: Multiple registers are connected to peripheral interfaces to receive input data sequentially through the peripheral interfaces; The input data is sequentially converted into at least one data segment; A page buffer is connected to the plurality of registers to write the current data segment stored in the plurality of registers into the page buffer, thereby writing the input data into the page buffer in a manner that converts it into the at least one data segment; In response to the current data segment received by the peripheral interface being the starting data segment, any one of the plurality of registers is used as the starting register, and the starting register and the registers arranged after it sequentially receive and store the starting data segment; the plurality of registers write the stored current data segment into the page buffer.

2. The page buffer circuit according to claim 1, characterized in that, The plurality of registers are arranged in parallel in sequence, and the current data segment received by the peripheral interface is written to the plurality of registers in sequence, wherein at least one of the plurality of registers respectively stores a portion of the current data segment.

3. The page buffer circuit according to claim 2, characterized in that, In response to each time the peripheral interface receives the current data segment, the plurality of registers are initialized, and the current data segment is received and stored sequentially; The multiple registers write the current data segment stored therein to the page cache.

4. The page buffer circuit according to claim 1, characterized in that, In response to the current data segment being the starting data segment, during the process of the plurality of registers writing the current data segment registered to the page buffer, the data registered in the registers preceding the starting register is masked, and the current data segment is written to the page buffer.

5. The page buffer circuit according to claim 3, characterized in that, In response to the fact that the current data segment received by the peripheral interface is an intermediate data segment, the plurality of registers receive and store the intermediate data segment in sequence according to their arrangement order; The multiple registers write the current data segment stored therein into the page cache.

6. The page buffer circuit according to claim 3, characterized in that, In response to the fact that the current data segment received by the peripheral interface is the tail data segment, the plurality of registers receive and store the tail data segment in sequence according to the arrangement order, and determine the register that stores the last part of the tail data segment as the tail register. The data stored in the registers following the tail register is masked, and the current data segment is written to the page buffer.

7. The page buffer circuit according to claim 3, characterized in that, In response to the fact that the current data segment received by the peripheral interface is the tail data segment, the plurality of registers receive and store the tail data segment in sequence according to the arrangement order, and determine the register that stores the last part of the tail data segment as the tail register. In response to the fact that the corresponding address space of the page buffer in other registers after the tail register has been occupied, the data in the corresponding address space of the page buffer is read sequentially into other registers after the tail register; and the current data segment is written into the page buffer.

8. The page buffer circuit of claim 1, wherein, The write speed of the page cache is not limited by the write speed specified by the data transmission protocol of the peripheral interface.

9. The page buffer circuit according to claim 1, characterized in that, The multiple registers write the current data segment they register into the page cache in parallel.

10. The page buffer circuit of claim 1, wherein, The peripheral interface is an SPI interface.

11. A storage device, characterized in that, Includes the page buffer circuit as described in any one of claims 1-10.

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