TSV micro-module structure and preparation process

Abstract

The application discloses a TSV micro module structure and a preparation process, which comprises the following steps: micro-bump connection is adopted between two adjacent TSV silicon substrates; an FC chip is arranged on the upper end surface of the topmost TSV silicon substrate; BGA solder balls are arranged on the lower end surface of the bottommost TSV silicon substrate; a thermal sensor is arranged inside the FC chip; the upper end surface of each TSV silicon substrate is provided with a cavity, and an active chip is embedded in the cavity; an organic film is arranged between the cavity and the active chip; and a TTC chip is arranged in the middle of the lower end surface of the bottommost TSV silicon substrate. The working junction temperature of each layer of active chip can be calculated according to the temperature measured by the top thermal sensor, the temperature measured by the bottom TTC chip and the thermal resistance data of the micro module structure. The application does not change the original TSV module structure, does not affect the original design, is convenient to integrate, has simple and reliable mounting process, has good process compatibility, and adopts surface soldering between the thermal sensor and the TSV module, so that the contact thermal resistance is small and the temperature measurement is more accurate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated design and packaging technology, and relates to a TSV micro-module structure and fabrication process. Background Technology

[0002] Micro-modules are a semiconductor packaging and integration technology that involves stacking multiple chips in a package to form an independent multi-chip micro-module.

[0003] Chinese patent CN112802834A, entitled "A Four-Layer SiP Based on Silicon Interconnection and Its Fabrication Method," proposes a four-layer three-dimensional stacked structure based on wire-bounding technology, such as... Figure 1 As shown, a spacer 14 is provided between adjacent bare chips 11, and they are connected by bonding leads 15. This method has the following problems: Due to the height limitation of the bonding leads 15, the thickness of the spacer 14 used in the stacking is generally around 500μm, and silicon wafers or ceramic wafers are generally used as stacking spacers. The use of spacer 14 increases the thermal resistance between bare chips 11; in addition, thermal testing equipment is not integrated in this stacking structure, so the junction temperature of the bare chip 1 during operation cannot be known.

[0004] Chinese patent CN111668195A proposes a stacked structure and method based on adhesive curing. Figure 2 As shown. This solution is similar to the one described above, except that the use of adhesive can slightly reduce the height between the bare chips 11. However, due to the lower thermal conductivity of the adhesive itself, the thermal resistance is greater. Similarly, this stacking structure does not integrate thermal testing equipment, and the junction temperature of the bare chips 11 cannot be known, which is not convenient for system thermal management.

[0005] Another novel stacking method is a stacking structure based on TSV technology. It uses a TSV silicon substrate 6 to embed an active chip 2 and reconstruct it into a new chip. The new chip achieves interlayer interconnection through microbumps 3, which is a bonding wire-free structure.

[0006] The first two stacking structures achieve three-dimensional stacking by adding spacers or encapsulating adhesive between bare chips. Since it is difficult to further optimize the height of the bonding wires, the thickness of the spacers and encapsulating adhesive is relatively large, generally 300um to 500um. On the other hand, since the spacers and encapsulating adhesive themselves have low thermal conductivity, the thermal resistance between bare chips is very large under these two structures, which does not enable the stacking of high-power chips.

[0007] The latter structure overcomes the problems of high thermal resistance and large fan-out area of ​​the two aforementioned bonding and stacking structures. However, this structure stacks multiple chips, resulting in a heat flux density several times that of the original monolithic circuit. Under the same ambient temperature, the chip junction temperature is higher, and without temperature detection and thermal management, excessive junction temperature may lead to functional abnormalities or even burnout. Therefore, there is an urgent need for a TSV micromodule capable of acquiring the module's junction temperature. Summary of the Invention

[0008] The purpose of this invention is to solve the problems in the prior art and provide a TSV micro-module structure and fabrication process, which can calculate the working junction temperature of each active chip layer by measuring the temperature through the top thermal sensor and the bottom TTC chip and the thermal resistance data of the TSV micro-module structure.

[0009] To achieve the above objectives, the present invention employs the following technical solution:

[0010] A TSV micro-module structure includes: an FC chip, an active chip, microbumps, an organic thin film, a TSV silicon substrate, BGA solder balls, a thermal sensor, and a TTC chip;

[0011] The adjacent TSV silicon substrates are connected by microbumps; the FC chip is located on the top surface of the top TSV silicon substrate; the BGA solder balls are located on the bottom surface of the bottom TSV silicon substrate; and the thermal sensor is located inside the FC chip.

[0012] Each TSV silicon substrate has a cavity on its upper surface, in which an active chip is embedded; an organic thin film is laid between the cavity and the active chip; and a TTC chip is located in the middle of the lower surface of the bottom TSV silicon substrate.

[0013] A further improvement of the present invention is that:

[0014] TTC chips are obtained from TTC wafers;

[0015] Specifically, TTC wafers are used to obtain TTC chips:

[0016] The TTC wafer is processed by RDL to form surface mount pads. The processed TTC wafer is then thinned and diced to obtain the TTC chip.

[0017] The space between two adjacent TSV silicon substrates is a layer space, which is filled with epoxy resin.

[0018] The distance from the bottom surface of each TSV silicon substrate to the top of the microbumps on the top surface of the next TSV silicon substrate is no more than 60 μm.

[0019] BGA solder ball diameter should be no less than 250um.

[0020] FC chips are either large-scale active chips or IPD passive chips.

[0021] Multiple microbumps are set in the hierarchical space between the top TSV silicon substrate and the FC chip to connect the top TSV silicon substrate and the FC chip.

[0022] The distance from the edge of the TTC chip to the edge of the BGA solder ball should be no less than 300µm.

[0023] A fabrication process for a TSV micromodule structure includes:

[0024] A cavity is set on a TSV silicon substrate, and an organic thin film and an active chip are sequentially deposited on the cavity of the TSV silicon substrate.

[0025] TSV silicon substrates with embedded organic thin films and active chips are vertically stacked and welded using microbumps, and epoxy adhesive is used to fill the gaps between the microbumps of the TSV silicon substrates.

[0026] The FC chip is placed on the top surface of the top TSV silicon substrate; BGA solder balls and TTC chips are placed on the bottom TSV silicon substrate.

[0027] BGA solder balls and TTC chips are laid on the bottom TSV silicon substrate, specifically as follows:

[0028] RDL processing is performed on the TTC wafer to form surface mount pads; the processed TTC wafer is then thinned and diced to obtain the TTC chip.

[0029] High-temperature solder is sprayed onto the bottom surface of the TSV silicon substrate and the pads of the TTC chip to attach the TTC chip; a laser ball-mounting process is used to place BGA balls on the bottom surface of the TSV silicon substrate; and the TSV micromodule is cleaned.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] This invention places the FC chip on the top surface of the top TSV silicon substrate, with micro-bumps connecting adjacent TSV silicon substrates. The thermal sensor is located inside the FC chip, and the TTC chip is placed in the middle of the bottom surface of the bottom TSV silicon substrate. This invention does not alter the original TSV module structure, requiring only a small area at the bottom for the TTC chip, thus not affecting the original design and facilitating integration. The mounting process is simple and reliable, does not change the original TSV module process flow, and has good process compatibility. The thermal sensor operates within a temperature range of -55℃ to 150℃, supporting applications in automotive, military, and other fields. The TTC chip offers high temperature resolution, good linearity, and high temperature measurement accuracy.

[0032] Furthermore, the thermal sensor and the TSV module are surface-mount soldered together, resulting in low contact thermal resistance and more accurate temperature measurement. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a diagram of a SiP structure based on a four-layer 3D stacked silicon interposer.

[0035] Figure 2 This is a diagram of a stacked structure based on adhesive curing.

[0036] Figure 3 This is a schematic diagram of the TSV micromodule structure.

[0037] Among them, 1-FC chip, 2-active chip, 3-microbump, 4-layer space, 5-organic thin film, 6-TSV silicon substrate, 7-BGA solder ball, 8-thermal sensor, 9-TTC chip; 11-bare chip, 14-pad, 15-bonding wire. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0040] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0041] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0043] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0044] The present invention will now be described in further detail with reference to the accompanying drawings:

[0045] See Figure 3 This invention discloses a TSV micro-module structure, including: FC chip 1, active chip 2, microbumps 3, organic thin film 5, TSV silicon substrate 6, BGA solder balls 7, thermal sensor 8 and TTC chip 9.

[0046] The adjacent TSV silicon substrates 6 are connected by microbumps 3; the FC chip 1 is set on the upper surface of the top TSV silicon substrate 6; the BGA solder ball 7 is set on the lower surface of the bottom TSV silicon substrate 6; the thermal sensor 8 is set inside the FC chip 1.

[0047] Each TSV silicon substrate 6 has a cavity on its upper surface, and an active chip 2 is embedded in the cavity; an organic thin film 5 is laid between the cavity and the active chip 2; and a TTC chip 9 is located in the middle of the lower surface of the bottom TSV silicon substrate 6.

[0048] The TTC chip 9 is obtained from TTC wafers; specifically, the TTC chip 9 is obtained from TTC wafers as follows:

[0049] The TTC wafer is processed by RDL to form surface mount pads. The processed TTC wafer is then thinned and diced to obtain the TTC chip 9.

[0050] Between two adjacent TSV silicon substrates 6 is a layer space 4, which is filled with epoxy resin. The distance from the bottom surface of each TSV silicon substrate 6 to the top of the microbump 3 on the top surface of the next TSV silicon substrate 6 is no greater than 60 μm. The diameter of the BGA solder ball 7 is no less than 250 μm. The FC chip 1 is a high-power active chip or an IPD passive chip. The top TSV silicon substrate 6 and the FC chip 1 are connected by multiple microbumps 3. The distance from the edge of the TTC chip 9 to the edge of the BGA solder ball 7 is no less than 300 μm.

[0051] First, this invention places a TTC chip 9 beneath the entire micromodule structure. The TTC chip 9 serves as a bottom thermal sensor to provide real-time feedback on the current bottom temperature. The bottom thermal sensor body is made of silicon, with dimensions not exceeding 1mm*1mm and a thickness not exceeding 100um, and is electrically connected using surface mount soldering. The distance from the edge of the bottom thermal sensor to the edge of the BGA solder ball 7 is no less than 300um. The diameter of the external BGA solder ball 7 of the entire micromodule is no less than 250um, and the electrical signal from the bottom thermal sensor is transmitted from the external BGA solder ball 7.

[0052] As a specific implementation method, the integration process based on the TTC thermal sensor in this invention specifically includes the following steps:

[0053] The entire TSV micro-module is stacked and integrated; that is:

[0054] A cavity is formed on the TSV silicon substrate 6, and an organic thin film 5 and an active chip 2 are sequentially deposited on the cavity of the TSV silicon substrate 6.

[0055] The TSV silicon substrate 6, in which the organic thin film 5 and the active chip 2 are embedded, is vertically stacked and welded through the microbumps 3, and the gaps between the microbumps 7 between the TSV silicon substrates 6 are filled with epoxy adhesive.

[0056] The FC chip 1 is placed on the top surface of the top TSV silicon substrate 6; BGA solder balls 7 and TTC chip 9 are placed on the bottom TSV silicon substrate 6.

[0057] BGA solder balls 7 and TTC chips 9 are laid on the bottom TSV silicon substrate 6, specifically as follows:

[0058] RDL processing is performed on the TTC wafer to form surface mount pads; the processed TTC wafer is then thinned and diced to obtain TTC chip 9; the TTC wafer is thinned to below 100um;

[0059] High-temperature solder is sprayed onto the bottom surface of the TSV silicon substrate 6 and the pads of the TTC chip 9. The high-temperature solder is either high-lead or lead-free. The TTC chip 9 is then attached. During the attachment process, the soldering station is heated to securely solder the TTC chip 9.

[0060] Laser ball-planting technology was used to plant balls on the lower end surface of the bottom TSV silicon substrate 6 to obtain BGA solder balls 7; finally, the TSV micro-module was cleaned.

[0061] This invention integrates an on-chip thermal sensor 8 into the top FC chip. The FC chip is typically a high-power active chip or an IPD passive chip. The top thermal sensor provides real-time feedback of the top temperature. The top thermal sensor is integrated into the silicon chip and electrically connected to the FC chip through soldering.

[0062] Finally, the operating junction temperature of each active chip layer was calculated by measuring the temperature and thermal resistance data of the micro-module structure using the top and bottom thermal sensors respectively.

[0063] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A TSV micro-module structure, characterized in that, include: FC chip (1), active chip (2), microbump (3), organic thin film (5), TSV silicon substrate (6), BGA solder ball (7), thermal sensor (8) and TTC chip (9). The adjacent two TSV silicon substrates (6) are connected by microbumps (3); the FC chip (1) is set on the upper surface of the top TSV silicon substrate (6); the BGA solder ball (7) is set on the lower surface of the bottom TSV silicon substrate (6); the thermal sensor (8) is set inside the FC chip (1). Each TSV silicon substrate (6) has a cavity on its upper surface, in which an active chip (2) is embedded; an organic thin film (5) is laid between the cavity and the active chip (2); and a TTC chip (9) is disposed in the middle of the lower surface of the bottom TSV silicon substrate (6). The TTC chip (9) is obtained from a TTC wafer; The TTC wafer is used to obtain the TTC chip (9) specifically as follows: RDL processing is performed on the TTC wafer to form surface mount pads, and the processed TTC wafer is thinned and diced to obtain the TTC chip (9). The space between the two adjacent TSV silicon substrates (6) is a layer space (4), which is filled with epoxy adhesive; the distance from the edge of the TTC chip (9) to the edge of the BGA solder ball (7) is not less than 300um.

2. The TSV micro-module structure according to claim 1, characterized in that, The distance from the bottom surface of each TSV silicon substrate (6) to the top of the microbump (3) provided on the top surface of the next TSV silicon substrate (6) is no more than 60 μm.

3. The TSV micro-module structure according to claim 1, characterized in that, The diameter of the BGA solder ball (7) is not less than 250um.

4. The TSV micro-module structure according to claim 1, characterized in that, The FC chip (1) is a large-scale active chip or an IPD passive chip.

5. The TSV micro-module structure according to claim 3, characterized in that, Multiple microbumps (3) are provided in the hierarchical space (4) between the top TSV silicon substrate (6) and the FC chip (1) to connect the top TSV silicon substrate (6) and the FC chip (1).

6. The fabrication process of a TSV micromodule structure according to any one of claims 1 to 5, characterized in that, include: A cavity is formed on the TSV silicon substrate (6), and an organic thin film (5) and an active chip (2) are sequentially deposited on the cavity of the TSV silicon substrate (6); The TSV silicon substrate (6) with embedded organic thin film (5) and active chip (2) is vertically stacked and welded through microbumps (3), and the gaps between the microbumps (7) between the TSV silicon substrates (6) are filled with epoxy adhesive. The FC chip (1) is laid on the top surface of the top TSV silicon substrate (6); BGA solder balls (7) and TTC chip (9) are laid on the bottom TSV silicon substrate (6).

7. The fabrication process of the TSV micromodule structure according to claim 6, characterized in that, BGA solder balls (7) and TTC chips (9) are laid on the bottom TSV silicon substrate (6), specifically: RDL processing is performed on the TTC wafer to form surface mount pads; and the processed TTC wafer is thinned and diced to obtain the TTC chip (9). High-temperature solder was sprayed onto the bottom surface of the TSV silicon substrate (6) and the pads of the TTC chip (9) to attach the TTC chip (9); the TTC chip (9) was attached by means of laser balling process to form BGA solder balls (7) on the bottom surface of the TSV silicon substrate (6); the TSV micro module was cleaned.

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