Charge frequency conversion circuit, conversion method and particle therapy dose monitoring device

Abstract

The present disclosure provides a charge-frequency conversion circuit and a particle therapy dose monitoring device. The conversion circuit includes: an integration circuit for integrating an input current signal to output a voltage signal; an amplitude modulation circuit for reducing the amplitude of the voltage signal to output a voltage signal with reduced amplitude; a digital-to-analog converter for outputting a threshold voltage signal; a comparator for comparing the voltage signal with reduced amplitude and the threshold voltage signal to output a pulse signal; a shaping circuit for adjusting the amplitude and pulse width of the pulse signal to output a target pulse signal; a control circuit for performing real-time compensation on the digital-to-analog converter according to the ambient temperature and the pulse frequency of the target signal, so that the digital-to-analog converter outputs a compensated threshold voltage; the compensated threshold voltage is used to be compared with the voltage signal with reduced amplitude in the next sub-cycle, so that the comparator outputs a pulse signal corresponding to the next sub-cycle according to the comparison result.

Description

Technical Field

[0001] The present disclosure relates to the technical field of particle therapy devices, and particularly to a charge-frequency conversion circuit, a conversion method, and a particle therapy dose monitoring device. Background Art

[0002] In a particle therapy device, dose monitoring is a key factor affecting the therapy system. To accurately irradiate a tumor with a dose and ensure the safety and reliability of the medical device, it is necessary to measure and monitor the irradiation dose in real time to provide important control data for doctors and physicists. Generally, in a therapy system, the span of the weak current signal output by a detector for dose monitoring can reach six orders of magnitude (ρA to μA). A charge-frequency conversion circuit converts the weak current signal into a frequency signal, and by reading the frequency signal with a counter, the irradiation dose can be quickly obtained. In order to ensure the conversion accuracy, the working frequency of the charge-frequency conversion circuit in the prior art is generally designed to be relatively low, resulting in difficulty in improving its resolution and bringing certain difficulties to the upgrade of product performance. Moreover, during the operation of the charge-frequency conversion circuit, it will span a large working ambient temperature range. Since the performance of electronic components is affected by the ambient temperature, it may cause a temperature drift problem in the circuit itself, and as the working time extends, the temperature drift problem becomes more serious and has uncertainty, and it is impossible to ensure the linearity and repeatability of the circuit conversion. Summary of the Invention

[0003] To solve the above problems in the prior art, the present disclosure provides a charge-frequency conversion circuit, a conversion method, and a particle therapy dose monitoring device, aiming to solve the technical problems such as long integration dead time, poor linearity, and no temperature drift compensation in the charge-frequency conversion circuit of the prior art.

[0004] The first aspect of the present disclosure provides a charge frequency conversion circuit, including: an integration circuit for integrating an input current signal and outputting a voltage signal; an amplitude modulation circuit connected to the integration circuit for reducing the amplitude of the voltage signal and outputting the voltage signal with reduced amplitude; a digital-to-analog converter for outputting a threshold voltage signal; a comparator having its first input terminal connected to the output terminal of the digital-to-analog converter and its second input terminal connected to the output terminal of the amplitude modulation circuit for comparing the voltage signal with reduced amplitude and the threshold voltage signal and outputting a pulse signal; a shaping circuit connected to the output terminal of the comparator for adjusting the amplitude and pulse width of the pulse signal and outputting a target pulse signal; a control circuit connected to the output terminal of the shaping circuit and the input terminal of the digital-to-analog converter for performing real-time compensation on the digital-to-analog converter according to the ambient temperature and the pulse frequency of the target signal, so that the digital-to-analog converter outputs a compensated threshold voltage; wherein the compensated threshold voltage is used to compare with the voltage signal with reduced amplitude in the next sub-cycle, so that the comparator outputs the pulse signal corresponding to the next sub-cycle according to the comparison result.

[0005] Further, the control circuit includes: an FPGA chip having its input terminal A12 connected to the output terminal of the shaping circuit, its input terminal A11 connected to the output terminal of the temperature acquisition module, and its output terminals A0 to A9 connected to the data input terminals B0 to B9 of the digital-to-analog converter for performing real-time compensation on the digital-to-analog converter according to the ambient temperature and the pulse frequency of the target pulse signal, so that the digital-to-analog converter outputs a compensated threshold voltage; a latch connected to the output terminal A10 of the FPGA chip for adjusting the integration state of the integration circuit according to the level signal TTL1 output by the FPGA chip.

[0006] Further, the integration circuit includes: a first operational amplifier U1 having its positive input terminal grounded, its negative input terminal connected to the input current terminal Iin, and its output terminal connected to the input terminal of the amplitude modulation circuit; a double-pole double-throw switch connected to the latch, one end of which is connected to the input current terminal Iin and the other end of which is connected to the negative input terminal of the first operational amplifier U1; a first capacitor C1 disposed in the double-pole double-throw switch.

[0007] Further, the double - pole double - throw switch includes: a first switch KA1, a second switch KB2, a third switch KB1, and a fourth switch KA2; wherein, the first switch KA1 and the second switch KB2 are sequentially arranged between the input current terminal Iin and the output terminal of the first operational amplifier, the third switch KB1 and the fourth switch KA2 are sequentially arranged between the negative input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1, the first switch KA1 and the fourth switch KA2 form a pair of switches and are simultaneously controlled by the first control signal output by the latch (620), the second switch KB2 and the third switch KB1 form a pair of switches and are simultaneously controlled by the second control signal output by the latch; wherein, the on - off state of the pair of switches formed by the first switch KA1 and the fourth switch KA2 is opposite to the on - off state of the pair of switches formed by the second switch KB2 and the third switch KB1.

[0008] Further, the integrating circuit further includes: a reset switch KCl, which is connected in parallel with the first capacitor C1 and is used for resetting the initial state of the charge - frequency conversion circuit.

[0009] Further, the logic unit in the FPGA chip includes a counter. When the count value of the counter reaches a threshold, the FPGA chip outputs a high - level signal, and this high - level signal is used for the latch to adjust the on - off state of the double - pole double - throw switch, so that the charge - frequency conversion circuit enters the next cycle.

[0010] Further, the logic unit further includes: a temperature compensation parameter module, a frequency compensation parameter module, and an operation module; wherein, the temperature compensation parameter module is used for performing linear fitting based on the PCB board temperature collected by the temperature acquisition module and the output frequency of the target pulse signal to obtain a temperature calibration coefficient; the frequency compensation parameter module is used for performing linear fitting based on the pulse frequency of the target pulse signal and the input current Iin to obtain a frequency calibration coefficient; the operation module is used for outputting the compensated threshold voltage in real - time according to the pulse frequency of the target pulse signal, the temperature calibration coefficient, and the frequency calibration coefficient.

[0011] The second aspect of the present disclosure provides a charge frequency conversion method, which is implemented based on the charge frequency conversion circuit provided in the first aspect of the present disclosure, and includes: inputting an input current Iin into an integration circuit, the integration circuit enters an integration working state and outputs a voltage signal; an amplitude modulation circuit reduces the amplitude of the voltage signal and outputs the voltage signal with reduced amplitude; a comparator compares the voltage signal with reduced amplitude and the threshold voltage signal output by a digital-to-analog converter, and outputs a pulse signal; a shaping circuit adjusts the amplitude and pulse width of the pulse signal and outputs a target pulse signal; a control circuit performs real-time compensation on the digital-to-analog converter according to the ambient temperature and the pulse frequency of the target signal, so that the digital-to-analog converter outputs a compensated threshold voltage; wherein, the compensated threshold voltage is used to compare with the voltage signal with reduced amplitude in the next sub-cycle, so that the comparator outputs a pulse signal corresponding to the next sub-cycle according to the comparison result.

[0012] Further, the method further includes: when the count of a counter in the control circuit reaches a threshold, the control circuit outputs a control signal to control the integration state of the integration circuit, so that the charge frequency conversion circuit enters the next integration cycle.

[0013] The third aspect of the present disclosure provides a particle therapy dose monitoring device, including: the charge frequency conversion circuit provided in the first aspect of the present disclosure, and the charge frequency conversion circuit is used to convert a current signal into a frequency signal.

[0014] The present disclosure provides a charge frequency conversion circuit, which uses a method of comparing the output voltage of an integration circuit with a continuously changing threshold voltage generated by a digital-to-analog converter (DAC) to generate an output pulse, extends the integration time, and reduces the number of charge discharges. The shaping circuit is used to precisely control the threshold voltage, and the threshold voltage output by the digital-to-analog converter is compensated in real time according to the ambient temperature and the output frequency, improving the conversion linear error of the charge frequency and achieving high-precision conversion from charge to frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more fully understand the present disclosure and its advantages, reference will now be made to the following description in conjunction with the accompanying drawings, where:

[0016] Figure 1 Schematically shows the schematic diagram of a charge frequency conversion circuit in the prior art;

[0017] Figure 2 Schematically shows the schematic diagram of a charge frequency conversion circuit according to an embodiment of the present disclosure;

[0018] Figure 3 Schematically shows the circuit diagram of a charge frequency conversion circuit according to an embodiment of the present disclosure;

[0019] Figure 4 Schematically shows the calibration principle diagram of the FPGA chip according to an embodiment of the present disclosure;

[0020] Figure 5 Schematically shows the working timing diagram of the charge-frequency conversion circuit according to an embodiment of the present disclosure;

[0021] Figure 6 Schematically shows the charge-frequency conversion linearity diagram of the charge-frequency conversion circuit according to an embodiment of the present disclosure. Detailed implementation manners

[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0023] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0024] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] During particle therapy, the treatment terminal realizes real-time monitoring of radiation dose by using a large number of dose ionization chambers, and the dose ionization chamber outputs a weak current signal. Converting the weak current signal into a pulse signal and using a counter to count the number of pulses can complete the real-time monitoring of beam intensity and dose, and then provide data for doctors and physicists to ensure the accuracy of irradiation dose. The weak current pulse signal needs to be read out after a series of front-end processing, conversion, and amplification. When processing such weak signals, attention needs to be paid to noise, interference, especially the problem of processing speed. Therefore, developing a high-precision weak current frequency conversion circuit has become an urgent problem to be solved.

[0026] Such as Figure 1The schematic diagram of a charge frequency conversion circuit in the prior art is shown. This charge frequency converter technology can basically meet the requirements of conventional dose monitoring and control. However, the following problems still exist during operation: 1) Long integration dead time: In the prior art solution, each time a pulse is output, it is discharged once, and the integration dead time is very large, affecting the linearity at different dose rates; 2) Poor linearity: In the prior art solution, the charge discharged by the integration capacitor is obtained from the current pulse generated by differentiating the control signal or the control pulse current source. If the differential signals are inconsistent or the pulse current action time is not sufficient to restore the circuit to the starting state, the charge discharged each time is not completely equal, resulting in poor linearity; 3) The circuit is prone to jamming: When the two analog switches SW1 and SW2 in the prior art solution are switched, the instantaneous noise generated affects the integration effect, and the output frequency is affected by the minimum switch switching time. When the output frequency is close to the minimum switching time, the circuit is prone to jamming and needs to be powered off to recover; 4) No temperature drift compensation device: During the operation of the charge frequency conversion circuit, it will span a large working ambient temperature range. Since the performance of electronic components is greatly affected by the ambient temperature, and there is no temperature drift compensation device in the prior art, it may cause temperature drift of the components, resulting in deterioration of linearity and stability.

[0027] With the improvement of the performance of particle therapy devices and the application of technologies such as Flash therapy, the beam intensity has increased significantly, and the current signal output by the dose monitoring detector has increased significantly. This poses higher requirements for the linearity, accuracy, and stability of the charge frequency converter in a wide measurement range.

[0028] To solve the problems existing in the prior art, the present disclosure provides a charge frequency conversion circuit. This circuit uses a method of comparing the output voltage of an integration circuit with a continuously changing threshold voltage generated by a digital-to-analog converter (DAC) to generate output pulses, extends the integration time, and reduces the number of charge discharges. An shaping circuit is used to precisely control the threshold voltage, and the threshold voltage output by the digital-to-analog converter is compensated in real time according to the ambient temperature and the output frequency, improving the conversion linear error of the charge frequency and achieving high-precision conversion from charge to frequency.

[0029] Figure 2 The schematic diagram of the charge frequency conversion circuit according to an embodiment of the present disclosure is schematically shown.

[0030] As Figure 2 shown, the charge frequency conversion circuit 100 includes: an integration circuit 10, an amplitude modulation circuit 20, a digital-to-analog converter 30, a comparator 40, a shaping circuit 50, a control circuit 60, and a temperature acquisition module 70.

[0031] In an embodiment of the present disclosure, the integrating circuit 10 is configured to perform integration processing on an input current signal Iin and output a voltage signal. Specifically, the integrating circuit 10 includes a first operational amplifier U1, a first capacitor C1, and a double-pole double-throw switch. The integrating circuit 10 converts the input current signal Iin into a voltage signal by integrating the input current signal Iin and integrating it on the first capacitor C1.

[0032] As Figure 3 shown, the positive input terminal of the first operational amplifier U1 is grounded, the negative input terminal is connected to the input current terminal Iin, and the output terminal is connected to the input terminal of the amplitude modulation circuit 20. The double-pole double-throw switch is controlled by a latch 620 to open and close, and mainly includes: a first switch KA1, a second switch KB2, a third switch KB1, and a fourth switch KA2. Among them, the first switch KA1 and the second switch KB2 are sequentially arranged between the input current terminal Iin and the output terminal of the first operational amplifier, and the third switch KB1 and the fourth switch KA2 are sequentially arranged between the negative input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1. The first switch KA1 and the fourth switch KA2 form a pair of switches and are simultaneously controlled by a first control signal output by the latch 620, and the second switch KB2 and the third switch KB1 form a pair of switches and are simultaneously controlled by a second control signal output by the latch 620. In an embodiment of the present disclosure, the opening and closing states of the pair of switches formed by the first switch KA1 and the fourth switch KA2 are opposite to the opening and closing states of the pair of switches formed by the second switch KB2 and the third switch KB1, that is: when the pair of switches formed by the first switch KA1 and the fourth switch KA2 are closed, the pair of switches formed by the second switch KB2 and the third switch KB1 are in the open state; conversely, when the pair of switches formed by the first switch KA1 and the fourth switch KA2 are open, the pair of switches formed by the second switch KB2 and the third switch KB1 are in the closed state.

[0033] In an embodiment of the present disclosure, the amplitude modulation circuit 20, which is connected to the integrating circuit 10, is configured to perform a reduction processing on the amplitude of the voltage signal and output a voltage signal after reduction.

[0034] Specifically, as Figure 3 shown, the amplitude modulation circuit 20 includes: a first resistor R1, a second resistor R2, and a second operational amplifier U2. One end of the first resistor R1 is connected to the output terminal of the first operational amplifier U1, the other end is connected to the negative input terminal of the second operational amplifier U2 and one end of the second resistor R2, the positive input terminal of the second operational amplifier U2 is grounded, and the other end of the second resistor R2 is connected to the output terminal of the second operational amplifier U2. The amplitude modulation circuit 20 attenuates the output voltage of the integrating circuit 10 by adjusting the resistance ratio of the first resistor R1 and the second resistor R2 in the circuit to ensure that the output voltage is compatible with the output voltage range of the DAC, thereby increasing the output range of the integrating circuit 10.

[0035] In an embodiment of the present disclosure, a comparator 40 has its first input terminal connected to the output terminal of a digital-to-analog converter 30 and its second input terminal connected to the output terminal of an amplitude modulation circuit 20, and is configured to compare the voltage signal after amplitude reduction and the threshold voltage signal output by the digital-to-analog converter 30, and output a pulse signal.

[0036] Specifically, as Figure 3 shown, the positive input terminal of the comparator 40 is connected to the output terminal of the second operational amplifier U2, and its negative input terminal is connected to the output terminal Vout of the digital-to-analog converter 30. The comparator 40 compares the voltage signal output by the amplitude modulation circuit 20 and the threshold voltage signal Vref output by the digital-to-analog converter 30. If the voltage at the positive input terminal is higher than the threshold voltage at the negative input terminal, the comparison circuit 40 outputs a pulse signal to a shaping circuit 50.

[0037] In an embodiment of the present disclosure, a shaping circuit 50 is connected to the output terminal of the comparator 40 and is configured to adjust the amplitude and pulse width of the pulse signal and output a target pulse signal.

[0038] Specifically, as Figure 3 shown, the shaping circuit 50 includes: a D flip-flop U4, a diode D1, a third resistor R3, and a second capacitor C2. Among them, the clock input terminal of the D flip-flop U4 is connected to the positive-phase output terminal of the comparator 40, its D terminal is connected to the high-level VCC, the clear terminal CLR is connected to one end of the third resistor R3, and the inverting output terminal is connected to the input terminal A12 of the FPGA chip 610, and the inverting output terminal is the output terminal Output of the charge-frequency conversion circuit 100. The other end of the third resistor R3 is connected to the second capacitor C2 and grounded, the other end of the second capacitor C2 is connected to the diode D1, and the other end of the diode D1 is connected to the inverting output terminal of the D flip-flop U4 In an embodiment of the present disclosure, the shaping circuit 50 is mainly configured to adjust the amplitude and pulse width of the pulse output by the comparator 40 so as to meet the actual application requirements.

[0039] In an embodiment of the present disclosure, a control circuit 60 is connected to the output terminal of the shaping circuit 50 and the input terminal of the digital-to-analog converter 30, and is configured to perform real-time compensation on the digital-to-analog converter 30 according to the ambient temperature and the pulse frequency of the target signal, so that the digital-to-analog converter 30 outputs a compensated threshold voltage. Wherein, the compensated threshold voltage is used to compare with the voltage signal after amplitude reduction in the next sub-cycle, so that the comparator outputs a pulse signal corresponding to the next sub-cycle according to the comparison result.

[0040] Specifically, as Figure 3As shown in the figure, the control circuit 60 includes: an FPGA chip 610, a latch 620, a first inverter InvA, and a second inverter InvB. The latch 620 includes a first latch latchA and a second latch latchB. The input terminal A12 of the FPGA chip 610 is connected to the output terminal Output of the shaping circuit 50, the input terminal A11 is connected to the output terminal of the temperature acquisition module 70, and the output terminals A0 - A9 are connected to the data input terminals B0 - B9 of the digital - to - analog converter 30. The FPGA chip 610 is used to perform real - time compensation on the digital - to - analog converter 30 according to the ambient temperature and the pulse frequency of the target pulse signal, so that the digital - to - analog converter 30 outputs a compensated threshold voltage. This compensated threshold voltage is used to compare with the decreased voltage signal in the next cycle, so that the comparator 40 outputs a pulse signal corresponding to the next sub - cycle according to the comparison result.

[0041] Further, the output terminal A10 of the FPGA chip 610 is connected to the E terminal of the first latch LatchA and the EN terminal of the second latch LatchB. The output terminal Q of the second latch LatchB is connected to the input terminal D of the first latch LatchA through the first inverter InvA. The output terminal Q of the first latch LatchA is connected to the input terminal D of the second latch LatchB and is connected to a double - pole double - throw switch. Among them, it is directly connected to the switch pair KB1 / KB2, and is connected to the switch pair KA1 / KA2 through the second inverter InvB, ensuring that the states of the two groups of switches in the double - pole double - throw switch are opposite at any time. The Reset terminals R of the first latch LatchA and the second latch LatchB are directly connected to the Reset key of the charge - frequency conversion circuit 100, so that the circuit is reset when the charge - frequency conversion circuit 100 is initially turned on.

[0042] According to an embodiment of the present disclosure, as Figure 4 shown, the logic units in the FPGA chip 610 include: a counter, a temperature compensation parameter module, a frequency compensation parameter module, and an operation module.

[0043] Among them, the counter is used to count the target pulse signals output within one period. For example, when the number of target pulse signals output in one period reaches a maximum threshold (such as 1024, 2048, etc.), at this time, the voltage on the integration capacitor C1 in the integration circuit 10 reaches the saturation state, and the integration capacitor C1 must be discharged. A high level is output from the output terminal A10 of the FPGA chip 610 to the latch 620, so that the latch 620 controls the states of the switch pairs KA1 / KA2 and KB1 / KB2 in the double-pole double-throw switch, discharges the integration capacitor C1, and at the same time makes the charge frequency conversion circuit 100 enter the next integration period. The temperature compensation parameter module is used to perform linear fitting based on the PCB board temperature collected by the temperature acquisition module 70 and the output frequency of the target pulse signal to obtain a temperature calibration coefficient for temperature compensation of each sub-cycle signal. The frequency compensation parameter module is used to perform linear fitting based on the pulse frequency of the target pulse signal and the input current Iin to obtain a frequency calibration coefficient. The operation module is used to output the compensated threshold voltage in real time according to the pulse frequency of the target pulse signal, the temperature calibration coefficient, and the frequency calibration coefficient.

[0044] In an embodiment of the present disclosure, the working principle of the charge frequency conversion circuit 100 is as follows: The input current signal Iin enters the integration circuit 10. At this time, KAl / KA2 is closed and KB1 / KB2 is open, and the integration circuit 10 performs integration work. The output voltage signal of the integration circuit 10 enters the amplitude modulation circuit 20. The first resistor R1 and the second resistor R2 in the amplitude modulation circuit 20 reduce the amplitude of the voltage signal output by the integration circuit 10 to ensure that the voltage range output by the amplitude modulation circuit 20 is within the threshold voltage range output by the DAC. As the output voltage of the integration circuit 10 continues to increase, the output voltage of the amplitude modulation circuit 20 also increases. When the output voltage of the amplitude modulation circuit 20 increases to the threshold voltage Vref of the comparator, the comparator U3 outputs a rising edge signal. This rising edge signal enters the shaping circuit 50 composed of the D flip-flop U4. The RC circuit composed of the third resistor R3 and the second capacitor C2 in the shaping circuit 50 adjusts the input pulse into a pulse signal with a certain width and amplitude. The shaped pulse is directly input to the output terminal Output. The FPGA chip collects the temperature of the PCB board, monitors the pulse frequency output in real time, calculates the threshold voltage in combination with the calibration coefficient, controls the threshold voltage by changing the output voltage of the DAC 30, and then changes the frequency of the output pulse to improve the circuit accuracy. As the integration circuit 10 continues to integrate, the output voltage of the DAC 30 also continues to increase. When the counter of the FPGA chip 610 reaches the maximum threshold, the output terminal A10 of the FPGA chip 610 is at a high level, and the voltage on the integration capacitor C1 in the corresponding integration circuit reaches the saturation state. At this time, the integration capacitor needs to be discharged. The first latch LatchA and the second latch LatchB generate a TTL1 signal output to the latch 620 according to the high-level signal given by the FPGA chip 610, so that the latch 620 outputs a reversed TTL2 signal to control the on-off state of the double-pole double-throw switch in the integration circuit 10, switching from KA1 / KA2 closed and KB1 / KB2 open to KA1 / KA2 open and KB1 / KB2 closed; then the integration circuit 10 continues to perform the integration work of the next cycle. In this cycle, the charge frequency conversion circuit 100 works in this way cyclically, converting the input current signal into a frequency signal.

[0045] In an embodiment of the present disclosure, the working timing diagram of the charge frequency conversion circuit 100 is as Figure 5 shown, where the stepped waveform is the output waveform of the DAC 30, and the linear waveform is the waveform output by the integration circuit 10 after attenuation by the amplitude modulation circuit 30. The integration voltage is compared with the threshold voltage multiple times within each cycle, greatly reducing the dead time duration. The fixed input charge amount ΔQ represented by each output pulse generated by the charge frequency conversion circuit 100 can be obtained from the following relational expression:

[0046] ΔQ = K × C × KnT × KnF × Vref

[0047] Among them, Vref represents the standard step voltage increase in each sub - cycle of the DAC 30; KnT represents the threshold voltage temperature calibration coefficient; KnF is the threshold voltage frequency calibration coefficient; C represents the value of the integration capacitor C1; K = R1 / R2. Then the total charge amount Q of the input signal is Q = N × ΔQ, where N is the pulse count value output by the charge - frequency conversion circuit 100 per unit time (i.e., the sub - cycle within one period). It can be seen that the input charge amount ΔQ mainly depends on the integration capacitor C1 and the value of the standard step voltage increase output by the DAC 30 each time, that is, the value of Vref. Therefore, the accuracy and linearity of the charge - frequency conversion circuit 100 can be improved through the temperature calibration coefficient and the frequency calibration coefficient.

[0048] Specifically, the threshold voltage temperature calibration coefficient KnT can be obtained in the following way: The relationship between the output frequency FT and the temperature T can be obtained through the n - order polynomial fitting formula. The specific formula can be expressed as: FT = A0 + A1×T + A2×T 2 + A3×T 3 +…+ A n ×T n . To determine the polynomial fitting order n and the coefficients of each term (A0, A1, …, A n ) in the formula, the charge - frequency conversion circuit 100 is operated within the full temperature range. At an interval of 5°C, the count value of the pulse signal is measured. The measured count value and the temperature value are curve - fitted to find the most suitable fitting order. When fitting, the temperature value can be used as the abscissa and the count value as the ordinate to obtain the temperature - count value curve, and then the least - squares method is used for fitting to find the most suitable fitting order. The temperature calibration coefficient KnT = FT 标 / FT, where FT standard is the pulse frequency at the set ambient temperature, and this set temperature is generally between 25°C and 30°C, and FT is the measured pulse frequency. The n - order polynomial fitting coefficients are stored in the temperature compensation parameter module. When the charge - frequency conversion circuit 100 operates, it calculates the threshold voltage temperature calibration coefficient KnT according to the collected ambient temperature T.

[0049] Furthermore, through the n - order polynomial fitting formula, the relationship between the pulse frequency F T标 at the set ambient temperature and the input current Iin can be obtained. The specific formula is as follows: Iin = B0 + B1×F T标 + B2×F T标 2 + B3×F T标 3 +…+ B n ×F T标 n; To determine the polynomial fitting order n and the coefficients of each term (B0, B1, …, B n ), operate the circuit at the set ambient temperature and measure the count value of the pulse signal at intervals of 10 nA within the full current range. Curve fit the measured count values with the actual input current to find the most suitable fitting order. When fitting, the actual input current Iin can be used as the abscissa and the pulse frequency F T标 as the ordinate to obtain the input current - pulse frequency curve, and then use the least squares method for fitting to find the most suitable fitting order. The frequency calibration coefficient KnF = (F T标 × ΔQ) / Iin, where Iin is the actual input current, F T标 is the current output pulse frequency, and ΔQ is the fixed charge amount represented by each pulse designed in advance. When the circuit is operating, calculate the threshold voltage frequency calibration coefficient KnF based on the collected output pulse frequency.

[0050] As Figure 4 shown, the charge - frequency conversion circuit 100 can achieve real - time calibration of the output frequency of the target pulse signal. The FPGA chip 610 can transmit the frequency and temperature information to the PC through the serial port. The PC controls the current source to output current and controls the modification of the DAC value. When the output frequency accuracy is optimal, record the value of the DAC. Calibrate point - by - point for multiple current values, and finally send the data to the FPGA chip 610 for storage. The FPGA chip 610 calculates the threshold voltage after DAC compensation based on the calibration coefficient, pulse frequency, and temperature.

[0051] The calibration results show that when the ambient temperature is 25 °C and the input current is - 30 pA to - 10 μA, the output frequency is 60 Hz to 20 MHz, and the accuracy is 1%. When the temperature is 25 ± 15 °C, the accuracy can still be controlled within 2%. As Figure 6 shown, the conversion accuracy and linearity of the charge - frequency conversion circuit 100 provided by the present disclosure are significantly improved and are closer to the theoretical values.

[0052] The charge - frequency conversion circuit provided by the present disclosure uses a method in which the output voltage of an integrating circuit is compared with the continuously changing threshold voltage generated by a digital - to - analog converter (DAC) to generate output pulses, extends the integration time, and improves the noise suppression ability. At the same time, the charge amount represented by each pulse generated within each sub - cycle is a constant, which is jointly determined by the step voltage of the DAC and the capacitance value of the integrating capacitor, improving the accuracy and linearity of the charge - frequency conversion circuit.

[0053] Another aspect of the present disclosure provides a charge frequency conversion method, which is implemented based on the charge frequency conversion circuit shown in the above embodiments, and includes: inputting an input current Iin into the integration circuit 10, the integration circuit 10 enters the integration working state and outputs a voltage signal; the amplitude modulation circuit 20 reduces the amplitude of the voltage signal and outputs the voltage signal with reduced amplitude; the comparator 40 compares the voltage signal with reduced amplitude and the threshold voltage signal output by the digital-to-analog converter 30, and outputs a pulse signal; the shaping circuit 50 adjusts the amplitude and pulse width of the pulse signal and outputs a target pulse signal; the control circuit 60 performs real-time compensation on the digital-to-analog converter 30 according to the ambient temperature and the pulse frequency of the target signal, so that the digital-to-analog converter 30 outputs a compensated threshold voltage. Wherein, the compensated threshold voltage is used to compare with the voltage signal with reduced amplitude in the next sub-cycle, so that the comparator outputs a pulse signal corresponding to the next sub-cycle according to the comparison result.

[0054] According to an embodiment of the present disclosure, the method further includes: when the counter in the control circuit 60 counts up to a threshold, the control circuit 60 outputs a control signal to control the integration state of the integration circuit 10, so that the charge frequency conversion circuit enters the next integration cycle.

[0055] It should be noted that the charge frequency conversion method is implemented based on the charge frequency conversion circuit 100 as shown in Figures 2 - 3 shown, and the charge frequency conversion circuit will not be described in detail here.

[0056] Another aspect of the present disclosure provides a particle therapy dose monitoring device, which includes: the charge frequency conversion circuit 100 shown in the above embodiments of the present disclosure, and the charge frequency conversion circuit 100 is used to convert a current signal into a frequency signal to provide stable and accurate dose monitoring for the particle therapy device.

[0057] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative or exemplary rather than restrictive.

[0058] Those skilled in the art can understand that the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ranges, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0059] Although the present disclosure has been shown and described with reference to specific exemplary embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims.

Claims

1. A charge frequency conversion circuit, characterized in that Comprising: An integrating circuit (10) for integrating an input current signal and outputting a voltage signal; An amplitude modulation circuit (20) connected to the integrating circuit (10) for reducing the amplitude of the voltage signal and outputting a voltage signal with reduced amplitude; A digital-to-analog converter (30) for outputting a threshold voltage signal; A comparator (40) having its first input terminal connected to the output terminal of the digital-to-analog converter (30) and its second input terminal connected to the output terminal of the amplitude modulation circuit (20) for comparing the voltage signal with reduced amplitude and the threshold voltage signal and outputting a pulse signal; A shaping circuit (50) connected to the output terminal of the comparator (40) for adjusting the amplitude and pulse width of the pulse signal and outputting a target pulse signal; A control circuit (60) connected to the output terminal of the shaping circuit (50) and the input terminal of the digital-to-analog converter (30) for performing real-time compensation on the digital-to-analog converter (30) according to the ambient temperature and the pulse frequency of the target pulse signal so that the digital-to-analog converter (30) outputs a compensated threshold voltage; wherein the compensated threshold voltage is used to compare with the voltage signal with reduced amplitude in the next sub-cycle so that the comparator outputs the pulse signal corresponding to the next sub-cycle according to the comparison result.

2. The charge frequency conversion circuit according to claim 1, wherein The control circuit (60) includes: An FPGA chip (610) having its input terminal A12 connected to the output terminal of the shaping circuit (50), its input terminal A11 connected to the output terminal of a temperature acquisition module (70), and its output terminals A0 - A9 connected to the data input terminals B0 - B9 of the digital-to-analog converter (30) for performing real-time compensation on the digital-to-analog converter (30) according to the ambient temperature and the pulse frequency of the target pulse signal so that the digital-to-analog converter (30) outputs a compensated threshold voltage; A latch (620) connected to the output terminal A10 of the FPGA chip (610) for adjusting the integration state of the integrating circuit (10) according to the level signal TTL1 output by the FPGA chip (610).

3. The charge frequency conversion circuit according to claim 2, wherein The integrating circuit (10) includes: A first operational amplifier U1 having its non-inverting input terminal grounded, its inverting input terminal connected to the input current terminal Iin, and its output terminal connected to the input terminal of the amplitude modulation circuit (20); A double-pole double-throw switch connected to the latch (620) having one end connected to the input current terminal Iin and the other end connected to the inverting input terminal of the first operational amplifier U1; A first capacitor C1 disposed in the double-pole double-throw switch.

4. The charge frequency conversion circuit according to claim 3, wherein The double-pole double-throw switch includes: A first switch KA1, a second switch KB2, a third switch KB1, and a fourth switch KA2; Among them, the first switch KA1 and the second switch KB2 are sequentially arranged between the input current terminal Iin and the output terminal of the first operational amplifier. The third switch KB1 and the fourth switch KA2 are sequentially arranged between the negative input terminal and the output terminal of the first operational amplifier U1. The first switch KA1 and the fourth switch KA2 form a pair of switches and are simultaneously controlled by the first control signal output by the latch (620). The second switch KB2 and the third switch KB1 form a pair of switches and are simultaneously controlled by the second control signal output by the latch (620). Among them, the on-off states of the pair of switches formed by the first switch KA1 and the fourth switch KA2 are opposite to the on-off states of the pair of switches formed by the second switch KB2 and the third switch KB1.

5. The charge frequency conversion circuit according to claim 3, wherein The integration circuit (10) further includes: A reset switch KC1, which is connected in parallel with the first capacitor C1 and is used to reset the initial state of the charge frequency conversion circuit.

6. The charge frequency conversion circuit according to claim 3, wherein The logic unit in the FPGA chip (610) includes a counter. When the count value of the counter reaches a threshold, the FPGA chip (610) outputs a high-level signal, and this high-level signal is used for the latch (620) to adjust the on-off state of the double-pole double-throw switch, so that the charge frequency conversion circuit enters the next cycle.

7. The charge frequency conversion circuit according to claim 6, wherein The logic unit further includes: A temperature compensation parameter module, a frequency compensation parameter module, and an operation module; among them, The temperature compensation parameter module is used to perform linear fitting based on the PCB board temperature collected by the temperature acquisition module (70) and the output frequency of the target pulse signal to obtain a temperature calibration coefficient; The frequency compensation parameter module is used to perform linear fitting based on the pulse frequency of the target pulse signal and the input current Iin to obtain a frequency calibration coefficient; The operation module is used to output the compensated threshold voltage in real time according to the pulse frequency of the target pulse signal, the temperature calibration coefficient, and the frequency calibration coefficient.

8. A charge frequency conversion method, characterized in that This method is implemented based on the charge frequency conversion circuit according to any one of claims 1 to 7, and includes: Input an input current Iin into the integration circuit (10), and the integration circuit (10) enters the integration working state and outputs a voltage signal; The amplitude modulation circuit (20) reduces the amplitude of the voltage signal and outputs the voltage signal with reduced amplitude; The comparator (40) compares the voltage signal with reduced amplitude and the threshold voltage signal output by the digital-to-analog converter (30) and outputs a pulse signal; The shaping circuit (50) adjusts the amplitude and pulse width of the pulse signal and outputs a target pulse signal; The control circuit (60) performs real-time compensation on the digital-to-analog converter (30) according to the ambient temperature and the pulse frequency of the target pulse signal, so that the digital-to-analog converter (30) outputs a compensated threshold voltage; wherein, the compensated threshold voltage is used to compare with the reduced voltage signal in the next sub-cycle, so that the comparator outputs the pulse signal corresponding to the next sub-cycle according to the comparison result.

9. The charge frequency conversion method according to claim 8, characterized in that The method further includes: When the counter in the control circuit (60) counts up to a threshold, the control circuit (60) outputs a control signal to control the integration state of the integration circuit (10), so that the charge-frequency conversion circuit enters the next integration period.

10. A particle therapy dose monitoring device, characterized in that, Comprising: The charge-frequency conversion circuit according to any one of claims 1 to 7, which is configured to convert a current signal into a frequency signal.

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