A Multi-Boundary Adaptive Clock Recovery Method and System for Controlling Delay Jitter

Abstract

The present invention discloses a multi-boundary adaptive clock recovery system and method for controlling delay jitter. The system includes: a data encapsulation module, a switching network, a clock recovery module, and a data decapsulation module. Among them, the data encapsulation module is used to encapsulate the serial bit stream into a payload packet in units of N bytes at the TDM data entrance, add an Ethernet header, and transmit it to the switching network. The switching network is used to connect the data encapsulation module to the clock recovery module. The clock recovery module sets a start threshold through the packet length setting and selects an adaptive clock recovery boundary value, which can effectively control the jitter interval of the clock recovery buffer, and achieve stable control of the data transmission delay and fast convergence of the data delay jitter control during the adaptive clock recovery process.

Description

Technical Field

[0001] The present invention belongs to the technical field of adaptive clock recovery, and in particular relates to a multi-boundary adaptive clock recovery system and method for controlling delay jitter. Background Art

[0002] To transparently transmit TDM data in packet-switched networks or packet transmission channels and achieve high-precision, co-frequency clock recovery, the industry has developed TOE (ToE Over TDM) technology. While TOE focuses on co-frequency clock recovery, it does not provide bounded control over the latency jitter of the recovered TDM data. Traditional packet-switched networks inevitably experience latency fluctuations in service transmission due to factors such as queue buffering and port congestion. This results in variable data lengths in the adaptive buffer. Furthermore, adaptive buffer clock recovery requires constant adjustment of the output clock frequency, which can significantly vary the buffer data length. When the adaptive buffer clock is in a slow adjustment mode, the recovered clock is slower than the source clock frequency, leading to a larger buffer size. Due to the increased buffer data backlog, the output time of the data lags behind the source time. When the adaptive buffer clock is in a fast adjustment mode, the recovered clock is faster than the source clock frequency, leading to a smaller buffer size. Due to the reduced buffer data backlog, the output time of the data lags behind the source time.

[0003] Therefore, while adaptive buffer clock recovery technology can withstand strong network fluctuations, it cannot eliminate data latency variations. Therefore, TOE functions implemented using traditional adaptive buffer clock recovery technology experience significant fluctuations in buffer depth due to inevitable network packet fluctuations and the dynamic adjustment of the recovery clock frequency. This inevitably leads to significant latency fluctuations in the output data stream.

[0004] However, in some communication networks, in order to achieve functions such as high-precision time synchronization and low-latency jitter industrial control, the delay of the communication network needs to be bidirectionally symmetrical, stable, and able to converge quickly.

[0005] Therefore, how to quickly control the end-to-end data transmission delay jitter of TOE within a bounded range and solve the problems of excessive data delay jitter and long convergence time in the traditional adaptive clock recovery process has become a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0006] In view of the above problems, the present invention provides a multi-boundary adaptive clock recovery system and method for controlling delay jitter, which can at least solve some of the above technical problems. By selecting an adaptive clock recovery boundary based on the packet length and setting a start threshold, it can effectively control the jitter range of the clock recovery buffer, achieve stable and controllable data transmission delay, and at the same time achieve fast convergence of data delay jitter control during the adaptive clock recovery process.

[0007] In a first aspect, an embodiment of the present invention provides a multi-boundary adaptive clock recovery system for controlling delay jitter. The system includes: a data encapsulation module, a switching network, a clock recovery module, and a data decapsulation module;

[0008] Among them, the data encapsulation module is used to encapsulate the serial bit stream into a payload packet in units of N bytes at the TDM data entry, add an Ethernet header, and transmit it to the switching network;

[0009] The switching network is used to connect the data encapsulation module to the clock recovery module;

[0010] The clock recovery module sets a start threshold based on the packet length of the payload packet and the depth of the message storage center of the adaptive buffer, and selects an adaptive clock recovery boundary value to control the delay jitter of the data during the adaptive clock recovery process;

[0011] The data decapsulation module is connected to the clock recovery module; the data decapsulation module is used to remove the Ethernet header information, convert the remaining N-byte payload into a serial bit stream, and synchronize the recovered clock with the data and then send it to the TDM interface.

[0012] Further, the clock recovery module is composed of a clock recovery controller, a buffer byte counter, and a multi-boundary low-jitter buffer controller;

[0013] Among them, the clock recovery controller is used to set the start threshold of clock recovery and synchronously generate three frequency output clocks; the three frequency output clocks are respectively: the center clock frequency F0, the high-speed clock frequency F1, and the low-speed clock frequency F2;

[0014] The buffer byte counter is used to count the real-time byte value M of the buffer;

[0015] The multi-boundary low-jitter buffer controller is used to select three boundary values for adaptive clock recovery from the buffer; and generate three frequency control words C0, C1, and C2 required by the clock recovery controller according to the depth of the buffer and the three boundary values;

[0016] The clock recovery controller selects a corresponding frequency output clock for clock recovery based on the frequency control word.

[0017] Further, when the data packet length in the data encapsulation module is N bytes and the packet storage center depth of the adaptive buffer is P packets, the clock recovery controller sets the start threshold of the adaptive buffer to P*N + 1 bytes; the multi-boundary low-jitter buffer controller sets the buffer adjustment intervals to three boundary values of (P + 1)*N - 6, (P + 1)*N - 4, and (P + 1)*N - 2.

[0018] Further, when the real-time byte value M of the buffer counted by the buffer byte counter is ≥ (P + 1)*N - 2 bytes, the frequency control word is C1, and the clock recovery controller sends data at the high-speed clock frequency F1;

[0019] When the real-time byte value M of the buffer counted by the buffer byte counter is = (P + 1)*N - 4 bytes, the frequency control word is C0, and the clock recovery controller sends data at the center clock frequency F0;

[0020] When the real-time byte value M of the buffer counted by the buffer byte counter is ≤ (P + 1)*N - 6 bytes, the frequency control word is C2, and the clock recovery controller sends data at the low-speed clock frequency F2.

[0021] Further, the frequency of the input clock in the data encapsulation module is F, and the frequency deviation is NPPM; the center clock frequency F0 = F, the high-speed clock frequency F1 = F0 + F0*2*NPPM, and the low-speed clock frequency F2 = F0 - F0*2*NPPM.

[0022] Further, when the input clock frequency in the data encapsulation module has a positive deviation, the multi-boundary low-jitter buffer controller controls the jitter interval of the buffer to remain between (P + 1)*N - 4 and (P + +1)*N - 2;

[0023] When the input clock frequency in the data encapsulation module has a negative deviation, the multi-boundary low-jitter buffer controller controls the jitter interval of the buffer to remain between (P + 1)*N - 6 and (P + 1)*N - 4.

[0024] Further, the multi-boundary low-jitter buffer controller can set the jitter interval of the buffer to 1 byte.

[0025] Second aspect, an embodiment of the present invention further provides a multi-boundary adaptive clock recovery method for controlling delay jitter, which is applied to the above multi-boundary adaptive clock recovery system for controlling delay jitter to achieve the control of the delay jitter of data during the adaptive clock recovery process; the method includes:

[0026] At the TDM data entry, the data encapsulation module encapsulates the serial bit stream into a payload packet in units of N bytes, adds an Ethernet header, and transmits it to the switching network;

[0027] The clock recovery controller sets the start threshold of the adaptive clock recovery according to the packet length of the payload packet and the message storage center depth of the adaptive buffer, and synchronously generates output clocks of three frequencies;

[0028] The buffer byte counter counts the real-time byte value of the buffer;

[0029] The multi-boundary low-jitter buffer controller selects three boundary values for the adaptive clock recovery from the buffer; and generates three frequency control words according to the depth of the buffer and the boundary values;

[0030] Based on the frequency control word, the clock recovery controller selects the corresponding frequency output clock for clock recovery;

[0031] The data de-encapsulation module removes the Ethernet header information, converts the remaining N-byte payload into a serial bit stream, and then synchronizes the recovered clock with the data in phase and sends it to the TDM interface.

[0032] Compared with the prior art, the beneficial effects of the present invention at least include:

[0033] 1. In the clock recovery module of the present invention, by setting the start threshold according to the packet length and selecting the adaptive clock recovery boundary, it is possible to control the delay jitter of data during the adaptive clock recovery process.

[0034] 2. Through the setting of the start threshold of the clock recovery controller in the clock recovery module of the present invention, not only can the rapid convergence of the delay jitter be achieved in cooperation with the boundary conditions, but also the influence of network jitter on the clock recovery can be reduced; the multi-boundary low-jitter buffer controller in it can effectively control the jitter range of the clock recovery buffer; the clock recovery controller can adjust the clock according to the frequency control word of the multi-boundary low-jitter buffer controller, realizing the stable and controllable data transmission delay.

[0035] 3. The present invention can also increase or decrease the jitter control range according to the actual network jitter situation and the jitter control accuracy requirement.

[0036] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention may be realized and attained by the structure particularly pointed out in the written description, claims, as well as the drawings.

[0037] The technical solution of the present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0038] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention, but do not constitute a limitation to the present invention. In the drawings:

[0039] Figure 1 It is a block diagram of a multi-boundary adaptive clock recovery system for controlling delay jitter provided by the present invention;

[0040] Figure 2 It is a flowchart of a multi-boundary adaptive clock recovery method for controlling delay jitter provided by the present invention. Detailed Embodiments

[0041] To make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention will be further described below in conjunction with specific embodiments.

[0042] The terms "comprising" and "having" in the specification and claims of the present invention and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but optionally further includes steps or modules not listed, or optionally further includes other steps or modules inherent to these processes, methods, products or devices.

[0043] In the description of the present invention, it should be noted that, unless otherwise clearly defined and limited, terms such as "set" and "connect" should be understood in a broad sense. For example, "connect" can be a communication connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0044] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0045] Referring to Figure 1 As shown, an embodiment of the present invention provides a multi-boundary adaptive clock recovery system for controlling delay jitter. The system includes: a data encapsulation module, a switching network, a clock recovery module, and a data decapsulation module;

[0046] Among them, the data encapsulation module is used to encapsulate the serial bit stream into a payload packet in units of N bytes at the TDM data entry, add an Ethernet header, and then transmit it to the switching network; the switching network is used to connect the data encapsulation module to the clock recovery module; in this embodiment, the clock recovery module sets the start threshold through the packet length of the payload packet and the depth setting of the message storage center of the adaptive buffer, and selects the adaptive clock recovery boundary value to achieve the recovery of the same-frequency clock and control the delay jitter of the data. The data decapsulation module is connected to the above clock recovery module; the data decapsulation module is used to remove the Ethernet header information, convert the remaining N-byte payload into a serial bit stream, and synchronize the recovered clock with the data and then send it to the TDM interface.

[0047] Furthermore, as Figure 1 shown, the clock recovery module is composed of a clock recovery controller, a buffer byte counter, and a multi-boundary low-jitter buffer controller;

[0048] Among them, the clock recovery controller is used to set the start threshold of clock recovery. When setting the start threshold of clock recovery, the clock recovery controller synchronously generates three kinds of frequency output clocks. The three kinds of frequency output clocks are: the center clock frequency F0, the high-speed clock frequency F1, and the low-speed clock frequency F2; the buffer byte counter counts the real-time byte value of the buffer as M;

[0049] In this embodiment, the data packet length in the data encapsulation module is N bytes, the packet storage center depth of the adaptive buffer is P, the clock recovery controller sets the start threshold of the adaptive buffer to P*N + 1 bytes. When the buffer reaches P*N + 1 bytes, clock recovery and data transmission are started. Since the data arrival rate on the network side is relatively fast, the buffer byte counter will reach (P + 1)*N bytes relatively quickly. And since 1 byte has been read and transmitted by the sender at this time, the actual buffer length is (P + 1)*N - 1 bytes. The multi-boundary low-jitter buffer controller sets the buffer adjustment intervals to three boundary values: (P + 1)*N - 6, (P + 1)*N - 4, and (P + 1)*N - 2. And it generates three frequency control words C0, C1, and C2 required by the clock recovery controller according to the buffer depth and the above three boundary values.

[0050] Based on the frequency control word, the clock recovery controller selects the corresponding frequency output clock for clock recovery. Specifically, when the real-time byte value M of the buffer counted by the buffer byte counter is ≥ (P + 1)*N - 2 bytes, the frequency control word is C1, and the clock recovery controller sends data at the high-speed clock frequency F1. When the real-time byte value M of the buffer counted by the buffer byte counter is = (P + 1)*N - 4 bytes, the frequency control word is C0, and the clock recovery controller sends data at the center clock frequency F0. When the real-time byte value M of the buffer counted by the buffer byte counter is ≤ (P + 1)*N - 6 bytes, the frequency control word is C2, and the clock recovery controller sends data at the low-speed clock frequency F2.

[0051] In this embodiment, the selection of the three boundaries and the setting of the start threshold are strongly correlated and related to the packet length. Let the packet length be N bytes, the start threshold be P*N + 1, and the boundary values be Q*N - 6 (Q = P + 1), Q*N - 4, Q*N - 2. At this time, the jitter interval is 2 bytes. It is also possible to increase or decrease the jitter control interval according to the actual network jitter situation and the jitter control accuracy requirements.

[0052] In this embodiment, let the TDM input clock be F, that is, the frequency of the input clock in the data encapsulation module is F, and the frequency deviation is NPPM. Then the three frequencies to be generated are: the center clock frequency F0 = F, the high-speed clock frequency F1 = F0 + F0*2*NPPM, and the low-speed clock frequency F2 = F0 - F0*2*NPPM.

[0053] Specifically, assume that the TDM input clock frequency is 2.048Mhz, with a frequency deviation of ±25PPM. Then F1 = 2.048Mhz + 2.048 * 2 * 25 ≈ 2.048100Mhz, and F2 = 2.048Mhz - 2.048Mhz * 2 * 2 ≈ 2.047900Mhz. If the input clock frequency has a positive deviation, the number of bytes in the buffer first reaches (P + 1) * N - 1 bytes and then is transmitted at F1. Through theoretical analysis, the transmission clock F1 can adjust approximately 6 bytes within 1S, that is, the buffer will become (P + 1) * N - 4 bytes within 500ms. At this time, after transmitting data at the central clock F0 for 300ms, the buffer will accumulate to (P + 1) * N - 2 bytes, and then the jitter range of the buffer will remain between (P + 1) * N - 4 and (P + 1) * N - 2; conversely, when the input clock frequency has a negative deviation, the jitter range of the buffer is (P + 1) * N - 6 to (P + 1) * N - 4; through the special selection of the start threshold and multiple boundaries, the jitter convergence of the buffer is achieved within 1S. In this embodiment, it can be seen that the jitter of the buffer is only two bytes. If the TDM clock is 2.048Mhz, then the limit value of the data delay jitter is approximately 8us. If the TDM clock is 8.192Mhz, then the limit value of the data delay jitter is approximately 2us.

[0054] Preferably, the multi-boundary low-jitter buffer controller can also set the jitter range of the dynamic buffer to 1 byte or even lower to further reduce the delay jitter. At the same time, according to the actual usage scenario, when the buffer jitter range control is the same, if the TDM line rate is higher, the actual delay jitter will be smaller.

[0055] Refer to Figure 2 As shown, based on the same inventive concept, an embodiment of the present invention also provides a multi-boundary adaptive clock recovery method for controlling delay jitter. Using the multi-boundary adaptive clock recovery system for controlling delay jitter in the above embodiment, the delay jitter of the data during the adaptive clock recovery process is controlled. The method includes:

[0056] S1. At the TDM data entry, the serial bit stream is encapsulated into a payload packet in units of N bytes through the data encapsulation module, and an Ethernet header is added, and it is transmitted to the switching network;

[0057] S2. The clock recovery controller sets the start threshold for the adaptive clock recovery according to the packet length of the payload packet and the message storage center depth of the adaptive buffer, and synchronously generates output clocks of three frequencies;

[0058] S3. The real-time byte value of the buffer is counted through the buffer byte counter;

[0059] S4 multi-boundary low jitter buffer controller selects three boundary values for adaptive clock recovery from the buffer; and generates three frequency control words based on the depth of the buffer and the boundary value;

[0060] S5. Based on the frequency control word, the clock recovery controller selects the corresponding frequency output clock for clock recovery;

[0061] S6. The data decapsulation module removes the Ethernet header information and converts the remaining N bytes of payload into a serial bit stream. The recovered clock is then phase-synchronized with the data and sent to the TDM interface.

[0062] The present invention provides a multi-boundary adaptive clock recovery method for controlling delay jitter, which can control data delay jitter and achieve stable and controllable data transmission delay. By setting the boundary conditions of the multi-boundary buffer controller and the start threshold in the clock recovery module, rapid convergence of data delay jitter control during the adaptive clock recovery process is achieved. Furthermore, the above method is applied to a time synchronization system, and actual testing shows that the time jitter is stabilized within the limit value. The present invention implements the function of adaptive clock recovery to control data delay jitter and has been successfully applied to communication equipment, achieving stable and controllable data transmission delay.

[0063] The embodiments of the present invention are introduced in detail above, and the principles and implementation methods of the present invention are explained. The description of the above embodiments is only used to help understand the method and core concept of the present invention.

[0064] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A multi-boundary adaptive clock recovery system for controlling delay jitter, characterized in that: The system includes: a data encapsulation module, a switching network, a clock recovery module and a data decapsulation module; The data encapsulation module is used to encapsulate the serial bit stream into a payload message in units of N bytes at the TDM data inlet, add an Ethernet header, and transmit it to the switching network; The switching network is used to connect the data encapsulation module to the clock recovery module; The clock recovery module sets a start threshold according to the packet length of the payload message and the message storage center depth of the adaptive buffer, and selects an adaptive clock recovery boundary value to achieve delay jitter control of data during the adaptive clock recovery process; The data decapsulation module is connected to the clock recovery module; the data decapsulation module is used to remove the Ethernet header information, convert the remaining N bytes of payload into a serial bit stream, and synchronize the recovered clock with the data before sending it to the TDM interface; The clock recovery module consists of a clock recovery controller, a buffer byte counter and a multi-boundary low jitter buffer controller; The clock recovery controller is used to set a start threshold for clock recovery and synchronously generate three frequency output clocks; the three frequency output clocks are: a center clock frequency F0, a high-speed clock frequency F1 and a low-speed clock frequency F2; The buffer byte counter is used to count the real-time byte value M of the buffer; The multi-boundary low-jitter buffer controller is used to select three boundary values for adaptive clock recovery from the buffer; and generate three frequency control words C0, C1 and C2 required by the clock recovery controller according to the depth of the buffer and the three boundary values; The clock recovery controller selects a corresponding frequency output clock for clock recovery based on the frequency control word; When the length of the data packet in the data encapsulation module is N bytes and the number of packets stored in the message storage center of the adaptive buffer is P, the clock recovery controller sets the start threshold of the adaptive buffer to P*N+1 bytes; the multi-boundary low-jitter buffer controller sets the buffer adjustment interval to three boundary values: (P+1)*N-6, (P+1)*N-4, and (P+1)*N-2; When the real-time byte value of the buffer area counted by the buffer area byte counter M≥(P+1)*N-2 bytes, the frequency control word is C1, and the clock recovery controller sends data at the high-speed clock frequency F1; When the buffer real-time byte value M counted by the buffer byte counter is (P+1)*N-4 bytes, the frequency control word is C0, and the clock recovery controller sends data at the central clock frequency F0; When the real-time byte value of the buffer area counted by the buffer area byte counter is M≤(P+1)*N-6 bytes, the frequency control word is C2, and the clock recovery controller sends data at the low-speed clock frequency F2.

2. The multi-boundary adaptive clock recovery system for controlling delay jitter according to claim 1, characterized in that: The frequency of the input clock in the data encapsulation module is F, and the frequency deviation is NPPM; the central clock frequency F0=F, the high-speed clock frequency F1=F0+F0*2*NPPM, and the low-speed clock frequency F2=F0-F0*2*NPPM.

3. The multi-boundary adaptive clock recovery system for controlling delay jitter according to claim 2, wherein: When the input clock frequency in the data encapsulation module is a positive deviation, the multi-boundary low jitter buffer controller controls the jitter range of the buffer to be maintained between (P+1)*N-4 and (P+1)*N-2; When the input clock frequency in the data encapsulation module has a negative deviation, the multi-boundary low jitter buffer controller controls the jitter range of the buffer to be maintained between (P+1)*N-6 and (P+1)*N-4.

4. The multi-boundary adaptive clock recovery system for controlling delay jitter according to claim 3, wherein: The multi-boundary low jitter buffer controller may set the jitter interval of the buffer to 1 byte.

5. A multi-boundary adaptive clock recovery method for controlling delay jitter, characterized in that: A multi-boundary adaptive clock recovery system for controlling delay jitter according to any one of claims 1 to 4, which controls the delay jitter of data during the adaptive clock recovery process; comprising: The data encapsulation module encapsulates the serial bit stream into a payload message in units of N bytes at the TDM data inlet, adds an Ethernet header, and transmits it to the switching network; The clock recovery controller sets a start threshold for adaptive clock recovery according to the packet length of the payload message and the message storage center depth of the adaptive buffer, and synchronously generates output clocks of three frequencies; Use the buffer byte counter to count the real-time byte value of the buffer; The multi-boundary low-jitter buffer controller selects three boundary values for adaptive clock recovery from the buffer; and generates three frequency control words according to the depth of the buffer and the boundary values; Based on the frequency control word, the clock recovery controller selects a corresponding frequency output clock for clock recovery; The data decapsulation module removes the Ethernet header information and converts the remaining N bytes of payload into a serial bit stream. The recovered clock is then phase-synchronized with the data and sent to the TDM interface.

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