An array of analog neural memory that stores synaptic weights in differential unit pairs in an artificial neural network.

Abstract

Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, with the columns arranged in physically adjacent column pairs. Within each adjacent pair, one column includes a cell storing a W+ value, and another column includes a cell storing a W- value. The adjacent cells in the adjacent pair store a differential weight W obtained according to the formula W = (W+) – (W-). In another embodiment, an analog neural memory system includes a first array of non-volatile memory cells storing W+ values ​​and a second array of non-volatile memory cells storing W- values.

Description

[0001] Priority Statement

[0002] This application claims priority to U.S. Provisional Application No. 62 / 985,826, filed March 5, 2020, entitled "Analog Neural Memory Array in Artificial Neural Network With Accurate Array Source Impedance With Adaptive Weight Mapping and Distributed Power," and U.S. Patent Application No. 16 / 987,101, filed August 6, 2020, entitled "Analog Neural Memory Array Storing Synapsis Weights In Differential Cell Pairs in Artificial Neural Network." Technical Field

[0003] Numerous embodiments of analog neural memory arrays are disclosed. In some embodiments, synaptic weights are stored in differential cell pairs within the array. In some embodiments, the power consumption from bit lines to bit lines within the array is substantially constant when reading cells. In some embodiments, weight mapping is adaptively performed to achieve optimal performance in terms of power and noise. Background Technology

[0004] Artificial neural networks mimic biological neural networks (the central nervous system of animals, especially the brain) and are used to estimate or approximate functions that can depend on a large number of inputs and are often unknown. Artificial neural networks typically consist of interconnected layers of "neurons" that exchange messages with each other.

[0005] Figure 1 An artificial neural network is illustrated, where circles represent the inputs or layers of neurons. Connections (called synapses) are indicated by arrows and have numerical weights that can be adjusted empirically. This allows the artificial neural network to adapt to its inputs and learn. Typically, an artificial neural network consists of layers with multiple inputs. There are usually one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions individually or collectively based on the data received from the synapses.

[0006] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of sufficient hardware technology. In reality, practical artificial neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e., very high computational parallelism. In principle, such complexity can be achieved using digital supercomputers or dedicated clusters of graphics processing units. However, compared to biological networks, these methods are generally energy inefficient, in addition to being costly, as biological networks consume far less energy primarily due to their ability to perform low-precision analog computations. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, most CMOS-implemented synapses are excessively large.

[0007] The applicant previously disclosed an artificial (simulated) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439 (published as U.S. Patent Publication 2017 / 0337466), which is incorporated herein by reference. The non-volatile memory array operates as a simulated neuromorphic memory. As used herein, the term "neuromorphic" refers to a circuit that implements a model of a nervous system. The simulated neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each memory cell includes: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region extends between the source and drain regions; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each memory cell is configured to store weight values ​​corresponding to a plurality of electrons on the floating gate. Multiple memory cells are configured to multiply a first plurality of inputs by stored weight values ​​to generate a first plurality of outputs. An array of memory cells arranged in this manner may be called a vector matrix multiplication (VMM) array.

[0008] Examples of different non-volatile memory cells that can be used in a VMM will now be discussed.

[0009] Non-volatile memory cells

[0010] Various types of known nonvolatile memory cells can be used in VMM arrays. For example, U.S. Patent 5,029,130 ​​(“130 Patent”), which is incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which is a type of flash memory cell. Such memory cells 210 in… Figure 2As shown in the figure. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controlling the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0011] The memory cell 210 is erased by applying a high positive voltage to the word line terminal 22 (where electrons are removed from the floating gate), which causes electrons on the floating gate 20 to tunnel from the floating gate 20 to the word line terminal 22 through the intermediate insulator via the Fowler-Nordheim tunnel.

[0012] Memory cell 210 is programmed by applying a positive voltage to word line terminal 22 and a positive voltage to source region 14 (where electrons are placed on the floating gate). Electron current flows from drain region 16 to source region 14 (source line terminal). When electrons reach the gap between word line terminal 22 and floating gate 20, they are accelerated and become excited (heated). Due to electrostatic attraction from floating gate 20, some heated electrons are injected into floating gate 20 through gate oxide.

[0013] Memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (which connects the portion of channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below the floating gate 20 is also turned on, and current flows through channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed electronically), the portion of channel region below the floating gate 20 is mostly or completely turned off, and current does not flow (or very little current) through channel region 18, which is sensed as a programmed state or a "0" state.

[0014] Table 1 shows the typical voltage ranges that can be applied to the terminals of memory cell 110 for performing read, erase, and program operations:

[0015] Table 1: Figure 2 Operation of flash memory cell 210

[0016]

[0017] "Read 1" is the read mode where the cell current is output on the bit line. "Read 2" is the read mode where the cell current is output on the source line terminal.

[0018] Figure 3 The memory cell 310 is shown, which is related to Figure 2 The memory cell 210 is similar, but with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, at a low or negative voltage (e.g., 0V / -8V) during erasure, and at a low or medium voltage (e.g., 0V / 2.5V) during reading. Other terminals are similar. Figure 2 That kind of bias.

[0019] Figure 4 A quad-gate memory cell 410 is shown, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 over a second portion of the channel region 18 (typically coupled to the word line WL), a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, meaning they are electrically connected to or can be electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0020] Table 2 shows the typical voltage ranges that can be applied to the terminals of memory cell 410 for performing read, erase, and program operations:

[0021] Table 2: Figure 4 Operation of flash memory cell 410

[0022]

[0023] "Read 1" is the read mode where the cell current is output on the bit line. "Read 2" is the read mode where the cell current is output on the source line terminal.

[0024] Figure 5 Memory cell 510 is shown, except that it does not have the erase gate EG terminal. Memory cell 510 is similar to... Figure 4 The memory cell 410 is similar. Erasure is performed by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low voltage or a negative voltage. Alternatively, erasure is performed by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are similar. Figure 4 As it is.

[0025] Figure 6 A tri-gate memory cell 610 is shown, which is another type of flash memory cell. Memory cell 610 and... Figure 4 The memory cell 410 is identical to the memory cell 610, except that the memory cell 610 does not have a separate control gate terminal. Except that no control gate bias is applied, the erase operation (erasing via the erase gate terminal) and read operation are similar. Figure 4 The programming operation is performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminals during the programming operation to compensate for the lack of a control gate bias.

[0026] Table 3 shows the typical voltage ranges that can be applied to the terminals of memory cell 610 for performing read, erase, and program operations:

[0027] Table 3: Figure 6 Operation of flash memory cell 610

[0028]

[0029] "Read 1" is the read mode where the cell current is output on the bit line. "Read 2" is the read mode where the cell current is output on the source line terminal.

[0030] Figure 7 The stacked gate memory cell 710 is shown, which is another type of flash memory cell. Memory cell 710 and... Figure 2 The memory cell 210 is similar, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (which will be coupled to the word line here) extends over the floating gate 20, separated by an insulating layer (not shown). Programming is performed using hot electron injection from the channel 18 to the channel region near the drain region 16, and erasure is performed using Fowler-Nordheim electron tunneling from the floating gate 20 to the substrate 12. Read operations operate in a similar manner to those previously described for memory cell 210.

[0031] Table 4 shows the typical voltage ranges that can be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations:

[0032] Table 4: Figure 7 Operation of flash memory cell 710

[0033]

[0034] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output at the source line terminal. Optionally, in an array comprising rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to a row of memory cells or two adjacent rows of memory cells. That is, the source line terminal can be shared by memory cells in adjacent rows.

[0035] Figure 8 A dual-split-gate memory cell 810 is shown. The dual-split-gate memory cell 810 includes a pair of memory cells (A on the left and B on the right), each memory cell including: a floating gate (FGA, FGB) 20 disposed above and insulated from a substrate 12; a control gate 28 (CGA, CGB) disposed on and insulated from the floating gate 20; an erase gate 30 (EG) disposed adjacent to and insulated from the floating gate 20 and the control gate 28, and disposed on and insulated from the substrate 12, wherein the erase gate is T-shaped, such that the apex corner of each control gate CGA, CGB faces the corresponding inner corner of the T-shaped erase gate to improve erasure efficiency; and a drain region 16 (DRA, DRB) adjacent to the floating gate 20 in the substrate (having bit line contacts 24 (BLA, BLB) connected to the corresponding drain diffusion region 16 (DRA, DRB)). The memory cells are formed as a pair of memory cells sharing a common erase gate 30. This cell design is consistent with the above reference. Figures 2-7 The memory cell under discussion differs at least in that it lacks a source region beneath the erase gate EG, a select gate (also known as a word line), and a channel region for each memory cell. Instead, a single, continuous channel region 18 extends beneath two memory cells (i.e., from the drain region 16 of one memory cell to the drain region 16 of another). To read or program a memory cell, the control gate 28 of the other memory cell is raised to a sufficient voltage to turn on the underlying channel region portion via a voltage-coupled floating gate 20 (e.g., to read or program cell A, the voltage on the FGB is raised via a voltage coupling from the CGB to turn on the channel region portion beneath the FGB). Erasure is performed using Fowler-Nordheim electron tunneling from floating gates 20A and / or 20B to the erase gate 30. Programming is performed using hot electron injection from channel 18 to floating gate 20.

[0036] Table 5 shows the typical voltage ranges that can be applied to the terminals of memory cell 810 for performing read, erase, and program operations. Cell A (FG, CGA, BLA) is selected for read, program, and erase operations.

[0037] Table 5: Figure 8 Operation of flash memory cell 810

[0038]

[0039] To utilize memory arrays comprising one of the aforementioned types of non-volatile memory cells in artificial neural networks, two modifications are made in some implementations. First, the circuitry is configured such that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as explained further below. Second, continuous (analog) programming of the memory cells is provided.

[0040] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can continuously change from a fully erased state to a fully programmed state independently with minimal interference to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can continuously change from a fully programmed state to a fully erased state, or from a fully erased state to a fully programmed state, independently with minimal interference to other memory cells. This means that the cell storage device is analog, or at least can store one discrete value from many discrete values ​​(such as 16 or 256 different values), which allows for very precise and individual tuning of all cells in the memory array, and makes the memory array ideal for storage and fine-tuning of synaptic weights in neural networks.

[0041] The methods and apparatus described herein can be applied to other non-volatile memory technologies, such as, but not limited to, FINFET split-gate flash memory or stacked-gate flash memory, SONOS (silicon-oxide-nitride-oxide-silicon with charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon with metal charge trapped in nitride), ReRAM (resistive RAM), PCM (phase-change memory), MRAM (magnetic RAM), FeRAM (ferroelectric RAM), OTP (double-layer or multi-layer programmable at one time), and CeRAM (associative electron RAM). The methods and apparatus described herein can also be applied to volatile memory technologies for neural networks, such as, but not limited to, SRAM, DRAM, and / or volatile synaptic cells.

[0042] Neural networks using non-volatile memory cell arrays

[0043] Figure 9 This conceptually illustrates a non-limiting example of a neural network using a non-volatile memory array in this embodiment. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application can also be implemented using a neural network based on a non-volatile memory array.

[0044] In this example, S0 is the input layer, which is a 32×32 pixel RGB image with 5-bit precision (i.e., three 32×32 pixel arrays, one for each color R, G, and B, with 5-bit precision per pixel). The synapse CB1 from the input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in others, and scans the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by one pixel (or more than one pixel depending on the model). Specifically, the values ​​of nine pixels in a 3×3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by appropriate weights, and after summing the output of this multiplication, a single output value is determined by the first synapse of CB1 and provided for generating one of the pixels in the feature map of layer C1. The 3×3 filter is then shifted one pixel to the right within the input layer S0 (i.e., adding a column of three pixels to the right and releasing a column of three pixels to the left), thereby providing the nine pixel values ​​from this newly positioned filter to synapse CB1, where they are multiplied by the same weights and the second single output value is determined by the associated synapse. This process continues until the 3×3 filter scans all three colors and all bits (precision values) across the entire 32×32 pixel image of the input layer S0. This process is then repeated using different sets of weights to generate different feature maps for C1 until all feature maps for layer C1 are computed.

[0045] At layer C1, in this example, there are 16 feature maps, each with 30×30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array. Therefore, in this example, layer C1 consists of a 16-layer two-dimensional array (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships; that is, the array does not have to be oriented as a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one set of sixteen different groups of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary recognition. For example, the first map (generated using the first weight recombination, shared for all scans used to generate the first map) can recognize circular edges, the second map (generated using the second weight recombination, different from the first weight recombination) can recognize rectangular edges, or the aspect ratio of certain features, and so on.

[0046] Before transitioning from layer C1 to layer S1, activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. The purpose of pooling function P1 is to average the neighboring locations (or, alternatively, use a max function) to reduce, for example, the dependence on edge locations and reduce the data size before moving to the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays, each 15×15 pixels). The synapse CB2 from layer S1 to layer C2 scans the map in layer S1 using a 4×4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12×12 feature maps. Before transitioning from layer C2 to layer S2, activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each mapping in layer S2 via a corresponding synapse in CB3. There are 64 neurons in layer C3. The synapse CB4 from layer C3 to the output layer S3 completely connects C3 to S3, meaning each neuron in layer C3 is connected to every neuron in layer S3. The output at S3 comprises 10 neurons, with the highest-output neuron determining the class. For example, this output could indicate the recognition or classification of the content of the original image.

[0047] Synapses for each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0048] Figure 10 This is a block diagram of a system that could be used for this purpose. The VMM system 32 includes non-volatile memory cells and serves as synapses between layers (such as...). Figure 6 (CB1, CB2, CB3, and CB4 in the original text). Specifically, the VMM system 32 includes a VMM array 33 (comprising non-volatile memory cells arranged in rows and columns), an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the corresponding inputs to the non-volatile memory cell array 33. The inputs to the VMM array 33 may come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the outputs of the VMM array 33. Alternatively, the bit line decoder 36 may decode the outputs of the VMM array 33.

[0049] The VMM array 33 serves two purposes. First, it stores weights that will be used by the VMM system 32. Second, the VMM array 33 efficiently multiplies the inputs with the weights stored in the VMM array 33 and adds them together at each output line (source line or bit line) to produce an output that will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient due to its in-situ memory computation.

[0050] The output of the VMM array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform the summation of both the positive and negative weight inputs to output a single value.

[0051] The output values ​​of the difference summer 38 are then summed and provided to the activation function circuit 39, which corrects the output. The activation function circuit 39 can provide a sigmoid, tanh, ReLU function, or any other nonlinear function. The corrected output value of the activation function circuit 39 becomes the next layer's (e.g., ...) Figure 8 The elements of the feature map of layer C1 are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes multiple synapses (which receive their input from existing neuron layers or from input layers such as an image database), and the summer 38 and activation function circuit 39 constitute multiple neurons.

[0052] Figure 10 The inputs to the VMM system 32 (WLx, EGx, CGx, and optional BLx and SLx) can be analog levels (e.g., current, voltage, or charge), binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to the appropriate input analog level), or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog level); the outputs can be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog level to digital bits).

[0053] Figure 11 A block diagram illustrating the use of a multi-layer VMM system 32 (here labeled VMM systems 32a, 32b, 32c, 32d, and 32e). For example... Figure 11As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be voltage or current. The first-level input D / A conversion can be accomplished by using a function or LUT (lookup table) of appropriate analog level to map Inputx to the input VMM system 32a. Input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. Input conversion can also be accomplished by a digital-to-digital pulse (D / P) converter to convert an external digital input to one or more digital pulses mapped to the input VMM system 32a.

[0054] The output generated by the input VMM system 32a is provided as input to the next VMM system (hidden level 1) 32b, which in turn generates the output provided as input to the next VMM system (hidden level 2) 32c, and so on. The layers of the VMM system 32 serve as different layers of synapses and neurons in a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d, and 32e can be an independent physical system comprising a corresponding non-volatile memory array, or multiple VMM systems can utilize different portions of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time-division multiplexed for different portions of its array or neurons. Figure 11 The example shown contains five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will recognize that this is merely exemplary, and conversely, a system may include more than two hidden layers and more than two fully connected layers.

[0055] VMM array

[0056] Figure 12 This illustrates a neuronal VMM array 1200, which is particularly suitable for... Figure 3 The memory cell 310 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1200 includes a memory array 1201 of non-volatile memory cells and a reference array 1202 of non-volatile reference memory cells (at the top of the array). Alternatively, another reference array may be placed at the bottom.

[0057] In VMM array 1200, control gate lines (such as control gate line 1203) extend vertically (therefore, reference array 1202 is orthogonal to control gate line 1203 in the row direction), and erase gate lines (such as erase gate line 1204) extend horizontally. Here, the inputs of VMM array 1200 are set on control gate lines (CG0, CG1, CG2, CG3), and the outputs of VMM array 1200 appear on source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The currents placed on each source line (SL0, SL1, respectively) perform a summation function of all currents from the memory cells connected to that particular source line.

[0058] As described herein with respect to neural networks, the non-volatile memory cells of the VMM array 1200 are preferably configured to operate in the subthreshold region.

[0059] The non-volatile reference memory cell and non-volatile memory cell described herein are biased in the subthreshold region:

[0060] Ids = Io e (Vg- Vth) / nVt = w Io e (Vg) / nVt ,

[0061] Where w = e (- Vth) / nVt

[0062] Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; and Vt is the thermal voltage = k T / q, where k is Boltzmann's constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1 + (Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at the gate voltage equal to the threshold voltage, and Io is related to (Wt / L). u Cox (n-1) Vt 2 Proportional, where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0063] For I-to-V logarithmic converters that use memory cells (such as reference memory cells or peripheral memory cells) or transistors to convert input current Ids to input voltage Vg:

[0064] Vg= n Vt log [Ids / wp Io]

[0065] Here, wp refers to the w in the reference memory cell or the peripheral memory cell.

[0066] For I-to-V logarithmic converters that use memory cells (such as reference memory cells or peripheral memory cells) or transistors to convert input current Ids to input voltage Vg:

[0067] Vg= n Vt log [Ids / wp Io]

[0068] Here, wp refers to the w in the reference memory cell or the peripheral memory cell.

[0069] For a memory array used as a VMM array for vector matrix multipliers, the output current is:

[0070] Iout = wa Io e (Vg) / nVt ,Right now

[0071] Iout = (wa / wp) Iin = W Iin

[0072] W = e (Vthp - Vtha) / nVt

[0073] Iin = wp Io e (Vg) / nVt

[0074] Here, wa = w for each memory cell in the memory array, and wp is w for the reference or peripheral memory cell.

[0075] Word lines or control gates can be used as inputs to memory cells that accept input voltages.

[0076] Alternatively, the non-volatile memory cells of the VMM array described herein can be configured to operate in a linear region:

[0077] Ids = β (Vgs-Vth) Vds; β = u Cox Wt / L,

[0078] W α (Vgs-Vth),

[0079] That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0080] Word lines, control gates, bit lines, or source lines can be used as inputs to memory cells operating in a linear region. Bit lines or source lines can be used as outputs to memory cells.

[0081] For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor or resistor operating in the linear region can be used to linearly convert the input / output current into the input / output voltage.

[0082] Alternatively, the memory cells of the VMM array described herein can be configured to operate in a saturation region:

[0083] Ids = ½ β (Vgs-Vth) 2 ;β = u Cox Wt / L

[0084] W α (Vgs-Vth) 2 That is, the weight W and (Vgs-Vth) 2 proportional

[0085] Word lines, control gates, or erase gates can be used as inputs to memory cells operating in saturation regions. Bit lines or source lines can be used as outputs of output neurons.

[0086] Alternatively, the memory cells of the VMM array described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturated regions) of each or more layers of a neural network.

[0087] Figure 13 This illustrates a neuronal VMM array 1300, which is particularly suitable for... Figure 2The memory cell 210 shown serves as a synapse between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302, arranged along the column direction of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected via a multiplexer 1314 (partially shown) through which current inputs flow. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0088] Memory array 1303 serves two purposes. First, it stores the weights used by VMM array 1300 on their respective memory cells. Second, memory array 1303 efficiently multiplies the inputs (i.e., the current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1301 and 1302 convert into input voltages to provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1303, and then sums all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input to the next layer or the final layer. By performing multiplication and addition functions, memory array 1303 eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, voltage inputs are provided on word lines (WL0, WL1, WL2, and WL3), and the output appears on the corresponding bit lines (BL0-BLN) during read (inference) operations. The current placed on each bit line in the bit lines BL0-BLN performs a summation function of the currents from all non-volatile memory cells connected to that particular bit line.

[0089] Table 6 shows the operating voltages used for the VMM array 1300. The columns in the table indicate the voltage applied to the word line for the selected cell, the word line for the unselected cell, the bit line for the selected cell, the bit line for the unselected cell, the source line for the selected cell, and the source line for the unselected cell, where FLT indicates floating, i.e., no voltage applied. The rows indicate read, erase, and program operations.

[0090] Table 6: Figure 13 Operation of VMM array 1300

[0091]

[0092] Figure 14The diagram shows a neuronal VMM array 1400, which is particularly suitable for... Figure 2 The memory cell 210 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of first non-volatile reference memory cells, and a reference array 1402 of second non-volatile reference memory cells. Reference arrays 1401 and 1402 extend in the row direction of the VMM array 1400. The VMM array is similar to VMM 1300, except that in VMM array 1400, word lines extend in the vertical direction. Here, inputs are set on word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during read operations. The current placed on each source line performs a summation function of all currents from the memory cells connected to that particular source line.

[0093] Table 7 shows the operating voltages used for the VMM array 1400. The columns in the table indicate the voltage applied to the word line for the selected cell, the word line for the unselected cell, the bit line for the selected cell, the bit line for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0094] Table 7: Figure 14 Operation of VMM array 1400

[0095]

[0096] Figure 15 This illustrates a neuronal VMM array 1500, which is particularly suitable for... Figure 3The memory cell 310 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells, a reference array 1501 of first non-volatile reference memory cells, and a reference array 1502 of second non-volatile reference memory cells. Reference arrays 1501 and 1502 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected via a multiplexer 1512 (partially shown), through which current inputs flow via BLR0, BLR1, BLR2, and BLR3. Each multiplexer 1512 includes a corresponding multiplexer 1505 and a common-source cascode transistor 1504 to ensure a constant voltage on the bit lines (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0097] Memory array 1503 serves two purposes. First, it stores weights that will be used by VMM array 1500. Second, memory array 1503 efficiently multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1501 and 1502 convert into input voltages to be provided to control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory array, and then sums all the results (cell currents) to produce an output that appears on BL0-BLN and will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly efficient. Here, the inputs are provided on control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on bit lines (BL0–BLN) during read operations. The currents placed on each bit line perform a summation function of all currents from the memory cells connected to that particular bit line.

[0098] The VMM array 1500 implements unidirectional tuning for the non-volatile memory cells in the memory array 1503. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge is reached on the floating gate. If too much charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the cell must be erased, and the sequence of partial programming operations must start again. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (this is called page erasure), and thereafter, each cell is partially programmed until the desired charge is reached on the floating gate.

[0099] Table 8 shows the operating voltages used for the VMM array 1500. The columns in the table indicate the voltage applied to the word lines for the selected cell, the word lines for the unselected cell, the bit lines for the selected cell, the bit lines for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0100] Table 8: Figure 15 Operation of VMM array 1500

[0101]

[0102] Figure 16 The diagram shows a neuronal VMM array 1600, which is particularly suitable for... Figure 3 The memory cell 310 shown serves as a synapse and component for neurons between the input layer and the next layer. The VMM array 1600 includes a memory array 1603 of non-volatile memory cells, a reference array 1601 of first non-volatile reference memory cells, and a reference array 1602 of second non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. Similar to VMM array 1600, but unlike VMM array 1600, VMM array 1600 implements bidirectional tuning, where each individual cell can be completely erased, partially programmed, and partially erased as needed to achieve the desired amount of charge on the floating gate due to the use of individual EG lines. As shown in the figure, reference arrays 1601 and 1602 convert the input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to memory cells in the row direction (through the operation of reference cells connected via diodes of multiplexer 1614). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from non-volatile memory cells connected to that particular bit line.

[0103] Table 9 shows the operating voltages used for the VMM array 1600. The columns in the table indicate the voltage applied to the word lines for the selected cell, the word lines for the unselected cell, the bit lines for the selected cell, the bit lines for the unselected cell, the control gate for the selected cell, the control gate for the unselected cell in the same sector as the selected cell, the control gate for the unselected cell in a different sector from the selected cell, the erase gate for the selected cell, the erase gate for the unselected cell, the source line for the selected cell, and the source line for the unselected cell. The rows indicate read, erase, and program operations.

[0104] Table 9: Figure 16 Operation of VMM array 1600

[0105]

[0106] The inputs of a VMM array can be analog, binary, timing pulse, or digital bits, and the outputs can be analog, binary, timing pulse, or digital bits (in which case an output ADC is needed to convert the output analog current or voltage into digital bits).

[0107] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or a hybrid memory cell (the average of two or more cells). In the case of differential cells, two memory cells are needed to implement the weight W as a differential weight (W = W+ – W-). In the case of two hybrid memory cells, two memory cells are needed to implement the weight W as the average of the two cells.

[0108] One drawback of existing non-volatile memory cell arrays is the significant difference between the array's source impedance and the source impedance along the array's output lines (such as bit lines), leading to variations in accuracy and power consumption depending on the cells selected and their states for read, program, or erase operations. Another drawback is its susceptibility to noise.

[0109] An improved VMM system with lower noise sensitivity is needed.

[0110] Further, there is a need for an improved VMM system that has a substantially constant source impedance of the array during operation (reading, programming, or erasing), regardless of which cell or cells are selected.

[0111] Further, there is a need for an improved VMM system that has substantially constant power consumption during operation (reading, programming, or erasing), regardless of which cell or cells are selected. Summary of the Invention

[0112] Numerous embodiments of analog neural memory arrays are disclosed. In some embodiments, the cells in the array have substantially constant source impedance when each memory cell is operating. In some embodiments, the power consumption from bit lines to bit lines within the array is substantially constant when a cell is read. In some embodiments, weight mapping is adaptively performed to achieve optimal performance in terms of power and noise.

[0113] In one embodiment, the analog neural memory system includes an array of non-volatile memory cells arranged in rows and columns, with the columns arranged in physically adjacent column pairs; wherein within each adjacent pair, one column in the adjacent pair includes a cell storing a W+ value, and another column in the adjacent pair includes a cell storing a W- value, wherein adjacent cells in the adjacent pair store a differential weight W obtained according to the formula W = (W+) – (W-).

[0114] In another embodiment, the analog neural memory system includes: a first array of non-volatile memory cells arranged in rows and columns, wherein the non-volatile memory cells in one or more columns store W+ values; and a second array of non-volatile memory cells arranged in rows and columns, wherein the non-volatile memory cells in one or more columns store W- values; wherein cell pairs from the first array and the second array store differential weights W obtained according to the formula W = (W+) – (W-). Attached Figure Description

[0115] Figure 1 This illustrates existing artificial neural networks.

[0116] Figure 2 This illustrates a split-gate flash memory cell from the prior art.

[0117] Figure 3 This illustrates another prior art split-gate flash memory cell.

[0118] Figure 4 This illustrates another prior art split-gate flash memory cell.

[0119] Figure 5 This illustrates another prior art split-gate flash memory cell.

[0120] Figure 6 This illustrates another prior art split-gate flash memory cell.

[0121] Figure 7 This illustrates a stacked gate flash memory cell from the prior art.

[0122] Figure 8 This shows a dual-split-gate memory cell.

[0123] Figure 9 Different layers of an exemplary artificial neural network using one or more VMM arrays are shown.

[0124] Figure 10 A VMM system including a VMM array and other circuitry is shown.

[0125] Figure 11 An exemplary artificial neural network using one or more VMM systems is shown.

[0126] Figure 12 An implementation scheme for a VMM array is shown.

[0127] Figure 13 Another implementation of the VMM array is shown.

[0128] Figure 14 Another implementation of the VMM array is shown.

[0129] Figure 15 Another implementation of the VMM array is shown.

[0130] Figure 16 Another implementation of the VMM array is shown.

[0131] Figure 17 The VMM system is shown.

[0132] Figure 18A , Figure 18B and Figure 18C This illustrates a VMM array based on existing technology.

[0133] Figure 19A , Figure 19B and Figure 19C An improved VMM array is shown.

[0134] Figure 20 Another improved VMM array is shown.

[0135] Figure 21A and Figure 21B Another improved VMM array is shown.

[0136] Figure 22 Another improved VMM array, including a redundant array, is shown.

[0137] Figure 23 Another improved VMM system is shown, which includes two VMM arrays and a shared virtual bit line switching circuit.

[0138] Figure 24 Another improved VMM system is shown.

[0139] Figure 25 An implementation scheme for the summer circuit is shown.

[0140] Figure 26 Another implementation of the summer circuit is shown.

[0141] Figure 27A Another implementation of the summer circuit is shown.

[0142] Figure 27B Another implementation of the summer circuit is shown.

[0143] Figure 28A An implementation scheme for the output circuit is shown.

[0144] Figure 28B Another implementation scheme of the output circuit is shown.

[0145] Figure 28C Another implementation scheme of the output circuit is shown.

[0146] Figure 29 The neuron output circuit is shown.

[0147] Figure 30 An implementation scheme for an analog-to-digital converter is shown.

[0148] Figure 31 Another implementation of the analog-to-digital converter is shown.

[0149] Figure 32 Another implementation of the analog-to-digital converter is shown.

[0150] Figure 33 Another implementation of the analog-to-digital converter is shown. Detailed Implementation

[0151] The artificial neural network of this invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0152] Improved VMM system implementation plan

[0153] Figure 17A block diagram of a VMM system 1700 is shown. The VMM system 1700 includes a VMM array 1701, a row decoder 1702, a high-voltage decoder 1703, a column decoder 1704, a bitline driver 1705, input circuitry 1706, output circuitry 1707, control logic unit 1708, and a bias generator 1709. The VMM system 1700 also includes a high-voltage generation block 1710, which includes a charge pump 1711, a charge pump regulator 1712, and a high-voltage level generator 1713. The VMM system 1700 also includes an algorithm controller 1714, analog circuitry 1715, control logic unit 1716, and test control logic unit 1717. The systems and methods described below can be implemented in the VMM system 1700.

[0154] Input circuitry 1706 may include circuitry such as a DAC (digital-to-analog converter), DPC (digital-to-pulse converter), DTC (digital-to-time converter), AAC (analog-to-analog converter, such as a current-to-voltage converter), PAC (pulse-to-analog level converter), or any other type of converter. Input circuitry 1706 may implement normalization, scaling, or arithmetic functions. Input circuitry 1706 may implement temperature compensation functions on the input, such as modulating the output voltage / current / time / pulse according to temperature. Input circuitry 1706 may implement activation functions, such as ReLU or sigmoid functions.

[0155] Output circuitry 1707 may include circuitry such as an ADC (analog-to-digital converter, used to convert the analog output of a neuron into digital bits), an AAC (analog-to-analog converter, such as a current-to-voltage converter), an ATC (analog-to-time converter), an APC (analog-to-pulse converter), or any other type of converter. Output circuitry 1707 may implement activation functions such as ReLU or sigmoid. Output circuitry 1707 may implement statistical normalization, regularization, up / down scaling functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shifting, logarithmic) on the neuron output, which is the output of the VMM array 1701. Output circuitry 1707 may implement temperature compensation functions on the neuron output (such as voltage / current / time / pulse) or array output (such as bitline output) to keep the power consumption of the VMM array 1701 approximately constant or to improve the accuracy of the VMM array 1701 (neuron) output, such as by keeping the VI slope approximately the same.

[0156] Figure 18AA prior art VMM system 1800 is illustrated. The VMM system 1800 includes exemplary cells 1801 and 1802, exemplary bit line switches 1803a, 1803b, 1803c, and 1803d (which connect bit lines to sensing circuitry), exemplary virtual bit line switches 1804a, 1804b, 1804c, and 1804d (which are coupled to a low bias level, such as a ground (or near-ground) level during reading), and exemplary virtual cells 1805 and 1806 (source-line pull-down cells). Bit line switch 1803a is coupled to a cell column, including cells 1801 and 1802 for storing data in the VMM system 1800. Virtual bit line switches 1804a, 1804b, 1804c, and 1804 are each coupled to a column (bit line) of cells that are virtual cells and are not used for storing data in the VMM system 1800. This virtual bit line (which may also be referred to as the source pull-down bit line) is used as a source pull-down during read operations, meaning it is used to pull the source line to a low bias level, such as ground (or near ground), through the virtual cells in the virtual bit line. It should be noted that virtual bit line switches 1804a, 1804b, 1804c, 1804 and bit line switches 1803a, 1803b, 1803c, 1803d all appear at the same end of the array, i.e., they all appear at the common end of the cell columns they are coupled to, and are therefore arranged in a single row.

[0157] One drawback of the VMM system 1800 is that the input impedance of each cell varies significantly due to the length of the electrical paths through the associated bit line switches, the cell itself, and the associated virtual bit line switches. For example, Figure 18B The electrical path is shown through bit line switch 1803, unit 1801, virtual unit 1805, and virtual bit line switch 1804. Similarly, Figure 18C The electrical path is shown through bit line switch 1803, vertical metal bit line 1807, cell 1802, dummy cell 1806, vertical metal bit line 1808, and dummy bit line switch 1804. It can be seen that the path through cell 1802 traverses a much longer bit line and dummy bit line, which is associated with higher capacitance and higher resistance. This results in a greater parasitic impedance in the bit line or source line of cell 1802 than... Figure 18B The parasitic impedance of cell 1801 in the array. For example, this variability is a disadvantage because it causes the accuracy of the cell output applied to the read or verify (for programming / erase tuning cycles) cells to vary depending on the position of these cells in the array.

[0158] Figure 19AA VMM system 1900 is shown, which improves upon the prior art VMM system 1800. VMM system 1900 includes: exemplary units 1901 and 1902; exemplary bit line switches 1903a, 1903b, 1903c, and 1903d that connect bit lines to sensing circuitry; exemplary virtual units 1905 and 1906 that can be used as source pull-down units; and exemplary virtual bit line switches 1904a, 1904b, 1904c, and 1904d. As an example, one end of virtual bit line switch 1904a is connected to a low voltage level, such as ground, during read operations, and the other end is connected to the virtual units 1905 and 1906 that are used as source pull-down units. It can be seen that exemplary virtual bit line switches 1904a and the other virtual bit line switches are located on the opposite end of the array to bit line switches 1903a and the other bit line switches.

[0159] exist Figure 19B and 19C The benefits of this design can be seen in [the text / image / etc.]. Figure 19B In the middle, select unit 1901 for reading, and in Figure 19C In the middle, select unit 1902 to read.

[0160] Figure 19B The electrical path is shown through bit line switch 1903, unit 1901, virtual unit 1905 (source line pull-down unit), vertical metal bit line 1908, and virtual bit line switch 1904 (which is coupled to a low level such as ground during read operations). Figure 19C The electrical paths are shown through bit line switch 1903, vertical metal line 1907, cell 1902, dummy cell 1906 (source line pull-down cell), and dummy bit line switch 1904. These paths are substantially identical in terms of interconnect length, which applies to all cells in the VMM system 1900. Therefore, the bit line impedance plus the source line impedance of each cell is substantially the same, meaning that the amount of parasitic voltage drop drawn during a read or verify operation of each cell in the array varies substantially the same.

[0161] Figure 20A VMM system 2000 with global source line pull-down bitlines is shown. The VMM system 2000 is similar to the VMM system 1900, except that: virtual bitlines 2005a-2005n or 2007a-2007n are connected together (to act as global source line pull-down lines to pull the memory cell source lines to ground level during read or verification); virtual bitline switches, such as virtual bitline switches 2001 and 2002, are connected or coupled to a common ground (array ground) labeled ARYGND; and the source lines are coupled together to source line switch 2004, which selectively pulls the source lines to ground. These changes further reduce the variation in parasitic impedance of each cell in the array during read or verification operations.

[0162] In an alternative implementation, one or more virtual bit lines and one or more virtual bit line switches can be used instead of source line switch 2004 to pull the source line to ground.

[0163] In another implementation, virtual rows can be used as physical barriers between rows to avoid FG-FG coupling between rows (of two adjacent units).

[0164] Figure 21A A VMM system 2100 is shown. In some embodiments, the weights W stored in the VMM are stored as differential pairs W+ (positive weights) and W- (negative weights), where W = (W+) - (W-). In VMM system 2100, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that will store positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement negative weights W-. The W- lines are distributed alternately between the W+ lines. The subtraction operation is performed by summing circuits (such as summing circuits 2101 and 2102) that receive current from the W+ and W- lines. The outputs of the W+ and W- lines are combined to effectively give W = W+ - W- for each (W+, W-) cell pair of all (W+, W-) line pairs. Optionally, as shown in Figure 19 and Figure 20 The virtual bit lines and source pull-down bit lines shown can be used in the VMM system 2100 to avoid (two adjacent cells) FG-FG coupling and / or reduce the IR voltage drop in the source lines during read or verification operations.

[0165] Figure 21BAnother embodiment is shown. In VMM system 2110, a positive weight W+ is implemented in a first array 2111, and a negative weight W- is implemented in a second array 2112 separate from the first array, and the resulting weights are appropriately combined by a summing circuit 2113. Optionally, virtual bit lines and source pull-down bit lines, such as those shown in Figures 19 and 20, can be used in VMM system 2110 to avoid FG-FG coupling and / or reduce the IR voltage drop in the source lines during read or verification operations.

[0166] VMM systems can be designed such that W+ and W- pairs are placed within the array in a manner that reduces FG-to-FG coupling, or that power consumption is distributed more evenly across the array and output circuitry. This is described below with reference to Tables 10 and 11. For further details on FG-to-FG coupling, please refer to U.S. Provisional Patent Application No. 62 / 981,757, filed February 26, 2020, entitled “Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network,” which is incorporated herein by reference.

[0167] Table 10A shows an exemplary physical layout for the arrangement of two pairs of (W+, W-) bit lines. One pair is BL0 and BL1, and the second pair is BL2 and BL3. In this example, four row lines are coupled to source line pull-down bit lines BLPWDN. BLPWDN is placed between each pair of (W+, W-) bit lines to prevent one pair of (W+, W-) bit lines from being coupled to the other pair (e.g., FG to FG coupling). Therefore, BLPWDN acts as a physical barrier between the pairs of (W+, W-) bit lines.

[0168] Table 10A: Exemplary layouts for W+ and W- pairs

[0169]

[0170] Table 10B shows different exemplary weight combinations. '1' means that a unit is used and there is a real output value, and '0' means that no unit is used and there is no value or no significant output value.

[0171] Table 10B: Exemplary weight combinations for W+, W- pairs

[0172]

[0173] Table 11A shows another array implementation of the physical arrangement of (w+, w-) pairs BL0 / 1 and BL2 / 3. The array includes redundant lines BL01 and BL23 and a source-line pull-down bit line BLPWDN. Redundant bit line BL01 is used to remap values ​​from pair BL0 / 1, and redundant bit line BL23 is used to remap values ​​from pair BL2 / 3, which will be shown in later tables.

[0174] Table 11A: Exemplary layouts for W+ and W- pairs

[0175]

[0176] Table 11B shows examples of distributed weight values ​​that do not require remapping between adjacent bit lines, where there are essentially no adjacent '1's between adjacent bit lines.

[0177] Table 11B: Exemplary weight combinations of W+ and W- pairs

[0178]

[0179] Table 11C shows an example where distributed weights need to be remapped. Here, there are adjacent '1's in BL1 and BL3, which couples adjacent bit lines. Therefore, these values ​​are remapped, as shown in Table 11D, so that there are no adjacent '1' values ​​between any adjacent bit lines. Furthermore, by remapping, the total current along the bit line is now reduced, making the values ​​in that bit line more accurate, which also results in more distributed power consumption along the bit line. Optionally, additional bit lines (BL01, BL23) can be optionally used as redundant columns.

[0180] Table 11C: Exemplary weight combinations of w+ and w- pairs

[0181]

[0182] Table 11D: Weight combinations for remapping w+, w- pairs

[0183]

[0184] Tables 11E and 11F illustrate another implementation of remapping noisy cells (or defective cells) to redundant columns (such as BL01, BL23 in Table 11E or BL0B and BL1B in Table 11F).

[0185] Table 11E: Weight Combinations for Remapping w+, w- Pairs

[0186]

[0187] Table 11F: Weight combinations for remapping w+, w- pairs

[0188]

[0189] Table 11G shows the applicable... Figure 21B The implementation scheme for the physical arrangement of the array. Since each bit line has a positive or negative weight, the virtual bit lines act as source pull-down bit lines or real virtual bit lines (unused, such as deep or partially programmed or partially erased) and physical barriers to avoid FG-FG coupling of each bit line.

[0190] Table 11G: Exemplary layouts for w+, w- pairs

[0191]

[0192] In Tables 10A to 10B and Tables 11A to 11G, the source pull-down bit line BLPWDN can be implemented as a true virtual bit line BLDUM or an isolation bit line BLISO. This means that these bit lines are used to isolate data bit lines from each other, thereby avoiding FG-FG coupling between adjacent cells. These bit lines are not used, so they are tuned (programmed or erased) to a state that will not cause FG-FG coupling or make them susceptible to interference from other cells tuned (programmed or erased) in the same row or sector (e.g., cells that are deeply or partially programmed or partially erased), resulting in a low FG voltage.

[0193] In another embodiment, the tuning bit line coupled to the cell column is adjacent to the target bit line coupled to the cell column, and the tuning bit line unit is used to tune the target bit line unit to a desired target value during programming operations using FG-FG coupling between adjacent cells. Optionally, the source pull-down bit line can be used on the side of the target bit line opposite to the side adjacent to the tuning bit line.

[0194] Alternative implementations for mapping noisy or defective units can be achieved by designating such units as unused units, meaning they will be (deeply) programmed not to contribute any value to the neuron output.

[0195] An alternative implementation scheme can be implemented for identifying fast units (which are units that can reach a certain value faster than typical units), wherein fast units are identified and undergo a more precise tuning algorithm to not exceed the target during programming operations.

[0196] Figure 22VMM system 2200 is shown. VMM system 2200 includes a redundancy array 2201, which can be included in any of the VMM arrays discussed so far. If any column attached to the bit line switch is considered defective, the redundancy array 2201 can be used as redundancy to replace the defective column. The redundancy array can have its own redundant array (neuron) outputs (e.g., bit lines) and / or redundant write and verification circuitry, and / or ADC circuitry for redundancy purposes. For example, when redundancy is required, the output of the redundant ADC will replace the output of the ADC for the bad bit line. Redundancy array 2201 can also be used for weight mapping as described in Tables 10A and 10B to achieve a relatively uniform power distribution among the bit lines.

[0197] Figure 23 A VMM system 2300 is shown, comprising arrays 2301 and 2302, column multiplexer 2303, local bit lines LBL 2305a-d, global bit lines GBL 2308 and 2309, and virtual bit line switches 2305a-2305d. Column multiplexer 2303 is used to select a corresponding top local bit line 2305 of array 2301 or a bottom local bit line 2305 of array 2302 to a global bit line 2308. In one embodiment, the (metallic) global bit line 2308 has the same number of lines as the local bit lines, for example, 8 or 16. In another embodiment, the global bit line 2308 has only one (metallic) line for every N local bit lines, for example, one global bit line for every 8 or 16 local bit lines. The column multiplexer 2303 can multiplex adjacent global bit lines (such as GBL 2309) into a global bit line of interest (such as GBL 2308) to effectively increase the width of the current global bit line. This reduces the voltage drop across the global bit line of interest (GBL 2308).

[0198] Various output circuits that can be used with any VMM system described herein will now be described.

[0199] Figure 24 A VMM system 2400 is shown. The VMM system 2400 includes: an array 2410; a shift register (SR) 2401; a digital-to-analog converter (DAC) 2402 that receives input from the SR 2401 and outputs equivalent (analog or pseudo-analog) levels or information (e.g., voltage / timing); a summer circuit 2403; an analog-to-digital converter (ADC) 2404; and a bit line switch (not shown). Virtual bit lines and virtual bit line switches are present but not shown. As shown, the ADC circuitry can be combined to produce a single ADC with greater accuracy (i.e., a larger number of bits).

[0200] The summer circuit 2403 may include Figure 25-Figure 2The circuit shown in 7. It may include, but is not limited to, circuitry for normalization, scaling, arithmetic operations (e.g., addition, subtraction), activation, or statistical rounding.

[0201] Figure 25 This diagram illustrates a current-to-voltage summer circuit 2500 adjustable by a variable resistor. The summer circuit includes current sources 2501-1, ..., 2501-n drawing currents Ineu(1), ..., Ineu(n) (these are the currents received from the bit lines of the VMM array, respectively), an operational amplifier 2502, a variable holding capacitor 2504, and a variable resistor 2503. The output voltage of operational amplifier 2502 is Vneuout = R2503. (Ineu(1) + ... + Ineu(n)), this voltage is proportional to the sum of currents Ineu(1), ..., Ineu(n). When switch 2506 is open, holding capacitor 2504 is used to hold the output voltage. This holding output voltage is used, for example, for conversion to digital bits by an ADC circuit.

[0202] Figure 26 This diagram illustrates a current-to-voltage summer circuit 2600 adjustable by a variable capacitor (essentially an integrator). The summer circuit includes current sources 2601-1, ..., 2601-n drawing currents Ineu(1), ..., Ineu(n) (which are the currents received from the bit lines of the VMM array, respectively), an operational amplifier 2602, a variable capacitor 2603, and a switch 2604. The output voltage of operational amplifier 2602 is Vneuout 2605 = (Ineu(1) + ... + Ineu(n)) The integration time / C2603 is proportional to the sum of the currents Ineu(1), ..., Ineu(n).

[0203] Figure 27A A voltage summer 2700, adjustable by a variable capacitor (i.e., a switched capacitor SC circuit), is shown. The voltage summer includes switches 2701 and 2702, variable capacitors 2703 and 2704, an operational amplifier 2705, a variable capacitor 2706, and a switch S1 2707. When switch 2701 is closed, input Vin0 is provided to operational amplifier 2705. When switch 2702 is closed, input Vin1 is provided to operational amplifier 2705. Optionally, switches 2701 and 2702 are not closed simultaneously. Operational amplifier 2705 generates an output Vout, which is an amplified version of the input (Vin0 and / or Vin1, depending on which switch between 2701 and 2702 is closed). That is, Vout = Cin / Cout (Vin), Cin is C2703 or C2704, and Cout is C2706. For example, Vout = Cin / Cout ∑ (Vinx), Cin = C2703 = C2704, where Vinx can be Vin0 or Vin1. In one embodiment, Vin0 is the W+ voltage and Vin1 is the W- voltage, and the voltage summer 2700 adds them together (i.e., W+ - W-, by appropriately enabling the polarity of the switch) to produce the output voltage Vout.

[0204] Figure 27b illustrates a voltage summer 2750, which includes switches 2751 (S1), 2752 (S3), 2753 (S2), and 2754 (S4), a variable input capacitor 2758, an operational amplifier 2755, a variable feedback capacitor 2756, and a switch 2757 (S5). In one embodiment, Vin0 is a W+ voltage and Vin1 is a W- voltage; the voltage summer 2750 adds them together (i.e., W+ - W-, by appropriately enabling the polarity of the switches) to produce an output voltage Vout.

[0205] For input = Vin0, when switches 2754 and 2751 are closed and switches 2753, 2752, and 2757 are open, input Vin0 is supplied to the top terminal of capacitor 2758, whose bottom terminal is connected to VREF. Then, switch 2751 is opened and switch 2753 is closed to transfer charge from capacitor 2758 to feedback capacitor 2756. Essentially, the output VOUT then equals (C2758 / C2756). Vin0 (for cases where, for example, VREF=0).

[0206] For input = Vin1: When switches 2753, 2754, and 2757 are closed, and switches 2751, 2752, and 2757 are open, both terminals of capacitor 2758 discharge to VREF. Then, opening switch 2754 and closing switch 2752 charges the bottom terminal of capacitor 2758 to Vin1, which in turn charges feedback capacitor 2756 to VOUT = -(C2758 / C2756). Vin1 (for the case where VREF=0).

[0207] Therefore, if the sequence for Vin1 input is implemented after the sequence for Vin0, then, for example, in the case of VREF=0, VOUT = (C2758 / C2756). (Vin 0 - Vin1). This is used, for example, to implement W = W+ - W-.

[0208] As shown in Figure 27, each ADC can be configured to be combined with the next ADC for a higher-level implementation with a suitable ADC design.

[0209] Refer again Figure 17 The inputs and outputs of the VMM array 1701 can be in digital or analog form. For example:

[0210] IN [0:q] to DAC sequential inputs:

[0211] In one implementation, the input circuit 1706 receives digital inputs sequentially, starting with IN0, then IN1, ..., then INq. All input bits have the same VCGin. The input bits are provided to a DAC, which then applies an analog signal as input to the VMM array 1701. Before or after the ADC, all bitline (neuron) outputs are summed using a modulated binary indexed multiplier.

[0212] In another implementation, a method using a modulated neuron (bit line) binary index multiplier is employed. For example... Figure 20 As shown, the exemplary summer has two bit lines, BL0 and BLn. Weights are distributed across multiple bit lines BL0 to BLn. For example, there are four bit lines: BL0, BL1, BL2, and BL3. The output of bit line BL0 is multiplied by 2^0 = 1. The output of bit line BLn, representing the position of the nth binary bit, is multiplied by 2^n; for example, for n=3, 2^3 = 8. The outputs of all bit lines, after being appropriately multiplied by the binary bit position 2^n, are then summed. This is then digitized by the ADC. This method means that all cells have only a binary range, and multi-level ranges (n bits) are handled by peripheral circuitry (i.e., the summer circuitry). Therefore, for the highest bias level of the memory cell, the voltage drop across all bit lines is approximately the same.

[0213] In another implementation, digital inputs IN0, IN1, ..., then INq are applied sequentially. Each input bit has a corresponding analog value VCGin. Before or after the ADC, all neuron outputs are summed to evaluate all input bits.

[0214] Parallel input of DAC:

[0215] In another implementation, inputs IN0, ..., INq are provided to the DAC in parallel. Each input in [0:q] has a corresponding analog value VCGin. The outputs of all neurons are summed using an adjusted binary index multiplier method, either before or after the ADC.

[0216] In implementations involving sequential operation of the array, the power distribution is more uniform.

[0217] In an implementation using the neuron (bit line) binary indexing method, power consumption in the array is reduced because each unit coupled to the bit line contains only binary levels, and 2^n levels are implemented by a summer circuit.

[0218] Figure 28A , Figure 28B and Figure 28C Showing what can be used Figure 24 The summer circuit 2403 and the output circuit of the analog-to-digital converter 2404 are described.

[0219] Figure 28A The output circuit 2800 is shown, which includes an analog-to-digital converter 2802 that receives neuron output 2801 and outputs digital bits 2803.

[0220] Figure 28B The output circuit 2810 is shown, which includes a neuron output circuit 2811 that receives neuron output 2801 and generates output 2813 together, and an analog-to-digital converter 2812.

[0221] Figure 28C The output circuit 2820 is shown, which includes a neuron output circuit 2821 that receives neuron output 2801 and generates output 2823 together, and a converter 2822.

[0222] The neuron output circuitry 2811 or 2821 may perform, for example, summation, scaling, normalization, or arithmetic operations, but is not limited thereto. For example, the converter 2822 may perform ADC, PDC, AAC, or APC operations, but is not limited thereto.

[0223] Figure 29 The diagram shows a neuron output circuit 2900, which includes adjustable (scaling) current sources 2901 and 2902. These two current sources together generate the output iOUT, i.e., the neuron output. This circuit can simultaneously perform the summation of positive weights W+ and negative weights W-, i.e., W = W+ - W-, and the scaling of the output neuron current (by adjusting the adjustable current sources 2901 and 2902). In other words, I... W+ A scaled-down version of W+, and I W-This is a scaled-up version of W-.

[0224] Figure 30 A configurable serial analog-to-digital converter 3000 is shown. It includes an integrator 3070 that integrates the neuron output current into an integrating capacitor 3002 (Cint).

[0225] In one implementation, VRAMP 3050 is provided to the inverting input of comparator 3004. Digital output (count value) 3021 is generated by causing VRAMP 3050 to ramp up until comparator 3004 switches polarity, wherein counter 3020 counts clock pulses from the ramp up.

[0226] In another implementation, VREF 3055 is provided to the inverting input of comparator 3004. VC 3010 ramps down via current 3051 (IREF) until VOUT 3003 reaches VREF 3055, at which point the EC 3005 signal disables the counting of counter 3020. The (n-bit) ADC 3000 can be configured to have lower accuracy (less than n bits) or higher accuracy (greater than n bits), depending on the target application. Accuracy configurability is achieved by configuring the capacitance of capacitor 3002, current 3051 (IREF), ramp rate of VRAMP 3050, or clock frequency of clock 3041, but is not limited to these.

[0227] In another embodiment, the ADC circuit of the VMM array is configured to have an accuracy of less than n bits, while the ADC circuit of another VMM array is configured to have a high accuracy of more than these bits.

[0228] In another embodiment, an instance of a serial ADC circuit 3000 of a neuron circuit is configured to be combined with another instance of a serial ADC circuit 3000 of a next neuron circuit to produce an ADC circuit with higher than n bits of accuracy, for example by combining the integrating capacitors 3002 of the two instances of the serial ADC circuit 3000.

[0229] Figure 31 A configurable neural SAR (successive approximation register) analog-to-digital converter 3100 is shown. This circuit is based on a successive approximation converter that uses binary capacitors for charge redistribution. The circuit includes a binary CDAC (capacitor-based DAC) 3101, an operational amplifier / comparator 3102, SAR logic, and a register 3103. As shown, GndV 3104 is a low-voltage reference level, such as ground. The SAR logic and register 3103 provides a digital output 3106.

[0230] Figure 32A configurable neuron-combined SAR analog-to-digital converter circuit 3200 is shown. This circuit combines two n-bit ADCs from two neuron circuits into one to achieve higher accuracy than n bits. For example, for a 4-bit ADC of a neuron circuit, this circuit can achieve >4-bit accuracy, such as 8-bit ADC accuracy, by combining two 4-bit ADCs. The combined circuit topology is equivalent to a split capacitor (bridge capacitor (cap) or focus cap) SAR ADC circuit, such as an 8-bit 4C-4C SAR ADC produced by combining two adjacent 4-bit 4C SAR ADC circuits. This is achieved using a bridge circuit 3204 (Csplit), whose capacitance is = (total number of CDAC capacitor cells / total number of CDAC capacitor cells - 1).

[0231] Figure 33 A pipelined SAR ADC circuit 3300 is shown, which can be combined with a next SAR ADC to increase the number of bits in a pipelined manner. The SAR ADC circuit 3300 includes a binary CDAC (capacitor-based DAC) 3301, operational amplifiers / comparators 3302 and 3303, SAR logic, and a register 3304. As shown, GndV 3104 is a low-voltage reference level, such as ground. The SAR logic and register 3103 provides a digital output 3106. Vin is the input voltage, VREF is the reference voltage, and GndV is ground. Vresidue is generated by capacitor 3305 and provided as an input to the next stage of the SAR ADC.

[0232] For additional specific implementation details of configurable output neuron (such as configurable neuron ADC) circuitry, please refer to U.S. Patent No. 16 / 449,201, filed June 21, 2019, entitled “Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in a Deep Learning Artificial Neural Network,” which is incorporated herein by reference.

[0233] It should be noted that, as used herein, the terms “above” and “on” both encompass “directly on” (without intermediate material, elements, or space between) and “indirectly on” (with intermediate material, elements, or space between). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, elements, or space between) and “indirectly adjacent” (with intermediate material, elements, or space between), “mounted to” includes “directly mounted to” (without intermediate material, elements, or space between) and “indirectly mounted to” (with intermediate material, elements, or space between), and “electrically coupled to” includes “directly electrically coupled to” (without intermediate material or elements electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or elements electrically connecting the elements together). For example, forming an element “above a substrate” can include forming an element directly on the substrate without intermediate material / elements between them, and forming an element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. A simulated neural memory system, comprising: A non-volatile split-gate or stacked-gate flash memory cell array, wherein the cells are arranged in rows and columns; Each row of memory cells is coupled to a corresponding common source line; The columns are arranged in groups of two physically adjacent column pairs, wherein within each physically adjacent column pair, one column includes cells storing positive weight values ​​and the other column includes cells storing negative weight values, wherein adjacent cells in a row within each physically adjacent column pair are configured to store differential weight bits. The array further includes two redundant columns, with one redundant column on each side of each pair of two physically adjacent columns. The system is configured to remap the weight bits of each physically adjacent column in the two physically adjacent column pairs to the corresponding redundant column, such that there are no adjacent "1" weight bits between any physically adjacent columns in the group. The array further includes two virtual cell columns configured as source line pull-down bit line operations, one virtual cell column on each side of each redundant column of the group, wherein each column in two physically adjacent column pairs is coupled to a bit line switch on a first side of the array and the two virtual cell columns are coupled to a virtual bit line switch on a second side of the array opposite the first side, wherein each virtual cell column is configured to connect the memory cell source line to ground via the virtual bit line switch; and The system further includes a summer configured to generate a first sum (W+) from the output of the first bit line and a second sum (W-) from the output of the second bit line, and output the difference between the first sum and the second sum (W=(W+) - (W-)).

2. The system of claim 1, wherein the summer is adjustable based on a variable resistor.

3. The system of claim 1, wherein the summer is adjustable based on a variable capacitor.

4. The system of claim 1, wherein the summer comprises a switched capacitor circuit and an operational amplifier.

5. The system of claim 1 further includes an analog-to-digital converter for converting the output of the summer into a digital signal.

6. The system of claim 5, wherein the analog-to-digital converter includes a successive approximation register.

7. The system of claim 6, wherein the analog-to-digital converter comprises a pipelined analog-to-digital converter.

8. The system of claim 1, wherein the remapping removes the coupling between two adjacent cells in adjacent column pairs.

9. The system of claim 1, wherein the remapping redistributes one or more of the power or voltage drop between bit lines.

10. The system of claim 1, wherein the remapping remaps the noise units to the redundant columns.

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