Control system, multi-power supply power-on system and its power-on timing control method

Abstract

This application provides a control system, a multi-power supply power-on system, and a power-on timing control method thereof. The system can be applied to a CPU and includes: a logic chip and N power supply chips, where N is a positive integer. By using the logic chip and power supply chips in combination, based on the relationship between the power-on timing time difference between two power supply chips and the time error of the internal time delay of the power supply chips, when the power-on timing time difference between two power supply chips is greater than the time error of the internal time delay of the power supply chips, the logic chip outputs an enable signal to trigger the next-level power supply chip to supply power to the CPU after receiving the normal output signal from the previous level. Conversely, it directly uses the normal output signal from the previous level power supply chip as the trigger condition for the current level power supply chip to supply power to the CPU. This solves the problem that the existing logic chip timing output function cannot avoid the power-on timing disorder and system power-on failure caused by the difference in the internal power-on delay time of different power supply modules.

Description

Technical Field

[0001] This invention relates to the field of control technology, specifically to a control system, a multi-power supply power-on system, and a power-on timing control method thereof. Background Technology

[0002] As the system architecture of mainstream CPU products in the market becomes increasingly integrated, the types of circuit modules within the central processing unit (CPU) are also becoming more diverse. To ensure the coordinated operation of each module within the system, it is necessary to define the power-on sequence of the various internal circuit modules. Currently, capacitor-resistor RC delay circuits are commonly used to adjust the resistor and capacitor values ​​to meet different power-on requirements.

[0003] In this process of adjusting the resistor and capacitor values ​​using a capacitor-resistor RC delay circuit, the first-stage power supply uses a smaller capacitor value to prioritize power-on, while the second-stage power supply uses a larger capacitor value, resulting in a longer delay time for the enable signal compared to the first-stage power supply, thus achieving different power-on sequences. Although this method is low-cost and simple to use, it suffers from poor accuracy. If multiple power supplies are present, the cumulative effect of these steps will prolong the overall power-on time, thereby affecting the processor's boot performance. Furthermore, passive components are highly sensitive to temperature, and with aging and changes in operating temperature, there is a risk of excessive degradation of nominal values ​​and component failure.

[0004] While using the timing output function of the logic chip to output the enable signal can solve the problems of poor delay stability and low accuracy of the RC delay circuit, if the time interval between each power module is very short and there is a strict power-on sequence requirement, this solution cannot avoid the problem of power-on sequence disorder and system power-on failure caused by the difference in the internal power-on delay time of different power modules. Summary of the Invention

[0005] In response, this application provides a control system, a multi-power supply power-on system, and a power-on timing control method thereof to solve the problem that existing logic chip timing output functions cannot avoid the power-on timing disorder and system power-on failure caused by the difference in internal power-on delay time of different power supply modules.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] The first aspect of this invention discloses a multi-power supply system applied to a CPU, the multi-power supply system comprising: a logic chip and N power supply chips, where N is a positive integer;

[0008] If the power-on timing difference between two power chips is greater than the time error of the internal time delay of the power chip, the logic chip enables the power chip to supply power to the CPU. All enable signals that are not output for the first time are output to the next power chip according to the preset power-on timing after receiving the output normal signal fed back by the previous power chip.

[0009] If the power-on timing difference between the two power chips is less than the time error of the internal time delay of the power chip, then the power chip directly uses the normal output signal fed back by the power chip above it as the trigger condition for powering the CPU.

[0010] Optionally, in the above-described multi-power supply power-on system, if the enable signal output by the logic chip is the first output signal, it is directly output to the corresponding power supply chip according to the preset power-on sequence.

[0011] Optionally, in the above-described multi-power supply power-on system, all non-first-time output enable signals of the logic chip are output to the next-level power supply chip according to a preset power-on sequence after receiving the normal output signal from the previous-level power supply chip, including:

[0012] The logic chip utilizes its own timing and I / O driving functions to output all non-first-time output enable signals to the next-level power chip according to a preset power-on sequence after receiving the normal output signal from the previous-level power chip.

[0013] Optionally, in the above-described multi-power supply system, the logic chip is a field-programmable gate array (FPGA).

[0014] Optionally, in the above-mentioned multi-power supply system, the power chip is model NCP45520.

[0015] The second aspect of this invention discloses a power-on timing control method for a multi-power-on system, applied to a logic chip in a multi-power-on system as described in any of the claims of the first aspect, the method comprising:

[0016] During CPU startup, it is determined whether the power chip to be enabled is the first enabled chip in the multi-power supply system.

[0017] If it is determined that the current power chip to be enabled is not the first enabled chip in the multi-power supply power-on system, then after receiving the normal output signal from the previous power chip, an enable signal is output to the current power chip to be enabled according to the preset power-on sequence.

[0018] Optionally, in the above-described power-on timing control method for a multi-power supply system, after determining whether the current power supply chip to be enabled is the first enabled chip in the multi-power supply system, if it is determined that the current power supply chip to be enabled is the first enabled chip in the multi-power supply system, the method further includes:

[0019] The enable signal is directly output to the currently enabled power chip according to the preset power-on sequence.

[0020] Optionally, in the above-described power-on timing control method for a multi-power supply system, after determining whether the current power supply chip to be enabled is the first enabled chip in the multi-power supply system, if it is determined that the current power supply chip to be enabled is not the first enabled chip in the multi-power supply system, the method further includes:

[0021] Determine whether a normal output signal is received from the previous power chip within a preset time period;

[0022] If it is determined that no normal output signal is received from the previous power supply within the preset time period, an error message will be output.

[0023] If it is determined that a normal output signal is received from the previous power chip within a preset time period, then the step of outputting an enable signal to the current power chip to be enabled according to the preset power-on sequence is executed.

[0024] A third aspect of the present invention discloses a control system comprising: a main controller, wherein the main controller integrates a multi-power supply system as described in any of the claims of the first aspect.

[0025] Based on the multi-power supply system provided by the present invention, it can be applied to a CPU. The system includes a logic chip and N power supply chips, where N is a positive integer. If the power-on timing difference between two power supply chips is greater than the internal time delay error of the power supply chip, the logic chip enables the power supply chip to supply power to the CPU. All non-first-time output enable signals are output to the next-level power supply chip according to a preset power-on timing after receiving the normal output signal from the previous-level power supply chip. If the power-on timing difference between two power supply chips is less than the internal time delay error of the power supply chip, the power supply chip directly uses the normal output signal from its previous-level power supply chip as the trigger condition for supplying power to the CPU, that is... This application can use logic chips and power chips together. Based on the relationship between the power-on timing difference between the two power chips and the time error of the internal time delay of the power chips, when the power-on timing difference between the two power chips is greater than the time error of the internal time delay of the power chips, the logic chip outputs an enable signal to trigger the next-level power chip to supply power to the CPU after receiving the normal output signal from the previous level. Conversely, it directly uses the normal output signal from the previous level power chip as the trigger condition for the current level power chip to supply power to the CPU. This solves the problem that the existing logic chip timing output function cannot avoid the power-on timing disorder and system power-on failure caused by the difference in the internal power-on delay of different power modules. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0027] Figure 1 A schematic diagram of a multi-power supply system provided in this application embodiment;

[0028] Figure 2 A circuit diagram for testing the switching characteristics of a power chip provided in an embodiment of this application;

[0029] Figure 3 A timing diagram of a power supply chip provided for an embodiment of this application;

[0030] Figure 4 A schematic diagram of the specific structure of a multi-power supply system provided in this application embodiment;

[0031] Figures 5 to 7 The flowchart shows three power-on timing control methods for multi-power supply power-on systems provided in the embodiments of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] First, it should be noted that when a CPU starts up, it often needs to limit the power-on sequence of its various internal circuit modules in order to meet the logic operation requirements of the chip.

[0034] This application provides a multi-power supply power-on system to solve the problem that existing logic chip timing output functions cannot avoid the power-on timing disorder and system power-on failure caused by the difference in internal power-on delay time of different power modules.

[0035] This multi-power supply system can be applied to CPUs; please refer to [link / reference]. Figure 1 The multi-power supply system mainly includes: a logic chip (10 in the figure) and N power chips (20 in the figure), where N is a positive integer.

[0036] If the power-on timing difference between two power chips is greater than the time error of the internal time delay of the power chips, the logic chip will power the CPU by enabling the power chips. All enable signals that are not output for the first time will be output to the next power chip according to the preset power-on timing after receiving the normal output signal from the previous power chip.

[0037] In practical applications, if the power supply chip uses the enable signal output by the logic chip as the trigger condition for powering the CPU, then the power supply chip at this stage is directly connected to the corresponding pin of the logic chip; if the power supply chip uses the normal output signal fed back from the previous stage power supply chip as the trigger condition for powering the CPU, then the power supply chip at this stage is connected to the previous stage power supply chip.

[0038] It should be noted that when the power-on timing difference between two power chips is greater than the time error of the internal time delay of the power chips, during the process of the logic chip powering the CPU through the power chip, all non-first-time output enable signals are output to the next power chip according to the preset power-on timing after receiving the normal output signal from the previous power chip.

[0039] In other words, when the power-on timing difference between two power supply chips exceeds the internal time delay error of the power supply chips, the normal output signal from the previous stage power supply chip is used as a necessary trigger condition for the next stage power supply chip to power the CPU. Only after receiving the normal output signal from the previous stage power supply chip will the logic chip output an enable signal to the next stage power supply chip according to the preset power-on sequence, after a preset interval, thus controlling the next stage power supply chip to power the corresponding circuit module in the CPU. Since the normal output signal is only output after the previous stage power supply chip has completed power-on, the next stage power supply chip will only power on after the previous stage power supply chip has successfully powered on. This allows for accurate control of the power-on sequence of the circuit modules in the CPU, eliminating the need to adjust resistor and capacitor values ​​using capacitor-resistor RC delay circuits, which can prolong the overall power-on time and affect processor boot performance when multiple power supply stages are present.

[0040] If the power-on timing difference between two power chips is less than the internal time delay of the power chip, the power chip directly uses the normal output signal fed back by the power chip above it as the power supply trigger condition for powering the CPU.

[0041] It should be noted that in a multi-power supply system, if the power-on timing difference between two power supply chips is less than the internal time delay of the power supply chip, the lower-level power supply chip will directly use the normal output signal fed back from the higher-level power supply chip as the power supply trigger condition for powering the CPU.

[0042] Combination Figure 1 The two power supply chips with a power-on timing difference less than the internal time delay of the power supply chip can be power supply chip 3 and power supply chip 4 in the figure.

[0043] It should be noted that when the power-on timing difference between two power chips is less than the internal time delay of the power chip, the normal output signal from the previous stage power chip can be directly used as the enable signal to trigger the next stage power chip to power the CPU. This addresses the issues of poor stability and accuracy of RC delay circuits, the increased overall power-on time after multiple accumulations, and the risk of excessive nominal value drift and device failure due to the high temperature sensitivity of passive capacitor components in RC delay circuits as the components age and operating temperature changes. This allows for a more precise control over the power-on timing difference between the two power chips. The difference is less than the internal time delay of the power supply chip. The normal output signal of the previous stage power supply is used as a necessary condition for triggering the next stage power supply chip. This avoids the solution of simply using the logic chip to time the output of the enable signal. When the power-on interval between two adjacent steps is very short, especially the microsecond level power-on interval, there is an internal time delay in the power supply chip from receiving the enable signal to the normal voltage output. When the difference of the internal time delay of the chip cancels out the difference of the external logic chip enable signal, it will cause the power-on timing to be misaligned, resulting in the system power-on failure. This solves the problem of complex CPU power-on timing requirements.

[0044] In practical applications, logic chips can utilize their own timing and I / O drive functions to output all non-first-time output enable signals to the next-level power chip according to a preset power-on sequence after receiving the normal output signal from the previous-level power chip.

[0045] Specifically, after the logic chip outputs an enable signal to the first-level power chip through its corresponding IO drive port, when the logic chip outputs an enable signal to the second-level power chip, it can start timing using its own timing function after receiving the normal output signal fed back by the first-level power chip after it has completed power-on. When the timing meets the power-on timing requirements between the first-level power chip and the second-level power chip, it then outputs an enable signal to the second-level power chip through the corresponding IO drive port, enabling the second-level power chip to supply power to the corresponding circuit module of the CPU.

[0046] In practical applications, since the first-stage power chip does not have a previous-stage power chip, the enable signal output by the logic chip to the first-stage power chip is generally simply output through its own corresponding IO port according to the preset power-on sequence requirements.

[0047] In other words, if the enable signal output by the logic chip is the first output signal, it will be directly output to the corresponding power supply chip according to the preset power-on sequence.

[0048] It should be noted that the logic chip can be a general-purpose field-programmable gate array (FPGA), but it is not limited to that; it can also be other existing programmable chips. This application does not limit the specific type of logic chip, and all of them are within the scope of protection of this application.

[0049] It should be noted that the power supply chip can be a chip with normal signal output function, such as the chip with model number NCP45520; of course, it is not limited to this, and other existing chips can also be used. This application does not limit the specific model of the power supply chip, and all of them are within the protection scope of this application.

[0050] In practical applications, the PG pin of the NCP45520 power supply chip is active high and has an open-drain output, indicating that when the MOSFET gate is fully charged, an external pull-up resistor of ≥1kΩ is required to connect to an external voltage source; if not used, it is connected to GND. Combined with... Figure 2 The diagram shows the switching characteristic test circuit and Figure 3 As shown in the timing diagram, the time delay between the output normal signal and the power-on of the NCP45520 power chip is 0.91 to 1.21 ms. Therefore, by applying the timing function of the logic chip, the IO drive function, and the output normal signal function of the power chip, the complex CPU power-on timing requirements can be met.

[0051] It should also be noted that the specific value of N can be determined according to the specific application environment and user needs. Generally, N can be equal to the number of power-on steps required by the CPU to power a specific module. This application does not impose specific limitations on the value of N, and all of them are within the protection scope of this application.

[0052] Based on the above principles, the multi-power supply system provided in this embodiment can be applied to a CPU. This system includes a logic chip and N power supply chips, where N is a positive integer. If the power-on timing difference between two power supply chips is greater than the internal time delay of the power supply chip, the logic chip enables the power supply chip to supply power to the CPU. All non-first-time output enable signals are output to the next-level power supply chip according to a preset power-on sequence after receiving the normal output signal from the previous-level power supply chip. That is, this application can use the logic chip and power supply chips together. When the power-on timing difference between two power supply chips is greater than the internal time delay of the power supply chip, the logic chip's timing output function outputs an enable signal, using the normal output signal from the previous-level power supply chip as the next-level power supply chip's signal. The necessary triggering condition solves the problems of existing capacitor-resistor RC delay circuits that adjust resistor and capacitor values, which, after multiple steps of accumulation, prolong the overall power-on time, affecting processor boot performance and causing passive components to suffer excessive attenuation of nominal values ​​and device failure, resulting in poor stability and low accuracy of power-on timing control. At the same time, if the power-on timing time difference between two power chips is less than the time error of the internal time delay of the power chip, the power chip directly uses the normal output signal fed back by the previous stage power chip as the enable trigger condition, which greatly shortens the control time of the two-stage power-on timing and solves the problem that the existing logic chip timing output function cannot avoid the power-on timing disorder and system power-on failure caused by the difference in the internal power-on delay time of different power modules.

[0053] It is worth noting that there is an existing scheme that uses a dedicated chip to control the CPU power-on timing. However, this scheme uses fixed power-on timing and voltage values ​​for multiple power supplies, which is only applicable to specific chips and has poor versatility. Each time the main chip is replaced, a dedicated chip circuit needs to be redesigned, which wastes a lot of time and effort and cannot be completed quickly. In contrast, the scheme provided in this application can achieve arbitrary CPU power-on timing requirements by programming the logic chip. It has high versatility and does not require redesigning a dedicated chip circuit every time the main chip is replaced, which reduces a lot of time and effort and can complete the design quickly.

[0054] Based on the multi-power supply system provided in the above embodiments, in practical applications, assuming the logic chip is a general-purpose FPGA and the power supply chip with normal signal output function is the NCP45520, taking 5 power supply chips as an example, combined with... Figure 4 The present invention specifically includes the following implementation process:

[0055] Step 1: Power on with 3.3V to trigger the RTC_VDD signal in the CPU and enable the RTC module.

[0056] Step 2: Power the FPGA with 3.3V, time it for 100ms, trigger the RTC_RSTn signal in the CPU, and reset the RTC module.

[0057] Step 3: After a 2-second timer, enable the first-stage power chip, supply 3.3V power to the first-stage power chip, and output the start signal VDD_RSM.

[0058] Step 4: The output normal signal from the first-stage power chip is timed for 1μs and output to the GMAC_VDDE signal in the CPU to start the power supply of the GMAC module in the CPU, and at the same time, it is fed back to the FPGA.

[0059] Step 5: After timing for 1μs, enable the second-stage power chip, supply 3.3V power to the second-stage power chip, and output the ACPI_3V3 / USBA3V3 signal to start the CPU, thus starting the ACPI and USB module power supply in the CPU.

[0060] Step 6: The output normal signal from the second-stage power chip is timed for 1ms and output to the RTC_RSMRSTn signal in the CPU to reset the RTC_RSM module, and at the same time, it is fed back to the FPGA.

[0061] Step 7: After a 20ms timer, activate the ACPI_PWRBTNn signal in the CPU.

[0062] Step 8: After a 1ms timer, activate the ACPI_S5n signal in the CPU.

[0063] Step 9: Time 1ms and activate the ACPI_S4n signal in the CPU.

[0064] Step 10: Time 1ms, trigger the ACPI_S3n signal in the CPU, and start the ACPI_S3n signal.

[0065] Step 11: After a 1ms timer, enable the third-stage power supply chip, supply 3.3V power to the third-stage power supply chip, and output the IO_3V3 / PEST_3V3 signal to start the CPU.

[0066] Step 12: The normal output signal of the third-stage power chip enables the fourth-stage power chip. The fourth-stage power chip is powered by 1.5V and outputs DDR_VDDE / DDR_VREF / VTT signals, which are then fed back to the FPGA.

[0067] Step 13: After a 1ms timeout, enable the fifth-stage power chip, supply 1.1V power to the fifth-stage power chip, and output the VDD / PEST_1V1 / PLL signal to start the CPU.

[0068] Step 14: After a 1ms timer, activate the ACPI_PWROK signal in the CPU.

[0069] Step 15: After 100ms, activate the ACPI_SYSRSTn signal in the CPU.

[0070] It should be noted that the above example only uses 5 power chips as an example, but in actual applications, the number of power chips is not limited to this.

[0071] It should also be noted that the above example is only one application example in a practical application, and does not mean that this application can only be implemented in this way. As long as the implementation principle is the same as this application, it falls within the protection scope of this application.

[0072] Based on the multi-power-on system provided in the above embodiments, another embodiment of this application provides a power-on timing control method for the multi-power-on system. This method can be applied to logic chips in the multi-power-on system provided in any of the above embodiments. Please refer to [link to relevant documentation]. Figure 5 This method mainly includes:

[0073] S100. During CPU startup, determine whether the power chip to be enabled is the first enabled chip in the multi-power supply system.

[0074] In practical applications, the power chip that is currently to be enabled is the power chip that the logic chip is about to be enabled but has not yet been enabled.

[0075] During CPU startup, it can be determined whether the power chip to be enabled is the first power chip in the multi-power supply system to be enabled by the logic chip outputting an enable signal.

[0076] If it is determined that the current power chip to be enabled is not the first enabled chip in the multi-power supply system, step S102 can be executed.

[0077] S102. After receiving the normal output signal from the previous power chip, output the enable signal to the current power chip to be enabled according to the preset power-on sequence.

[0078] The power-on timing control method for the multi-power supply system provided in this embodiment can be applied to logic chips in the multi-power supply system provided in any of the above embodiments. During the CPU startup process, this method can first determine whether the current power chip to be enabled is the first enabled chip in the multi-power supply system. If it is determined that the current power chip to be enabled is not the first enabled chip in the multi-power supply system, then after receiving the output normal signal from the previous power chip, an enable signal is output to the current power chip to be enabled according to the preset power-on timing. That is, the power-on timing control method for the multi-power supply system can control the next power chip to power on only after the previous power chip has been powered on. This can solve the problems of poor stability and low accuracy of power-on timing control caused by using capacitor-resistor RC delay circuits to adjust the resistor and capacitor values, which results in multiple steps accumulating and prolonging the overall power-on time, affecting the processor's boot performance, and the risk of excessive attenuation of nominal values ​​and device failure of passive components.

[0079] Optionally, in another embodiment provided in this application, after performing step S100, during the CPU startup process, determining whether the power chip to be enabled is the first enabled chip in the multi-power supply system, if it is determined that the power chip to be enabled is the first enabled chip in the multi-power supply system, please refer to [link to relevant documentation]. Figure 6 The power-on timing control method for the multi-power supply power-on system further includes step S200.

[0080] Step S200: Directly output the enable signal to the power supply chip to be enabled according to the preset power-on sequence.

[0081] In practical applications, since the current power chip to be enabled is the first chip to be enabled in a multi-power supply power-on system, it means that this level of power chip does not have a previous level of power chip. It does not need to wait for the previous level of power chip to complete power-on and output a normal signal before it can be executed. It can directly output the enable signal according to the preset power-on sequence.

[0082] Optionally, in another embodiment provided in this application, after performing step S100, during the CPU startup process, determining whether the power chip to be enabled is the first enabled chip in the multi-power supply system, if it is determined that the power chip to be enabled is not the first enabled chip in the multi-power supply system, please refer to [link to relevant documentation]. Figure 7 The power-on timing control method for the multi-power supply power-on system also includes:

[0083] S300: Determine whether a normal output signal is received from the previous power chip within a preset time period.

[0084] In practical applications, the specific value of the preset time period can be determined according to the application environment and user needs, or it can be determined according to the CPU performance requirements. This application does not impose any specific limitations on it. Regardless of the value, it is within the protection scope of this application.

[0085] If it is determined that no normal output signal is received from the previous power supply within the preset time period, then step S302 is executed; if it is determined that a normal output signal is received from the previous power supply chip within the preset time period, then the step of outputting an enable signal to the current power supply chip to be enabled according to the preset power-on sequence is executed, that is, step S102 is executed.

[0086] S302, Output error message.

[0087] In practical applications, once it is determined that no normal output signal is received from the previous power supply within a preset time period, error information can be output through indicator lights. For example, changing the color and brightness of the indicator lights can indicate abnormal power-on of the multi-power supply system, thereby prompting the user that the CPU is not powered on.

[0088] The indicator light can be an externally added LED, etc.; of course, it is not limited to this, and can be determined according to the specific application environment and user needs. This application does not limit the type of indicator light, and all of them are within the protection scope of this application.

[0089] Optionally, another embodiment of this application also provides a control system, which includes: a main controller, and the main controller integrating a multi-power supply system as described in any of the above embodiments.

[0090] In practical applications, the main controller can be the main controller in the instrumentation control system of a nuclear power plant. Of course, it is not limited to this and can also be the main controller in other control systems. This application does not limit the specific type of control system to which the main controller belongs, and all of them are within the protection scope of this application.

[0091] It should be noted that the relevant descriptions of the multi-power supply system can be found in the corresponding embodiments described above, and will not be repeated here.

[0092] The features described in the various embodiments of this specification can be substituted for or combined with each other. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0093] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0094] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0095] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A multi-power supply system, characterized in that, Applied to a CPU, the multi-power supply system includes: a logic chip and N power supply chips, where N is a positive integer; Wherein, if the power-on timing difference between two power chips is greater than the time error of the internal time delay of the power chip, the logic chip enables the power chip to supply power to the CPU. All non-first-time output enable signals are output to the next-level power chip according to the preset power-on timing after receiving the output normal signal fed back by the previous-level power chip. The non-first-time output enable signals are the other enable signals besides enabling the first power chip to power on among the multiple enable signals output by the logic chip that can enable the power chip to power on. If the power-on timing difference between the two power chips is less than the time error of the internal time delay of the power chip, then the power chip directly uses the normal output signal fed back by the power chip above it as the trigger condition for powering the CPU.

2. The multi-power supply system according to claim 1, characterized in that, If the enable signal output by the logic chip is the first output signal, it will be directly output to the corresponding power chip according to the preset power-on sequence.

3. The multi-power supply system according to claim 1, characterized in that, All enable signals that are not output for the first time by the logic chip are output to the next stage power chip according to a preset power-on sequence after receiving the normal output signal from the previous stage power chip, including: The logic chip utilizes its own timing and I / O driving functions to output all non-first-time output enable signals to the next-level power chip according to the preset power-on sequence after receiving the normal output signal from the previous-level power chip.

4. The multi-power supply system according to any one of claims 1-3, characterized in that, The logic chip is a field-programmable gate array (FPGA).

5. The multi-power supply system according to any one of claims 1-3, characterized in that, The power chip is model NCP45520.

6. A power-on timing control method for a multi-power supply power-on system, characterized in that, The method, applied to a logic chip in a multi-power supply system as described in any one of claims 1-5, comprises: During CPU startup, it is determined whether the power chip to be enabled is the first enabled chip in the multi-power supply system. If it is determined that the current power chip to be enabled is not the first enabled chip in the multi-power supply power-on system, then after receiving the normal output signal from the previous power chip, an enable signal is output to the current power chip to be enabled according to the preset power-on sequence.

7. The power-on timing control method for a multi-power supply power-on system according to claim 6, characterized in that, After determining whether the power chip to be enabled is the first enabled chip in the multi-power supply system, if it is determined that the power chip to be enabled is the first enabled chip in the multi-power supply system, the process further includes: The enable signal is directly output to the currently enabled power chip according to the preset power-on sequence.

8. The power-on timing control method for a multi-power supply power-on system according to claim 6, characterized in that, After determining whether the current power supply chip to be enabled is the first enabled chip in the multi-power supply power-on system, if it is determined that the current power supply chip to be enabled is not the first enabled chip in the multi-power supply power-on system, the process further includes: Determine whether a normal output signal is received from the previous power chip within a preset time period; If it is determined that no normal output signal is received from the previous power supply within the preset time period, an error message will be output. If it is determined that a normal output signal is received from the previous power chip within a preset time period, then the step of outputting an enable signal to the current power chip to be enabled according to the preset power-on sequence is executed.

9. A control system, characterized in that, include: The main controller integrates the multi-power supply system as described in any one of claims 1-5.

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