Simulation device and simulation method

Abstract

Analog device, analog method, analog equipment and nonvolatile computer readable storage medium. The analog device is used to simulate the calculation of a spiking neural network model, and the device comprises an expression module, a flow module and a calculation module, wherein the expression module is configured to obtain the parameters of the spiking neural network model; the flow module is configured to determine first information associated with simulating the data calculation process of the spiking neural network model and second information associated with simulating the data storage process of the spiking neural network model based on the parameters of the spiking neural network model; and the calculation module is configured to simulate the data calculation process and the data storage process of the spiking neural network model based on the first information and the second information.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a simulation apparatus, simulation method, simulation device, and non-volatile computer-readable storage medium. Background Technology

[0002] Neuromorphic computing is a general term for computational theories, architectures, chip designs, application models, and algorithms that draw on the information processing modes and structures of biological nervous systems. Various neuromorphic computing systems with neuromorphic computing chips at their core are developing rapidly and are gradually showing their advantages in handling certain intelligent problems and low-power intelligent computing.

[0003] Spiking Neural Networks (SNNs) are a major computational paradigm in neuromorphic computing systems and are considered one of the important computational paradigms for next-generation neural networks. However, current spiking neural network frameworks are designed using a tightly coupled approach. As SNN functionality becomes increasingly complex, there is a growing demand for higher performance. The current tightly coupled design of spiking neural network frameworks can no longer meet the performance improvement requirements of SNNs. Summary of the Invention

[0004] Embodiments of this disclosure provide simulation apparatus, simulation method, simulation device, and non-volatile computer-readable storage medium.

[0005] At least one embodiment of this disclosure provides a simulation apparatus for simulating the computation of a spiking neural network model. The apparatus includes an expression module, a process module, and a calculation module. The expression module is configured to acquire parameters of the spiking neural network model. The process module is configured to determine, based on the parameters of the spiking neural network model, first information associated with the data computation process of simulating the spiking neural network model and second information associated with the data storage process of simulating the spiking neural network model. The calculation module is configured to simulate the data computation process and data storage process of the spiking neural network model based on the first information and the second information.

[0006] At least one embodiment of this disclosure provides a simulation method for simulating the computation of a spiking neural network model, comprising: acquiring parameters of the spiking neural network model; determining, based on the parameters of the spiking neural network model, first information associated with simulating the data computation process of the spiking neural network model and second information associated with simulating the data storage process of the spiking neural network model; and simulating the data computation process and data storage process of the spiking neural network model based on the first information and the second information.

[0007] At least one embodiment of this disclosure also provides a simulation device, the device including a memory and a processor, wherein the memory stores executable code, and when the executable code is executed by the processor, the processor performs the simulation method as described above.

[0008] At least one embodiment of this disclosure also provides a non-volatile computer-readable storage medium having executable code stored thereon, which, when executed by a processor, causes the processor to perform the simulation method as described above.

[0009] Embodiments of this disclosure also provide a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a verification method across multiple verification domains according to embodiments of this disclosure.

[0010] This disclosure provides at least one embodiment of a simulation apparatus, simulation method, simulation device, and non-volatile computer-readable storage medium. Based on the principle of hierarchical decoupling, the embodiments of this disclosure propose a novel spiking neural network simulation apparatus. Compared to traditional simulation apparatuses under tightly coupled frameworks, the spiking neural network simulation apparatus according to the embodiments of this disclosure is more flexible, achieving a balance between functionality and performance, thereby ensuring both functional completeness and high performance efficiency. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0012] Figure 1A This is a schematic diagram of a spiking neural network model according to an embodiment of the present disclosure.

[0013] Figure 1B The pseudocode for a typical tightly coupled architecture simulation device is shown.

[0014] Figure 2 This is a schematic diagram of a simulation device provided for at least one embodiment of the present disclosure.

[0015] Figure 3 This is a schematic diagram of an expression module provided in at least one embodiment of the present disclosure.

[0016] Figure 4 The following is a first example pseudocode illustrating how the flow module of an embodiment of this disclosure optimizes the first and second information.

[0017] Figure 5A Examples of process modules and computation modules optimized based on sparsity are shown in embodiments of this disclosure.

[0018] Figure 5B This illustrates yet another example of optimizing the process module and computing module of embodiments of the present disclosure based on hardware characteristics.

[0019] Figure 6 Partial pseudocode of the simulation device provided in at least one embodiment of this disclosure is shown.

[0020] Figure 7 A flowchart of a simulation method 70 according to at least one embodiment of the present disclosure is shown.

[0021] Figure 8 A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0022] Figure 9 A schematic diagram of the architecture of an exemplary computing device according to an embodiment of the present disclosure is shown.

[0023] Figure 10 A schematic diagram of a storage medium according to an embodiment of the present disclosure is shown. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising,” “including,” or “including,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0026] At least one embodiment of this disclosure provides a simulation apparatus for simulating the computation of a spiking neural network model. The apparatus includes an expression module, a process module, and a calculation module. The expression module is configured to acquire parameters of the spiking neural network model. The process module is configured to determine, based on the parameters of the spiking neural network model, first information associated with the data computation process of simulating the spiking neural network model and second information associated with the data storage process of simulating the spiking neural network model. The calculation module is configured to simulate the data computation process and data storage process of the spiking neural network model based on the first information and the second information.

[0027] At least one embodiment of this disclosure provides a simulation method for simulating the computation of a spiking neural network model, comprising: acquiring parameters of the spiking neural network model; determining, based on the parameters of the spiking neural network model, first information associated with simulating the data computation process of the spiking neural network model and second information associated with simulating the data storage process of the spiking neural network model; and simulating the data computation process and data storage process of the spiking neural network model based on the first information and the second information.

[0028] This disclosure provides at least one embodiment of a simulation apparatus, simulation method, simulation device, and non-volatile computer-readable storage medium. Based on the principle of hierarchical decoupling, the embodiments of this disclosure propose a novel spiking neural network model simulation framework. Compared to traditional spiking neural network model simulation frameworks, the spiking neural network model simulation framework according to the embodiments of this disclosure is more flexible, achieving a balance between functionality and performance, thereby ensuring both functional completeness and high performance efficiency.

[0029] The embodiments and examples of this disclosure will now be described in detail with reference to the accompanying drawings.

[0030] Figure 1A This is a schematic diagram of a spiking neural network model 100 according to an embodiment of the present disclosure.

[0031] Traditional neural networks are based on the multilayer perceptron (MLP) architecture, which simulates the human brain through multiple hidden layers. However, traditional neural networks may suffer from problems such as vanishing gradients, leading to increased training difficulty and weak inference effectiveness.

[0032] like Figure 1A As shown, compared to traditional neural networks, spiking neural network (SNN) models attempt to bridge the gap between neuroscience and machine learning by simulating the mechanisms of biological neurons. The neurons in spiking neural network models use... Figure 1AThe diagram illustrates communication via pulses, synapses, and postsynaptic potentials. A pulse is a time-based discrete value. A synapse is the structure connecting two neurons, each with its own delay and weight. Synapses convert pulses into postsynaptic potentials and transmit these potentials to the next neuron. Through this structure, because each synapse has a different delay and weight, pulses emitted by preceding neurons can have different effects on subsequent neurons within different timeframes. This mechanism allows spiking neural network models to better simulate the real conduction mechanisms of bioelectricity, thus making AI agents trained based on spiking neural network models more intelligent.

[0033] Because the working mechanism of spiking neural network (SNN) models is more complex than that of traditional neural networks, simulation devices adapted to this mechanism are needed to assist in the development, operation, and research of SNNs. Currently, several SNN simulation devices exist. For example, NEURON, NEST, and GeNN are commonly used SNN simulation devices. NEURON and NEST are both developed for computational neuroscience applications, emphasizing the realistic simulation of biological structures and functions. NEST is developed entirely in C++, centralizing the SNN model description, compilation, and simulation processes, with the running platform fixed to the CPU. The GeNN framework, on the other hand, accelerates performance using GPGPUs (general-purpose graphics processing units), i.e., it uses GPGPUs to execute the SNN simulation process. GeNN is also developed entirely in C++, centralizing the SNN model description and compilation processes to generate executable code.

[0034] However, the aforementioned simulation devices are typically designed using a tightly coupled approach, characterized by treating the simulation device as a whole. Whether it's the user-facing development interface (i.e., SNN developers and researchers) or the specific computing modules serving as the running hardware (such as CPU / GPGPU), the simulation device is implemented as a unified whole from top to bottom. Therefore, these simulation devices can also be referred to as simulation devices within a tightly coupled framework. In this paper, a tightly coupled framework refers to a centralized control development approach. Programs within a tightly coupled framework have strong interrelationships and dependencies, communicating and transmitting data through a centralized control system. Tightly coupled architectures are suitable for relatively simple environments; due to the tight connections between programs, their scalability and further development potential are relatively weak.

[0035] As SNN functionality becomes increasingly complex, there is a growing demand for higher performance. Current tightly coupled simulation architectures are no longer sufficient to meet these performance enhancement requirements. Tightly coupled architectures lack flexibility, making further performance improvements difficult without significant overall modifications to the simulation framework. Furthermore, adding or adjusting functionality may conflict with performance enhancement modules, making it challenging to simultaneously achieve both functional completeness and high performance efficiency.

[0036] For example, NEURON and NEST focus on functionality implementation, making it difficult to optimize internal data structures and simulation processes, as well as accelerate underlying computations, especially on other computing platforms (such as GPGPU). GeNN, on the other hand, is designed to optimize performance on GPGPU. If new features or adjustments are needed, they will conflict with its tightly coupled performance optimization modules, making it difficult to optimize the features.

[0037] Figure 1B The pseudocode for a typical tightly coupled architecture simulation device is shown. As... Figure 1B As shown, the tightly coupled scheme is a centralized control scheme (as defined by the method `def simulation()`), which uses the `storagecpu` method to arrange the CPU's memory (see reference). Figure 1B (Command line with gray background and black text). Figure 1B In this approach, for each loop, not only is each neuron group enumerated (as defined in the command line "for pin network.neurons" shown in black on white), but each neuron within each neuron group is also enumerated (as defined in the command line "for n in p" shown in black on white). As the code demonstrates, the commands within each loop in the traditional approach are fixed. If optimization of individual commands within the loop is needed, the entire function must be modified. Such modifications often lead to unexpected bugs.

[0038] Therefore, various embodiments of this disclosure provide a spiking neural network simulation device based on the principle of hierarchical decoupling, which is a spiking neural network simulation device under a loosely coupled architecture. In this document, a loosely coupled architecture refers to a distributed control development approach. In a loosely coupled architecture, the correlation and dependency between programs are weak, and programs communicate with each other through pre-defined interfaces. A loosely coupled architecture is suitable for more complex environments, and because the programs do not interfere with each other, it is more suitable for expansion and parallel development.

[0039] Next reference Figures 2 to 10The various embodiments of this disclosure will be further described below. Those skilled in the art should understand that this disclosure is not limited thereto.

[0040] Figure 2 This is a schematic diagram of a simulation device 20 provided in at least one embodiment of the present disclosure, which is used to simulate the calculation of a spiking neural network model.

[0041] like Figure 2 As shown, the device 20 includes an expression module 201, a process module 202, and a calculation module 203. The expression module 201, process module 202, and calculation module 203 transmit information in a loosely coupled manner. For example, the expression module 201 and process module 202 can be interconnected via a first interface (e.g., an application programming interface, also known as an API), and the process module 202 and calculation module 203 can be interconnected via a second interface. Furthermore, the device 20 may include more or fewer modules, such as a display module (not shown), etc. The display module and calculation module 203 can be interconnected via a third interface. Those skilled in the art should understand that this disclosure is not limited thereto.

[0042] The expression module 201 is configured to acquire parameters of the spiking neural network model. Optionally, the expression module 201 can send the parameters of the spiking neural network model to the process module 202 via a first interface.

[0043] The process module 202 is configured to determine, based on the parameters of the spiking neural network model, first information associated with the data computation process simulating the spiking neural network model and second information associated with the data storage process simulating the spiking neural network model. Optionally, the process module 202 can send the first and second information to the calculation module 203 via a second interface.

[0044] The calculation module 203 is configured to simulate the data calculation and data storage processes of a spiking neural network model based on the first and second information. Optionally, the calculation module 203 can transmit the results of the simulated data calculation and data storage processes of the spiking neural network model to the output module via a third interface.

[0045] The apparatus 20 according to an embodiment of this disclosure simulates the computation process of a spiking neural network model using three loosely coupled modules (i.e., an expression module 201, a process module 202, and a computation module 203). Compared to conventional tightly coupled architectures (e.g., NEURON and NEST), apparatus 20 isolates the expression module 201 and the computation module 203 through the aforementioned first and second interfaces, thereby optimizing the data structure design process and accelerating the underlying computation. Compared to other conventional tightly coupled architectures (e.g., GeNN), apparatus 20 further isolates the process module 202 and the computation module 203 through the second interface to avoid conflicts between the optimization of the process module 202 and the optimization of the computation module 203. Therefore, if adjustments to the simulation apparatus are needed, conflicts between its built-in modules will not occur, achieving a balance between functionality and performance, thus ensuring functional completeness and high performance efficiency.

[0046] The following is for reference Figure 3 Let's further explain the expression module 201. Figure 3 This is a schematic diagram of an expression module 201 provided in at least one embodiment of the present disclosure.

[0047] For example, the expression module 201 can be a computer program product written in programming languages ​​such as Python and C++, a non-volatile computer-readable storage medium storing executable code, or a programmable hardware circuit, etc. This disclosure uses a Python program as an example to describe the details of the expression module 201; those skilled in the art should understand that this disclosure does not limit the programming language. For ease of description, Python will be used to describe and define the parameters of the spiking neural network model, and based on this, the spiking neural network model whose data computation and data storage processes are to be simulated will be determined. Furthermore, in some example embodiments of this disclosure, other user-defined languages ​​(e.g., general-purpose SNN description languages ​​such as PyNN) can also be used to describe or define the parameters of the spiking neural network model. Those skilled in the art should understand that this disclosure is not limited thereto.

[0048] As an example, the parameters of the spiking neural network model may optionally include at least one of the following: parameters related to the neural primitives of the spiking neural network model, parameters related to the computing environment corresponding to the spiking neural network model, parameters for initializing the spiking neural network model, parameters for defining the computing method of the spiking neural network model, parameters for resetting the spiking neural network model, etc. This disclosure does not limit the types and value ranges of the parameters of the spiking neural network model; they can all be adjusted according to the specific spiking neural network model during the actual use of the device 20.

[0049] For example, the parameters related to the neural primitives of the spiking neural network model include at least one of the following: neuron-related parameters, synapse-related parameters, neuron group-related parameters, and parameters describing the connections between neuron groups (hereinafter also referred to as connection structure parameters), etc. Figure 3 As shown, the expression module 201 may acquire user-defined neuron and synapse models, or it may pre-set some neuron and synapse models. Neuron and synapse models can be collectively referred to as neural primitive models, such as common IF, LIF, HH, and Izhikevich neuron models.

[0050] When the simulation device 20 acquires a user-defined neural primitive model, it can also provide a fourth interface to allow the user to customize the spiking neural network model. The user can use this fourth interface to describe the internal parameters and calculation process of neurons in detail, thereby expanding the functionality of the simulation device 20. Furthermore, the fourth interface can also be used by the user to set parameters of the spiking neural network model (such as threshold voltage, refractory period length, etc.).

[0051] For example, users can... Figure 3 The pseudocode in the example defines a Jellylif neuron model. The code `class jellylif(Neuron):` defines a Jellylif neuron model; the code `def param_list(self,precision,param):` indicates that the parameters and variables in the Jellylif neuron model will be defined based on `self`, `precision`, and `param`. The parameters and variables in the Jellylif neuron model include, but are not limited to, those mentioned above. Figure 3 The values ​​shown include dtype (indicating the precision of the variable and parameter), vth (indicating the threshold voltage), vrest (reset voltage), tao (indicating the decay constant), v (voltage), input (input), rate (discharge rate), etc. For example, users can... Figure 3 The pseudocode in the document defines a synaptic model, where, as indicated by the pseudocode, synaptic delay and synaptic weight are both 1. Those skilled in the art will understand that... Figure 3 The description of the jellylif neuron model shown is merely an example, and this disclosure does not limit how synaptic models are declared.

[0052] For example, it can also be done through Figure 3 Similar pseudocode to that used in the example is used to define multiple neuron groups. For example, Figure 3The pseudocode shown illustrates the definition of two neuron groups, G1 and G2, which consist of 800 and 200 Izhikevich neurons, respectively. The i_e parameter of neurons in neuron group G1 is 6.0, while the i_e parameter of neurons in neuron group G2 is 8.0.

[0053] For example, parameters used to describe the connection between neurons also include at least one of the following: the internal state of the synapse constituting the connection between neurons (e.g., synaptic delay and synaptic weight) and the manner in which the synapse connects to the neuron (e.g., one-to-one connection, all-to-all connection, connection with a preset probability, etc.). This disclosure does not limit how the expression module declares the connection structure. Figure 3 As shown, net.all_to_all(G1,G2,S12,'exc') can be used to indicate that the two groups of neurons are connected in an all-to-all manner.

[0054] The expression module 201 will acquire parameters related to the computational environment corresponding to the spiking neural network model. For example, the expression module 201 will acquire parameters related to the computational environment of the data computation and data storage processes simulating the spiking neural network model. As an example, the expression module 201 will acquire or set parameters corresponding to the loops that the spiking neural network model needs to execute. Parameters corresponding to the loops that the spiking neural network model needs to execute include: the real-time execution of one loop, the number of loops, etc. For example, the expression module 201 will use... Figure 3 The pseudocode is used to set the parameters corresponding to the loops that the spiking neural network model needs to execute. Here, dt = 1.0 means that the actual time corresponding to one loop in the calculation process of running the spiking neural network model is 1 millisecond; T = dt * 500 means that a total of 500 loops need to be executed in the calculation process of running the spiking neural network model.

[0055] The expression module 201 can also initialize the spiking neural network model based on the parameters related to the aforementioned computing environment. For example, the expression module 201 can initialize the spiking neural network model using the pseudocode net = Network(dt = dt), where the code dt = dt passes the actual time corresponding to one loop execution as a parameter to the spiking neural network model.

[0056] The expression module 201 also allows users to specify the hardware environment in which the actual loop is executed. For example, the expression module 201 can use the pseudocode net.building(gpu='cuda:0') to indicate that the hardware environment for simulating the computation process of the spiking neural network model is a CUDA environment.

[0057] Figure 3 The document also includes pseudocode for initializing the parameters of the spiking neural network model. This code exemplifies a scheme for setting parameters in two groups of neurons based on key-value pairs, where different neurons can have different initialization parameters. Furthermore, pseudocode is shown for parameters defining the computational method of the spiking neural network model, illustrating some example schemes for transmitting voltage between neurons and between neurons and synapses. This involves determining whether to send a voltage from a neuron to the synapse connecting that neuron, at least in part, based on the neuron's own firing rate (self.rate). Additionally, parameters for resetting the spiking neural network model are shown, indicating how to clear the data stored in a neuron (e.g., resetting the neuron's pending firing voltage based on v.reset). Figure 3 Only a few examples have been given, and those skilled in the art should understand that the embodiments of this disclosure are not limited thereto.

[0058] As an example, a user can also input a command on the user interface to trigger the simulation device 20 to perform a simulation of the spiking neural network model (e.g., `$python brunel_easy.py`). During the execution of this command, after the expression module 201 parses the aforementioned parameters and commands, it can execute the command "ret = net.running(T, profiling = {'rate'})", which is passed to the process module 202 through the first interface to start the simulation of the spiking neural network model. Assuming the user previously defined that the firing frequency of each neuron group should be displayed after the simulation is completed, the calculation module 203 can then feed back the corresponding calculation results to the user interface after the calculation module 203 completes the calculation. The command related to the firing frequency is "for k,v in ret['rate'].items():

[0059] print('{}:{}Hz'.format(k,v / T*1000))”

[0060] The corresponding display format for this command can be "G1:6.0Hz" and "G2:8.0Hz".

[0061] The expression module 201 provided in this embodiment offers a user-friendly interaction method, which not only achieves sufficient functional expressiveness but also allows users to easily customize various parameters of the spiking neural network model without worrying about subsequent hardware execution-related performance issues.

[0062] Next reference Figures 4 to 5BExamples of the process module 202 and the calculation module 203 of embodiments of this disclosure will be further described below. Figure 4 The following is a first example pseudocode illustrating how the process module 202 of this disclosure optimizes the first and second information. Figure 5A An example of sparsity-based optimization of process module 202 and calculation module 203 according to embodiments of this disclosure is shown. Figure 5B This illustrates yet another example of how the process module 202 and the computing module 203 of the embodiments of this disclosure are optimized based on hardware characteristics.

[0063] As shown above, the process module 202 and the expression module 201 are connected through a first interface to receive references. Figure 3 The parameters of the spiking neural network model are described in detail. Process module 202 can convert these parameters into information that conforms to the reading and parsing rules of calculation module 203. That is, process module 202 is used to compile the spiking neural network model.

[0064] In one aspect, process module 202 can be configured to determine first information associated with the data computation process of simulating the spiking neural network model based on the parameters of the model. For example, the first information may optionally include the execution order and dependencies between various stages of the spiking neural network model's data processing. Specifically, example stages include at least two of a plurality of stages: a neuron update stage, a synaptic plasticity update stage, and a neuron spiking stage, with the first information indicating the sequence and dependencies between these stages. In some cases, process module 202 may also adjust the execution order based on the dependencies between these stages to optimize performance during the simulation process in a pipelined manner.

[0065] In another aspect, process module 202 can be configured to determine second information associated with the data storage process simulating the spiking neural network model, based on the parameters of the spiking neural network model. For example, the second information may optionally include: the manner in which the spiking neural network model stores data and the manner in which data is transferred between multiple stages of data processing in the spiking neural network model. The stored and transferred data includes voltages within each neuron, pulses fired by each neuron, potentials after each synapse, etc.

[0066] Based on the first and second information described above, the process module 202 can generate an executable file describing the spiking neural network model and transmit the executable file to the computation module 203 through the second interface. In one example of this disclosure, the executable file describes information about neurons, synapses, the structural information of the spiking neural network model, the computation process, etc. It is worth noting that the executable file does not need to consider how the computation module 203 executes the executable file or how the computation module 203 optimizes the execution of the executable file.

[0067] Although process module 202 does not involve specific optimization schemes for the execution of executable files, it can achieve load balancing and optimized execution efficiency by optimizing the first and second information. It is worth noting that the aforementioned optimization of the first and second information does not affect the optimization or design of expression module 201 and calculation module 203.

[0068] For example, refer to Figure 4 In some embodiments of this disclosure, process module 202 can optimize the first and second information to enable computation module 203 to more easily parallelize the processing of information across neurons, reducing the data read / write overhead of computation module 203 during the processing of cross-neuron groups. For example, process module 202 can preprocess the information of neuron groups (e.g., using the commands in the pseudocode "def process_optimize()…"). Process module 202 can merge neuron groups with the same type of neurons based on the information of the neuron groups (e.g., using the pseudocode "newn = merged(neurons,t)"), and generate the first and second information based on the information of the merged neuron groups. Thus, neurons of the same type can be stored contiguously within process module 202, even if these neurons of the same type come from different neuron groups. This further enables computation module 203 to more easily write the data of neurons of the same type to adjacent storage locations in the hardware, thereby reducing data read / write overhead.

[0069] For example, process module 202 can also optimize data dependencies between stages based on information from neuron groups, enabling the computation module to process neuron groups more easily in parallel. For instance, in the exemplary neuron update stage illustrated by pseudocode "defneuron_update():", process module 202 can enumerate each neuron group (e.g., refer to pseudocode "for p in network.neurons:") and generate (e.g., through compilation) an executable file that instructs the computation module to update neurons on a neuron group basis. Thus, computation module 202 can execute the executable file with higher parallelism.

[0070] For example, in some other embodiments of this disclosure, the process module 202 may further optimize the first information and the second information based on the sparsity characteristics of the spiking neural network model to generate a sparsity optimization operator so that the hardware device in the computing module 203 can simulate the data computing process and data storage process of the spiking neural network model with a balanced load.

[0071] For example, refer to Figure 5A The process module 202 can also determine first information based on the sparsity characteristics of the spiking neural network model. This first information indicates the use of multiple thread resources to compute the voltage firing information for each neuron. As an example, the process module 202 can use the method "def spike_prop_cuda_sparse(fires,connect,input:") to generate a sparsity optimization operator. The inputs of this operator include fires, connect, and input. Here, "fires" indicates the multiple neurons to fire; "connect" indicates the backward connections between neurons; and "input" indicates the weight input for each neuron at this time step.

[0072] The process module 202 compiles the sparse optimization operator and sends the compiled sparse optimization operator to the calculation module 203. The calculation module 203 is connected to the process module 202 through a second interface to receive the sparse optimization operator and use the sparse optimization operator to simulate the data calculation and data storage process of the spiking neural network model.

[0073] The computation module 203 uses N threads to process the sparsity optimization operator in parallel. As shown in the pseudocode, in the pseudocode of the actual computation of each thread, connect[i][j] represents the j-th connection of i neurons, connect[i][j].dst represents the target neuron number of the connection, and connect[i][j].weight represents the weight of the connection. That is, each thread from thread 0 to thread N undertakes the computation of voltage output of the i-th neuron.

[0074] For example, refer to Figure 5B The process module 202 can also determine first information based on the hardware characteristics of the computing module 203. This first information indicates the use of operators adapted to the hardware characteristics to simulate the data computation process of the spiking neural network model. For example, the computing module 203 can use a CPU, GPGPU, or dedicated hardware modules (such as FPGA chips, neuromorphic computing chips, etc.) to perform data computation on the spiking neural network model. Then, the process module 202 can generate dedicated operators adapted to the CPU, GPGPU, or dedicated hardware modules based on the characteristics of each of these hardware components.

[0075] For example, when using a GPGPU platform to perform data computation for a spiking neural network model, process module 202 can generate a dedicated operator adapted to the GPGPU platform. As an example, process module 202 can use the method "defneuron_update_cuda(fires,neurons,input:") to generate a CUDA operator whose input includes fires, neurons, and input. Here, "fires" indicates multiple neurons to be charged; "neurons" indicates multiple neurons (each containing several internal states); and "input" indicates the weight input for each neuron at that time step. Computation module 203 is connected to process module 202 via a second interface to receive the dedicated operator adapted to the GPGPU platform and uses this dedicated operator to simulate the data computation and data storage processes of the spiking neural network model.

[0076] Process module 202 compiles the CUDA operator and sends the compiled CUDA operator to computation module 203. Computation module 203 uses N threads to process the CUDA operator in parallel. Specifically, within each simulation time step of the data computation process simulating the spiking neural network model, each neuron in the spiking neural network model updates its internal state. In the pseudocode of the actual computation of each thread, each thread performs computation on its specific neuron neurons[j], thereby achieving parallel updates of each neuron among multiple neurons.

[0077] Since the computation module 203 has been decoupled from the process module 202 and the expression module 201, the data computation process of the spiking neural network model will not change if the neuron and synapse models remain unchanged. As... Figure 5A and Figure 5B As shown, sparse optimization operators or CUDA operators that can be executed on the GPGPU platform can be pre-compiled in the process module 202. During the simulation process in the computing module 203, no additional compilation time is required to run, thereby improving the execution response speed and thus improving the execution efficiency.

[0078] Furthermore, as an example of this disclosure, process module 202 can be implemented using Python and employs a Tensor structure to store the first and second information. The advantage of the Tensor structure lies in its mature data storage method, widely adopted by deep learning frameworks (such as PyTorch and Tensorflow). In addition, the Tensor structure has a clear operation interface and facilitates the transfer of data to computation module 203. The Tensor structure also helps to more easily implement the aforementioned optimization algorithms. Of course, this disclosure is not limited to this.

[0079] As can be seen, the process module 202 can not only flexibly execute various processes and adapt to different computing modes, but also improve the final execution performance through different optimization algorithms. In the computing module 203, the computing hardware completes the computational steps required to simulate the spiking neural network model. In some embodiments, the computing module 203 can not only perform the corresponding calculations and improve computing performance, but also provide an interface for the specific computation of newly added neural primitive models. Based on the "cross-neuron group parallel processing" and "sparse optimization operator" detailed above, the simulation device 20 greatly improves its operating efficiency, with an average running speed more than five times that of the fastest known open-source simulator.

[0080] Next reference Figure 6 To further describe an example of the simulation device 20 provided according to embodiments of the present disclosure. Figure 6 Partial pseudocode of the simulation device 20 provided in at least one embodiment of this disclosure is shown.

[0081] like Figure 6 As shown, the simulation device 20 can use the command line (network=user.network and network=process_optimize(network,user.config)) in gray background and black text as the first interface to transmit the parameters of the spiking neural network model obtained by the expression module 201 to the process module 202.

[0082] During the process of obtaining the corresponding first and second information in process module 202, the process module can use the command line "network.setup_storage(network.backend)" to trigger the process of determining the second information. It can adaptively set the storage based on the parameters obtained from "network.backend". Compared to... Figure 1B In the pseudocode, the simulation device 20 provided in the embodiments of this disclosure no longer centrally arranges the storage of the CPU, but performs distributed control.

[0083] Process module 202 can also use the `firing` parameter to conduct the voltage emitted during the neuronal spike firing phase to subsequent phases. For example, it can conduct the voltage to the subsequent synaptic update phase (e.g., using the command line `network.synapse_update(firing)`) and the postsynaptic voltage conduction phase (e.g., using the command line `network.spike_prop(firing)`). Figure 6 As shown, the simulation device 20 also correspondingly and separately defines the `synapse_update(firing)` and `spike_prop(firing)` methods. These methods, based on the `firing` parameter, define how to perform synaptic updates and propagation. Compared to Figure 1B The synaptic update and conduction process is described in an enumeration manner within a loop (e.g., "for s in network.synapse..."). The simulation device 20 further modularizes the synaptic update and conduction process to facilitate further optimization of these two processes.

[0084] Process module 202 further restricts neuron updates (for example, as defined by the neuron_update() method), taking into account whether the computing layer hardware is a GPU or a CPU during the neuron update process, and setting the firing parameter accordingly.

[0085] The computing module 203 further specifies how to perform neuron updates for the GPU, for example, it specifies how to update the firing rate and / or voltage (V) taking into account the GPU as the execution hardware environment.

[0086] Compared to Figure 1B The simulation device in Figure 6 The simulation device 20 with the loosely coupled architecture shown can be divided into several modules, each of which can be optimized and expanded, and the optimization and expansion of each module will not affect other modules.

[0087] Next reference Figure 7 The simulation method 70 of the embodiments of this disclosure will be further described below. Figure 7 A flowchart of a simulation method 70 according to at least one embodiment of the present disclosure is shown.

[0088] The simulation method 70 includes the following steps S701 to S703. Those skilled in the art should understand that this method is not limited thereto.

[0089] In step S701, the parameters of the spiking neural network model are obtained. Step S701 can be executed by the expression module 201.

[0090] For example, the parameters of the spiking neural network model include at least one of the following: parameters related to the neural primitives of the spiking neural network model, parameters related to the computing environment corresponding to the spiking neural network model, parameters for initializing the spiking neural network model, parameters for defining the computing method of the spiking neural network model, and parameters for resetting the spiking neural network model.

[0091] For example, the parameters related to the neural primitives of the spiking neural network model include at least one of the following: neuron-related parameters, synapse-related parameters, neuron group-related parameters, parameters describing the connection between neuron groups, and parameters describing the connection between neurons.

[0092] For example, the parameters used to describe the connection between neurons include at least one of the following: the internal state of the synapse constituting the connection between neurons, and the manner in which the synapse connects to the neuron. The internal state of the synapse includes synaptic delay and synaptic weight. The manner in which the synapse connects to the neuron includes one-to-one connection, all-to-all connection, and connection with a preset probability.

[0093] For example, the computational environment parameters corresponding to the spiking neural network model include at least one of the following: the actual time and number of loops for one execution of the spiking neural network model, and the type of hardware operating environment for actually executing the loop.

[0094] In step S702, based on the parameters of the spiking neural network model, first information associated with the data computation process simulating the spiking neural network model and second information associated with the data storage process simulating the spiking neural network model are determined. Step S702 can be executed by process module 202.

[0095] For example, the first information includes the execution order and dependencies between multiple stages of the data processing by the spiking neural network model, wherein the multiple stages include at least two of the following stages: neuron update stage, synaptic plasticity update stage, and neuron spiking stage.

[0096] For example, the second information includes: the way the spiking neural network model stores data and the way data is transmitted between multiple stages of the spiking neural network model's data processing, wherein the stored and transmitted data includes the voltage inside each neuron, the pulses emitted by each neuron, and the potentials after the pulses pass through each synapse.

[0097] For example, in step S702, an executable file describing the spiking neural network model can be generated based on the first information and the second information, and the executable file can be transmitted to the computing module.

[0098] For example, the determination of the first information associated with the data calculation process simulating the spiking neural network model based on the parameters of the spiking neural network model further includes: merging neuron groups with the same type of neurons based on the information of the neuron groups, and generating the first information based on the information of the merged neuron groups, so that neurons of the same type are stored continuously.

[0099] For example, the method of generating an executable file describing a spiking neural network model further includes: enumerating each neuron group based on information about the neuron group, generating an executable file based on the first information and the second information, wherein the executable file instructs the computing module to update neurons on a neuron group basis.

[0100] For example, determining the first information associated with simulating the data computation process of the spiking neural network model based on the parameters of the spiking neural network model further includes: determining the first information based on the sparsity characteristics of the spiking neural network model, wherein the first information indicates the use of resources from multiple threads to compute the voltage firing information of each neuron; and / or determining the first information based on the hardware characteristics of the computing module, wherein the first information indicates the use of operators adapted to the hardware characteristics to simulate the data computation process of the spiking neural network model.

[0101] In step S703, based on the first information and the second information, the data calculation process and data storage process of the spiking neural network model are simulated. Step S703 can be executed by the calculation module.

[0102] The method 70 of this disclosure proposes a novel approach to simulating a spiking neural network model based on the principle of hierarchical decoupling. Compared to traditional simulation methods within a tightly coupled framework, the method 70 according to embodiments of this disclosure is more flexible, achieving a balance between functionality and performance, thereby ensuring both functional completeness and high performance efficiency.

[0103] According to another aspect of this disclosure, an electronic device is also provided for performing the method. Figure 8 A schematic diagram of an electronic device 2000 according to an embodiment of the present disclosure is shown.

[0104] like Figure 8 As shown, the electronic device 2000 may include one or more processors 2010 and one or more memories 2020. The memories 2020 store computer-readable code that, when executed by the one or more processors 2010, can perform the verification method across multiple verification domains as described above.

[0105] The processor in this embodiment can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor, and can be based on an x86 architecture or an ARM architecture.

[0106] In general, the various exemplary embodiments of this disclosure can be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device. When aspects of embodiments of this disclosure are illustrated or described as block diagrams, flowcharts, or using some other graphical representation, it will be understood that the blocks, apparatuses, systems, techniques, or methods described herein can be implemented as non-limiting examples in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0107] For example, the method or apparatus according to embodiments of this disclosure can also be used by means of Figure 9 The architecture of the computing device 3000 shown is used for implementation. For example... Figure 9As shown, the computing device 3000 may include a bus 3010, one or more CPUs 3020, a read-only memory (ROM) 3030, a random access memory (RAM) 3040, a communication port 3050 connected to a network, an input / output component 3060, a hard disk 3070, etc. The storage devices in the computing device 3000, such as the ROM 3030 or the hard disk 3070, may store various data or files used in the processing and / or communication of the method for determining the driving risk of a vehicle provided in this disclosure, as well as program instructions executed by the CPU. The computing device 3000 may also include a user interface 3080. Of course, Figure 7 The architecture shown is merely exemplary and can be omitted as needed when implementing different devices. Figure 7 One or more components in the computing device shown.

[0108] According to another aspect of this disclosure, a computer-readable storage medium is also provided. Figure 10 A schematic diagram 4000 of a storage medium according to the present disclosure is shown.

[0109] like Figure 10 As shown, the computer storage medium 4020 stores computer-readable instructions 4010. When the computer-readable instructions 4010 are executed by a processor, a verification method across multiple verification domains according to embodiments of the present disclosure, as described with reference to the above figures, can be performed. The computer-readable storage medium in the embodiments of the present disclosure may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct memory bus random access memory (DR RAM). It should be noted that the memory used in the methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0110] Embodiments of this disclosure also provide a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a method according to an embodiment of this disclosure.

[0111] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0112] In general, the various exemplary embodiments of this disclosure can be implemented in hardware or dedicated circuitry, software, firmware, logic, or any combination thereof. Some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device. When aspects of embodiments of this disclosure are illustrated or described as block diagrams, flowcharts, or using some other graphical representation, it will be understood that the blocks, apparatuses, systems, techniques, or methods described herein can be implemented as non-limiting examples in hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0113] The exemplary embodiments of this disclosure described in detail above are merely illustrative and not restrictive. Those skilled in the art will understand that various modifications and combinations of these embodiments or their features can be made without departing from the principles and spirit of this disclosure, and such modifications should fall within the scope of this disclosure.

Claims

1. A simulation device for simulating the computation of a spiking neural network model, the device comprising an expression module, a process module, and a computation module, wherein, The expression module is configured to acquire parameters of a spiking neural network model and send the parameters of the spiking neural network model to the process module through a first interface; The process module is configured to determine, based on the parameters of the spiking neural network model, first information associated with the data calculation process simulating the spiking neural network model and second information associated with the data storage process simulating the spiking neural network model, and send the first information and the second information to the calculation module through a second interface; The computing module is configured to simulate the data calculation and data storage processes of the spiking neural network model based on the first information and the second information. The first information includes the execution order and dependencies between multiple stages of the data processing by the spiking neural network model, and the second information includes the method of storing data by the spiking neural network model and the method of transmitting data between multiple stages of the data processing by the spiking neural network model.

2. The simulation device as claimed in claim 1, wherein, The parameters of the spiking neural network model include at least one of the following: parameters related to the neural primitives of the spiking neural network model, parameters related to the computing environment corresponding to the spiking neural network model, parameters for initializing the spiking neural network model, parameters for defining the computing method of the spiking neural network model, and parameters for resetting the spiking neural network model.

3. The simulation device as described in claim 2, wherein, The parameters related to the neural primitives of the spiking neural network model include at least one of the following: neuron-related parameters, synapse-related parameters, neuron group-related parameters, parameters describing the connection between neuron groups, and parameters describing the connection between neurons.

4. The simulation device as described in claim 3, wherein, The relevant parameters used to describe the connection between neurons include at least one of the following: the internal state of the synapse that constitutes the connection between neurons, and the way the synapse connects to the neuron; The internal state of the synapse includes synaptic delay and synaptic weight. The synaptic connections between neurons can be one-to-one, all-to-all, or with a preset probability.

5. The simulation apparatus as described in claim 2, wherein, The computational environment parameters corresponding to the spiking neural network model include at least one of the following: the actual time and number of loops for one execution of the spiking neural network model, and the type of hardware operating environment for actually executing the loop.

6. The simulation apparatus as claimed in claim 1, wherein, The multiple phases include at least two of the following multiple phases: neuronal renewal phase, synaptic plasticity renewal phase, and neuronal spiking phase.

7. The simulation apparatus as claimed in claim 1, wherein, The stored and transmitted data includes the voltage inside each neuron, the pulses emitted by each neuron, and the potentials after the pulses pass through each synapse.

8. The simulation apparatus as claimed in claim 1, wherein, The process module is configured to: generate an executable file describing a spiking neural network model based on the first information and the second information, and transmit the executable file to the calculation module.

9. The simulation apparatus as claimed in claim 1, wherein, The first information, determined based on the parameters of the spiking neural network model, and associated with the data calculation process simulating the spiking neural network model, further includes: Based on information from neuron groups, neuron groups with the same type of neurons are merged. Based on the information from the merged neuron groups, first information is generated so that neurons of the same type are stored consecutively.

10. The simulation apparatus as claimed in claim 8, wherein, The executable file that generates the description of the spiking neural network model also includes: Based on the information from the neuron groups, enumerate each neuron group. Based on the first information and the second information, an executable file is generated, which instructs the computing module to update neurons in units of neuron groups.

11. The simulation apparatus as claimed in claim 1, wherein, The first information, determined based on the parameters of the spiking neural network model, and associated with the data calculation process simulating the spiking neural network model, further includes: Based on the sparsity characteristics of the spiking neural network model, first information is determined, which indicates the use of resources from multiple threads to compute the voltage firing information of each neuron; and / or Based on the hardware characteristics of the computing module, first information is determined, which indicates the use of operators adapted to the hardware characteristics to simulate the data computation process of the spiking neural network model.

12. A simulation method for simulating the computation of a spiking neural network model, comprising: Obtain the parameters of the spiking neural network model and send the parameters of the spiking neural network model through the first interface; Based on the parameters of the spiking neural network model, first information associated with the data calculation process simulating the spiking neural network model and second information associated with the data storage process simulating the spiking neural network model are determined, and the first information and the second information are sent through the second interface; as well as Based on the first information and the second information, the data calculation and data storage processes of the spiking neural network model are simulated. The first information includes the execution order and dependencies between multiple stages of the data processing by the spiking neural network model, and the second information includes the method of storing data by the spiking neural network model and the method of transmitting data between multiple stages of the data processing by the spiking neural network model.

13. The simulation method as described in claim 12, wherein, The parameters of the spiking neural network model include at least one of the following: parameters related to the neural primitives of the spiking neural network model, parameters related to the computing environment corresponding to the spiking neural network model, parameters for initializing the spiking neural network model, parameters for defining the computing method of the spiking neural network model, and parameters for resetting the spiking neural network model.

14. The simulation method as described in claim 13, wherein, The parameters related to the neural primitives of the spiking neural network model include at least one of the following: neuron-related parameters, synapse-related parameters, neuron group-related parameters, parameters describing the connection between neuron groups, and parameters describing the connection between neurons.

15. The simulation method as described in claim 14, wherein, The relevant parameters used to describe the connection between neurons include at least one of the following: the internal state of the synapse that constitutes the connection between neurons, and the way the synapse connects to the neuron; The internal state of the synapse includes synaptic delay and synaptic weight. The synaptic connections between neurons include one-to-one connections, all-to-all connections, and connections with a preset probability. The computational environment parameters corresponding to the spiking neural network model include at least one of the following: the actual time and number of loops for one execution of the spiking neural network model, and the type of hardware operating environment for actually executing the loop.

16. The simulation method as described in claim 12, wherein, The plurality of phases includes at least two of the following: neuronal renewal phase, synaptic plasticity renewal phase, neuronal impulse firing phase; and / or The stored and transmitted data includes the voltage inside each neuron, the pulses emitted by each neuron, and the potentials after the pulses pass through each synapse.

17. The simulation method as described in claim 12, wherein, The determination of the first information associated with the data calculation process simulating the spiking neural network model and the second information associated with the data storage process simulating the spiking neural network model further includes: generating an executable file describing the spiking neural network model based on the first information and the second information, and transmitting the executable file to the calculation module.

18. The simulation method as described in claim 12, wherein, The first information, determined based on the parameters of the spiking neural network model, and associated with the data calculation process simulating the spiking neural network model, further includes: Based on information from neuron groups, neuron groups with the same type of neurons are merged. Based on the information from the merged neuron groups, first information is generated so that neurons of the same type are stored consecutively.

19. The simulation method as described in claim 17, wherein, The executable file that generates the description of the spiking neural network model also includes: Based on the information from the neuron groups, enumerate each neuron group. Based on the first information and the second information, an executable file is generated, which instructs the computing module to update neurons in units of neuron groups.

20. The simulation method as described in claim 12, wherein, The first information, determined based on the parameters of the spiking neural network model, and associated with the data calculation process simulating the spiking neural network model, further includes: Based on the sparsity characteristics of the spiking neural network model, first information is determined, which indicates the use of resources from multiple threads to compute the voltage firing information of each neuron; and / or Based on the hardware characteristics of the computing module, first information is determined, which indicates the use of operators adapted to the hardware characteristics to simulate the data computation process of the spiking neural network model.

21. A simulation device, comprising: processor; and A memory, wherein the memory stores computer-executable code, which, when run by the processor, performs the simulation method according to any one of claims 12-20.

22. A non-volatile computer-readable storage medium having executable code stored thereon, said executable code, when executed by a processor, causing the processor to perform the simulation method according to any one of claims 12-20.

Images