Display device, driving method thereof, and display equipment

Abstract

The embodiments of the present application provide a display device and a driving method thereof, and a display apparatus. The display device includes a sub-pixel array, a plurality of first shift registers, or a plurality of selectors. The sub-pixel array includes a plurality of sub-pixel units arranged in an array, and the sub-pixel unit includes N sub-pixel circuits; when the sub-pixel unit corresponds to N first shift registers, in the data writing phase, the N first shift registers output the first scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner; when the sub-pixel unit corresponds to N selectors, in the data writing phase, the N selectors receive the selection signal in a time-sharing manner to be turned on to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner. By adopting the present application, not only can the driving current be increased to meet the high-current pixel requirements of the display device, but also the driving of the IC will not be affected, and the problem of being unable to drive multiple sub-pixel circuits will not occur, thereby ensuring the display effect.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display device and a driving method thereof, and a display apparatus. Background Art

[0002] With the development of industries such as outdoor advertising and indoor education, large-screen displays have become a significant branch of the display industry. A typical indoor spliced ​​screen is composed of multiple LCDs (Liquid Crystal Displays) or Mini LEDs (submillimeter light-emitting diodes). LCDs have unavoidable seams due to the borders, while Mini LEDs are expensive due to the difficulty of the mass transfer process required for refined displays. Therefore, OLEDs (Organic Light-Emitting Diodes) are poised to become a key development direction in this field.

[0003] The PPI (Pixels Per Inch, pixel density unit) of the spliced ​​display device is low, requiring a very large driving current for the sub-pixels, with the current value of the driving current reaching the uA (microampere) level.

[0004] Existing methods for increasing driving current all involve increasing the capacitance of the sub-pixel circuit. Increasing the capacitance by several or dozens of times will affect the driving capability of the IC. Since the driving capability of the IC is limited, it may cause the IC to be unable to drive multiple sub-pixel circuits simultaneously. Summary of the Invention

[0005] In response to the shortcomings of existing methods, this application proposes a display device and its driving method, and a display equipment to solve the technical problem in the existing technology that the increase of driving current affects the driving capability of the IC, which may cause the IC to be unable to drive multiple sub-pixel circuits at the same time.

[0006] In a first aspect, an embodiment of the present application provides a display device, comprising:

[0007] A sub-pixel array, wherein the sub-pixel array includes a plurality of sub-pixel units arranged in an array and a light-emitting element, wherein each of N sub-pixel circuits is connected to the anode of the light-emitting element, and the sub-pixel unit includes N sub-pixel circuits, where N is an integer not less than 1;

[0008] Multiple first shift registers or multiple selectors, each sub-pixel unit corresponds to N first shift registers, or each sub-pixel unit corresponds to N selectors;

[0009] When the sub-pixel unit corresponds to N first shift registers, the N first shift registers are connected to the N sub-pixel circuits in a one-to-one correspondence, and the N sub-pixel circuits are connected to one data line. During the data writing phase, the N first shift registers output the first scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner.

[0010] When the sub-pixel unit corresponds to N selectors, the N selectors are connected to the N sub-pixel circuits one-to-one, and the N selectors are connected to one data line. In the data writing phase, the N selectors receive the selection signal in a time-sharing manner and are turned on to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner.

[0011] In a possible implementation, it further includes a plurality of second shift registers;

[0012] The sub-pixel unit corresponds to one second shift register;

[0013] A second shift register is connected to the N sub-pixel circuits and is used to output a light-emitting control signal to the N sub-pixel circuits in a light-emitting phase to control the light-emitting element to emit light.

[0014] In one possible implementation, when the sub-pixel unit corresponds to N first shift registers, the N first shift registers are connected one-to-one with the N sub-pixel circuits, and the N sub-pixel circuits are connected to a first signal terminal. In the reset phase, the N first shift registers output the second scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the reset signal of the first signal terminal in a time-sharing manner.

[0015] In a possible implementation, when the sub-pixel unit corresponds to N selectors, the display device further includes a plurality of first shift registers;

[0016] The sub-pixel unit corresponds to one first shift register;

[0017] A first shift register is connected to the N sub-pixel circuits and is used to output a third scanning signal to the N sub-pixel circuits in a reset phase to control the sub-pixel circuits to reset.

[0018] In one possible implementation, the light-emitting element includes an organic light-emitting device, which includes an anode, a light-emitting layer, and a cathode;

[0019] The anode is connected to the N sub-pixel circuits, and the cathode is connected to the second signal terminal.

[0020] In a possible implementation, the display device includes at least two display panels spliced ​​together; the display panel includes a display area and a non-display area;

[0021] The sub-pixel array is located in the display area;

[0022] Multiple selectors are located in the non-display area.

[0023] In a possible implementation, it further includes a source driving circuit;

[0024] The source driving circuit includes a plurality of output terminals; each output terminal is connected to a data line.

[0025] In a second aspect, an embodiment of the present application provides a display device, comprising the display apparatus according to the first aspect.

[0026] In a third aspect, an embodiment of the present application provides a method for driving a display device, which is applied to the display device according to the first aspect, comprising:

[0027] In the data writing phase, the N first shift registers output the first scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner;

[0028] Alternatively, in the data writing phase, N selectors receive the selection signal in a time-sharing manner and are turned on to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner.

[0029] In a possible implementation, the method further includes:

[0030] In the light-emitting phase, a light-emitting control signal is output to N sub-pixel circuits to control the light-emitting elements to emit light.

[0031] In a possible implementation, when the sub-pixel unit corresponds to N first shift registers, the method further includes:

[0032] In the reset phase, the N first shift registers output the second scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the reset signal from the first signal terminal in a time-sharing manner.

[0033] In a possible implementation, when the sub-pixel unit corresponds to N selectors, the method further includes:

[0034] In the reset phase, a third scanning signal is output to the N sub-pixel circuits to control the sub-pixel circuits to reset.

[0035] The beneficial technical effects brought about by the technical solutions provided in the embodiments of the present application include:

[0036] The display device provided in the embodiment of the present application controls multiple independent sub-pixel circuits to receive data signals on the data line in a time-sharing manner during the data writing phase by adding a first shift register or by adding a selector. Compared with the prior art, multiple independent sub-pixel circuits simultaneously receive data signals on the data line during the data writing phase. This not only increases the driving current to meet the high-current pixel requirements of the display device, but also does not affect the driving of the IC, and does not cause the problem of being unable to drive multiple sub-pixel circuits, thereby ensuring the display effect.

[0037] Additional aspects and advantages of the present application will be given in part in the following description, which will become apparent from the following description, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0039] Figure 1 A schematic diagram of the architecture of a driving solution for a display device provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of a connection scheme for a display device provided in an embodiment of the present application;

[0041] Figure 3 A timing diagram of a driving method for a display device provided in an embodiment of the present application;

[0042] Figure 4 A connection diagram of another driving scheme for a display device provided in an embodiment of the present application;

[0043] Figure 5 A timing diagram of another method for driving a display device provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of the layout of a single display panel in a display device provided in an embodiment of the present application;

[0045] Figure 7 A schematic flow chart of a method for driving a display device provided in an embodiment of the present application;

[0046] Figure 8 A schematic flow chart of another method for driving a display device provided in an embodiment of the present application.

[0047] Reference numerals:

[0048] 1-display device, 11-sub-pixel unit, 12-selector, 10-display area, 20-source driving circuit, 13-non-display area. DETAILED DESCRIPTION

[0049] The present application is described in detail below. Examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components having the same or similar functions. In addition, if the detailed description of the known technology is not necessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0050] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0051] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0052] The inventors of the present application have discovered through research that a display device formed by splicing at least two display panels together is relatively large in size, and therefore the PPI (Pixels Per Inch, pixel density unit) of its subunits (display panels) is relatively low. For example, the PPI of a conventional 0.722um (micrometer) Pitch is only about 34. However, in order to meet the long life requirements of the spliced ​​display device, the OLED pixel area is large and the pixel current is large. Compared with the conventional mobile phone OLED pixel current of tens of nA (nanoamperes), the pixel current of the OLED spliced ​​display device is in the uA (microampere) level, which is about 10 times the current.

[0053] Under the premise of meeting the driving range of the IC (chip) under the LTPS (Low Temperature Poly-Silicon) backplane, the main methods to increase the driving current are: 1) increasing the aspect ratio of the driving transistor in the sub-pixel circuit or connecting multiple driving transistors in parallel; 2) connecting multiple sub-pixel circuits to the anode of the same light-emitting element to realize multiple sub-pixel circuit driving.

[0054] However, both of the above two existing methods increase the capacitance of the sub-pixel circuit. Increasing the capacitance by several or dozens of times will affect the driving capability of the IC. Since the driving capability of the IC is limited, it may cause the IC to be unable to drive multiple sub-pixel circuits simultaneously.

[0055] The embodiments of the present application provide a display device and a driving method thereof, as well as a display apparatus, to solve the technical problem in the prior art that an increase in driving current affects the driving capability of an IC, which may cause the IC to be unable to drive multiple sub-pixel circuits simultaneously.

[0056] The following describes in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems with specific embodiments.

[0057] The embodiment of the present application provides a display device, such as Figure 1 and Figure 4 As shown, the display device 1 includes: a sub-pixel array, a plurality of first shift registers (such as Figure 1 Gate(i), Gate(i+1), Gate(i+2), Gate(i+3), Gate(i+4), Gate(i+5)) or multiple selectors (such as Figure 4 MUX1, MUX2, MUX3).

[0058] The sub-pixel array includes a plurality of sub-pixel units 11 arranged in an array. The sub-pixel unit 11 includes N sub-pixel circuits and one light-emitting element. The N sub-pixel circuits are all connected to the anode of one light-emitting element, where N is an integer not less than 1.

[0059] The structure of the light emitting element can include multiple types, which can be selected according to actual needs. For example, the light emitting element can be OLED, quantum dot light emitting diode (QLED) or micro light emitting diode (Micro LED). Figure 1 As shown, the sub-pixel unit 11 corresponds to N first shift registers, and N is taken as an example. Or, as Figure 4 As shown, the sub-pixel unit 11 corresponds to N selectors 12 , and N is taken as 3 as an example in the figure.

[0060] like Figure 1 、 Figure 2 and Figure 3 As shown, when the sub-pixel unit 11 corresponds to N first shift registers, the N first shift registers are connected to the N sub-pixel circuits in a one-to-one correspondence, and the N sub-pixel circuits are connected to one data line. In the data writing phase, the N first shift registers output the first scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner;

[0061] like Figure 4 and Figure 5 As shown, when the sub-pixel unit 11 corresponds to N selectors 12, the N selectors 12 are connected to the N sub-pixel circuits one-to-one, and the N selectors 12 are connected to one data line. In the data writing stage, the N selectors 12 receive the selection signal in a time-sharing manner and are turned on to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner.

[0062] The display device provided in the embodiment of the present application controls multiple independent sub-pixel circuits to receive data signals on the data line in a time-sharing manner during the data writing phase by adding a first shift register or by adding a selector. Compared with the prior art, multiple independent sub-pixel circuits simultaneously receive data signals on the data line during the data writing phase. This not only increases the driving current to meet the high-current pixel requirements of the display device, but also does not affect the driving of the IC, and does not cause the problem of being unable to drive multiple sub-pixel circuits, thereby ensuring the display effect.

[0063] It should be noted that, in the case of a low PPI display device, it is easy to implement only the first shift register (Gate GOA). Alternatively, in the case of a low PPI display device, only the selector (MUX) can be added, thereby increasing the number of data lines within the display area. However, the selector's on-time is short, which has no impact on the charging of each sub-pixel circuit.

[0064] In one possible implementation, Figure 2 and Figure 4 As shown, the display device further includes a plurality of second shift registers (such as Figure 1 EM(i~i+2), EM(i+3~i+5) in Figure 2 EM and Figure 4 EM in );

[0065] The sub-pixel unit 11 corresponds to one second shift register. Figure 2-5 As shown, one second shift register is connected to N sub-pixel circuits and is used to output a light-emitting control signal to the N sub-pixel circuits in the light-emitting phase to control the light-emitting element to emit light.

[0066] In one possible implementation, Figure 2 As shown, when the sub-pixel unit 11 corresponds to N first shift registers, the N first shift registers are connected to the N sub-pixel circuits one-to-one, and the N sub-pixel circuits are connected to a first signal terminal Vini. In the reset phase, the N first shift registers output the second scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the reset signal of the first signal terminal Vini in a time-sharing manner.

[0067] Figure 1 、 Figure 2 and Figure 3 For the first driving scheme, Figure 4 、 Figure 5 and Figure 6 This is the second driving scheme, and the two are parallel driving schemes.

[0068] In a specific embodiment, Figure 1 As shown, Figure 1 In the figure, the R sub-pixel circuit represents a red sub-pixel circuit, the G sub-pixel circuit represents a green sub-pixel circuit, and the B sub-pixel circuit represents a blue sub-pixel circuit. Gate(i), Gate(i+1), Gate(i+2), Gate(i+3), Gate(i+4), and Gate(i+5) all represent first shift registers, or they can also be called GateGOA circuits; EM(i~i+2) and EM(i+3~i+5) all represent second shift registers, or they can also be called EMGOA circuits, where i is an integer not less than 1. One second shift register is connected to each sub-pixel circuit in the sub-pixel unit 11, and each first shift register is connected to each sub-pixel circuit in the sub-pixel unit 11 in a one-to-one correspondence.

[0069] A pixel unit is composed of three sub-pixel units 11: R (red), G (green), and B (blue), each of which is composed of an independent pixel circuit. A single sub-pixel unit 11 is driven by multiple sub-pixel circuits (three in the figure). The multiple sub-pixel circuits of a single sub-pixel unit 11 are driven by multiple Gate GOA circuits, where the Gate GOA drives the multiple sub-pixel circuits in a single sub-pixel unit 11 in a 1:1 ratio, that is, the Gate GOA is connected to the multiple sub-pixel circuits in the sub-pixel unit 11 in a one-to-one correspondence, and the Gate GOA drives the sub-pixel circuits connected to it accordingly. The EM GOA drives multiple sub-pixel circuits in a single sub-pixel unit in a 1:3 ratio, that is, the EM GOA is connected to the multiple sub-pixel circuits in the sub-pixel unit 11, and the EM GOA drives the sub-pixel circuits connected to it simultaneously.

[0070] For example, Figure 1In the example, three sub-pixel circuits drive one sub-pixel, and one pixel unit includes nine sub-pixel circuits (three each of R, G, and B sub-pixel circuits). That is, one pixel unit is driven by three Gate GOAs and one EM GOA.

[0071] Optionally, Figure 1 The figure only shows the case of unilateral driving, that is, Gate GOA and EM GOA are only located on one side of the display panel. In practice, bilateral driving can also be used, that is, Gate GOA and EM GOA are located on both sides of the display panel. This application does not make any special restrictions.

[0072] In another specific embodiment, Figure 2 and Figure 3 As shown, the sub-pixel unit 11 corresponds to N first shift registers (Gate GOA). For the convenience of description, only N=3 is used as an example. N can be 2, 3, 4, 5, 6, 7, 8, 9, 10 or other integers not less than 1.

[0073] The sub-pixel unit 11 includes three sub-pixel circuits, namely sub-pixel circuit 1, sub-pixel circuit 2, and sub-pixel circuit 3. Sub-pixel circuit 1, sub-pixel circuit 2, and sub-pixel circuit 3 are all connected to the anode of the light-emitting element EL, and the cathode of the light-emitting element EL is connected to the second signal terminal ELVSS.

[0074] Figure 2 In the example, three sub-pixel circuits (or more) are used to simultaneously drive a light-emitting element EL. Figure 2 The signals of the first signal terminal Vini, the second signal terminal ELVSS, the third signal terminal ELVDD, and the data signal terminal Data connected to sub-pixel circuit 1, the first signal terminal Vini, the second signal terminal ELVSS, the third signal terminal ELVDD, and the data signal terminal Data connected to sub-pixel circuit 2, and the first signal terminal Vini, the second signal terminal ELVSS, the third signal terminal ELVDD, and the data signal terminal Data connected to sub-pixel circuit 3 are shared. The data signal terminal Data is used to receive the data signal output by the source driver circuit. A Gate GOA independently drives one sub-pixel circuit, and an EM GOA simultaneously drives three sub-pixel circuits; the three sub-pixel circuits are connected in parallel to the anode of the light-emitting element EL, and the cathode of the light-emitting element EL is connected to the second signal terminal ELVSS. Since the PPI (Pixels Per Inch, pixel density unit) of the spliced ​​display device is low, a larger sub-pixel driving current is required. Therefore, multiple sub-pixel circuits need to be driven together to achieve multiple sub-pixel circuits driving the same light-emitting element EL, thereby increasing the driving current.

[0075] Figure 3Gate1, Gate2, and Gate3 are Figure 2 The signals output by the three GateGOA circuits Gate(i), Gate(i+1), and Gate(i+2); Data represents Figure 2 The data signal output by the data signal terminal Data; EM stands for Figure 2 The light-emitting control signal output by the EM GOA circuit.

[0076] During the data writing phase (T1) of each sub-pixel circuit, EM is set to a high level, so that each sub-pixel circuit writes the same data signal in a time-sharing manner (e.g. Figure 3 The same Data in the sub-pixel circuits is connected to the same data signal terminal Data, that is, since each sub-pixel circuit is connected to the same data signal terminal Data, during the data writing process of the sub-pixel circuits, the Data value of the sub-pixel unit is the same. Figure 3 The data writing phase (T1) shown in FIG. 1 is the data writing time, and is also the reset time of the next row of sub-pixels.

[0077] During the light emitting phase (T2) of each sub-pixel circuit, EM is set to a low level, and the three sub-pixel circuits are simultaneously enabled, and the light emitting elements EL are driven to emit light at the same time.

[0078] In the display device provided in the embodiment of the present application, only the number of Gate GOAs corresponding to the number of sub-pixel circuits is increased, and the number of EMGOAs remains unchanged, that is, the number of EMGOAs is the same as the resolution of the display device; the number of data lines (Data) remains unchanged, that is, the number of data lines is the same as the resolution of the display device.

[0079] For example, an OLED spliced ​​screen with a resolution of 270×192 Real RGB (the traditional sub-pixel arrangement is called Real RGB, which divides square pixels into three sub-pixels and gives them red, green, and blue colors) is a display device formed by splicing at least two display panels together. The resolution of a single display panel is 270×192. Under conventional design, 1H takes about 60us (that is, the time taken to drive a row of sub-pixel units at 60Hz); the number of data lines (Data) is 192×3, and the number of Gate GOA and EM GOA is 270.

[0080] For example, 6 sub-pixel circuits are connected in parallel to drive the same light-emitting element, that is, 6 sub-pixel circuits are connected in parallel to drive the same sub-pixel. The 1H time is 60 / 6=10us (microseconds), which is sufficient for charging on a mobile phone. The number of data lines (Data) remains unchanged at 192×3, the number of Gate GOAs is 270×6=1620, and the number of EM GOAs is 270.

[0081] In this application, if the display device has a resolution of V×H and a frame rate of 60 Hz, the charging time corresponding to a pixel is 1 / 60 / V, and the charging time corresponding to multiple sub-pixel circuits is 1 / 60 / V / N, where " / " represents a division sign and N is the number of independent sub-pixel circuits in the same pixel. The number of Gate GOAs is V×N, the number of EM GOAs remains unchanged, and the number of data lines remains unchanged.

[0082] The display device provided in the embodiment of the present application provides a high-current pixel circuit through a parallel driving design of multiple sub-pixel circuits. The multi-level Gate GOA drives each sub-pixel circuit of a sub-pixel unit respectively; the first-level EM GOA simultaneously drives multiple sub-pixel circuits of a sub-pixel unit, and the multiple sub-pixel circuits are connected to the anode of the same light-emitting element.

[0083] The display device provided in the embodiment of the present application has the following improved effects through a new pixel drive design:

[0084] (1) By driving a light-emitting element simultaneously through multiple independent sub-pixel circuits, the high-current pixel requirements of the OLED splicing screen can be met;

[0085] (2) Only the number of Gate GOAs is increased to control the timing of data writing. Each sub-pixel circuit is driven by an independent Gate GOA to achieve reset and data writing. Each sub-pixel circuit writes the same data signal, that is, each sub-pixel circuit writes the same data value. During the reset and data writing phases, multiple Gate GOAs control multiple independent sub-pixel circuits to receive data signals on the data line in a time-sharing manner. During the light-emitting phase, the EM GOA controls multiple independent sub-pixel circuits to emit light simultaneously. This does not affect the IC drive, and the problem of being unable to drive multiple sub-pixel circuits will not occur, thus ensuring the display effect.

[0086] In one possible implementation, Figure 4 As shown, when the sub-pixel unit 11 corresponds to N selectors 12 , the display device 1 further includes a plurality of first shift registers (Gate GOA).

[0087] The sub-pixel unit 11 corresponds to a first shift register;

[0088] A first shift register is connected to the N sub-pixel circuits and is used to output a third scanning signal to the N sub-pixel circuits in a reset phase to control the sub-pixel circuits to reset.

[0089] In another specific embodiment, Figure 4 and Figure 5As shown, the sub-pixel unit 11 corresponds to N selectors 12. For the convenience of description, only N=3 is used as an example for illustration. N can be 2, 3, 4, 5, 6, 7, 8, 9, 10 or other integers not less than 1.

[0090] The sub-pixel unit 11 includes three sub-pixel circuits, namely sub-pixel circuit 1, sub-pixel circuit 2, and sub-pixel circuit 3. Sub-pixel circuit 1, sub-pixel circuit 2, and sub-pixel circuit 3 are all connected to the anode of the light-emitting element EL, and the cathode of the light-emitting element EL is connected to the second signal terminal ELVSS.

[0091] Figure 4 In the example, three sub-pixel circuits (or more) are used to simultaneously drive a light-emitting element EL. Figure 4 The signals of the first signal terminal Vini, the second signal terminal ELVSS, the third signal terminal ELVDD, and the data signal terminal Data are shared. That is, the signals of the first signal terminal Vini, the second signal terminal ELVSS, the third signal terminal ELVDD, and the data signal terminal Data connected to sub-pixel circuit 1, the first signal terminal Vini, the second signal terminal ELVSS, the third signal terminal ELVDD, and the data signal terminal Data connected to sub-pixel circuit 2, and the first signal terminal Vini, the second signal terminal ELVSS, the third signal terminal ELVDD, and the data signal terminal Data connected to sub-pixel circuit 3 are shared. The data signal terminal Data is used to receive the data signal output by the source drive circuit. GateGOA and EM GOA drive three sub-pixel circuits simultaneously; the three sub-pixel circuits are connected in parallel to the anode of the light-emitting element EL, and the cathode of the light-emitting element EL is connected to the second signal terminal ELVSS, so that multiple sub-pixel circuits drive the same light-emitting element EL. GateGOA is connected to multiple sub-pixel circuits in the sub-pixel unit 11, and Gate GOA drives the sub-pixel circuits connected to it simultaneously. The EM GOA is connected to multiple sub-pixel circuits in the sub-pixel unit 11 , and the EM GOA drives the sub-pixel circuits connected thereto simultaneously.

[0092] Each sub-pixel circuit is connected to the data signal terminal Data through a separate selector 12, that is, sub-pixel circuit 1 is connected to the data signal terminal Data through MUX1, sub-pixel circuit 2 is connected to the data signal terminal Data through MUX2, and sub-pixel circuit 3 is connected to the data signal terminal Data through MUX3. By controlling the selector to be turned on in time-sharing mode, the data signal at the data signal terminal Data is transmitted to each sub-pixel circuit in a time-sharing manner, that is, each sub-pixel circuit receives the data signal in a time-sharing manner. The data signal terminal Data is connected to an output terminal of the source driver circuit through a data line to receive the data signal output by the source driver circuit.

[0093] Optionally, the selector 12 includes a transistor, a first electrode of the transistor is connected to the data signal terminal Data, a second electrode of the transistor is connected to the sub-pixel circuit, and a control electrode of the transistor receives a control signal.

[0094] Optionally, the transistors may be N-type transistors or P-type transistors. Figure 4 The transistor shown in is a P-type transistor.

[0095] In a specific implementation, the transistor may be a thin film transistor (TFT) or a metal oxide semiconductor field effect transistor (MOS), without limitation herein. In a specific implementation, the first electrode of the transistor may be a source electrode, and the second electrode of the transistor may be a drain electrode, or the first electrode of the transistor may be a drain electrode, and the second electrode of the transistor may be a source electrode. Depending on the transistor type and the input signal, their functions may be interchangeable, and no specific distinction is made herein.

[0096] from Figure 5 As can be seen from the timing diagram in Figure 1, each sub-pixel driving circuit receives the same data signal (the same Data). This data signal is output by the same channel of the source driving circuit to the data signal terminal Data, and is then written to the sub-pixel circuits connected to the corresponding data lines in a time-sharing manner through multiple selectors. The sub-pixel circuits receive the same data signal in a time-sharing manner, meaning that the same Data value is written to the multiple sub-pixel circuits.

[0097] like Figure 5 As shown in FIG, Reset1 and Gate1 are both scanning signals output by Gate GOA.

[0098] In the reset phase (T1) of each sub-pixel circuit, Gate1 and EM are set to high level, and Reset1 is set to low level, so that each sub-pixel circuit is reset at the same time.

[0099] During the data writing phase (T2) of each sub-pixel circuit, Reset1 and EM are set to high level, Gate1 is set to low level, MUX1, MUX2, and MUX3 are turned on in time-sharing mode, so that each sub-pixel circuit writes the same data signal in time-sharing mode (such as Figure 5 The same Data in the sub-pixel circuits is connected to the same data signal terminal Data, that is, since each sub-pixel circuit is connected to the same data signal terminal Data, during the data writing process of the sub-pixel circuits, the Data value of the sub-pixel unit is the same.

[0100] During the light-emitting phase (T3) of each sub-pixel circuit, Reset1 and Gate1 are set to high level, EM is set to low level, and the three sub-pixel circuits are simultaneously effective, driving the light-emitting element EL to emit light. In a possible implementation, as Figure 2 and Figure 4 As shown, the light-emitting element EL includes an organic light-emitting device, which includes an anode, a light-emitting layer, and a cathode; the anode is connected to N sub-pixel circuits, and the cathode is connected to the second signal terminal ELVSS. In one possible implementation, the display device 1 includes at least two display panels spliced ​​together; that is, the display devices of the two driving schemes are both spliced ​​display devices. The display device 1 includes at least two display panels spliced ​​together, and the display panel includes a display area 10 and a non-display area 13, as shown in FIG. Figure 6 As shown; the sub-pixel array is located in the display area 10; and a plurality of selectors 12 are located in the non-display area 13.

[0101] The non-display area 13 is located at the edge of the display area 10, or the non-display area 13 is located at the side of the first row of sub-pixel units 11 in the display area 10 away from the display area 10. Figure 6 As shown, a plurality of selectors 12 are located in the non-display area 13 ( Figure 6 mid-grey shaded areas).

[0102] In one possible implementation, Figure 6 As shown, the display device further includes a source driving circuit 20; the source driving circuit 20 includes a plurality of output terminals; each output terminal is connected to a data line for outputting a data signal to the corresponding data line.

[0103] For details, see Figure 6 As shown, the display device provided by the embodiment of the present application includes at least two display panels spliced ​​together. By providing multiple selectors 12 in the non-display area 13 of the display panel, the source driver circuit 20 forms multiple data lines in the display area 10 through multiple data lines passing through the selectors 12. The number of data lines is equal to the number of sub-pixel circuits, and the data lines are connected to the sub-pixel circuits in a one-to-one correspondence. Each data line transmits the same data signal to the sub-pixel circuit, and the data signal is output by the source driver circuit 20.

[0104] For example, a display device includes multiple interconnected display panels, each with a resolution of 270×192, and a total of 192×3 data lines. At 60 Hz, the write time for a row of pixels is 1 hour, which is 1 / 60 / 270 = 60 microseconds (microseconds), where the " / " represents a division sign, providing sufficient charging time. For example, if one sub-pixel requires three sub-pixel circuits to drive it, the actual number of data lines in the display area under this technical solution is 192×3×3 = 1728. At 60 Hz, 1 hour takes 60 microseconds, and with three selectors (MUXs), the charging time is sufficient, eliminating the risk of undercharging.

[0105] In this application, if the display device has a resolution of V×H and a frame rate of 60 Hz, the corresponding charging time for a pixel is 1 / 60 / V, and the corresponding charging time for a pixel is 1 / 60 / VN×c, where N is the number of selectors, c is the selector on-time, and " / " represents a division sign. The number of data lines in the display area is H×3×N, and the number of source driver circuit (IC) output channels is H×3. The number of gate GOAs and EM GOAs remains unchanged.

[0106] The display device provided in the embodiments of the present application utilizes a parallel drive design for multiple sub-pixel circuits to provide a high-current pixel circuit. By adding a selector, the data signal output by the source driver circuit (IC) is written to each sub-pixel circuit in a time-sharing manner. Multiple sub-pixel circuits are connected to the anode of the same light-emitting element. Data is written to each sub-pixel circuit simultaneously, enabling independent drive and simultaneous light emission.

[0107] The display device provided in the embodiment of the present application has the following improved effects through a new pixel drive design:

[0108] (1) By driving a light-emitting element simultaneously through multiple independent sub-pixel circuits, the high-current pixel requirements of the OLED splicing screen can be met;

[0109] (2) Only the number of selectors is increased to control the data writing time. That is, during the data writing phase, by controlling the conduction time of the selectors, the data signal output by the source driver circuit is transmitted to each sub-pixel circuit in a time-sharing manner. Each sub-pixel circuit then receives the data signal from the data line in a time-sharing manner. During the light-emitting phase, the EM GOA controls multiple independent sub-pixel circuits to emit light simultaneously. This does not affect the IC drive, and the problem of being unable to drive multiple sub-pixel circuits will not occur, thus ensuring the display effect.

[0110] Based on the same inventive concept, an embodiment of the present application provides a display device, including the display apparatus 1 provided in any of the above embodiments.

[0111] The display device provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the display device can be referred to the previous embodiments and will not be repeated here.

[0112] Based on the same inventive concept, an embodiment of the present application provides a driving method for a display device 1, which is applied to a display device 1 provided in any of the above embodiments, such as Figure 7 and Figure 8 As shown, including:

[0113] S2A: In the data writing phase, the N first shift registers output the first scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner;

[0114] Alternatively, S2B: in the data writing phase, the N selectors receive the selection signal in a time-sharing manner and are turned on to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner.

[0115] The driving method of the display device provided in the embodiment of the present application adopts two technical solutions of adding a first shift register or adding a selector in parallel. In the data writing stage, N first shift registers output the first scanning signal in a time-sharing manner to control N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner, or, in the data writing stage, N selectors receive the selection signal in a time-sharing manner and turn on to control the sub-pixel circuits to receive the data signal on the data line in a time-sharing manner. Compared with the prior art, in the data writing stage, multiple independent sub-pixel circuits receive the data signal on the data line at the same time. This not only improves the driving current to meet the high-current pixel requirements of the display device, but also does not affect the driving of the IC, and does not cause the problem of being unable to drive multiple sub-pixel circuits, thereby ensuring the display effect.

[0116] In one possible implementation, Figure 7 and Figure 8 As shown, it also includes:

[0117] S3: In the light-emitting stage, a light-emitting control signal is output to N sub-pixel circuits to control the light-emitting elements to emit light.

[0118] In a possible implementation, when the sub-pixel unit corresponds to N first shift registers, as shown in FIG. Figure 7 As shown, it also includes:

[0119] S1A: In the reset phase, the N first shift registers output the second scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the reset signal from the first signal terminal in a time-sharing manner.

[0120] In a possible implementation, when the sub-pixel unit corresponds to N selectors, such as Figure 8 As shown, it also includes:

[0121] S1 B: In the reset phase, a third scanning signal is output to N sub-pixel circuits to control the sub-pixel circuits to reset.

[0122] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0123] The display device provided in the embodiment of the present application controls multiple independent sub-pixel circuits to receive data signals on the data line in a time-sharing manner during the data writing phase by adding a first shift register or by adding a selector in parallel. Compared with the prior art, multiple independent sub-pixel circuits simultaneously receive data signals on the data line during the data writing phase. This not only increases the driving current to meet the high-current pixel requirements of the display device, but also does not affect the driving of the IC, and does not cause the problem of being unable to drive multiple sub-pixel circuits, thereby ensuring the display effect.

[0124] Those skilled in the art will appreciate that the steps, measures, and schemes in the various operations, methods, and processes discussed in this application may be interchanged, modified, combined, or deleted. Furthermore, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be interchanged, modified, rearranged, decomposed, combined, or deleted.

[0125] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0126] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.

[0127] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to direct connections, indirect connections through an intermediate medium, or internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0128] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0129] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0130] The above description is only part of the implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A display device, characterized in that: include: A sub-pixel array, the sub-pixel array comprising a plurality of sub-pixel units arranged in an array, the sub-pixel unit comprising N sub-pixel circuits and one light-emitting element, the N sub-pixel circuits each being connected to an anode of the one light-emitting element, where N is an integer not less than 1; a plurality of first shift registers or a plurality of selectors, wherein the sub-pixel unit corresponds to N first shift registers, or the sub-pixel unit corresponds to N selectors; When the sub-pixel unit corresponds to N first shift registers, the N first shift registers are connected to the N sub-pixel circuits in a one-to-one correspondence, and the N sub-pixel circuits are connected to one data line. In a data writing phase, the N first shift registers output first scanning signals in a time-sharing manner to control the N sub-pixel circuits to receive data signals on the data line in a time-sharing manner. When the sub-pixel unit corresponds to N selectors, the N selectors are connected to the N sub-pixel circuits in a one-to-one correspondence, and the N selectors are connected to one data line. During the data writing phase, the N selectors receive the selection signal in a time-sharing manner and are turned on to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner. Also included are a plurality of second shift registers; The sub-pixel unit corresponds to one second shift register; One second shift register is connected to each of the N sub-pixel circuits, and is used to output a light-emitting control signal to the N sub-pixel circuits in a light-emitting phase to control the light-emitting element to emit light.

2. The display device according to claim 1, wherein When the sub-pixel unit corresponds to N first shift registers, the N first shift registers are connected to the N sub-pixel circuits one-to-one, and the N sub-pixel circuits are connected to a first signal terminal. In the reset phase, the N first shift registers output the second scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the reset signal of the first signal terminal in a time-sharing manner.

3. The display device according to claim 1, wherein When the sub-pixel unit corresponds to N selectors, the display device further includes a plurality of first shift registers; The sub-pixel unit corresponds to a first shift register; One first shift register is connected to each of the N sub-pixel circuits, and is configured to output a third scanning signal to the N sub-pixel circuits during a reset phase, so as to control the sub-pixel circuits to reset.

4. The display device according to claim 1, wherein The light-emitting element includes an organic light-emitting device, and the organic light-emitting device includes an anode, a light-emitting layer and a cathode; The anode is connected to N sub-pixel circuits, and the cathode is connected to the second signal terminal.

5. The display device according to claim 1, wherein The display device includes at least two display panels spliced ​​together; the display panel includes a display area and a non-display area; The sub-pixel array is located in the display area; A plurality of selectors are located in the non-display area.

6. The display device according to claim 1, wherein Also included is a source driver circuit; The source driving circuit includes a plurality of output terminals; each output terminal is connected to a data line.

7. A display device, characterized in that: The device comprises the display device according to any one of claims 1 to 6.

8. A method for driving a display device according to any one of claims 1 to 6, characterized in that: include: In the data writing phase, the N first shift registers output the first scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner; Alternatively, in the data writing phase, the N selectors receive the selection signal in a time-sharing manner and are turned on to control the N sub-pixel circuits to receive the data signal on the data line in a time-sharing manner.

9. The method for driving a display device according to claim 8, wherein: Also includes: In the light emitting stage, a light emitting control signal is output to the N sub-pixel circuits to control the light emitting elements to emit light.

10. The method for driving a display device according to claim 9, wherein: Applied to the display device according to claim 2, when the sub-pixel unit corresponds to N first shift registers, further comprising: In the reset phase, the N first shift registers output the second scanning signal in a time-sharing manner to control the N sub-pixel circuits to receive the reset signal from the first signal terminal in a time-sharing manner.

11. The method for driving a display device according to claim 9, wherein: When the sub-pixel unit corresponds to N selectors, the method further includes: In the reset phase, a third scanning signal is output to the N sub-pixel circuits to control the sub-pixel circuits to reset.

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