Display Devices

Abstract

A display device includes: a substrate having a pixel area with at least a first rounded corner, and first to third non-pixel areas arranged sequentially along the periphery of the pixel area. An internal circuit portion in the first non-pixel area has a first end adjacent to the first rounded corner of the pixel area. The first end of the internal circuit portion is rounded according to the first rounded corner. A plurality of wirings are in the third non-pixel area below the pixel area. The wiring extends to the pixel area via the second non-pixel area and the first non-pixel area. The wiring includes at least a first wiring that passes through the area of ​​the first end of the internal circuit portion and is connected to the pixel area.

Description

[0001] This application is a divisional application of the patent application with application number 201710346624.2 and title “Display Device” filed on May 17, 2017.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] Korean Patent Application No. 10-2016-0060429, filed on May 17, 2016, and entitled “DISPLAY DEVICE” is hereby incorporated by reference in its entirety. Technical Field

[0004] One or more embodiments described herein relate to a display device. Background Art

[0005] Various types of display devices have been developed. One type of display device includes a non-pixel area surrounding a pixel area. The non-pixel area has a drive circuit or wire for supplying a power supply voltage or a drive signal to the pixel in the pixel area. The non-pixel area may also include a material for sealing at least the pixel area or the bonding area of ​​the encapsulation layer. The size of the non-pixel area may limit the size of the screen in the pixel area. Summary of the invention

[0006] According to one or more embodiments, a display device includes: a substrate, including a pixel area having at least a first rounded corner, and a first non-pixel area, a second non-pixel area, and a third non-pixel area arranged in sequence along the periphery of the pixel area; a plurality of pixels in the pixel area; an internal circuit portion, in the first non-pixel area and having a first end portion adjacent to the first rounded corner portion of the pixel area, the first end portion of the internal circuit portion being rounded according to the first rounded corner; and a plurality of wirings, in a third non-pixel area below the pixel area, the wirings extending to the pixel area via the second non-pixel area and the first non-pixel area, the wirings including at least a first wiring, the first wiring passing through an area of ​​the first end portion of the internal circuit portion and connected to the pixel area.

[0007] The display device may include an encapsulation layer for covering the pixel and the internal circuit part, wherein the encapsulation layer includes a first encapsulation layer covering the pixel area and the first non-pixel area, and a second encapsulation layer covering the first encapsulation layer and having an end in the second non-pixel area. The second encapsulation layer may be superimposed on at least the first wiring located at the periphery of the first end of the internal circuit part.

[0008] The internal circuit portion may include a plurality of stages for sequentially outputting control signals. The first wiring may traverse regions between adjacent stages in the plurality of stages and may be connected to pixels in the first column. The display device may include at least one power line at the periphery of the internal circuit portion. At least one region of the power line may be superimposed on the internal circuit portion. At least one region of the power line may be superimposed on a first end of the internal circuit portion.

[0009] The internal circuit portion may include a transistor, and the power line may include a first conductive layer located on the same layer as one electrode of the transistor, and a second conductive layer located on the first conductive layer and electrically connected to the first conductive layer, with one or more insulating layers between the first conductive layer and the second conductive layer. The first conductive layer may be located on the same layer as the uppermost electrode of the plurality of electrodes of the transistor. The first conductive layer may be located only on another region other than the region overlapping with the internal circuit portion.

[0010] At least one region of the second conductive layer may overlap with the first end of the internal circuit portion. The width of the region of the second conductive layer that may overlap with the first end is greater than the width of the remaining regions outside the region. The power line may branch into at least a first sub-power line and a second sub-power line in a region adjacent to the first end of the internal circuit portion, and the first end may be located between the first sub-power line and the second sub-power line.

[0011] The first sub-power line may be adjacent to the outer periphery of the first end portion, and the second sub-power line may be adjacent to the inner periphery of the first end portion. The power line may include a connecting line connecting the first sub-power line and the second sub-power line. The connecting line may pass through an area between a plurality of stages in the internal circuit portion, and may electrically connect the first sub-power line and the second sub-power line.

[0012] The connection line may include a conductive layer located on a different layer from the transistors in the internal circuit portion. In an area where the first sub-power line and the second sub-power line face each other, the sum of the widths of the first sub-power line and the second sub-power line may have a width substantially equal to the width in an unbranched area of ​​the power line, with a first end portion between the first sub-power line and the second sub-power line.

[0013] According to one or more embodiments, a display device includes a substrate, a plurality of pixels, a driving circuit, and at least one power line. The substrate includes a pixel area and a non-pixel area. A plurality of pixels are in the pixel area. At least one of the pixels includes: a transistor on the substrate; a first electrode on a first layer on the transistor; a light-emitting layer on the first electrode; and a second electrode on the light-emitting layer. The transistor has a semiconductor layer, a gate electrode, and a source electrode and a drain electrode. The driving circuit is disposed in the non-pixel area and is configured to drive the pixel. At least one power line is in the non-pixel area, and at least a portion of the power line is disposed between the driving circuit and an edge portion of the display device. The power line includes a first line on the second layer, and a second line on the first line and electrically connected to the first line. The second line is disposed on a third layer between the first layer and the second layer.

[0014] The power line may overlap the driving circuit. The power line may be electrically connected to the second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 An embodiment of a display device is shown;

[0017] Figure 2 showing an enlarged view of an area of ​​a display device;

[0018] Figure 3 Shown along Figure 1 A view taken along section line II' in FIG.

[0019] Figure 4 A comparative example is shown;

[0020] Figure 5 An embodiment of a pixel is shown;

[0021] Figure 6 An embodiment of a scan driver is shown;

[0022] Figure 7 An embodiment of a scanning stage is shown;

[0023] Figure 8 An embodiment of a method for driving a scanning stage is shown;

[0024] Fig. 9 An embodiment of a light emitting control driver is shown;

[0025] Fig.10 An embodiment of a light emission control stage is shown;

[0026] Fig.11An embodiment of a method for driving a light emitting control stage is shown;

[0027] Fig.12 Another embodiment of a display device is shown;

[0028] Fig.13 Another embodiment of a display device is shown;

[0029] Fig.14 Shown along Fig.13 A view taken along section line II-II';

[0030] Fig.15 Show Fig.13 An embodiment of a region of a display device in;

[0031] Fig.16 Show Fig.13 Another embodiment of a region of a display device in;

[0032] Fig.17 Show Fig.13 Another embodiment of a region of a display device in; and

[0033] Fig.18 Another embodiment of a display device is shown. DETAILED DESCRIPTION

[0034] Example embodiments will now be described with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the exemplary implementations to those skilled in the art. The embodiments (or portions thereof) may be combined to form additional embodiments.

[0035] In the figures, the sizes of layers and regions may be exaggerated for clarity of illustration. It should also be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer. In addition, it should be understood that when a layer is referred to as being "below" another layer, it can be directly below, and there can also be one or more intermediate layers. Furthermore, it should also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intermediate layers. The same reference numerals always refer to the same elements.

[0036] It should be understood that when an element is described as "coupled" or "connected" to another element, the element may be directly coupled or directly connected to another element, or coupled or connected to another element through a third element. On the contrary, it should be understood that when an element is referred to as "directly connected to" or "directly coupled to" another element, other elements will not be interposed. Other expressions describing the relationship between parts (i.e., "between..." and "directly between..." or "adjacent to..." and "directly adjacent to...") need to be explained in the same manner. In addition, in order to clearly explain the present disclosure, the description of parts not related to the present disclosure is omitted from the accompanying drawings, and in the illustrations of the accompanying drawings, the sizes of some configuration elements may be exaggerated. Throughout the specification, the same figure numerals refer to the same configuration elements.

[0037] Figure 1 An embodiment of a display device 100 is shown. Figure 2 1 is an enlarged view of the area PA of the display device 100. The display device 100 includes: a substrate 101 including a pixel area AA and a non-pixel area NA surrounding the pixel area AA; a plurality of pixels 102 in the pixel area AA; and driving circuits 110, 120, 130 in the non-pixel area NA on the substrate 101. According to an embodiment, at least one of the driving circuits 110, 120, 130 may constitute an internal circuit portion. For example, the first driving circuit 110 may constitute a first internal circuit portion, and the second driving circuit 120 may constitute a second internal circuit portion.

[0038] The substrate 101 may be made of various insulating materials such as glass or resin. In addition, the substrate 101 may be embodied as a rigid substrate that is not easily bent or a flexible substrate that can be bent or easily folded. The substrate 101 includes a pixel area AA and a non-pixel area NA. The substrate 101 may be embodied as having a predetermined angle (e.g., 90°) or a rounded corner. In one embodiment, the four corners of the substrate 101 may be rounded to have a curved form. When a corner or end is described as being rounded, the corner or end may have, for example, a curved, clipped, diagonal or stepped form or a combination of these.

[0039] The pixel area AA includes a plurality of scan lines S and data lines D, and a plurality of pixels 102 connected to the scan lines S and the data lines D. According to an embodiment, control lines such as a light emitting control line E may be arranged in the pixel area AA. In this case, each pixel 102 is connected to the scan lines S and the light emitting control line E arranged in its corresponding row and to the data line D arranged in its corresponding column. According to an embodiment, the rows and columns may be switched. For example, the scan lines S and the light emitting control line E may extend in the column direction, while the data lines D extend in the row direction. In addition, the rows and columns may be interpreted oppositely according to the arrangement direction of the display device 100.

[0040] According to an embodiment, at least one corner of the pixel area AA may be rounded. For example, all four corners of the pixel area AA may be rounded.

[0041] The non-pixel area NA includes a first non-pixel area NA1, a second non-pixel area NA2, and a third non-pixel area NA3 sequentially arranged along the periphery of the pixel area AA. In the first non-pixel area NA1, internal circuit parts 110, 120 sealed together with the pixels 102 of the pixel area AA may be arranged. For example, in the first non-pixel area NA1 at both sides of the pixel area AA, the first internal circuit part 110 and the second internal circuit part 120 may be arranged respectively. According to an embodiment, any one of the first internal circuit part 110 and the second internal circuit part 120 may be omitted. The first internal circuit part 110 or the second internal circuit part 120 may be arranged only on one side of the pixel area AA.

[0042] The first internal circuit section 110 and the second internal circuit section 120 may include at least one of a scan driver and a light emission control driver, respectively. For example, the first internal circuit section 110 may be a scan driver, and the second internal circuit section 120 may be a light emission control driver. In addition, any one of the first internal circuit section 110 or the second internal circuit section 120 may include both a scan driver and a light emission control driver.

[0043] According to an embodiment, when at least one corner of the pixel area AA is rounded, the ends of the first internal circuit portion 110 and the second internal circuit portion 120 may also be rounded along the shape of the corner. For example, when at least one corner of the pixel area AA is rounded, the first ends of the first internal circuit portion 110 and / or the second internal circuit portion 120 adjacent to the corner may also be rounded along the shape of the corner.

[0044] The second non-pixel region NA2 may include an adhesive portion of the encapsulation layer.

[0045] The third non-pixel area NA3 is the outermost area of ​​the substrate 101 and includes a data driver 130. According to an embodiment, the data driver 130 may be mounted on a circuit board or the like outside the substrate 101 and may be connected to the substrate 101 through a pad portion.

[0046] A plurality of wirings DR may be disposed between the data driver 130 and the pixel area AA. The wirings DR may be, for example, data wirings. The wirings DR may be electrically connected to the data lines D in the pixel area AA. According to an embodiment, the wirings DR may be integrally formed with the data lines D.

[0047] The wiring DR may be connected to the pixel area AA from the third non-pixel area NA3 adjacent to the lower end of the pixel area AA via the second non-pixel area NA2 and the first non-pixel area NA1 in sequence. For example, the wiring DR may be in the third non-pixel area NA3 below the pixel area AA, and extend to the pixel area AA via the second non-pixel area NA2 and the first non-pixel area NA1. According to an embodiment, the upper end and the lower end of the pixel area AA may be opposite to each other. For example, when the display device 100 is rotated 180°, the wiring DR and the data driver 130 may be regarded as being arranged at the upper end of the pixel area AA.

[0048] According to an embodiment, at least one of the wirings DR starts from the third non-pixel area NA3 , passes through a region where the ends of the first internal circuit part 110 and / or the second internal circuit part 120 are rounded, and is then connected to the pixel area AA.

[0049] For example, in addition to at least the left corner (e.g., the first corner) of the pixel area AA being rounded, when the lower end (e.g., the first end) of the first internal circuit portion 110 adjacent to the first corner is rounded, one or more wirings DR (e.g., the first wiring DR1 to the kth wiring DRk) may pass through the area where the first end of the first internal circuit portion 110 is arranged and extend to the pixel area AA, the one or more wirings DR including the first wiring DR1 connected from the third non-pixel area NA3 near the lower end (or lower edge portion) of the pixel area AA and extending to the first corner of the pixel area AA.

[0050] To this end, one or more wirings DR including the first wiring DR1 may pass from the third non-pixel area NA3 below the lower end of the pixel area AA to reach a portion of the second non-pixel area NA2 adjacent to the periphery of the first end of the first internal circuit portion 110. Subsequently, the one or more wirings DR may enter or extend to the first non-pixel area NA1 and pass through a portion of the area of ​​the first internal circuit portion 110 (e.g., the first end), and then extend to the pixel area AA.

[0051] According to an embodiment, in addition to the right end corner (e.g., the second corner) of the pixel area AA being rounded, when the lower end (e.g., the second end) of the second internal circuit portion 120 adjacent to the second corner is rounded, other wirings among the wirings DR connected and / or extending to the lower right end of the pixel area AA (e.g., the mk-th wiring DRm-k to the m-th wiring DRm) can proceed from the third non-pixel area NA3 to the area where the second end of the second internal circuit portion 120 is arranged, and then extend to the pixel area AA.

[0052] The circuit elements or wires may be designed so that a short circuit defect therebetween can be prevented when at least one of the wirings DR passes through the first internal circuit portion 110 and / or the second internal circuit portion 120. For example, when the first wiring DR1 is superimposed on the first internal circuit portion 110, the first wiring DR1 may be designed so that a conductive layer constituting the first wiring DR1 may be located on a different layer from a layer in which circuit elements in the first internal circuit portion 110 are formed in a region superimposed on the first internal circuit portion 110, with at least one insulating layer therebetween.

[0053] In addition, Figure 2 As shown, for example, assuming that the first to third wirings DR1, DR2, DR3 pass through the region where the first internal circuit portion 110 is arranged, each of the first to third wirings DR1, DR2, DR3 may be arranged to cross the region between the stages 112 of the first internal circuit portion 110. For example, the first internal circuit portion 110 may include a plurality of stages 112 that sequentially output control signals (e.g., scan signals or light emission control signals). The first wiring DR1 may cross the region between two adjacent stages 112 among the stages 112 and be electrically connected to the pixels 102 in the first column.

[0054] The display device 100 of the present embodiment can be compared with a comparative example in which the wiring DR is arranged between the first internal circuit portion 110 and / or the second internal circuit portion 120 in the rounded corner of the pixel area AA so that the wiring DR is not superimposed on the first internal circuit portion 110 and / or the second internal circuit portion 120. Therefore, the space of the non-pixel area NA can be effectively used.

[0055] In addition, according to the display device 100 of the present embodiment, by arranging the wiring DR at the periphery of the first internal circuit part 110 and / or the second internal circuit part 120 and overlapping on the bonding area of ​​the encapsulation layer, space utilization can be increased or maximized and the number of dead zones can be reduced.

[0056] Figure 3 According to one embodiment, Figure 1A cross section taken along line II' in FIG. Figure 4 FIG. 2 shows an example of a cross section of a display device 100 ′ according to a comparative example. Figure 3 and Figure 4 , an encapsulation layer for sealing at least the pixel area is shown.

[0057] refer to Figure 3 and Figure 4 , the areas on the substrate 101 and the substrate 101' are defined as a pixel area AA, a first non-pixel area NA1, a second non-pixel area NA2, and a third non-pixel area NA3 in order from the inside to the outside. At least the pixel area AA and the first non-pixel area NA1 are sealed by the encapsulation layer 140. The encapsulation layer 140 is bonded to the substrate 101 in the second non-pixel area NA2. The third non-pixel area NA3 is a peripheral area of ​​the encapsulation layer 140 and may be the outermost area of ​​the substrate 101.

[0058] According to an embodiment, an encapsulation layer 140 may be formed on the substrate 101 to cover the first internal circuit part 110 and / or the second internal circuit part 120 .

[0059] The encapsulation layer 140 includes: a first encapsulation layer 142 in a sealing area (e.g., the pixel area AA and the first non-pixel area NA1); and a second encapsulation layer 144 covering the upper and side surfaces of the first encapsulation layer 142 and having an edge area bonded to the substrate 101 in the second non-pixel area NA2.

[0060] The first encapsulation layer 142 may include at least one organic film and / or inorganic film for effectively protecting at least the circuit elements in the pixel area AA from damage from the external environment. For example, the first encapsulation layer 142 may include a single organic film or inorganic film of a single-layer structure. The first encapsulation layer 142 may include multiple organic films and / or inorganic films of a multi-layer structure. For example, the first encapsulation layer 142 may include multiple organic films, multiple inorganic films, or a multi-layer structure including at least one organic film and an inorganic film. In addition, the first encapsulation layer 142 may include at least one organic-inorganic composite film.

[0061] The second encapsulation layer 144 is located on the upper portion of the first encapsulation layer 142. The second encapsulation layer 144 includes one or more inorganic films. For example, the second encapsulation layer 144 may include a stacked structure of an inorganic film in the first encapsulation layer 142 and an inorganic film located on the upper portion of the first encapsulation layer 142. Such a second encapsulation layer 144 covers both the upper portion and the side surface of the organic film in the first encapsulation layer 142, and prevents moisture from penetrating into the sealing area.

[0062] In one embodiment, one or more wirings DR (eg, first to k-th wirings DR1 to DRk) are stacked under the second encapsulation layer 144 in the second non-pixel region NA2 and arranged at the periphery of the first end of the first internal circuit portion 110. As an example, Figure 3 The first to k-th wirings DR1 to DRk are illustrated as one box, but in one embodiment, the first to k-th wirings DR1 to DRk may actually be configured as a plurality of wires separated from each other.

[0063] Therefore, at least a portion of the wiring region where the wirings DR are arranged may overlap the adhesion region of the encapsulation layer 140 (ie, the second non-pixel region NA2 ), thereby effectively utilizing the space of the non-pixel region NA.

[0064] On the other hand, Figure 4 In the case of the display device 100' of the comparative example, Figure 1 In the area corresponding to the I-I' area of ​​the first non-pixel area 101', the first wiring DR1' to the kth wiring DRk' are not wired beside the outside of the first internal circuit portion 110', but are directly wired between the pixel area AA and the first internal circuit portion 110'. This allows the first non-pixel area NA1 to have a larger width. In addition, since the second encapsulation layer 144' is bonded to the substrate 101' to cover both the upper portion and the side surface of the first encapsulation layer 142', and thereby protect the sealing area from moisture penetration, it is necessary to ensure a certain width or greater width of the second non-pixel area NA2 to facilitate stable sealing. Therefore, there is a limitation on reducing the width of the second non-pixel area NA2. That is, according to the present embodiment, the dead zone of the display device 100 can be reduced by effective space utilization.

[0065] Figure 5 1 shows an embodiment of a pixel 102, where the pixel 102 is connected to the mth data line Dm and the ith scan line Si, for example. Figure 5 , the pixel 102 includes an organic light emitting diode (OLED), first to seventh transistors T1 to T7, and a storage capacitor Cst. In another embodiment, the pixel may have a different structure.

[0066] The organic light emitting diode (OLED) has an anode electrode connected to the first transistor T1 via a sixth transistor T6, and a cathode electrode connected to the second power supply (ELVSS). The organic light emitting diode (OLED) generates light of a brightness corresponding to the amount of driving current supplied from the first transistor T1. The voltage level of the first power supply (ELVDD) may be greater than the voltage level of the second power supply (ELVSS) so that current may flow to the organic light emitting diode (OLED). For example, the first power supply (ELVDD) may be set as a high potential pixel power supply, and the second power supply (ELVSS) may be set as a low potential pixel power supply.

[0067] According to an embodiment, an organic light emitting diode (OLED) may generate any of various colors of light including red, green, and blue based on a driving current. In one embodiment, an organic light emitting diode (OLED) may generate white light based on a driving current. In this case, a separate color filter or the like may be used to realize a color image.

[0068] The seventh transistor T7 is connected between the initialization power supply Vint and the anode electrode of the organic light emitting diode (OLED). The gate electrode of the seventh transistor T7 is connected to the i+1th scan line Si+1. When the scan signal is supplied to the i+1th scan line Si+1, the seventh transistor T7 is turned on, and the voltage of the initialization power supply Vint is supplied to the anode electrode of the organic light emitting diode (OLED). The voltage of the initialization power supply (Vint) may be lower than the voltage of the data signal. For example, the voltage of the initialization power supply (Vint) may be lower than the minimum voltage of the data signal.

[0069] The sixth transistor T6 is connected between the first transistor T1 and the organic light emitting diode (OLED). The sixth transistor T6 has a gate electrode connected to the i-th emission control line Ei. The sixth transistor T6 is turned off when the emission control signal is supplied to the i-th emission control line Ei, but can be turned on otherwise.

[0070] The fifth transistor T5 is connected between the first power source (ELVDD) and the first transistor T1. The fifth transistor T5 may have a gate electrode connected to the i-th light emitting control line Ei. The fifth transistor T5 is turned off when the light emitting control signal is supplied to the i-th light emitting control line Ei, but may be turned on otherwise.

[0071] The first transistor T1 (driving transistor) has a first electrode connected to the first power source (ELVDD) via the fifth transistor T5, and a second electrode connected to the anode electrode of the organic light emitting diode (OLED) via the sixth transistor T6. The gate electrode of the first transistor T1 is connected to the tenth node N10. The first transistor T1 controls the amount of current flowing from the first power source (ELVDD) to the second power source (ELVSS) via the organic light emitting diode (OLED) based on the voltage of the tenth node N10.

[0072] The third transistor T3 is connected between the second electrode of the first transistor T1 and the tenth node N10. The gate electrode of the third transistor T3 is connected to the i-th scan line Si. The third transistor T3 is turned on when the scan signal is supplied to the i-th scan line Si, and can electrically connect the second electrode of the first transistor T1 and the tenth node N10. Therefore, when the third transistor T3 is turned on, the first transistor T1 is in a diode connection state.

[0073] The fourth transistor T4 is connected between the tenth node N10 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 is connected to the i-1th scan line Si-1. The fourth transistor T4 is turned on when the scan signal is supplied to the i-1th scan line Si-1, and the fourth transistor T4 then supplies the voltage of the initialization power supply Vint to the tenth node N10.

[0074] The second transistor T2 is connected between the mth data line Dm and the first electrode of the first transistor T1. The gate electrode of the second transistor T2 is connected to the i-th scan line Si. The second transistor T2 is turned on when the scan signal is supplied to the i-th scan line Si, and the second transistor T2 then electrically connects the mth data line Dm and the first electrode of the first transistor T1.

[0075] The storage capacitor Cst is connected between the first power source ELVDD and the tenth node N10. The storage capacitor Cst stores a voltage corresponding to the data signal and a threshold voltage of the first transistor T1.

[0076] Figure 6 An embodiment of the scan driver 110 is shown, and the scan driver 110 may be, for example, inside the first internal circuit part 110 and / or the second internal circuit part 120. For convenience, the following description will be based on the assumption that the first internal circuit part 110 is configured as a scan driver. The scan driver includes a plurality of scan stages that sequentially output scan signals.

[0077] like Figure 6As shown, the scan driver 110 has a plurality of scan stages SST1 to SST4. In another embodiment, the scan driver may have a different number of scan stages. The scan stages SST1 to SST4 are connected to the corresponding scan lines S1 to S4 and are driven based on clock signals CLK1 and CLK2. The scan stages SST1 to SST4 may have, for example, the same structure.

[0078] Each of the scanning stages SST1 to SST4 includes a first input terminal 1001 to a third input terminal 1003 and an output terminal 1004. The first input terminal 1001 of each of the scanning stages SST1 to SST4 is supplied with an output signal (e.g., a scanning signal) of a previous scanning stage or a first start pulse SSP1. For example, the first input terminal 1001 of the first scanning stage SST1 may be supplied with a first start pulse SSP1. The first input terminals 1001 of the remaining scanning stages SST2 to SST4 may be supplied with an output signal of a previous scanning stage.

[0079] The second input terminal 1002 of the jth (j is an odd or even number) scanning stage SSTj is supplied with the first clock signal CLK1, and the third input terminal 1003 is supplied with the second clock signal CLK2. The second input terminal 1002 of the j+1th scanning stage SSTj+1 is supplied with the second clock signal CLK2, and the third input terminal 1003 is supplied with the first clock signal CLK1.

[0080] The first clock signal CLK1 and the second clock signal CLK2 may have the same period and non-overlapping phases. For example, based on the assumption that the period in which the scan signal is supplied to the first scan line S1 is 1 horizontal period 1H, each of the clock signals CLK1 and CLK2 has a period of 2H, and the clock signals CLK1 and CLK2 may be supplied in different horizontal periods from each other.

[0081] Each of the scanning stages SST1 to SST4 is supplied with a first driving power supply VDD and a second driving power supply VSS. The first driving power supply VDD may be set to a gate-off voltage, such as a high voltage. The second driving power supply VSS may be set to a gate-on voltage, such as a low voltage.

[0082] Figure 7 Show Figure 6 For convenience, Figure 7 A first scanning stage SST1 and a second scanning stage SST2 are shown. The first scanning stage SST1 includes a first driver 1210, a second driver 1220, and an output circuit 1230 (or a buffer). The output circuit 1230 controls a voltage supplied to an output terminal 1004 based on a first node N1 and a second node N2.

[0083] To this end, the output circuit 1230 includes a fifth transistor M5 and a sixth transistor M6. The fifth transistor M5 is connected between the first driving power supply VDD and the output terminal 1004. The gate electrode of the fifth transistor M5 is connected to the first node N1. The fifth transistor M5 controls the connection between the first driving power supply VDD and the output terminal 1004 based on the voltage applied to the first node N1.

[0084] The sixth transistor M6 is connected between the output terminal 1004 and the third input terminal 1003. The gate electrode of the sixth transistor M6 is connected to the second node N2. The sixth transistor M6 controls the connection between the output terminal 1004 and the third input terminal 1003 based on the voltage applied to the second node N2. The output circuit 1230 operates as a buffer. In addition, the fifth transistor M5 and / or the sixth transistor M6 may include a plurality of transistors connected in parallel to each other.

[0085] The first driver 1210 controls the voltage of the third node N3 based on the signal supplied to the first input terminal 1001 to the third input terminal 1003. To this end, the first driver 1210 includes a second transistor M2 to a fourth transistor M4. The second transistor M2 is connected between the first input terminal 1001 and the third node N3. The gate electrode of the second transistor M2 is connected to the second input terminal 1002. The second transistor M2 controls the connection between the first input terminal 1001 and the third node N3 based on the signal supplied to the second input terminal 1002.

[0086] The third transistor M3 and the fourth transistor M4 are connected in series between the third node N3 and the first driving power supply VDD. The third transistor M3 is connected between the fourth transistor M4 and the third node N3. The gate electrode of the third transistor M3 is connected to the third input terminal 1003. The third transistor M3 controls the connection between the fourth transistor M4 and the third node N3 based on the signal supplied to the third input terminal 1003.

[0087] The fourth transistor M4 is connected between the third transistor M3 and the first driving power source VDD. A gate electrode of the fourth transistor M4 is connected to the first node N1. The fourth transistor M4 controls the connection between the third transistor M3 and the first driving power source VDD based on the voltage of the first node N1.

[0088] The second driver 1220 controls the voltage of the first node N1 based on the voltage of the second input terminal 1002 and the third node N3. To this end, the second driver 1220 includes a seventh transistor M7, an eighth transistor M8, a first capacitor C1, a second capacitor C2 and a first transistor M1. The first capacitor C1 is connected between the second node N2 and the output terminal 1004. The first capacitor C1 is charged with a voltage corresponding to the turn-on and turn-off of the sixth transistor M6.

[0089] The second capacitor C2 is connected between the first node N1 and the first driving power source VDD. The second capacitor C2 charges a voltage to be applied to the first node N1.

[0090] The seventh transistor M7 is connected between the first node N1 and the second input terminal 1002. A gate electrode of the seventh transistor M7 is connected to the third node N3. The seventh transistor M7 controls connection between the first node N1 and the second input terminal 1002 based on a voltage of the third node N3.

[0091] The eighth transistor M8 is connected between the first node N1 and the second driving power source VSS. A gate electrode of the eighth transistor M8 is connected to the second input terminal 1002. The eighth transistor M8 controls the connection between the first node N1 and the second driving power source VSS based on a signal of the second input terminal 1002.

[0092] The first transistor M1 is connected between the third node N3 and the second node N2. The gate electrode of the first transistor M1 is connected to the second driving power supply VSS. Such a first transistor M1 maintains the electrical connection between the third node N3 and the second node N2 while maintaining its on state. In addition, the first transistor M1 limits the degree of reduction of the voltage of the third node N3 based on the voltage of the second node N2. For example, even if the voltage of the second node N2 is reduced to a voltage lower than the second driving power supply VSS, the voltage of the third node N3 will not drop below the threshold voltage of the first transistor M1 subtracted from the second driving power supply VSS.

[0093] Figure 8 Shown is the drive Figure 7 For convenience, reference will be made to Figure 8 The operation is explained using the first scanning stage SST1.

[0094] refer to Figure 8, the first clock signal CLK1 and the second clock signal CLK2 have two (2) horizontal periods (2H) cycles, and can be supplied in different horizontal periods from each other. For example, the second clock signal CLK2 is set to be a signal shifted from the first clock signal CLK1 by up to half a period (for example, 1 horizontal period). The first start pulse SSP1 supplied to the first input terminal 1001 is synchronized with the clock signal (for example, the first clock signal CLK1) supplied to the second input terminal 1002.

[0095] When the first start pulse SSP1 is supplied, the first input terminal 1001 may be set to the voltage of the second drive power supply VSS. When the first start pulse SSP1 is not supplied, the first input terminal 1001 may be set to the voltage of the first drive power supply VDD. In addition, when the clock signal CLK is supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 may be set to the voltage of the second drive power supply VSS. When the clock signal CLK is not supplied to the second input terminal 1002 and the third input terminal 1003, the second input terminal 1002 and the third input terminal 1003 may be set to the voltage of the first drive power supply VDD.

[0096] For example, first, the first start pulse SSP1 is supplied to synchronize with the first clock signal CLK1. When the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 are turned on. When the second transistor M2 is turned on, the first input terminal 1001 and the third node N3 are electrically connected. Since the first transistor M1 is always set to the on state, the second node N2 maintains its electrical connection with the third node N3.

[0097] When the first input terminal 1001 and the third node N3 are electrically connected, the voltages of the third node N3 and the second node N2 are set to a low voltage by the first start pulse SSP1 supplied to the first input terminal 1001. When the voltages of the third node N3 and the second node N2 are set to a low voltage, the sixth transistor M6 and the seventh transistor M7 are turned on.

[0098] When the sixth transistor M6 is turned on, the third input terminal 1003 is electrically connected to the output terminal 1004. The third input terminal 1003 is set to a high voltage, for example, the second clock signal CLK2 is not supplied. Therefore, the high voltage is output to the output terminal 1004. When the seventh transistor M7 is turned on, the second input terminal 1002 is electrically connected to the first node N1. Then, the voltage of the first clock signal CLK1 is supplied to the second input terminal 1002, for example, a low voltage is supplied to the first node N1.

[0099] When the first clock signal CLK1 is supplied, the eighth transistor M8 is turned on. When the eighth transistor M8 is turned on, the voltage of the second driving power supply VSS is supplied to the first node N1. The voltage of the second driving power supply VSS is set to a voltage that is the same (or similar) as the voltage of the first clock signal CLK1. Therefore, the first node N1 stably maintains a low voltage.

[0100] When the first node N1 is set to a low voltage, the fourth transistor M4 and the fifth transistor M5 are turned on. When the fourth transistor M4 is turned on, the first driving power supply VDD and the third transistor M3 are electrically connected. Since the third transistor M3 is set to a cut-off state, the third node N3 stably maintains a low voltage even when the fourth transistor M4 is turned on. When the fifth transistor M5 is turned on, the voltage of the first driving power supply VDD is supplied to the output terminal 1004. The voltage of the first driving power supply VDD is set to the same voltage as the high voltage supplied to the third input terminal 1003. Therefore, the output terminal 1004 stably maintains a high voltage.

[0101] After that, the supply of the first start pulse SSP1 and the first clock signal CLK1 is stopped. When the supply of the first clock signal CLK1 is stopped, the second transistor M2 and the eighth transistor M8 are turned off. The sixth transistor M6 and the seventh transistor M7 remain in a conducting state based on the voltage stored in the first capacitor C1. Therefore, the second node N2 and the third node N3 maintain a low voltage based on the voltage stored in the first capacitor C1.

[0102] When the sixth transistor M6 remains in the on state, the output terminal 1004 and the third input terminal 1003 remain electrically connected. When the seventh transistor M7 remains in the on state, the first node N1 remains electrically connected to the second input terminal 1002. The voltage of the second input terminal 1002 is set to a high voltage based on stopping the supply of the first clock signal CLK1. Therefore, the first node N1 is also set to a high voltage. When the high voltage is supplied to the first node N1, the fourth transistor M4 and the fifth transistor M5 are turned off.

[0103] Thereafter, the second clock signal CLK2 is supplied to the third input terminal 1003. Since the sixth transistor M6 is set to the on state, the second clock signal CLK2 supplied to the third input terminal 1003 is supplied to the output terminal 1004. In this case, the output terminal 1004 outputs the second clock signal CLK2 to the first scan line S1 as a scan signal.

[0104] When the second clock signal CLK2 is supplied to the output terminal 1004, the voltage of the second node N2 is reduced to a voltage lower than the second driving power source VSS by coupling of the first capacitor C1. Therefore, the sixth transistor M6 stably maintains its on state.

[0105] Even if the voltage of the second node N2 is lowered, the third node N3 maintains the normal voltage of the second driving power source VSS (the threshold voltage of the first transistor M1 subtracted from the second driving power source VSS) through the first transistor M1.

[0106] After the scan signal is output to the first scan line S1, the second clock signal CLK2 is stopped. When the second clock signal is stopped, the output terminal 1004 outputs a high voltage. In addition, the voltage of the second node N2 increases to the normal voltage of the second driving power supply VSS based on the high voltage of the output terminal 1004.

[0107] Thereafter, the first clock signal CLK1 is supplied. When the first clock signal CLK1 is supplied, the second transistor M2 and the eighth transistor M8 are turned on. When the second transistor M2 is turned on, the first input terminal 1001 and the third node N3 are electrically connected. The first start pulse SSP1 is not supplied to the first input terminal 1001. Therefore, the first input terminal 1001 is set to a high voltage. Thus, when the first transistor M1 is turned on, a high voltage is supplied to the third node N3 and the second node N2. Therefore, the sixth transistor M6 and the seventh transistor M7 are turned off.

[0108] When the eighth transistor M8 is turned on, the second driving power supply VSS is supplied to the first node N1. Therefore, the fourth transistor M4 and the fifth transistor M5 are turned on. When the fifth transistor M5 is turned on, the voltage of the first driving power supply VDD is supplied to the output terminal 104. Afterwards, the fourth transistor M4 and the fifth transistor M5 maintain their on state based on the voltage charged in the second capacitor C2. Therefore, the output terminal 1004 is stably supplied with the voltage of the first driving power supply VDD.

[0109] When the second clock signal CLK2 is supplied, the third transistor M3 is turned on. Since the fourth transistor M4 is set to the on state, the voltage of the first driving power supply VDD is supplied to the third node N3 and the second node N2. In this case, the sixth transistor M6 and the seventh transistor M7 stably maintain their off state.

[0110] The second scanning stage SST2 is supplied with the output signal (e.g., scanning signal) of the first scanning stage SST1 synchronized with the second clock signal CLK2. In this case, the second scanning stage SST2 outputs the scanning signal synchronized with the second clock signal CLK2 to the second scanning line S2. The scanning stage SST according to the present embodiment can repeat the above process to sequentially output the scanning signal to the scanning line S.

[0111] In the present embodiment, the first transistor M1 limits the degree of decrease of the voltage of the third node N3 regardless of the voltage of the second node N2, thereby ensuring manufacturing cost and reliability of operation.

[0112] For example, when the scan signal is supplied to the output terminal 1004, the voltage of the second node N2 decreases to a voltage of about VSS-(VDD-VSS). Assuming that the first driving power supply VDD is 7V and the second driving power supply VSS is -8V, the voltage of the second node N2 decreases to a voltage of about -20V even in consideration of the threshold voltage of the transistor.

[0113] When the first transistor M1 is removed, the source electrode-drain electrode voltage Vds of the second transistor M2 and the source electrode-gate voltage Vgs of the seventh transistor M7 are set to about -27V. Therefore, components with high voltage resistance can be used for the second transistor M2 and the seventh transistor M7. In addition, when a high voltage is applied to the second transistor M2 and the seventh transistor M7, power consumption may be high. In addition, the reliability of the operation may be deteriorated. However, when the first transistor M1 is added between the third node N3 and the second node N2, the voltage of the third node N3 maintains the normal voltage of the second power supply VSS. Therefore, the source electrode-drain electrode voltage Vds of the second transistor M2 and the source electrode-gate voltage Vgs of the seventh transistor M7 can be set to about -14V.

[0114] Fig. 9 An embodiment of the light emission control driver 120 is shown. Fig. 9 The light emission control driver 120 may be configured inside the first internal circuit part 110 and / or the second internal circuit part 120. For convenience, the second internal circuit part 120 may be considered as a light emission control driver including a plurality of light emission control stages that sequentially output light emission control signals.

[0115] refer to Fig. 9 , the light emission control driver 120 is provided with a plurality of light emission control stages EST1 to EST4. Each of the light emission control stages EST1 to EST4 is connected to a corresponding one of the light emission control lines E1 to E4. The light emission control stages EST1 to EST4 operate based on clock signals CLK3, CLK4. In one embodiment, the light emission control stages EST1 to EST4 may be in the same circuit. Furthermore, in another embodiment, the number of light emission control stages may be different from four.

[0116] Each of the light emitting control stages EST1 to EST4 includes first to third input terminals 2001 to 2003 and an output terminal 2004. The first input terminal 2001 of each of the light emitting control stages EST1 to EST4 is supplied with an output signal (e.g., a light emitting control signal) of a previous light emitting control stage or a second start pulse SSP2. For example, the first input terminal 2001 of the first light emitting control stage EST1 is supplied with a second start pulse SSP2. The first input terminals 2001 of the remaining light emitting control stages EST2 to EST4 are supplied with an output signal of a previous light emitting control stage.

[0117] The second input terminal 2002 of the jth light emission control stage ESTj is supplied with the third clock signal CLK3 and the third input terminal 2003 is supplied with the fourth clock signal CLK4. The second input terminal 2002 of the j+1th light emission control stage ESTj+1 is supplied with the fourth clock signal CLK4 and the third input terminal 2003 is supplied with the third clock signal CLK3.

[0118] The third clock signal CLK3 and the fourth clock signal CLK4 may have the same period and non-overlapping phases. For example, each clock signal CLK3, CLK4 may have a period of 2H and may be supplied in different horizontal periods.

[0119] In addition, each of the light emission control stages EST1 to EST4 is supplied with a third driving power supply VDD1 and a fourth driving power supply VSS1. The third driving power supply VDD1 may be set as a gate-off voltage, and the fourth driving power supply VSS1 may be set as a gate-on voltage. According to an embodiment, the third driving power supply VDD1 may be set to the same voltage as the first driving power supply VDD, and the fourth driving power supply VSS1 may be set to the same voltage as the second driving power supply VSS.

[0120] Fig.10 Show Fig. 9 For convenience, Fig.10 A first light emission control stage EST1 and a second light emission control stage EST2 are shown.

[0121] refer to Fig.10 The first light emission control stage EST1 includes a first signal processor 2100, a second signal processor 2200, a third signal processor 2300 and an output circuit 2400 (or a buffer). The first signal processor 2100 controls the voltages of the 22nd node N22 and the 21st node N21 based on the signals supplied to the first input terminal 2001 and the second input terminal 2002.

[0122] To this end, the first signal processor 2100 includes 11th to 13th transistors M11 to M13. The 11th transistor M11 is connected between the first input terminal 2001 and the 21st node N21. The gate electrode of the 11th transistor M11 is connected to the second input terminal 2002. The 11th transistor M11 is turned on when the third clock signal CLK3 is supplied to the second input terminal 2002.

[0123] The twelfth transistor M12 is connected between the second input terminal 2002 and the 22nd node N22. A gate electrode of the twelfth transistor M12 is connected to the 21st node N21. The twelfth transistor M12 is turned on or off in response to a voltage of the 21st node N21.

[0124] The thirteenth transistor M13 is connected between the fourth driving power source VSS1 and the twenty-second node N22. A gate electrode of the thirteenth transistor M13 is connected to the second input terminal 2002. The thirteenth transistor M13 is turned on when the third clock signal CLK3 is supplied to the second input terminal 2002.

[0125] The second signal processor 2200 controls the 21st and 23rd nodes N21 and N23 based on the signal supplied to the third input terminal 2003 and the voltage of the 22nd node N22. To this end, the second signal processor 2200 includes 14th to 17th transistors M14 to M17, 11th and 12th capacitors C11 and C12.

[0126] The fourteenth transistor M14 is connected between the fifteenth transistor M15 and the twenty-first node N21. A gate electrode of the fourteenth transistor M14 is connected to the third input terminal 2003. The fourteenth transistor M14 is turned on when the fourth clock signal CLK4 is supplied to the third input terminal 2003.

[0127] The fifteenth transistor M15 is connected between the third driving power source VDD1 and the fourteenth transistor M14. A gate electrode of the fifteenth transistor M15 is connected to the twenty-second node N22. The fifteenth transistor M15 is turned on or off based on the voltage of the twenty-second node N22.

[0128] The sixteenth transistor M16 is connected between the first electrode of the seventeenth transistor M17 and the third input terminal 2003. A gate electrode of the sixteenth transistor M16 is connected to the twenty-second node N22. The sixteenth transistor M16 is turned on or off based on the voltage of the twenty-second node N22.

[0129] The seventeenth transistor M17 is connected between the first electrode of the sixteenth transistor M16 and the twenty-third node N23. The gate electrode of the seventeenth transistor M17 is connected to the third input terminal 2003. The seventeenth transistor M17 is turned on when the fourth clock signal CLK4 is supplied to the third input terminal 2003.

[0130] The eleventh capacitor C11 is connected between the twenty-first node N21 and the third input terminal 2003 .

[0131] The twelfth capacitor C12 is connected between the twenty-second node N22 and the first electrode of the seventeenth transistor M17.

[0132] The third signal processor 2300 controls the voltage of the 23rd node N23 based on the voltage of the 21st node N21. To this end, the third signal processor 2300 includes an 18th transistor M18 and a 13th capacitor C13. The 18th transistor M18 is connected between the third driving power supply VDD1 and the 23rd node N23. The gate electrode of the 18th transistor M18 is connected to the 21st node N21. The 18th transistor M18 is turned on or off based on the voltage of the 21st node N21.

[0133] The thirteenth capacitor C13 is connected between the third driving power source VDD1 and the twenty-third node N23.

[0134] The output circuit 2400 controls the voltage supplied to the output terminal 2004 based on the voltages of the 21st node N21 and the 23rd node N23. To this end, the output circuit 2400 includes a 19th transistor M19 and a 20th transistor M20. The 19th transistor M19 is connected between the third driving power supply VDD1 and the output terminal 2004. The gate electrode of the 19th transistor M19 is connected to the 23rd node N23. Such a 19th transistor M19 is turned on or off based on the voltage of the 23rd node N23.

[0135] The twentieth transistor M20 is connected between the output terminal 2004 and the fourth driving power supply VSS1. The gate electrode of the twentieth transistor M20 is connected to the twenty-first node N21. The twentieth transistor M20 is turned on or off based on the voltage of the twenty-first node N21. The output circuit 2400 operates as a buffer. In addition, the nineteenth transistor M19 and / or the twentieth transistor M20 can be configured so that a plurality of transistors are connected in parallel.

[0136] Fig.11 Shown for drive Fig.10 For convenience, Fig.11 An operation process using the first light emission control stage EST1 is shown.

[0137] refer to Fig.11 , the third clock signal CLK3 and the fourth clock signal CLK4 have two (2) horizontal periods (2H) cycles and are supplied in different horizontal periods. For example, the fourth clock signal CLK4 is set to be a signal shifted from the third clock signal CLK3 by up to half a period (for example, 1 horizontal period).

[0138] When the second start pulse SSP2 is supplied, the first input terminal 2001 may be set to the voltage of the third drive power supply VDD1. When the second start pulse SSP2 is not supplied, the first input terminal 2001 may be set to the voltage of the fourth drive power supply VSS1. In addition, when the clock signal CLK is supplied to the second input terminal 2002 and the third input terminal 2003, the second input terminal 2002 and the third input terminal 2003 may be set to the voltage of the fourth drive power supply VSS1. When the clock signal CLK is not supplied, the second input terminal 2002 and the third input terminal 2003 may be set to the voltage of the third drive power supply VDD1.

[0139] The second start pulse SSP2 supplied to the first input terminal 2001 may be supplied to be synchronized with the clock signal (e.g., the third clock signal CLK3) supplied to the second input terminal 2002. In addition, the second start pulse SSP2 is set to have a greater width than the third clock signal CLK3. For example, the second start pulse SSP2 may be supplied for four (4) horizontal periods 4H.

[0140] During operation, during the first time t1, the third clock signal CLK3 is supplied to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 are turned on. When the eleventh transistor M11 is turned on, the first input terminal 2001 and the twenty-first node N21 are electrically connected. Since the second start pulse SSP2 is not supplied to the first input terminal 2001, a low voltage is supplied to the twenty-first node N21.

[0141] When the low voltage is supplied to the 21st node N21, the 12th transistor M12, the 18th transistor M18 and the 20th transistor M20 are turned on. When the 18th transistor M18 is turned on, the third driving power supply VDD1 is supplied to the 23rd node N23. Therefore, the 19th transistor M19 is turned off. The 13th capacitor C13 is charged with a voltage corresponding to the third driving power supply VDD1. Therefore, even after the first time t1, the 19th transistor M19 stably maintains a turned-off state.

[0142] When the twentieth transistor M20 is turned on, the voltage of the fourth driving power source VSS1 is supplied to the output terminal 2004. Therefore, during the first time t1, the light emitting control signal is not supplied to the first light emitting control line E1.

[0143] When the twelfth transistor M12 is turned on, the third clock signal CLK3 is supplied to the twenty-second node N22. In addition, when the thirteenth transistor M13 is turned on, the voltage of the fourth driving power supply VSS1 is supplied to the twenty-second node N22. The third clock signal CLK3 is set to the voltage of the fourth driving power supply VSS1. Therefore, the twenty-second node N22 is stably set to the voltage of the fourth driving power supply VSS1. At the same time, when the voltage of the twenty-second node N22 is set to the voltage of the fourth driving power supply VSS1, the seventeenth transistor M17 is set to a cut-off state. Therefore, regardless of the twenty-second node N22, the twenty-third node N23 maintains the voltage of the third driving power supply VDD1.

[0144] During the second time t2, the third clock signal CLK3 is stopped from being supplied to the second input terminal 2002. When the third clock signal CLK3 is stopped, the eleventh transistor M11 and the thirteenth transistor M13 are turned off. The voltage of the twenty-first node N21 is maintained at a low voltage through the eleventh capacitor C11. Therefore, the twelfth transistor M12, the eighteenth transistor M18 and the twentieth transistor M20 remain in a conducting state.

[0145] When the twelfth transistor M12 is turned on, the second input terminal 2002 and the twelfth node N22 are electrically connected to each other and the twelfth node N22 is set to a high voltage.

[0146] When the eighteenth transistor M18 is turned on, the voltage of the third driving power source VDD1 is supplied to the twenty-third node N23. Therefore, the nineteenth transistor M19 maintains a turned-off state.

[0147] When the twentieth transistor M20 is turned on, the voltage of the fourth driving power source VSS1 is supplied to the output terminal 2004 .

[0148] During the third time t3, the fourth clock signal CLK4 is supplied to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 are turned on. When the seventeenth transistor M17 is turned on, the twelfth capacitor C12 is electrically connected to the twenty-third node N23. The twenty-third node N23 maintains the voltage of the third driving power supply VDD1. In addition, when the fourteenth transistor M14 is turned on, the fifteenth transistor M15 is set to a cut-off state. Therefore, even when the fourteenth transistor M14 is turned on, the voltage of the twenty-first node N21 will not change.

[0149] When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the voltage of the 21st node N21 is reduced to a voltage lower than the voltage of the fourth driving power supply VSS1 through the coupling of the 11th capacitor C11. When the voltage of the 21st node N21 is reduced to a voltage lower than the voltage of the fourth driving power supply VSS1, the driving characteristics of the 18th transistor M18 and the 20th transistor M20 are improved (for example, the lower the level of the voltage applied to the PMOS transistor, the better the driving characteristics of the PMOS transistor).

[0150] During the fourth time t4, the second start pulse SSP2 is supplied to the first input terminal 2001, and the third clock signal CLK3 is supplied to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 are turned on. When the eleventh transistor M11 is turned on, the first input terminal 2001 and the twenty-first node N21 are electrically connected. Since the second start pulse SSP2 is supplied to the first input terminal 2001, a high voltage is supplied to the twenty-first node N21. When the high voltage is supplied to the twenty-first node N21, the twelfth transistor M12, the eighteenth transistor M18 and the twentieth transistor M20 are turned off.

[0151] When the thirteenth transistor M13 is turned on, the voltage of the fourth driving power source VSS1 is supplied to the twenty-second node N22. Since the fourteenth transistor M14 is set to the off state, the twenty-first node N21 maintains a high voltage. In addition, since the seventeenth transistor M17 is set to the off state, the voltage of the twenty-third node N23 is maintained at a high voltage through the thirteenth capacitor C13. Therefore, the nineteenth transistor M19 maintains the off state.

[0152] During the fifth time t5, the fourth clock signal CLK4 is supplied to the third input terminal 2003. When the fourth clock signal CLK4 is supplied to the third input terminal 2003, the fourteenth transistor M14 and the seventeenth transistor M17 are turned on. Since the voltage of the twenty-second node N22 is set to the voltage of the fourth driving power supply VSS1, the fifteenth transistor M15 and the sixteenth transistor M16 are turned on.

[0153] When the sixteenth transistor M16 and the seventeenth transistor M17 are turned on, the fourth clock signal CLK4 is supplied to the twenty-third node N23. When the fourth clock signal CLK4 is supplied to the twenty-third node N23, the nineteenth transistor M19 is turned on. When the nineteenth transistor M19 is turned on, the voltage of the third driving power supply VDD1 is supplied to the output terminal 2004. The voltage of the third driving power supply VDD1 supplied to the output terminal 2004 is a light emitting control signal supplied to the first light emitting control line E1 on the first horizontal line.

[0154] When the voltage of the fourth clock signal CLK4 is supplied to the 23rd node N23, the voltage of the 22nd node N22 is lowered to a voltage lower than the voltage of the fourth driving power source VSS1 by the coupling of the twelfth capacitor C12. Therefore, the driving characteristics of the transistor connected to the 22nd node N22 can be improved.

[0155] When the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the voltage of the third driving power source VDD1 is supplied to the twenty-first node N21. When the voltage of the third driving power source VDD1 is supplied to the twenty-first node N21, the twentieth transistor M20 remains in the off state. Therefore, the voltage of the third driving power source VDD1 can be stably supplied to the first light emitting control line E1.

[0156] During the sixth time t6, the third clock signal CLK3 is supplied to the second input terminal 2002. When the third clock signal CLK3 is supplied to the second input terminal 2002, the eleventh transistor M11 and the thirteenth transistor M13 are turned on. When the eleventh transistor M11 is turned on, the twenty-first node N21 and the first input terminal 2001 are electrically connected. Therefore, the voltage of the twenty-first node N21 is set to a low voltage. When the voltage of the twenty-first node N21 is set to a low voltage, the eighteenth transistor M18 and the twentieth transistor M20 are turned on.

[0157] When the eighteenth transistor M18 is turned on, the voltage of the third driving power supply VDD1 is supplied to the twenty-third node N23. Therefore, the nineteenth transistor M19 is turned off. When the twentieth transistor M20 is turned on, the voltage of the fourth driving power supply VSS1 is supplied to the output terminal 2004. The voltage of the fourth driving power supply VSS1 supplied to the output terminal 2004 is supplied to the first light emission control line E1. Therefore, the light emission control signal is stopped from being supplied.

[0158] As the above process is repeated, the light emission control stage EST according to the present embodiment can sequentially output light emission control signals to the light emission control lines. Figures 5 to 11 In one embodiment, the transistor is a PMOS transistor. In another embodiment, the transistor may be an NMOS transistor.

[0159] Fig.12 Another embodiment of a display device 300 is shown, and the display device 300 includes at least one power line 310 arranged on the periphery of the first internal circuit part 110 and / or the second internal circuit part 120. For example, the power line 310 may be a first power line or a second power line for supplying the first power ELVDD or the second power ELVSS to the pixel area AA.

[0160] According to an embodiment, the first power line may be arranged on different sides or only one side of the pixel area AA. In addition, the second power line may be separated from the first power line and arranged on different sides or only one side of the pixel area AA.

[0161] According to an embodiment, the power line 310 may be arranged in the first non-pixel area NA1 together with the first internal circuit portion 110 and / or the second internal circuit portion 120. In addition, according to an embodiment, the power line 310 may be arranged in the second non-pixel area NA2, or arranged on a boundary between the first non-pixel area NA1 and the second non-pixel area NA2. According to an embodiment, at least a portion of the power line 310 may be provided between the first internal circuit portion 110 and / or the second internal circuit portion 120 and an edge portion (or corner) of the display device 300.

[0162] The power line 310 is connected to one or more power connection lines. According to an embodiment, one or more power connection lines may be arranged to pass between levels in the first internal circuit portion 110 and / or the second internal circuit portion 120. In addition, according to an embodiment, the power connection line may be arranged on a different layer from the circuit elements in the first internal circuit portion 110 and / or the second internal circuit portion 120, with at least one insulating layer therebetween. The power line 310 may be connected to the pad portion via a power supply line. The power line 310 may be provided with a certain power supply from an external power supply circuit.

[0163] According to an embodiment, the power line 310 may have at least one end rounded in the form of a curve corresponding to the shape of the pixel area AA as in the first internal circuit part 110 and / or the second internal circuit part 120 .

[0164] Fig.13Another embodiment of a display device 400 is shown, and the display device 400 includes at least one power line or line 410 overlapping an adjacent internal circuit portion (e.g., the first internal circuit portion 110 or the second internal circuit portion 120). For example, at least one area of ​​the power line 410 may be superimposed on a first end of the adjacent first internal circuit portion 110 or the second internal circuit portion 120. The power line 410 may be designed, for example, so that at least one area adjacent to a circular first corner of the pixel area AA is superimposed on a circular first end of the first internal circuit portion 110 or the second internal circuit portion 120.

[0165] When the power line 410 and the first internal circuit portion 110 or the second internal circuit portion 120 are superimposed in this manner, the power line 410 can ensure insulation quality from the circuit elements in the first internal circuit portion 110 or the second internal circuit portion 120. For example, the power line 410 may include one or more conductive layers on a layer different from a layer in which the circuit elements in the first internal circuit portion 110 or the second internal circuit portion 120 are formed, and the first internal circuit portion 110 or the second internal circuit portion 120 is superimposed on the power line 410. In addition, in the region superimposed with at least the first internal circuit portion 110 or the second internal circuit portion 120, the power line 410 may be embodied as a connection line that passes between the stages of the first internal circuit portion 110 or the second internal circuit portion 120.

[0166] As described above, at least one area of ​​the power line 410 (eg, an area adjacent to the rounded corner of the display device 400) may overlap with the first internal circuit part 110 or the second internal circuit part 120. Therefore, the corner dead zone of the display device 400 may be reduced.

[0167] Fig.14 Shown along Fig.13 An embodiment of a cross section taken along line II-II'. Fig.14 , each pixel region 102A includes a pixel transistor P_TR and an organic light emitting diode OLED electrically connected to the pixel transistor P_TR. The internal circuit portion region 110A includes a driving transistor D_TR, and the power line region 410A includes a power line 410. The pixel transistor P_TR and the driving transistor D_TR are located on a buffer layer 103 formed on the substrate 101. The buffer layer 103 may be omitted.

[0168] The pixel transistor P_TR includes a semiconductor layer 102a, a gate electrode 102b, and a source electrode and a drain electrode 102c. A first insulating layer 104 (e.g., a gate insulating layer) is between the semiconductor layer 102a and the gate electrode 102b. A second insulating layer 105 (e.g., a first interlayer insulating layer) is between the gate electrode 102b and the source electrode and the drain electrode 102c. A third insulating layer 106 (e.g., a second interlayer insulating layer) is disposed on the source electrode and the drain electrode 102c. A passivation layer 107 is disposed on the upper portion of the third insulating layer 106. The pixel transistor P_TR is electrically connected to the organic light emitting diode OLED through a through hole (or contact hole) that penetrates the third insulating layer 106 and the passivation layer 107.

[0169] The organic light emitting diode OLED includes: a first electrode 102d (e.g., an anode electrode) located on a passivation layer 107, a light emitting layer 102e located on the first electrode 102d, and a second electrode 102f (e.g., a cathode electrode) located on the light emitting layer 102e. An encapsulation layer 140 including a first encapsulation layer 142 and a second encapsulation layer 144 is formed on the upper portion of the organic light emitting diode OLED. Reference numeral 102g is a pixel defining layer.

[0170] The driving transistor D_TR includes a semiconductor layer 110a, a gate electrode 110b, and a source electrode and a drain electrode 110c. The first insulating layer 104 is between the semiconductor layer 110a and the gate electrode 110b. The second insulating layer 105 is between the gate electrode 110b and the source electrode and the drain electrode 110c. A third insulating layer 106 and a passivation layer 107 are formed on the upper portion of the driving transistor D_TR. An encapsulation layer 140 including a first encapsulation layer 142 and a second encapsulation layer 144 is formed on the upper portion of the third insulating layer 106 and the passivation layer 107.

[0171] According to an embodiment, the power line 410 may have a double-layer structure including a first conductive layer 410a and a second conductive layer 410b electrically connected to the first conductive layer 410a. The first conductive layer 410a may constitute a first line, and the second conductive layer 410b may constitute a second line. In other words, the power line 410 may have a multi-layer structure including a first line and a second line electrically connected to each other. When the power line 410 adopts a double-layer structure, the resistance of the line can be reduced, thereby preventing screen degradation caused by RC delay.

[0172] The third insulating layer 106 is located between the first conductive layer 410a and the second conductive layer 410b. The first conductive layer 410a and the second conductive layer 410b may be electrically connected to each other through a contact hole in the third insulating layer 106.

[0173] According to an embodiment, the first conductive layer 410a may be formed on the same layer (e.g., a first source electrode drain electrode layer) as the electrode of the driving transistor D_TR and / or the electrode of the pixel transistor P_TR. For example, the first conductive layer 410a may be located on the same layer as the source electrode and drain electrode 102c, 110c of the uppermost layer of the electrodes constituting the driving transistor D_TR and the pixel transistor P_TR. In addition, the second conductive layer 410b is located on the first conductive layer 410a, and one or more insulating layers (e.g., a third insulating layer 106) are provided between the first conductive layer 410a and the second conductive layer 410b. For example, the second conductive layer 410b may be located on a second source electrode drain electrode layer arranged on a further upper portion of the first source electrode drain electrode layer. The second conductive layer 410b may be provided on a layer between a layer on which the first electrode 102d is provided and a layer on which the first conductive layer 410a is provided. For example, when the first electrode 102d is located on a first layer and the first conductive layer 410a is located on a second layer, the second conductive layer 410b is located on a third layer between the first layer and the second layer.

[0174] Fig.14 An embodiment in which the first encapsulation layer 142 is formed only on one region of the power line 410 is shown. In other embodiments, the arrangement relationship between the power line 410 and the first encapsulation layer 142 may be different. In the display device 400, the power line 410 includes at least one second conductive layer 410b, which is on a layer different from the layer on which the circuit element (e.g., the driving transistor D_TR in the internal circuit portion region 110A) is formed. Therefore, when at least one region of the power line 410 is superimposed on the first internal circuit portion 110 or the second internal circuit portion 120 to reduce the dead zone, the power line 410 and the first internal circuit portion 110 or the second internal circuit portion 120 can be designed to ensure electrical stability (insulation) therebetween.

[0175] According to an embodiment, the power line 410 may be a first power line for supplying a first power source ELVDD to the pixel 102. In this case, the power line 410 may be electrically connected to the first electrode 102d via the pixel transistor P_TR. According to another embodiment, the power line 410 may be a second power line for supplying a second power source ELVSS to the pixel 102. In this case, the power line 410 may be electrically connected to the second electrode 102f.

[0176] Fig.15 Show Fig.13 An embodiment of a region (PB region) of a display device in FIG. Fig.15The power supply line 410 includes a first conductive layer 410a and a second conductive layer 410b. One region of the power supply line 410 is superimposed on, for example, a first end portion (eg, a lower end portion) of the first internal circuit portion 110.

[0177] The first conductive layer 410a arranged on the same layer as the circuit elements in the first internal circuit portion 110 has a width that decreases and becomes thinner in a direction approaching a corner portion adjacent to the first end portion so that it is not superimposed on the first end portion of the first internal circuit portion 110. For example, the width of the first conductive layer 410a decreases as it approaches a corner portion where the width of the region where the power line 410 overlaps the first internal circuit portion 110 increases.

[0178] The first conductive layer 410a may be located on the rest of the region except for the region where the power line 410 overlaps the first internal circuit portion 110. This may prevent a short circuit defect from being formed between the power line 410 and the first internal circuit portion 110.

[0179] On the other hand, at least one region of the second conductive layer 410b located on a layer different from the layer on which the circuit element in the first internal circuit portion 110 is formed may be superimposed on the first end portion of the first internal circuit portion 110 with one or more insulating layers between the circuit element and the at least one region.

[0180] As in the above embodiment, by superimposing at least one region of the power line 410 (eg, a region adjacent to a corner of the display device 400 ) on the first internal circuit portion 110 , the dead area of ​​the non-pixel area NA may be significantly reduced.

[0181] Fig.16 Show Fig.13 Another embodiment of a region (PB region) of a display device in FIG. Fig.16 , the width of the second conductive layer 410b of the power line 410 may be expanded in the region overlapping with the first internal circuit portion 110. For example, the width of the second conductive layer 410b in the region overlapping with the first internal circuit portion 110 (e.g., the second width w2) may be greater than its width in the remaining region not overlapping with the first internal circuit portion 110 (e.g., the first width w1). For example, the second width w2 may be set to be approximately two times or more greater than the first width w1.

[0182] As described above, when the width of the second conductive layer 410b is expanded in the region overlapping with the first internal circuit portion 110, the resistance increase can be compensated by removing the first conductive layer 401a from the overlapping region. Therefore, the resistance value of the power line 410 can be maintained at a constant or substantially constant value.

[0183] Fig.17 Show Fig.13 Another embodiment of a region (PB region) of a display device in FIG. Fig.17 In an area adjacent to a first end portion of the first internal circuit portion 110 (one of the ends in a rounded corner of the display device), the power line 410 is branched into at least two sub-power lines 412, 414 (e.g., a first sub-power line 412 and a second sub-power line 414), with a first end portion between the two sub-power lines 412, 414.

[0184] Each of the first sub power line 412 and the second sub power line 414 is located at the outside and inside of the first internal circuit portion 110. For example, the first sub power line 412 may be arranged adjacent to the outer periphery of the first end portion of the first internal circuit portion 110. The second sub power line 414 may be arranged adjacent to the inner periphery of the first end portion. According to an embodiment, the first sub power line 412 and / or the second sub power line 414 may be superimposed on at least one wiring line DR.

[0185] According to an embodiment, in the area where the first sub-power line 412 and the second sub-power line 414 face each other, the sum of the widths (w3+w4) of the first sub-power line 412 and the second sub-power line 414 can be set to be approximately the same as the first width w1 in the remaining area (unbranched area) of the power line 410, with the first internal circuit part 110 between the first sub-power line 412 and the second sub-power line 414. Approximately the same width may mean that the widths are the same or similar within a certain error range. Therefore, a constant (or approximately constant) resistance value (e.g., uniform resistance value) of the power line 410 can be maintained.

[0186] To this end, the width of the first sub power line 412 may decrease in a direction approaching the rounded corner of the display device 400. The width of the second sub power line 414 may increase in a direction approaching the rounded corner of the display device 400.

[0187] The first sub power line 412 and / or the second sub power line 414 may have a single-layer structure or a multi-layer structure. For example, as described above, both the first sub power line 412 and the second sub power line 414 may have a multi-layer structure including a first conductive layer 410a and a second conductive layer 410b. In this case, the wiring DR may be formed on a layer different from the first conductive layer 410a and the second conductive layer 410b, with one or more insulating layers between the wiring DR and the first conductive layer 410a and the second conductive layer 410b. The wiring DR may be located, for example, on a gate layer.

[0188] When the wiring DR is located on the same layer as the first conductive layer 410a or the second conductive layer 410b, in the area where the first sub-power line 412 and / or the second sub-power line 414 is superimposed on the wiring DR, the conductive layer located on the same layer as the wiring DR (i.e., the first conductive layer 410a or the second conductive layer 410b) can be partially removed.

[0189] The power line 410 may include a connection line 416 for electrically connecting the first sub power line 412 and the second sub power line 414 .

[0190] According to an embodiment, the connection line 416 may pass through the region between the plurality of stages in the first internal circuit portion 110 and connect the first sub power line 412 and the second sub power line 414. In this case, the connection line 416 may be formed by the first conductive layer 410a and / or the second conductive layer 410b. For example, the connection line 416 may be integrally located with the first conductive layer 410a on the first source electrode drain electrode layer, or integrally located with the second conductive layer 410b on the second source electrode drain electrode layer.

[0191] When the connection line 416 is implemented as the second conductive layer 410b located on the second source electrode and drain electrode layer, the connection line 416 is connected to the driving transistor (eg, Fig.14 The D_TR in the power supply line 410 is located on a different layer, and at least one insulating layer is provided between the connection line 416 and the transistor. In this case, even if the connection line 416 is superimposed on at least one level in the first internal circuit portion 110, a short circuit defect between the power supply line 410 and the first internal circuit portion 110 can be prevented.

[0192] Fig.18 Another embodiment of a display device 500 is shown. Fig.18 In the above-described embodiment, the following embodiment may be applied without considering the arrangement structure of the wiring DR, in which the dead zone is reduced by superimposing the power line 410 on the first internal circuit portion 110 or the second internal circuit portion 120 adjacent to the power line 410 in at least one area (for example, a corner of the display device). For example, Figures 13 to 17 The embodiment in the embodiment can also be applied to the display device 500, in which the wiring DR is as follows Fig.18 The general fan-out pattern shown is used for routing.

[0193] By selectively applying Figures 1 to 18 The embodiments or a combination of these embodiments can significantly reduce the dead area in the display device.

[0194] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art as of the filing of this application, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically stated. Therefore, it will be understood by those skilled in the art that various modifications may be made to form and detail without departing from the spirit and scope of the embodiments set forth in the claims.

Claims

1. A display device, include: A substrate including a pixel region having at least a first rounded corner and non-pixel regions sequentially arranged along a periphery of the pixel region; A plurality of pixels in the pixel area, at least one of the pixels comprising: a transistor on the substrate, the transistor having a semiconductor layer, a gate electrode, and source and drain electrodes; a first electrode on a first layer on the transistor; a light emitting layer on the first electrode; and a second electrode on the light emitting layer; an internal circuit in the non-pixel region and having a first end adjacent to the first rounded corner of the pixel region; a plurality of wirings, in the non-pixel region below the pixel region, the wirings extending from the non-pixel region to the pixel region; and a power supply line in the non-pixel region and partially overlapping the first end portion in a plan view of the display device, at least a portion of the power supply line being provided between the internal circuit and an edge of the display device; wherein the power line branches into at least a first sub-power line and a second sub-power line in a region adjacent to the first end of the internal circuit, and wherein the first end is located between the first sub-power line and the second sub-power line.

2. The display device according to claim 1, in, The wiring includes at least a first wiring that passes through a region of the first end portion of the internal circuit and is connected to the pixel region.

3. The display device according to claim 2, in, The internal circuit includes a plurality of stages to sequentially output control signals.

4. The display device according to claim 3, in, The first wiring crosses a region between adjacent stages among the plurality of stages and is connected to the pixels in a first column.

5. The display device according to claim 2, in, The power supply line includes a first conductive layer on the second layer and a second conductive layer on the first conductive layer and electrically connected to the first conductive layer, the second conductive layer being provided on a third layer between the first layer and the second layer.

6. The display device according to claim 5, in: The first sub power line is adjacent to the outer periphery of the first end portion, and The second sub power line is adjacent to an inner circumference of the first end portion.

7. The display device according to claim 5, in, The power line further includes a connection line connecting the first sub power line and the second sub power line.

8. The display device according to claim 7, in, The connection line crosses a region between a plurality of stages in the internal circuit and electrically connects the first sub power line and the second sub power line.

9. The display device according to claim 7, in, The connection line includes a conductive layer on a different layer from the transistors in the internal circuit.

10. The display device according to claim 7, in, In an area where the first sub-power line and the second sub-power line face each other and the first end is located between the first sub-power line and the second sub-power line, the sum of the widths of the first sub-power line and the second sub-power line has a width equal to the width of the power line in an unbranched area.

11. The display device according to claim 1, in, The power line is electrically connected to the first electrode or the second electrode.

12. The display device according to claim 5, in, The wiring is on a layer different from the first conductive layer and the second conductive layer.

13. The display device according to claim 12, in, The second layer is interposed between the wiring and the first conductive layer.

14. The display device according to claim 5, in, The wiring is on the same layer as the first conductive layer or the second conductive layer.

15. The display device according to claim 14, in: When the wiring is on the same layer as the first conductive layer, the first conductive layer is partially removed in a region where the first sub power supply line and / or the second sub power supply line is superimposed on the wiring, and When the wiring is on the same layer as the second conductive layer, the second conductive layer is partially removed in a region where the first sub power supply line and / or the second sub power supply line is superimposed on the wiring.

16. A display device, include: A substrate including a pixel region and a non-pixel region; A plurality of pixels in the pixel area, at least one of the pixels comprising: a transistor on the substrate, the transistor having a semiconductor layer, a gate electrode, and source and drain electrodes; a first electrode on a first layer on the transistor; a light emitting layer on the first electrode; and a second electrode on the light emitting layer; a driving circuit in the non-pixel area, the driving circuit being configured to drive the pixel; and at least one power line partially overlapping an end of the drive circuit in the non-pixel region and in a plan view of the display device, at least a portion of the power line being provided between the drive circuit and an edge portion of the display device, the power line comprising a first conductive layer and a second conductive layer on the first conductive layer and electrically connected to the first conductive layer, and one or more insulating layers being present between the first conductive layer and the second conductive layer, so that the first conductive layer overlaps at least a portion of the second conductive layer in the plan view of the display device, Wherein, the second conductive layer is formed on an insulating layer covering a source electrode and a drain electrode of at least one driving transistor.

17. The display device according to claim 16, in, The power line is electrically connected to the second electrode.

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