Phased Array Chip Test System Architecture

Abstract

An embodiment of the present invention provides a phased array chip test system architecture, which relates to the field of chip testing technology. The phased array chip test system architecture includes a test circuit board, a phased array chip, a radio frequency probe, and a digital signal processing module. During actual testing, the test instrument can be communicatively connected with the radio frequency probe and the test circuit board, thereby respectively realizing functional testing of the radio frequency part and the digital part of the phased array chip. Compared with the prior art, the present invention is based on the design of the test circuit board structure and is combined with the digital wiring layer to realize complete functional testing of the phased array chip, and has low cost, short production cycle, and reliable structure. At the same time, it simplifies the requirements of the test environment and test equipment, and only requires external test instruments to realize the interconnection of the test platform and complete the corresponding test. In addition, the present invention is more comprehensive in testing the phased array chip, avoiding incomplete chip testing and potential risks of use.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a phased array chip testing system architecture. Background Art

[0002] Currently, the integrated circuit industry is rapidly developing, with chip manufacturing, packaging, and testing becoming key areas of development for the entire industry. As chip integration increases, more and more phased array chips are appearing. The requirements for testing phased array chips are becoming increasingly complex. Currently, there are a variety of chip testing solutions, but they primarily target functional verification of digital chips. There is a lack of comprehensive testing solutions for phased array chips on the market. The inventors' research has revealed that existing testing technologies struggle to fully perform comprehensive functional testing on phased array chips. Therefore, a new testing method is urgently needed to address the complex functional verification of phased array chips. Summary of the Invention

[0003] The objectives of the present invention include, for example, providing a phased array chip test system architecture that can test phased array chips, simultaneously perform functional testing of the RF and digital parts of the phased array chip, and fully test whether the RF function of the phased array chip is qualified and whether there are any problems with digital signal transmission, thereby solving the problem of complex functional verification of phased array chips.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a phased array chip test system architecture, comprising:

[0006] Test circuit boards;

[0007] A phased array chip, wherein the phased array chip is mounted on the test circuit board;

[0008] A radio frequency probe is provided above the test circuit board and is used to electrically contact the phased array chip to achieve transmission of radio frequency signals of the phased array chip;

[0009] The test circuit board is provided with a digital wiring layer, the phased array chip is electrically connected to the digital wiring layer, and the digital wiring layer is used to realize the transmission of digital signals of the phased array chip.

[0010] In an optional embodiment, the phased array chip test system architecture further includes a digital signal processing module, which is communicatively connected to the digital wiring layer and is used to control the digital signal of the phased array chip and implement digital signal testing of the phased array chip.

[0011] In an optional embodiment, a mounting area for mounting the phased array chip is provided on the test circuit board, the phased array chip is mounted in the mounting area, and a plurality of conductive gold wires are provided on a surface of the phased array chip away from the test circuit board. The conductive gold wires are connected to the digital wiring layer to electrically connect the phased array chip to the digital wiring layer.

[0012] In an optional embodiment, the digital wiring layer includes a power supply line and a digital transmission line, and a power interface and a digital interface are also provided on the test circuit board. The power interface is provided at one end of the power supply line, and the other end of the power supply line extends to the phased array chip and is electrically connected to the phased array chip through the conductive gold wire; the digital interface is provided at one end of the digital transmission line, and the other end of the digital transmission line extends to the phased array chip and is electrically connected to the phased array chip through the conductive gold wire, and the digital signal processing module is communicatively connected to the digital interface.

[0013] In an optional embodiment, the power supply line and the digital transmission line both extend to the mounting area, a digital pin is provided at an end of the digital transmission line away from the digital interface, and the digital pin is electrically connected to the phased array chip through the conductive gold wire, and a power supply pin is provided at an end of the power supply line away from the power interface, and the power supply pin is electrically connected to the phased array chip through the conductive gold wire.

[0014] In an optional embodiment, the power supply lines are distributed on both sides of the mounting area, and the power supply pins are set on both sides of the mounting area, and the power supply interfaces are set at the ends of the two power supply lines away from the mounting area.

[0015] In an optional implementation, the digital signal processing module and the digital interface are connected via an SPI serial port communication.

[0016] In an optional embodiment, the phased array chip is bonded to the mounting area by conductive adhesive.

[0017] In an optional embodiment, the digital signal processing module is an FPGA module, and the FPGA module is used to connect to a central control computer and to set the register state of the phased array chip.

[0018] In an optional embodiment, the phased array chip test system architecture also includes a probe station, the RF probe is arranged on the probe station, and a RF pin is provided on the side of the phased array chip away from the test circuit board. The RF probe is used to move to the top of the phased array chip under the drive of the probe station and align with the RF pin to achieve RF signal interconnection.

[0019] The beneficial effects of the embodiments of the present invention include, for example:

[0020] The phased array chip testing system architecture provided by the present invention utilizes an additional test circuit board with a digital wiring layer. The phased array chip is mounted on the test circuit board, and the digital wiring layer is electrically connected to the phased array chip to transmit the phased array chip's digital signals. Furthermore, a probe located above the test circuit board and in electrical contact with the phased array chip enables transmission of the phased array chip's radio frequency (RF) signals. During actual testing, the test instrument can be communicatively connected to the RF probe and the test circuit board, thereby separately performing functional testing of the RF and digital components of the phased array chip. The test circuit board has a simple structure and is easy to manufacture, addressing the high cost and incomplete functional verification issues of prior art phased array chip testing. Compared to prior art, the present invention, based on the design of the test circuit board structure and combined with the digital wiring layer, enables complete functional testing of phased array chips with low cost, short production cycle, and reliable structure. It also simplifies the requirements for the test environment and test equipment, requiring only external test instruments to interconnect the test platform and complete the corresponding tests. Furthermore, the present invention provides more comprehensive testing of phased array chips, avoiding potential risks associated with incomplete chip testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of the structure of the phased array chip test system architecture provided by the present invention from a first perspective;

[0023] Figure 2 This is a structural schematic diagram of the phased array chip testing system architecture provided by the present invention from a second perspective.

[0024] Icons: 100-Phase-controlled array chip test system architecture; 110-Test circuit board; 111-Digital wiring layer; 113-Power supply line; 115-Digital transmission line; 130-Phase-controlled array chip; 131-Conductive gold wire; 133-Conductive adhesive; 150-RF probe; 170-Digital signal processing module; 180-Power interface; 190-Digital interface. DETAILED DESCRIPTION

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0027] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0028] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0029] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0030] As disclosed in the background art, the test systems for digital chips in the prior art are very mature and there are various test solutions. However, they are mainly aimed at functional verification of digital chips.

[0031] Considering some digital chip testing methods, the main ones include probe card testing, built-in self-test (BIST), and FPGA testing. These methods are highly effective for digital chip testing, enabling rapid and accurate performance verification. However, for phased array chips, these testing solutions struggle to verify their RF functionality and digital components. They can only simply test the interconnectivity between chip pads, failing to fully verify the RF functionality of the phased array chip or identify issues with digital signal transmission. Consequently, they offer no reference data for optimizing chip performance indicators and mass production.

[0032] For example, when testing phased array chips using low-frequency probe cards or probes, pin positions vary for different chips, requiring custom probe cards. During testing, if the low-frequency probe card or probe is used to power the RF chip, a relative offset in position can easily cause some power pins to open, preventing the test from completing properly.

[0033] In response to the above problems, the present invention provides a novel phased array chip test system architecture. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict. Specific embodiments

[0035] See also Figure 1 and Figure 2 This embodiment provides a phased array chip test system architecture 100 that can test a phased array chip 130, simultaneously performing functional testing on both the RF and digital components of the phased array chip 130. This system can fully verify the RF functionality of the phased array chip 130 and any issues with digital signal transmission, solving the complex functional verification challenges of the phased array chip 130. Furthermore, this system is cost-effective, has a short production cycle, and simplifies the requirements for the test environment and equipment. Simply connecting external test instruments is all that is required to interconnect the test platform and complete the corresponding tests.

[0036] The phased array chip test system architecture 100 provided in this embodiment includes a test circuit board 110, a phased array chip 130, a radio frequency probe 150, and a digital signal processing module 170. The phased array chip 130 is mounted on the test circuit board 110. The radio frequency probe 150 is disposed above the test circuit board 110 and is configured to electrically contact the phased array chip 130 to enable transmission of radio frequency signals from the phased array chip 130. A digital wiring layer 111 is provided on the test circuit board 110, electrically connected to the phased array chip 130, and configured to transmit digital signals from the phased array chip 130. The digital signal processing module 170 is communicatively connected to the digital wiring layer 111 and is configured to control the digital signals of the phased array chip 130 and perform digital signal testing on the phased array chip 130.

[0037] In this embodiment, the digital signal processing module 170 may be an FPGA module, which is programmed using an FPGA (Field Programmable Gate Array). The FPGA module is used to connect to a central control computer and set the register status of the phased array chip 130. The central control computer may be a conventional PC capable of performing programming, control, and analysis functions.

[0038] It should be noted that the FPGA-based digital signal processing module 170 in this embodiment primarily consists of a digital logic processing unit. Program code is loaded into the FPGA to implement SPI digital signal communication within the FPGA. This allows code to be input from a PC, controlling the FPGA module to set the register states of the phased array chip 130 via the SPI protocol. This allows for functional testing and verification of the PC's control of the phased array chip 130. Compared to traditional digital signal testing, this provides a more reliable testing environment and relatively simpler operation.

[0039] In this embodiment, the test circuit board 110 is provided with a mounting area for mounting a phased array chip 130. The phased array chip 130 is mounted upright in the mounting area. A plurality of conductive gold wires 131 are provided on the side of the phased array chip 130 facing away from the test circuit board 110. The conductive gold wires 131 are connected to the digital wiring layer 111, thereby electrically connecting the phased array chip 130 to the digital wiring layer 111. Specifically, the mounting area is located in the center of the test circuit board 110. The phased array chip 130 is mounted upright, with its backside facing downward and its RF and digital pins / pads (PADs) facing upward. A gold wire bonding process forms the plurality of conductive gold wires 131, establishing an electrical connection between the phased array chip 130 and the digital wiring layer 111.

[0040] It should be noted that in this embodiment, the test circuit board 110 is a PCB, which can be designed to match the position of the phased array chip 130 with the digital circuit layer based on the position information of the PAD on the phased array chip 130. Furthermore, in this embodiment, the conductive gold wire 131 can be made of copper and secured by soldering. Alternatively, the conductive gold wire 131 can be made of silver, aluminum, or other materials, without specific limitation.

[0041] In this embodiment, the phased array chip 130 is bonded to the mounting area via conductive adhesive 133. Specifically, the phased array chip 130 is bonded to the test circuit board 110 at high temperature via conductive adhesive 133, thereby achieving a structural connection between the phased array chip 130 and the test circuit board 110. Furthermore, a gold wire bonding process is used to achieve signal connections between different links of the phased array chip 130, and a gold wire bonding process is also used to achieve an electrical connection between the phased array chip 130 and the test circuit board 110.

[0042] The digital wiring layer 111 includes a power supply line 113 and a digital transmission line 115. The test circuit board 110 is also provided with a power interface 180 and a digital interface 190. The power interface 180 is arranged at one end of the power supply line 113, and the other end of the power supply line 113 extends to the phased array chip 130 and is electrically connected to the phased array chip 130 through a conductive gold wire 131; the digital interface 190 is arranged at one end of the digital transmission line 115, and the other end of the digital transmission line 115 extends to the phased array chip 130 and is electrically connected to the phased array chip 130 through a conductive gold wire 131. The digital signal processing module 170 is communicatively connected to the digital interface 190.

[0043] In this embodiment, the digital signal processing module 170 and the digital interface 190 communicate via an SPI serial port. Specifically, the digital interface 190 provided by the test circuit board 110 communicates with the digital processing module, thereby enabling program-controlled digital functions of the phased array chip 130. Finally, the RF probe 150 connects to the RF input and output of the phased array chip 130, completing the construction of a complete test platform for the phased array chip 130.

[0044] In this embodiment, both the power supply line 113 and the digital transmission line 115 extend to the mounting area. A digital pin is provided at the end of the digital transmission line 115 away from the digital interface 190. The digital pin is electrically connected to the phased array chip 130 via a conductive gold wire 131. A power supply pin is provided at the end of the power supply line 113 away from the power interface. The power supply pin is electrically connected to the phased array chip 130 via a conductive gold wire 131. Specifically, both the power supply line 113 and the digital transmission line 115 can be adaptively designed based on the structural and positional characteristics of the phased array chip 130.

[0045] It should be noted that in this embodiment, the power supply line 113 and the digital transmission line 115 are divided into multiple links, and each link is electrically connected to the phased array chip 130 through at least one conductive gold wire 131. By properly allocating the positions of the conductive gold wires 131, the number of channel tests of the phased array chip 130 can be increased, ensuring that all RF links and designed functions of the phased array chip 130 can be tested.

[0046] In this embodiment, the power supply lines 113 are distributed on both sides of the mounting area, and the power supply pins are set on both sides of the mounting area. The ends of the two power supply lines 113 away from the mounting area are both provided with power interfaces 180. By providing two power supply lines 113, the line power supply function can be better realized.

[0047] It should be noted that the test circuit board 110 can re-route the power supply line 113 and the digital transmission line 115 on the test circuit board 110 according to the PAD distribution on the phased array chip 130, so as to meet the power supply requirements and digital signal communication requirements of the phased array chip 130, and provide corresponding power supply interfaces and digital communication interfaces to provide hardware support for subsequent testing. During assembly, the phased array chip 130 can be bonded to the test circuit board at high temperature using conductive glue 133 to ensure that the phased array chip 130 and the test circuit board are fully bonded. Then, a gold wire bonding machine is used to bond the GND (Ground), power and digital signal PADs of the phased array chip 130 to the pin PADs of the circuit test board with gold wires to ensure that the phased array chip 130 and the corresponding GND, power PADs, and digital signal PADs on the test circuit board 110 are structurally connected to each other, thereby realizing signal transmission from the test circuit board 110 to the phased array chip 130. In order to ensure that all links of the chip can be tested, the chip power supply and GND need to be structurally interconnected through gold wire bonding to achieve power supply for each RF link.

[0048] Furthermore, the phased array chip test system architecture 100 also includes a probe station (not shown), on which a radio frequency probe 150 is arranged. A radio frequency pin is provided on the side of the phased array chip 130 away from the test circuit board 110. The radio frequency probe 150 is used to move to the top of the phased array chip 130 under the drive of the probe station and align with the radio frequency pin to achieve radio frequency signal interconnection.

[0049] In this embodiment, the RF probe 150 primarily performs RF functional testing and verification of the phased array chip 130. Calibration components are used to remove the effects of the cable and RF probe 150 on the RF signal. A probe station is then used to move the RF probe 150 to the chip's corresponding RF input and output pads, enabling RF signal interconnection. This is then connected to a network analyzer via a cable to collect and analyze data on the RF performance of the phased array chip 130. It should be noted that the network analyzer can also be connected to a central control computer for overall control.

[0050] This embodiment primarily addresses the high testing costs and incomplete functional verification of phased array chips 130. Conventional testing methods suffer from high costs, long cycles, demanding testing environments, poor stability, and difficulty in implementation. This embodiment, based on the structural design of the test circuit board 110 and cleverly integrated with FPGA digital communication, enables PC-controlled test programs and complete functional testing of the phased array chip 130. This embodiment also leverages the cost advantages and short production cycles of existing PCBs, combined with the relatively stable and mature FPGA digital signal processing technology, to provide a stable and comprehensive testing method for phased array chip 130 performance verification.

[0051] The phased array chip test system architecture 100 provided in this embodiment primarily addresses several issues with existing phased array chip 130 performance testing. First, cost and production cycle: Existing testing technologies, such as automated test equipment testing, probe card testing, and built-in self-test (BIST), have relatively high production costs and long production cycles, significantly increasing chip production costs and production time. This embodiment effectively addresses this issue. The PCB manufacturing process used to form the test circuit board 110 is mature and has a short production cycle, allowing it to be completed within the chip tape-out cycle. Furthermore, the bonding and gluing processes between the phased array chip 130 and the test circuit board 110 are mature and reliable, significantly reducing production costs. Second, testing environment and equipment requirements: Automated test equipment testing, probe card testing, and built-in self-test generally require specialized equipment and instruments, and can only be performed in wafer fabrication plants or packaging factories. This embodiment utilizes an organic combination of FPGA and PCB, significantly simplifying the testing environment and test equipment requirements. Only a computer, probe station, and cables are required to interconnect the test platforms and complete the corresponding tests. 3. Comprehensiveness of Testing: Existing testing methods can only simply test the digital signals of the phased array chip 130, but cannot fully and comprehensively test the RF performance of the phased array chip 130. This embodiment uses a computer-side test program to communicate with the FPGA through the serial port. Then, according to the digital signal protocol of the phased array chip 130, the chip's corresponding function register information is sent to the corresponding register position on the chip. This fully verifies all functions of the phased array chip 130, avoiding potential risks caused by incomplete chip testing.

[0052] In summary, the phased array chip test system architecture 100 utilizes an additional test circuit board with a digital wiring layer 111. The phased array chip 130 is mounted on the test circuit board 110, and the digital wiring layer 111 is electrically connected to the phased array chip 130 to enable transmission of digital signals from the phased array chip 130. Furthermore, the digital wiring layer 111 is located above the test circuit board 110 and in electrical contact with the phased array chip 130, enabling transmission of RF signals from the phased array chip 130. During actual testing, the test instrument can be communicatively connected to the RF probe 150 and the test circuit board 110, thereby separately performing functional testing of the RF and digital components of the phased array chip 130. Furthermore, the test circuit board 110 has a simple structure and is easy to manufacture, resolving the existing issues of high testing costs and incomplete functional verification of phased array chips 130. This embodiment, based on the structural design of test circuit board 110 and integrated with digital wiring layer 111, enables complete functional testing of phased array chip 130. This approach offers low cost, a short production cycle, and reliable structure. It also simplifies the requirements for the test environment and test equipment, requiring only external test equipment to interconnect the test platform and complete the corresponding tests. Furthermore, this invention provides more comprehensive testing of phased array chip 130, avoiding potential operational risks associated with incomplete chip testing.

[0053] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A phased array chip test system architecture, characterized in that: include: Test circuit boards; A phased array chip, wherein the phased array chip is mounted on the test circuit board; A radio frequency probe is provided above the test circuit board and is used to electrically contact the phased array chip to achieve transmission of radio frequency signals of the phased array chip; The test circuit board is provided with a digital wiring layer, the phased array chip is electrically connected to the digital wiring layer, and the digital wiring layer is used to realize the transmission of digital signals of the phased array chip; The phased array chip test system architecture further includes a digital signal processing module, which is communicatively connected to the digital wiring layer and is used to control the digital signal of the phased array chip and implement digital signal testing of the phased array chip; The digital wiring layer includes a power supply line and a digital transmission line. The test circuit board is also provided with a power interface and a digital interface. The power interface is provided at one end of the power supply line, and the other end of the power supply line extends to the phased array chip and is electrically connected to the phased array chip via a conductive gold wire. The digital interface is provided at one end of the digital transmission line, and the other end of the digital transmission line extends to the phased array chip and is electrically connected to the phased array chip via the conductive gold wire. The digital signal processing module is communicatively connected to the digital interface. The power supply circuit and the digital transmission circuit respectively meet the power supply requirements and digital signal communication requirements of the phased array chip.

2. The phased array chip test system architecture according to claim 1, characterized in that: The test circuit board is provided with a mounting area for mounting the phased array chip, the phased array chip is mounted on the mounting area, and a plurality of conductive gold wires are provided on a surface of the phased array chip away from the test circuit board. The conductive gold wires are connected to the digital wiring layer to electrically connect the phased array chip to the digital wiring layer.

3. The phased array chip test system architecture according to claim 2, characterized in that: The power supply line and the digital transmission line both extend to the mounting area. A digital pin is provided at one end of the digital transmission line away from the digital interface, and the digital pin is electrically connected to the phased array chip through the conductive gold wire. A power supply pin is provided at one end of the power supply line away from the power interface, and the power supply pin is electrically connected to the phased array chip through the conductive gold wire.

4. The phased array chip test system architecture according to claim 3, characterized in that: The power supply lines are distributed on both sides of the mounting area, and the power supply pins are arranged on both sides of the mounting area, and the power supply interfaces are arranged at the ends of the two power supply lines away from the mounting area.

5. The phased array chip test system architecture according to claim 1, characterized in that: The digital signal processing module is connected to the digital interface via an SPI serial communication port.

6. The phased array chip test system architecture according to claim 2, characterized in that: The phased array chip is bonded to the mounting area by conductive adhesive.

7. The phased array chip test system architecture according to claim 1, characterized in that: The digital signal processing module is an FPGA module, which is used to connect to a central control computer and to set the register state of the phased array chip.

8. The phased array chip test system architecture according to claim 1, characterized in that: The phased array chip test system architecture also includes a probe station, the RF probe is arranged on the probe station, and a RF pin is provided on the side of the phased array chip away from the test circuit board. The RF probe is used to move to the top of the phased array chip under the drive of the probe station and align with the RF pin to achieve RF signal interconnection.

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