Quality of service information for multi-memory systems

Abstract

This application relates to quality of service information for multi-memory systems. An interface controller can receive a first command from a host device during a set of clock cycles. The first command can be received over a command bus that includes a pin, such as a command select pin configured for double data rate signaling. The interface controller can decode the first command based on a state of the command select pin during at least one clock cycle of the set of clock cycles. Also, the interface controller can determine quality of service information for a second command based on decoding the first command and information included in the first command, such as a number of bits.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 648,400, filed January 19, 2022, entitled "Quality-of-Service Information for a Multi-Memory System" by Malik et al., which claims the benefit of U.S. Provisional Patent Application No. 63 / 184,404, filed May 5, 2021, entitled "Quality-of-Service Information for a Multi-Memory System," each of which is assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] This technical field relates to quality of service information for multi-memory systems. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, and chalcogenide memory technology. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. Volatile memory devices (such as DRAM) may lose their stored state when disconnected from external power. Summary of the Invention

[0006] An apparatus is described. The apparatus may include non-volatile memory; volatile memory configured to serve as a cache memory for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller may be operable to cause the apparatus to: receive a first command from a host device via a command bus during a set of clock cycles, the command bus including a command select pin configured for double data rate signaling; decode the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles; and determine quality of service (QoS) information for a second command, including a read command or a write command, based at least in part on the decoding of the first command and a plurality of bits included in the first command.

[0007] A device is described. The device may include non-volatile memory; volatile memory configured to serve as a cache memory for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller may be operable to cause the device to: receive a first command from a host device during a set of clock cycles and via a command bus, the command bus including a command select pin configured for double data rate signaling; decode the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles; determine QoS information for a read command received via the command bus after the first command based at least in part on the decoding of the first command and a plurality of bits included in the first command; and prioritize the transmission of data associated with the read command to the host device based at least in part on the QoS information of the read command.

[0008] A device is described. The device may include non-volatile memory; volatile memory configured to serve as a cache memory for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller may be operable to cause the device to: receive a first command from a host device during a set of clock cycles and via a command bus, the command bus including a command select pin configured for double data rate signaling; decode the first command at least in part based on the state of the command select pin during at least one clock cycle of the set of clock cycles; determine QoS information of a write command received via the command bus after the first command, at least in part based on the decoding of the first command and a plurality of bits included in the first command; and prioritize the transmission of the write command to the non-volatile memory or the volatile memory at least in part based on the QoS information of the write command. Attached Figure Description

[0009] Figure 1 An example of a system for supporting quality of service information, as disclosed herein, is shown.

[0010] Figure 2 An example of a memory die supporting quality of service information for multiple memory devices, as disclosed herein, is shown.

[0011] Figure 3 An example of a storage subsystem for supporting quality of service information, as disclosed herein, is shown.

[0012] Figure 4 An example of a process flow supporting quality of service information for multi-memory systems, as disclosed herein, is shown.

[0013] Figure 5 A block diagram of a memory device supporting quality of service information for a multi-memory system, based on examples disclosed herein, is shown.

[0014] Figures 6 to 8 A flowchart is shown illustrating one or more methods for supporting quality of service information for multi-memory systems, based on examples disclosed herein. Detailed Implementation

[0015] Devices such as electronic devices may include non-volatile memory (e.g., main memory for storing information in other operations) and volatile memory (e.g., secondary memory), which may serve as a cache for the non-volatile memory. Such a configuration allows the device to benefit from the advantages of non-volatile memory (e.g., non-volatile and persistent storage, high storage capacity, low power consumption) while maintaining compatibility with the host device through volatile memory, among other things. To support this type of configuration, the device may include an interface controller that interfaces the volatile and non-volatile memory with the host device. In some instances, the host device may prioritize communication with certain commands from the interface controller. However, command priority may be lost at the interface controller due to the lack of a priority indicator for the commands or performance aspects at the interface controller, potentially resulting in lower-priority commands being executed before higher-priority commands.

[0016] According to the techniques described herein, an interface controller can improve device performance by prioritizing commands based on or in response to Quality of Service (QoS) information received from a host device. This technique allows the interface controller to use interfaces (e.g., DRAM interfaces) compatible with protocols supported by the host device and volatile memory (e.g., Low Power Double Data Rate (LPDDR) protocols), among other advantages. By considering or executing actions based on QoS information, the interface controller may be able to correctly prioritize commands as expected by the host device, while also taking into account interface controller operation or other constraints or conditions that would otherwise affect or alter command priority.

[0017] The features of this disclosure were originally described in reference to Figure 1 and 2 Described in the context of the system and memory subsystem described. (See references...) Figure 3 The system described and as referenced Figure 4 The features of this disclosure are described in the context of the described process flow. These and other features of this disclosure are illustrated by reference to, for example, [reference needed]. Figures 5 to 8 The device diagrams and flowcharts described herein, which relate to quality of service information for multi-memory systems, are used to further illustrate and describe this.

[0018] Figure 1An example of a system 100 supporting quality of service information according to examples disclosed herein is shown. System 100 may be included in an electronic device such as a computer or telephone. System 100 may include a host device 105 and a memory subsystem 110. Host device 105 may be a processor or system-on-a-chip (SoC) that interfaces with interface controller 115, as well as other components of the electronic device including system 100. Memory subsystem 110 may store electronic information (e.g., digital information, data) for host device 105 and provide access to said electronic information. Memory subsystem 110 may include interface controller 115, volatile memory 120, and non-volatile memory 125. In some instances, interface controller 115, volatile memory 120, and non-volatile memory 125 may be included in the same physical package such as package 130. However, interface controller 115, volatile memory 120, and non-volatile memory 125 may be disposed on different corresponding dies (e.g., silicon dies).

[0019] The devices in system 100 can be coupled via various wires (e.g., traces, printed circuit board (PCB) wiring, redistribution layer (RDL) wiring) that enable the transmission of information (e.g., commands, addresses, data) between the devices. These wires can form channels, data buses, command buses, address buses, etc.

[0020] The memory subsystem 110 can be configured to provide the benefits of non-volatile memory 125 while maintaining compatibility with host device 105 that supports protocols for different types of memory, such as volatile memory 120 and other instances. For example, non-volatile memory 125 can provide benefits (e.g., relative to volatile memory 120) such as non-volatility, higher capacity, or lower power consumption. However, host device 105 may be incompatible with or inefficiently configured with various aspects of non-volatile memory 125. For example, host device 105 may support voltages, access latency, protocols, page sizes, etc., that are incompatible with non-volatile memory 125. To compensate for the incompatibility between host device 105 and non-volatile memory 125, memory subsystem 110 can be configured with volatile memory 120 that is compatible with host device 105 and serves as a cache for non-volatile memory 125. Therefore, host device 105 can use protocols supported by volatile memory 120 while also benefiting from the advantages of non-volatile memory 125.

[0021] In some instances, system 100 may be included in, or coupled to, a computing device, electronic device, mobile computing device, or wireless device. The device may be a portable electronic device. For example, the device may be a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, etc. In some instances, the device may be configured for bidirectional wireless communication via a base station or access point. In some instances, the device associated with system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication. In some instances, the device associated with system 100 may be referred to as user equipment (UE), station (STA), mobile terminal, etc.

[0022] Host device 105 can be configured to interface with memory subsystem 110 using a first protocol (e.g., Low Power Double Data Rate (LPDDR)) supported by interface controller 115. Therefore, in some instances, host device 105 can interface directly with interface controller 115 and indirectly with non-volatile memory 125 and volatile memory 120. In alternative instances, host device 105 can interface directly with non-volatile memory 125 and volatile memory 120. Host device 105 can also interface with other components of the electronic device including system 100. Host device 105 can be or includes a SoC, general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these types of components. In some instances, host device 105 can be referred to as a host.

[0023] Interface controller 115 can be configured to interface with volatile memory 120 and non-volatile memory 125 on behalf of host device 105 (e.g., based on or in response to one or more commands or requests issued by host device 105). For example, interface controller 115 can facilitate the retrieval and storage of data in volatile memory 120 and non-volatile memory 125 on behalf of host device 105. Therefore, interface controller 115 can facilitate data transfer between various sub-components, such as data transfer between host device 105, volatile memory 120, or at least some of non-volatile memory 125. Interface controller 115 can interface with host device 105 and volatile memory 120 using a first protocol, and can interface with non-volatile memory 125 using a second protocol supported by non-volatile memory 125.

[0024] Non-volatile memory 125 can be configured to store digital information (e.g., data) of electronic devices including system 100. Therefore, non-volatile memory 125 may include one or more arrays of memory cells and a local memory controller configured to operate the arrays of memory cells. In some instances, the memory cells may be or include FeRAM cells (e.g., non-volatile memory 125 may be FeRAM). Non-volatile memory 125 can be configured to interface with interface controller 115 using a second protocol, different from the first protocol used between interface controller 115 and host device 105. In some instances, non-volatile memory 125 may have a longer access operation latency than volatile memory 120. For example, retrieving data from non-volatile memory 125 may take longer than retrieving data from volatile memory 120. Similarly, writing data to non-volatile memory 125 may take longer than writing data to volatile memory 120. In some instances, as described herein, non-volatile memory 125 may have a smaller page size than volatile memory 120.

[0025] Volatile memory 120 can be configured to serve as a cache memory for one or more components, such as non-volatile memory 125. For example, volatile memory 120 can store information (e.g., data) of electronic devices including system 100. Therefore, volatile memory 120 can include one or more arrays of memory cells and a local memory controller configured to operate the arrays of memory cells. In some instances, the memory cells may be or include DRAM cells (e.g., the volatile memory may be DRAM). Non-volatile memory 125 can be configured to interface with interface controller 115 using a first protocol used between interface controller 115 and host device 105.

[0026] In some instances, volatile memory 120 may have shorter access operation latency than non-volatile memory 125. For example, retrieving data from volatile memory 120 may take less time than retrieving data from non-volatile memory 125. Similarly, writing data to volatile memory 120 may take less time than writing data to non-volatile memory 125. In some instances, volatile memory 120 may have a larger page size than non-volatile memory 125. For example, the page size of volatile memory 120 may be 2 kilobytes (2kB), and the page size of non-volatile memory 125 may be 64 bytes (64B) or 128 bytes (128B).

[0027] While non-volatile memory 125 may be a higher-density memory than volatile memory 120, accessing non-volatile memory 125 may take longer than accessing volatile memory 120 (e.g., due to different architectures and protocols, and other reasons). Therefore, using volatile memory 120 as a cache memory can reduce latency in system 100. As an example, by retrieving data from volatile memory 120 instead of from non-volatile memory 125, data access requests from host device 105 can be satisfied relatively quickly. To facilitate the operation of volatile memory 120 as a cache memory, interface controller 115 may include multiple buffers 135. Buffers 135 may be located on the same die as interface controller 115 and may be configured to temporarily store data for transfer between volatile memory 120, non-volatile memory 125, or host device 105 (or any combination thereof) during one or more access operations (e.g., store and retrieve operations).

[0028] An access operation may also be referred to as an access process or access procedure, and may involve one or more sub-operations performed by one or more components of the memory subsystem 110. Examples of access operations may include a storage operation in which data provided by the host device 105 is stored (e.g., written) to volatile memory 120 or non-volatile memory 125 (or both); and a retrieval operation in which data requested by the host device 105 is obtained (e.g., read) from volatile memory 120 or non-volatile memory 125 and returned to the host device 105.

[0029] To store data in memory subsystem 110, host device 105 can initiate a storage operation (or “stored procedure”) by sending a storage command (also referred to as a storage request, write command, or write request) to interface controller 115. The storage command may target a set of non-volatile memory cells in non-volatile memory 125. In some instances, the set of memory cells may also be referred to as a portion of memory. Host device 105 may also provide interface controller 115 with data to be written to the set of non-volatile memory cells. Interface controller 115 may temporarily store the data in buffer 135-a. After storing the data in buffer 135-a, interface controller 115 may transfer the data from buffer 135-a to volatile memory 120 or non-volatile memory 125, or both. In write-through mode, interface controller 115 may transfer data to both volatile memory 120 and non-volatile memory 125. In write-back mode, the interface controller 115 can simply transfer data to volatile memory 120 (wherein data is transferred to non-volatile memory 125 during a later eviction process).

[0030] In any mode, interface controller 115 may identify an appropriate set of one or more volatile memory cells in volatile memory 120 for storing data associated with a store command. To this end, interface controller 115 may implement set association mapping, wherein each set of one or more non-volatile memory cells in non-volatile memory 125 may be mapped to multiple sets (e.g., rows) of volatile memory cells in volatile memory 120. For example, interface controller 115 may implement an n-way association mapping, which allows data from a set of non-volatile memory cells to be stored in one of n sets of volatile memory cells in volatile memory 120. Therefore, interface controller 115 can manage volatile memory 120, which serves as a cache for non-volatile memory 125, by referring to n sets of volatile memory cells associated with a target set of non-volatile memory cells. As used herein, unless otherwise described or referenced, a “set” of objects may refer to one or more objects. Although described with reference to set association mapping, interface controller 115 can manage volatile memory 120 as cache memory by implementing one or more other types of mapping (e.g., direct mapping or association mapping, and other instances).

[0031] After determining which n sets of volatile memory cells are associated with the target set of non-volatile memory cells, the interface controller 115 can store the data in one or more of the n sets of volatile memory cells. This allows subsequent (e.g., follow-up) retrieval commands from the host device 105 to efficiently satisfy data by retrieving data from the volatile memory 120 with lower latency instead of the non-volatile memory 125 with higher latency. The interface controller 115 can determine which set of the n sets of volatile memory 120 stores the data based on or in response to one or more parameters (e.g., data validity, age, or modification status) associated with the data stored in the n sets of volatile memory 120. Therefore, the host device 105's storage commands can be fully (e.g., in write-back mode) or partially (e.g., in write-through mode) satisfied by storing the data in the volatile memory 120. In order to track data stored in volatile memory 120, interface controller 115 can store tag addresses for one or more sets of volatile memory cells (e.g., each set of volatile memory cells), the tag address indicating a non-volatile memory cell having data stored in a given set of volatile memory cells.

[0032] To retrieve data from memory subsystem 110, host device 105 can initiate a retrieval operation (also referred to as a retrieval process) by sending a retrieval command (also referred to as a retrieval request, read command, or read request) to interface controller 115. The retrieval command can target one or more sets of non-volatile memory cells in non-volatile memory 125. Once a retrieval command is received, interface controller 115 can examine the requested data in volatile memory 120. For example, interface controller 115 can examine the requested data in n sets of volatile memory cells associated with the target set of non-volatile memory cells. If the requested data is stored in one of the n sets of volatile memory cells (e.g., data from the target set of non-volatile memory cells is stored), interface controller 115 can transfer the data from volatile memory 120 to buffer 135-a (e.g., in response to determining whether the requested data is stored in one of the n sets of volatile memory cells, such as...). Figure 4 and 5 (as described in the text), so that it can be transmitted to the host device 105.

[0033] Generally, the term "hit" can be used to refer to a situation where volatile memory 120 stores the data targeted by host device 105. If the set of n one or more volatile memory cells does not store the requested data (e.g., the set of n volatile memory cells stores data from a set of non-volatile memory cells other than the target set of non-volatile memory cells), then interface controller 115 can transfer the requested data from non-volatile memory 125 to buffer 135-a (e.g., in response to determining whether the set of n volatile memory cells does not store the requested data, as referenced). Figure 4 and 5 (as described), so that it can be transmitted to host device 105. Generally, the term "miss" can be used to refer to a situation where the volatile memory 120 does not store the data targeted by host device 105.

[0034] In the event of a data miss, after transferring the requested data to buffer 135-a, interface controller 115 may transfer the requested data from buffer 135-a to volatile memory 120 so that subsequent read requests for the data can be satisfied via volatile memory 120 instead of non-volatile memory 125. For example, interface controller 115 may store the data in one of n sets of volatile memory cells associated with a target set of non-volatile memory cells. However, the n sets of volatile memory cells may already be storing data for other sets of non-volatile memory cells. Therefore, to preserve this other data, interface controller 115 may transfer the other data to buffer 135-b so that the data can be transferred to non-volatile memory 125 for storage. This process can be referred to as "eviction," and the data transferred from volatile memory 120 to buffer 135-b can be referred to as "victimized" data.

[0035] In some cases, interface controller 115 may transfer a subset of compromised data from buffer 135-b to non-volatile memory 125. For example, interface controller 115 may transfer one or more subsets of compromised data that have changed since the data was initially stored in non-volatile memory 125. Data that is inconsistent between volatile memory 120 and non-volatile memory 125 (e.g., due to an update in one memory but not the other) may be referred to as “modified” or “dirty” data in some cases. In some instances (e.g., if the interface controller is operating in a mode such as write-back mode), dirty data may be data that exists in volatile memory 120 but not in non-volatile memory 125.

[0036] Therefore, if volatile memory 120 is full, interface controller 115 can execute an eviction procedure to save data from volatile memory 120 to non-volatile memory 125 (e.g., to make room for new data in volatile memory 120). In some instances, interface controller 115 can execute a "filling" procedure, in which data from non-volatile memory 125 is saved to volatile memory 120. Interface controller 115 can execute a filling procedure in the event of a miss (e.g., to fill volatile memory 120 with relevant data). For example, in the event of a read miss if a read command from host device 105 targets data stored in non-volatile memory 125 instead of volatile memory 120, interface controller 115 can retrieve the data requested by the read command (from non-volatile memory 125) and, in addition to returning the data to the host device, also store the data in volatile memory 120 (e.g., so that the data can be quickly retrieved in the future).

[0037] Therefore, depending on whether the request is hit or miss, the memory subsystem 110 can use volatile memory 120 or non-volatile memory 125 to satisfy (or "fulfill") requests from the host device 105 (e.g., read commands, write commands). For example, in the case of a read miss, a read command from the host device 105 can be satisfied via non-volatile memory 125, meaning that the data returned from the host device 105 can originate from non-volatile memory 125. And in the case of a read hit, a read command from the host device 105 can be satisfied via volatile memory 120, meaning that the data returned from the host device 105 can originate from volatile memory 120. In some instances, the hit-to-miss ratio ("hit-to-miss ratio") may be relatively high (e.g., the hit percentage (or "hit rate") may be about 85%, while the miss percentage (or "miss rate") may be about 15%).

[0038] In some instances, the interface controller 115 may include an interface (e.g., a DRAM interface) compatible with protocols supported by the host device 105 and the volatile memory 120 (e.g., the LPDDR protocol). However, in some instances, the interface may not include any pins for or dedicated to signaling for QoS information. According to the techniques described herein, the host device 105 may indicate QoS information for functional commands (e.g., read commands, write commands) to the interface controller. For example, the host device 105 may indicate QoS information for functional commands by including (e.g., embedding) QoS information in other commands for the memory subsystem 110. QoS information may also be referred to as priority information, service information, or other suitable terms, and may indicate the priority level, service expectation, or latency tolerance of the corresponding functional command, and other instances.

[0039] System 100 may include any number of non-transitory computer-readable media that support the quality of service information as described herein. For example, host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 may include or otherwise access one or more non-transitory computer-readable media (e.g., firmware) for performing the functions attributed herein to host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125. For example, such instructions, if executed by host device 105 (e.g., by a host device controller), by interface controller 115, by volatile memory 120 (e.g., by a local controller), or by non-volatile memory 125 (e.g., by a local controller), may cause host device 105, interface controller 115, volatile memory 120, or non-volatile memory 125 to perform the relevant functions as described herein.

[0040] Figure 2 An example of a storage subsystem 200 supporting quality of service information, as disclosed herein, is shown. Storage subsystem 200 may be used as a reference. Figure 1 An example of the described memory subsystem 110. Therefore, the memory subsystem 200 can be compared with, as in the reference... Figure 1 The host device interaction is described. The memory subsystem 200 may include an interface controller 202, volatile memory 204, and non-volatile memory 206, which may be as described in reference... Figure 1 The described interface controller 115, volatile memory 120, and non-volatile memory 125 are examples. Therefore, the interface controller 202 can represent, as referenced... Figure 1 The described host device interfaces with volatile memory 204 and non-volatile memory 206. For example, interface controller 202 can use volatile memory 204 as a cache for non-volatile memory 206. Using volatile memory 204 as a cache allows the subsystem to provide the benefits of non-volatile memory 206 (e.g., non-volatile, high-density storage) while maintaining compatibility with host devices that support protocols different from those of non-volatile memory 206.

[0041] exist Figure 2 In this diagram, dashed lines between components represent data flows or data transmission paths, while solid lines between components represent command flows or command transmission paths. In some cases, the memory subsystem 200 is one of several similar or identical subsystems that can be included in an electronic device. In some instances, each subsystem may be referred to as a slice and may be associated with a corresponding channel of the host device.

[0042] Non-volatile memory 206 can be configured to be used as main memory for a host device (e.g., memory for long-term data storage). In some cases, non-volatile memory 206 may include one or more arrays of FeRAM cells. Each FeRAM cell may include a select component and a ferroelectric capacitor and can be accessed by applying appropriate voltage to one or more access lines, such as word lines, board lines, and digital lines. In some instances, a subset of FeRAM cells coupled to an active word line may be sensed, for example, in parallel or simultaneously, without having to sense all FeRAM cells coupled to an active word line. Therefore, the page size of the FeRAM array may be different from (e.g., smaller than) the DRAM page size. In the context of a memory device, a page may refer to memory cells in a row (e.g., a group of memory cells with a common row address), and the page size may refer to the number of memory cells or column addresses in a row, or the number of column addresses accessed during an access operation. Alternatively, the page size may refer to the size of data disposed of by various interfaces, or the amount of data that a row can store. In some cases, different memory device types may have different page sizes. For example, a DRAM page size (e.g., 2kB) can be a superset of a non-volatile memory (e.g., FeRAM) page size (e.g., 64B).

[0043] The smaller page size of FeRAM arrays can offer various efficiency benefits because a single FeRAM cell may require more power to read or write than a single DRAM cell. For example, the smaller page size of a FeRAM array can facilitate efficient energy use because fewer FeRAM cells can be activated if the relevant changes in information are small. In some instances, depending on the nature of the data and commands utilizing FeRAM operations, the page size of the FeRAM cell array can, for example, change dynamically (e.g., during the operation of the FeRAM cell array).

[0044] While a single FeRAM cell may require more power to read or write than a single DRAM cell, FeRAM cells can maintain their stored logic state for extended periods without an external power supply because the ferroelectric material within the FeRAM cell can remain non-zero polarized in the absence of an electric field. Therefore, including an FeRAM array in the non-volatile memory 206 can provide power and efficiency benefits relative to volatile memory cells (e.g., DRAM cells in the volatile memory 204) because it reduces or eliminates constraints on performing refresh operations.

[0045] Volatile memory 204 can be configured to serve as a cache memory for non-volatile memory 206. In some cases, volatile memory 204 may include one or more arrays of DRAM cells. Each DRAM cell may include a capacitor comprising a dielectric material to store charge representing a programmable state. The memory cells of volatile memory 204 may be logically grouped or arranged into one or more memory banks (as referred to herein as “banks”). For example, volatile memory 204 may include sixteen banks. The memory cells of a bank may be arranged in a grid or an array of intersecting columns and rows, and each memory cell may be accessed or refreshed by applying appropriate voltages to the digital lines (e.g., column lines) and word lines (e.g., row lines) for the memory cell. A row of a bank may be referred to as a page, and the page size may be referred to as the number of columns or memory cells in the row (and therefore, the amount of data that the row can store). As mentioned, the page size of volatile memory 204 may be different from (e.g., larger than) the page size of non-volatile memory 206.

[0046] Interface controller 202 may include various circuitry for interfacing (e.g., communicating) with other devices, such as host devices, volatile memory 204, and non-volatile memory 206. For example, interface controller 202 may include a data (DA) bus interface 208, a command and address (C / A) bus interface 210, a data bus interface 212, a C / A bus interface 214, a data bus interface 216, and a C / A bus interface 264. The data bus interfaces may support communication of information using one or more communication protocols. For example, data bus interface 208, C / A bus interface 210, data bus interface 216, and C / A bus interface 264 may support information transmitted using a first protocol (e.g., LPDDR signaling), while data bus interface 212 and C / A bus interface 214 may support information transmitted using a second protocol. Therefore, the various bus interfaces coupled to interface controller 202 may support different data volumes or data rates.

[0047] Data bus interface 208 can be coupled to data bus 260, transaction bus 222, and buffer circuitry 224. Data bus interface 208 can be configured to send and receive data via data bus 260 and to send and receive control information (e.g., acknowledgment / negative acknowledgment) or metadata via transaction bus 222. Data bus interface 208 can also be configured to transfer data between data bus 260 and buffer circuitry 224. Data bus 260 and transaction bus 222 can be coupled to interface controller 202 and host device, establishing a conductive path between interface controller 202 and host device. In some instances, the pin of transaction bus 222 may be referred to as a Data Mask Inversion (DMI) pin. Although shown as having one data bus 260 and one transaction bus 222, any number of data buses 260 and any number of transaction buses 222 may be coupled to one or more data bus interfaces 208.

[0048] C / A bus interface 210 can be coupled to C / A bus 226 and decoder 228. C / A bus interface 210 can be configured to send and receive commands and addresses via C / A bus 226. Commands and addresses received via C / A bus 226 can be associated with data received or sent via data bus 260. C / A bus interface 210 can also be configured to send commands and addresses to decoder 228, enabling decoder 228 to decode commands and relay the decoded commands and associated addresses to command circuitry system 230.

[0049] Data bus interface 212 can be coupled to data bus 232 and memory interface circuitry 234. Data bus interface 212 can be configured to send and receive data via data bus 232, which can be coupled to non-volatile memory 206. Data bus interface 212 can also be configured to transfer data between data bus 232 and memory interface circuitry 234. C / A bus interface 214 can be coupled to C / A bus 236 and memory interface circuitry 234. C / A bus interface 214 can be configured to receive commands and addresses from memory interface circuitry 234 and relay commands and addresses to non-volatile memory 206 via C / A bus 236 (e.g., to a local controller of non-volatile memory 206). Commands and addresses sent via C / A bus 236 can be associated with data received or sent via data bus 232. The data bus 232 and the C / A bus 236 can be coupled to the interface controller 202 and the non-volatile memory 206, thereby establishing a conductive path between the interface controller 202 and the non-volatile memory 206.

[0050] Data bus interface 216 can be coupled to data bus 238 (e.g., data bus 238-a, data bus 238-b) and memory interface circuitry 240. Data bus interface 216 can be configured to send and receive data via data bus 238, which can be coupled to volatile memory 204. Data bus interface 216 can also be configured to transfer data between data bus 238 and memory interface circuitry 240. C / A bus interface 264 can be coupled to C / A bus 242 and memory interface circuitry 240. C / A bus interface 264 can be configured to receive commands and addresses from memory interface circuitry 240 and relay commands and addresses to volatile memory 204 (e.g., to a local controller of volatile memory 204) via C / A bus 242. Commands and addresses sent via C / A bus 242 can be associated with data received or sent via data bus 238. The data bus 238 and the C / A bus 242 can be coupled to the interface controller 202 and the volatile memory 204, thereby establishing a conductive path between the interface controller 202 and the volatile memory 204.

[0051] In addition to the bus and bus interface for communicating with the coupled device, the interface controller 202 may also include circuitry for using non-volatile memory 206 as main memory and volatile memory 204 as cache memory. For example, the interface controller 202 may include command circuitry 230, buffer circuitry 224, cache memory management circuitry 244, one or more engines 246, and one or more schedulers 248.

[0052] Command circuitry system 230 may be coupled to buffer circuitry system 224, decoder 228, cache memory management circuitry system 244, scheduler 248, and other components. Command circuitry system 230 may be configured to receive command and address information from decoder 228 and store the command and address information in queue 250. Command circuitry system 230 may include logic 262 that processes command information (e.g., from the host device) and stored information from other components (e.g., cache memory management circuitry system 244, buffer circuitry system 224), and uses this information to generate one or more commands for scheduler 248. Command circuitry system 230 may also be configured to transmit address information (e.g., address bits) to cache memory management circuitry system 244. In some instances, logic 262 may be circuitry configured to function as a finite state machine (FSM).

[0053] Buffer circuitry system 224 may be coupled to data bus interface 208, command circuitry system 230, memory interface circuitry system 234, and memory interface circuitry system 240. Buffer circuitry system 224 may include a collection of one or more buffer circuits for at least some (if not every) banks of volatile memory 204. Buffer circuitry system 224 may also include components for accessing the buffer circuits (e.g., a memory controller). In one example, volatile memory 204 may include sixteen banks and buffer circuitry system 224 may include sixteen sets of buffer circuits. Each set of buffer circuits may be configured to store data from or for (or both) a corresponding bank of volatile memory 204. As an example, the set of buffer circuits for bank 0 (BK0) may be configured to store data from or for (or both) a first bank of volatile memory 204, and the set of buffer circuits for bank 15 (BK15) may be configured to store data from or for (or both) a sixteenth bank of volatile memory 204.

[0054] Each set of buffer circuits in buffer circuit system 224 may include a pair of buffers. The pair of buffers may include: one buffer (e.g., an Open Page Data (OPD) buffer) configured to store data targeted by an access command (e.g., a write command or read command) from a host device; and another buffer (e.g., a Victim Page Data (VPD) buffer) configured to store data for use in an eviction process triggered by an access command. For example, the set of buffer circuits for BK0 may include buffers 218 and 220, which may be instances of buffers 135-a and 135-b, respectively. Buffer 218 may be configured to store BK0 data targeted by an access command from a host device. And buffer 220 may be configured to store data transferred from BK0 as part of an eviction process triggered by an access command. Each buffer in the set of buffer circuits may be configured to have a size (e.g., storage capacity) corresponding to the page size of volatile memory 204. For example, if the page size of volatile memory 204 is 2kB, then the size of each buffer may be 2kB. Therefore, in some instances, the size of the buffer can be equivalent to the page size of the volatile memory 204.

[0055] The cache memory management circuitry system 244 may be coupled to the command circuitry system 230, the engine 246, and the scheduler 248, as well as other components. The cache memory management circuitry system 244 may include a set of cache memory management circuits for one or more banks of volatile memory (e.g., each bank of memory). As an example, the cache memory management circuitry system 244 may include sixteen sets of cache memory management circuits for BK0 through BK15. Each set of cache memory management circuits may include two memory arrays that can be configured to store storage information of volatile memory 204. As an example, the set of cache memory management circuits for BK0 may include memory array 252 (e.g., a cache memory DRAM (CDRAM) tag array (CDT-TA)) and memory array 254 (e.g., a CDRAM active (CDT-V) array) that can be configured to store storage information of BK0. In some instances, the memory array may also be referred to as an array or a buffer. In some cases, the memory array may be or include volatile memory cells, such as static RAM (SRAM) cells.

[0056] Storage information (or “metadata”) may include content information, validity information, and / or dirty information (or any combination thereof) associated with volatile memory 204, and other instances. Content information (which may also be referred to as tag information or address information) indicates which data is stored in a set of volatile memory cells. For example, the content information (e.g., tag address) of a row in volatile memory 204 may indicate which set of one or more non-volatile memory cells currently contains data stored in that row. As mentioned, validity information may indicate whether the data stored in the set of volatile memory cells is actual data (e.g., data with an expected order or form) or placeholder data (e.g., random or dummy data without an expected or important order). Dirty information may indicate whether the data stored in the set of one or more volatile memory cells of volatile memory 204 differs from the corresponding data stored in the set of one or more non-volatile memory cells of non-volatile memory 206. For example, dirty information may indicate whether the data stored in the set of volatile memory cells has been updated relative to the data stored in non-volatile memory 206.

[0057] Memory array 252 may include memory cells storing storage information (e.g., tag information, validity information, dirty information) of associated memory banks (e.g., BK0) of volatile memory 204. The storage information may be stored on a row-by-row basis (e.g., there may be corresponding storage information for each row of an associated non-volatile memory bank). Interface controller 202 can examine requested data in volatile memory 204 by referring to the storage information in memory array 252. For example, interface controller 202 may receive a retrieval command from a host device for data in a set of non-volatile memory cells in non-volatile memory 206. Interface controller 202 may refer to the storage information in memory array 252 using a set of one or more address bits (e.g., a set of row address bits) targeted by the access request. For example, using set association mapping, interface controller 202 may refer to content information in memory array 252 to determine which set of volatile memory cells (if any) stores the requested data.

[0058] In addition to storing content information for the volatile memory cells, memory array 252 may also store validity information indicating whether data in the set of volatile memory cells is actual data (also called valid data) or random data (also called invalid data). For example, volatile memory cells in volatile memory 204 may initially store random data and continue to do so until data is written to the volatile memory cells from a host device or non-volatile memory 206. To track which data is valid, memory array 252 may be configured to set a bit for each set of volatile memory cells (e.g., a row) if actual data is stored there. This bit may be called a validity bit or validity flag. Like content information, validity information stored in memory array 252 may be stored on a row-by-row basis. Thus, in some instances, each validity bit may indicate the validity of data stored in the associated row.

[0059] In some instances, memory array 252 may store dirty information indicating whether a set of volatile memory cells (e.g., rows) stores any dirty data. Similar to validity information, the dirty information stored in memory array 252 may be stored on a row-by-row basis.

[0060] Memory array 254 may be similar to memory array 252 and may also include memory cells that store storage information of the banks (e.g., BK0) of volatile memory 204 associated with memory array 252. For example, memory array 254 may store validity information and dirt information of the banks of volatile memory 204. However, the storage information stored in memory array 254 may be stored on a sub-block basis rather than on a row basis. For example, validity information stored in the memory cells of memory array 254 may indicate the validity of data for a subset of volatile memory cells in a row of volatile memory 204.

[0061] As an example, validity information in memory array 254 can indicate the validity of each subset (e.g., 32B or 64B) of data stored in row BK0 of volatile memory 204. Similarly, dirty information stored in memory cells of memory array 254 can indicate which subsets of volatile memory cells in rows of volatile memory 204 store dirty data. For example, dirty information in memory array 254 can indicate the dirty state of each subset (e.g., 32B or 64B) of data stored in row BK0 of volatile memory 204. Storing storage information (e.g., tag information, validity information) on a row-by-row basis in memory array 252 allows interface controller 202 to determine whether data in volatile memory 204 has a hit or a miss. Storing storage information (e.g., validity information, dirty information) on a sub-block basis in memory array 254 allows interface controller 202 to determine which one or more data subsets to return to the host device (e.g., during a retrieval process) and which one or more data subsets to retain in non-volatile memory 206 (e.g., during an eviction process).

[0062] Each cache management circuitry may also include a corresponding pair of registers coupled to command circuitry 230, engine 246, memory interface circuitry 234, memory interface circuitry 240, and the memory array for the cache management circuitry, as well as other components. For example, the cache management circuitry may include a first register (e.g., register 256, which may be an Open Page Tag (OPT) register) configured to receive storage information (e.g., tag information, validity information, dirty information, other information, or any combination of bits) from memory array 252 or scheduler 248-b, or both. The cache management circuitry may also include a second register (e.g., register 258, which may be a Victim Page Tag (VPT) register) configured to receive storage information (e.g., validity information and / or dirty information, or both) from memory array 254 and scheduler 248-a, or both. Information in registers 256 and 258 may be transmitted to command circuitry 230 and engine 246 to enable decisions to be made by these components. For example, the command circuitry 230 may issue a command to read the non-volatile memory 206 or the volatile memory 204 based on or in response to stored information in register 256 or register 258 or both.

[0063] Engine 246-a can be coupled to registers 256 and 258 and scheduler 248. Engine 246-a can be configured to receive storage information from the various components and issue commands to scheduler 248 based on the storage information. For example, if interface controller 202 is in a first mode such as write-through mode, engine 246-a can issue a command to scheduler 248-b, and in response, scheduler 248-b initiates or facilitates the transfer of data from buffer 218 to volatile memory 204 and non-volatile memory 206. Alternatively, if interface controller 202 is in a second mode such as write-back mode, engine 246-a can issue a command to scheduler 248-b, and in response, scheduler 248-b can initiate or facilitate the transfer of data from buffer 218 to volatile memory 204. In the case of a write-back operation, the data stored in volatile memory 204 can eventually be transferred to non-volatile memory 206 during a subsequent (e.g., subsequent) eviction process.

[0064] Engine 246-b may be coupled to register 258 and scheduler 248-a. Engine 246-b may be configured to receive stored information from register 258 and issue commands to scheduler 248-a based on the stored information. For example, engine 246-b may issue a command to scheduler 248-a to initiate or facilitate dirty data transfer from buffer 220 to non-volatile memory 206 (e.g., as part of an eviction process). If buffer 220 holds a set of data transferred from volatile memory 204 (e.g., victim data), engine 246-b may indicate which subsets (e.g., which 64B) of the set of data in buffer 220 should be transferred to non-volatile memory 206.

[0065] Scheduler 248-a can be coupled to various components of interface controller 202 and can facilitate access to non-volatile memory 206 by issuing commands to memory interface circuitry 234. Commands issued by scheduler 248-a can be based on or in response to commands from command circuitry 230, engine 246-a, engine 246-b, or a combination of these components. Similarly, scheduler 248-b can be coupled to various components of interface controller 202 and can facilitate access to volatile memory 204 by issuing commands to memory interface circuitry 240. Commands issued by scheduler 248-b can be based on or in response to commands from command circuitry 230 or engine 246-a, or both.

[0066] The memory interface circuitry 234 can communicate with the non-volatile memory 206 via one or more of the data bus interface 212 and the C / A bus interface 214. For example, the memory interface circuitry 234 can prompt the C / A bus interface 214 to relay commands issued by the memory interface circuitry 234 via the C / A bus 236 to the local controller in the non-volatile memory 206. Furthermore, the memory interface circuitry 234 can send data to or receive data from the non-volatile memory 206 via the data bus 232. In some instances, commands issued by the memory interface circuitry 234 may be supported by the non-volatile memory 206 but not by the volatile memory 204 (e.g., commands issued by the memory interface circuitry 234 may differ from commands issued by the memory interface circuitry 240).

[0067] The memory interface circuitry 240 can communicate with the volatile memory 204 via one or more of the data bus interface 216 and the C / A bus interface 264. For example, the memory interface circuitry 240 can prompt the C / A bus interface 264 to relay commands issued by the memory interface circuitry 240 via the C / A bus 242 to the local controller of the volatile memory 204. Furthermore, the memory interface circuitry 240 can send data to or receive data from the volatile memory 204 via one or more data buses 238. In some instances, commands issued by the memory interface circuitry 240 may be supported by the volatile memory 204 but not by the non-volatile memory 206 (e.g., commands issued by the memory interface circuitry 240 may differ from commands issued by the memory interface circuitry 234).

[0068] In summary, the components of interface controller 202 can use non-volatile memory 206 as main memory and volatile memory 204 as cache memory. This operation can be prompted by one or more access commands (e.g., read / retrieve command / request and write / store command / request) received from the host device.

[0069] In some instances, interface controller 202 may receive a storage command from the host device. The storage command may be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. The storage command may include or be accompanied by address bits targeting the memory address of non-volatile memory 206. Data to be stored may be received via data bus 260 and transmitted to buffer 218 via data bus interface 208. In write-through mode, interface controller 202 may transmit data to both non-volatile memory 206 and volatile memory 204. In write-back mode, in some instances, interface controller 202 may transmit data only to volatile memory 204.

[0070] In either mode, the interface controller 202 may first check whether the volatile memory 204 has space available for storing data in its memory cells. To this end, the command circuitry 230 may refer to the memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n volatile memory cell sets (e.g., rows) associated with a memory address are empty (e.g., storing random or invalid data) or whether one or more of the n volatile memory cell sets (e.g., rows) associated with a memory address are full (e.g., storing valid data). For example, the command circuitry 230 may determine whether one or more of the n volatile memory cell sets (e.g., rows) are available (or unavailable) based on tag information and validity information stored in the memory array 252. In some cases, the set of volatile memory cells in the volatile memory 204 may be referred to as a line, a cache line, or a row.

[0071] If one of the n associated volatile memory cell sets is available for storing information, the interface controller 202 can transfer data from buffer 218 to volatile memory 204 for storage in said volatile memory cell set. However, if no associated volatile memory cell set is empty, the interface controller 202 can initiate an eviction process to free up space in volatile memory 204 for data. The eviction process may include transferring compromised data from one of the n associated volatile memory cell sets to buffer 220. Dirty information of the compromised data can be transferred from memory array 254 to register 258 to identify a dirty subset of the compromised data. After the compromised data is stored in buffer 220, new data can be transferred from buffer 218 to volatile memory 204, and compromised data can be transferred from buffer 220 to non-volatile memory 206. In some cases, a dirty subset of old data can be transferred to non-volatile memory 206, and a clean subset (e.g., an unmodified subset) can be discarded. A dirty subset can be identified by engine 246-b based on or in response to dirty information transferred from memory array 254 to register 258 during the eviction process.

[0072] In another example, interface controller 202 may receive commands, such as retrieval commands, from a host device. Retrieval commands can be received via C / A bus 226 and transmitted to command circuitry 230 via one or more of C / A bus interface 210 and decoder 228. Retrieval commands may include address bits targeting a memory address of non-volatile memory 206. Before attempting to access the target memory address of non-volatile memory 206, interface controller 202 may check to see if volatile memory 204 stores data. To this end, command circuitry 230 may refer to memory array 252 (e.g., using a set of memory address bits) to determine whether one or more of the n volatile memory cell sets (e.g., rows) associated with the memory address store the requested data (e.g., whether one or more of the n volatile memory cell sets associated with the memory address store the requested data or alternatively, not store the requested data). If the requested data is stored in volatile memory 204, the interface controller 202 can transfer the requested data to buffer 218 for transmission to the host device via data bus 260.

[0073] If the requested data is not stored in volatile memory 204 (e.g., the requested data may be stored in non-volatile memory 206 or other locations), interface controller 202 can retrieve the data from non-volatile memory 206 and transfer the data to buffer 218 for transmission to the host device via data bus 260. Alternatively, interface controller 202 can transfer the requested data from buffer 218 to volatile memory 204, allowing access to the data with lower latency during subsequent retrieval operations. However, before transferring the requested data, interface controller 202 can first determine whether one or more of the n associated volatile memory cell sets are available to store the requested data (e.g., whether one or more of the n associated volatile memory cell sets are empty or full). Interface controller 202 can determine the availability of the n associated volatile memory cell sets by communicating with the associated cache memory management circuitry. If the associated volatile memory cell sets are available, interface controller 202 can transfer the data from buffer 218 to volatile memory 204 without performing an eviction process. Otherwise, the interface controller 202 may transfer data from the buffer 218 to the volatile memory 204 after the eviction process.

[0074] The memory subsystem 200 can be implemented in one or more configurations, including packaged, single-chip, and multi-chip versions. A multi-chip version may include one or more components of the memory subsystem 200, including interface controller 202, volatile memory 204, and non-volatile memory 206 (and other components or combinations thereof), on a separate chip from the chip that includes one or more other components of the memory subsystem 200. For example, in a multi-chip version, the corresponding individual chip may include each of interface controller 202, volatile memory 204, and non-volatile memory 206. Conversely, a single-chip version may include interface controller 202, volatile memory 204, and non-volatile memory 206 on a single chip.

[0075] In some instances, the C / A bus interface 210 can be configured to be compatible with protocols supported by the host device 105 and the volatile memory 120. However, the C / A bus interface 210 may not include any pins for signaling (e.g., dedicated to) QoS information. According to the techniques described herein, the host device 105 can indicate the QoS information of functional commands (e.g., read commands, write commands) by including (e.g., embedding) QoS information in other commands of the memory subsystem 110. For this purpose, in some instances, the host device can use a command select (CS) pin to indicate whether a command carries QoS information for a functional command (e.g., a subsequent functional command) (as opposed to other control information). Therefore, in some instances, the C / A bus interface 210 can be used to signal QoS information without modifying the pin configuration of the C / A bus interface 210, a modification that could otherwise compromise or break compatibility with protocols supported by the host device and the volatile memory 120.

[0076] Figure 3 An example of a system 300 supporting quality of service information, as disclosed herein, is shown. System 300 may include a host device 305 and a memory subsystem 310, and may be as described in reference [reference needed]. Figure 1 An example of system 100 is described. The memory subsystem 310 may include an interface controller 315, volatile memory 320, and non-volatile memory 325, which may be coupled to each other via one or more transmission lines, buses, or both. As described herein, in some instances, the interface controller 315 may receive QoS information from the host device 305 and may use this QoS information to prioritize the issuance and execution of commands and the return of requested data.

[0077] Interface controller 315 can receive commands and control information (e.g., address, QoS information) from host device 305 via C / A bus 330, which may be an instance of C / A bus 226. As described in more detail below, interface controller 315 can receive commands as a series or sequence of voltages on C / A pin 335, which may be included in C / A bus interface 340. C / A bus interface 340 may be an instance of C / A bus interface 210 and may be configured to support protocols (e.g., DDR protocol) used by host device 305 and volatile memory 320. C / A bus interface 340 can transmit commands received from host device 305 to command decoder 345, enabling the decoding of the commands.

[0078] Command decoder 345 can distinguish various commands from host device 305 based on the state of the C / A pin during each command period. For example, host device 305 can transmit commands to interface controller 315 by generating a series of voltages on C / A pin 335 within a set of clock cycles of clock signal 350. Clock signal 350 can be received from host device 305 or generated internally by interface controller 315. Clock cycle may also be referred to as clock pulse or other suitable terms.

[0079] For example, if system 300 is implementing a DDR protocol, in some instances, command decoder 345 can decode commands by capturing the state of C / A pin 335 at the rising and falling edges of clock signal 350. For instance, command decoder 345 can capture the state of C / A pin 335 during the rising edge of clock signal 350 (which may be referred to as the rising edge state) and determine the type of command based on (e.g., using) that rising edge state. Furthermore, command decoder 345 can capture the state of C / A pin 335 during the falling edge of clock signal 350 (which may be referred to as the falling edge state) and determine additional control information based on (e.g., using) that falling edge state. In some other instances, in contrast to double data rate protocols, single data rate protocols can capture the state of C / A pin 335 during a single edge of a clock cycle (e.g., a rising edge or a falling edge, but not both).

[0080] As a non-limiting example, C / A pin 335 may include C / A pins 0 (denoted as CA0) to C / A pins 6 (denoted as CA6) and command selection pin 0 (denoted as CS[0]). However, to maintain compatibility with protocols supported by host device 305, C / A pin 335 may not include one or more pins dedicated to QoS information. According to the techniques described herein, host device 305 can provide QoS information for a function command by including (e.g., embedding) QoS information in a command (which may be referred to as a metadata command) preceding the function command (or following it in some alternative instances). The metadata command may be a command that includes control information for another command, and the function command may be a command for memory operations.

[0081] Metadata commands can be distinguished from other commands using pins, such as the CS[0] pin, which can be configured for double data rate communication (as opposed to single data rate communication). For example, host device 305 can use the XCAS command to transmit QoS information for subsequent function commands, and the edge state indicating the XCAS command can be similar to the edge state indicating the Command Access Strobe (CAS) command, except that the edge state (e.g., falling edge state) of the CS[0] pin may differ for the XCAS command relative to the CAS command. For example, the rising edge state indicating the CAS command (including the rising edge state of the CS[0] pin) may be the same for the XCAS command, but the falling edge state of the CS[0] pin may be high for the CAS command and low for the XCAS command (or vice versa). As another example, host device 305 can use the XREAD command to transmit QoS information for subsequent function commands, and the edge state indicating the XREAD command can be similar to the edge state indicating the read command, except that the edge state (e.g., falling edge state) of the CS[0] pin may differ for the XREAD command relative to the read command. For example, the rising edge state of the read command (including the rising edge state of the CS[0] pin) may be the same for the XREAD command, but the falling edge state of the CS[0] pin may be high for the read command and low for the XREAD command (or vice versa).

[0082] The XCAS command can transmit QoS information as a set of bits via a subset of C / A pins 335 (e.g., CA0 to CA3), and in some instances, identification information (e.g., a read identifier (RID)) can be transmitted as a set of bits via different subsets of C / A pins 335 (e.g., CA4 to CA6). For example, QoS information can be indicated by bits corresponding to the falling edge states of CA0 to CA3, and the RID can be indicated by bits corresponding to the falling edge states of CA4 to CA6. The RID allows the interface controller 315 to recognize read commands associated with QoS information, which in turn allows the interface controller 315 to perform out-of-order read operations. Similarly, the XREAD command can transmit QoS information as a set of bits via a subset of C / A pins 335 (e.g., CA0 to CA3), and in some instances, other control information can be transmitted via different subsets of C / A pins 335.

[0083] In some instances, the QoS information indicated by the metadata command may be a QoS category used for the corresponding functional command. The QoS category may be an instance of an Advanced Extensible Interface (AXI) QoS category, and thus may represent very high priority QoS (e.g., HH QoS), high priority QoS (e.g., H QoS), medium priority QoS (e.g., M QoS), or low priority QoS (e.g., L QoS), and other instances. Other instances of QoS categories are expected and are within the scope of this disclosure. In some instances, the QoS category may be referred to as a QoS classification, QoS category, QoS level, or other suitable terminology.

[0084] When decoding a command from host device 305, command decoder 345 may transmit (e.g., send) the decoded command to Transaction Command Queuing (TCQ) component 355. TCQ component 355 may be configured to temporarily buffer commands from host device 305 and distribute the commands to other components of memory subsystem 310, such as NVM scheduler 360-a and VM scheduler 360-b. Therefore, TCQ component 355 may include array 365 (which may also be referred to as a buffer, queue, or storage structure) and logic 370. Array 365 may store commands received from command decoder 345, along with corresponding control information such as address information (e.g., bank information, row information, column information) and QoS information. Logic 370 may be configured to determine command hits and misses, and other information, such that TCQ component 355 may transmit commands and other control information from array 365 to the appropriate scheduler 360.

[0085] If a command for non-volatile memory 325 is buffered at array 365, TCQ component 355 can transmit the command and QoS information for that command to NVM scheduler 360-a. NVM scheduler 360-a can then use the QoS information to prioritize the transmission of the command to non-volatile memory 325 over other commands. For example, NVM scheduler 360-a can prioritize command transmission based on (e.g., according to) or in response to the QoS information of the command and the QoS information of other commands queued at NVM scheduler 360-a. Prioritizing command transmission can include transmitting the command to non-volatile memory 325 before other commands (e.g., commands previously received from host device 305, commands that have been queued long ago at NVM scheduler 360-a or interface controller 315). Therefore, command prioritization can allow commands to be executed and serviced faster than they would otherwise occur.

[0086] In some instances, the NVM scheduler 360-a may use additional information to prioritize command delivery, such as the command's age, which may refer to the amount of time the command has been queued at the NVM scheduler 360-a (or typically at the interface controller 315). In some instances, the TCQ component 355 may deliver commands to the NVM scheduler 360-a independently of or without considering QoS information. That is, QoS information may be the basis for prioritizing command delivery from the NVM scheduler 360-a to the non-volatile memory 325, but it is not necessarily the basis for prioritizing command delivery from the TCQ component to the NVM scheduler 360-a.

[0087] If a command for volatile memory 320 is buffered at array 365, TCQ component 355 can transmit the command and QoS information for that command to VM scheduler 360-b. VM scheduler 360-b can then use the QoS information to prioritize the transmission of the command to volatile memory 320 over other commands. For example, VM scheduler 360-b may prioritize the transmission of the command based on (e.g., according to) or in response to the QoS information of the command and the QoS information of other commands queued at VM scheduler 360-b. Prioritizing the transmission of commands may include transmitting the command to volatile memory 320 before other commands (e.g., commands previously received from host device 305, commands that have been queued long ago at VM scheduler 360-b or interface controller 315). Therefore, command prioritization can allow commands to be executed and serviced faster than would otherwise occur.

[0088] In some instances, the VM scheduler 360-b may use additional information to prioritize command delivery, such as the command's age, which may refer to the amount of time the command has been queued at the VM scheduler 360-b (or typically at the interface controller 315). In some instances, the TCQ component 355 may deliver commands to the VM scheduler 360-b independently of or without considering QoS information. That is, QoS information may be the basis for prioritizing command delivery from the VM scheduler 360-b to the volatile memory 320, but it is not necessarily the basis for prioritizing command delivery from the TCQ component to the VM scheduler 360-b.

[0089] Data associated with a read command may be received from non-volatile memory 325 or volatile memory 320, or both, and may be stored in one or more read buffers coupled to TCQ component 355. If the read command is associated with QoS information received from host device 305, TCQ component 355 may prioritize the transmission of data for the read command based on (e.g., according to) or in response to the QoS information of the read command (and possibly based on the QoS information of other read commands with buffered data). Therefore, interface controller 315 may prioritize the return (e.g., transmission) of the data to host device 305 based on or in response to the QoS information associated with the read command for the requested data.

[0090] Figure 4 An example of a process flow 400 supporting quality of service information for a multi-memory system, as disclosed herein, is shown. Process flow 400 can be derived from, as referenced... Figure 1 The memory subsystem 110 or interface controller 115 described, as referenced Figure 2 The memory subsystem 200 or interface controller 202 described herein, or as referenced Figure 3 The described memory subsystem 310 or interface controller 315 is used to implement process 400. However, other types of devices or components (or combinations thereof) can implement process 400. Process 400 can illustrate the operation of a device that receives QoS information for function commands.

[0091] For ease of reference, the reference apparatus describes process flow 400. For example, aspects of process flow 400 may be implemented by means including volatile memory and non-volatile memory. Alternatively, aspects of process flow 400 may be implemented as instructions stored in memory (e.g., firmware stored in volatile memory 120 or non-volatile memory 125, or both). For example, if the instructions are executed by a controller, the controller may be caused to perform operations of process flow 400.

[0092] At 405, commands, such as metadata commands, can be received from the host device. For example, the interface controller 315 can receive commands, such as XCAS or XREAD commands, via a C / A bus interface 340, which may be a DRAM interface. In some instances, one or more activation (ACT) commands can be received before 405. Activation commands can activate one or more rows in one or more banks of memory in the memory subsystem 310.

[0093] At 410, metadata commands can be decoded. For example, command decoder 345 can decode metadata commands based on (e.g., using) the rising and falling edge states of the CS[0] pin and other states of other pins. The rising and falling edge states of CS[0] may distinguish metadata commands from similar commands (e.g., CAS commands or read commands).

[0094] At 415, QoS information for a function command (e.g., a function command following the metadata command, such as a function command immediately after the metadata command) can be determined based on (e.g., in response to) decoding the metadata command. For example, command decoder 345 can determine the QoS information included in the metadata command. In some instances, command decoder 345 can also determine the identifier of the function command based on (e.g., in response to) decoding the metadata command. For example, command decoder 345 can determine a read identifier included in the metadata command.

[0095] At 420, function commands can be received. For example, a read command or write command can be received from the host device 305 via the C / A bus 330. Other examples of function commands include precharge commands and activation commands. At 425, function commands and QoS information used for the function commands can be stored. For example, the interface controller 315 can store function commands and QoS information in array 365, possibly along with other control information for the function commands.

[0096] At 430, a function command and QoS information can be transmitted to the scheduler, possibly along with other control information for the function command. For example, if the function command is for volatile memory 320, the TCQ component 355 can transmit the function command to the VM scheduler 360-b. If the function command is for non-volatile memory 325, the TCQ component 355 can transmit the function command to the NVM scheduler 360-a. The TCQ component 355 can determine the appropriate scheduler for the function command based on the hit or miss status of the function command and other factors. In some instances, the TCQ component 355 can prioritize the transmission of the function command to the scheduler based on (e.g., according to) QoS information. In some instances, the TCQ component 355 can transmit the function command and QoS information to the scheduler independently of the QoS information.

[0097] At 435, a function command can be transmitted to the appropriate memory. The transmission of the function command can be prioritized based on (e.g., according to) the QoS information of the function command, and in some instances, the QoS information of other function commands queued at the scheduler. If the function command is for volatile memory 320, the VM scheduler 360-b can transmit the function command to volatile memory 320. If the function command is for non-volatile memory 325, the NVM scheduler 360-a can transmit the function command to non-volatile memory 325. If the function command is associated with a high QoS category, prioritizing the transmission of the function command can mean transmitting the function command to the appropriate memory before other commands for that memory (e.g., commands received from the host device before the function command, commands that have been waiting longer than the function command). If a function command is associated with a low QoS category, prioritizing the delivery of the function command can mean delivering the function command to the appropriate memory after other commands for that memory (e.g., commands received from the host device after the function command, commands that have a shorter waiting time than the function command). In some instances, the scheduler can deliver the function command to memory based on its age.

[0098] At 440, data can be received. For example, interface controller 315 can receive data from volatile memory 320 or non-volatile memory 325. The data may correspond to a function command, which may be a read command. At 445, data can be transmitted. For example, the interface controller can transmit data to host device 305. Data transmission can be prioritized based on QoS information of the read command associated with the data, and in some instances, QoS information of other read commands with data buffered at interface controller 315.

[0099] Alternative instances as described above may be implemented, in which some operations may be performed in a different order, in parallel, or not at all. In some cases, operations may include additional features not mentioned herein, or additional operations may be added. Furthermore, some operations may be performed multiple times, or certain combinations of operations may be repeated or cyclical.

[0100] Figure 5 A block diagram 500 is shown of a memory device 520 supporting quality of service information for a multi-memory system, according to an example disclosed herein. The memory device 520 may be as described in the reference... Figures 1 to 4 Examples of aspects of the described memory device. Memory device 520 or its various components may be examples of means for performing various aspects of quality of service information for a multi-memory system as described herein. For example, memory device 520 may include bus interface 525, decoder 530, TCQ circuitry system 535, scheduling component 540, NVM scheduler 545, VM scheduler 550, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0101] Bus interface 525 may be or include a command / address bus, command / address bus interface, buffer, logic, circuitry, processor, controller, receiver, or other components capable of performing the functions described herein. Decoder 530 may be logic or circuitry capable of performing the functions described herein. TCQ circuitry 535 may be or include logic, circuitry, processor, controller, or other components capable of performing the functions described herein. Scheduling component 540 may be or include logic, circuitry, processor, controller, or other components capable of performing the functions described herein. NVM scheduler 545 may be or include logic, circuitry, processor, controller, or other components capable of performing the functions described herein. VM scheduler 550 may be or include logic, circuitry, processor, controller, or other components capable of performing the functions described herein. In some instances, NVM scheduler 545 and VM scheduler 550 may be included in scheduling component 540.

[0102] Bus interface 525 may be configured or otherwise supported for receiving a first command from a host device via a command bus during a set of clock cycles, the command bus including a command select pin configured for double data rate signaling. Decoder 530 may be configured or otherwise supported for decoding the first command based at least in part on the state of the command select pin during at least one clock cycle in the set of clock cycles. In some instances, decoder 530 may be configured or otherwise supported for determining QoS information of a second command, including a read command or a write command, based at least in part on decoding the first command and multiple bits included in the first command.

[0103] In some instances, multiple bits indicate the QoS category of the second command. In some instances, the first command is decoded at least in part based on the state of the command select pin during at least one rising edge and one falling edge of at least one clock cycle. In some instances, the scheduling component 540 may be configured or otherwise supported to provide means for prioritizing the transfer of the second command to non-volatile or volatile memory based at least in part on the QoS information of the second command.

[0104] In some instances, scheduling component 540 may be configured or otherwise supported to prioritize the transfer of the second command to non-volatile or volatile memory based at least in part on the amount of time the second command has been queued at the interface controller. In some instances, the second command includes a read command, and TCQ circuitry 535 may be configured or otherwise supported to prioritize the transfer of data associated with the second command to the host device based at least in part on QoS information of the second command.

[0105] In some instances, the NVM scheduler 545 may be configured or otherwise supported to support means for storing the second command and its QoS information in the array. In some instances, the NVM scheduler 545 may be configured or otherwise supported to support means for prioritizing the transfer of the second command to non-volatile memory based at least in part on the QoS information of the second command.

[0106] In some instances, the VM scheduler 550 may be configured or otherwise supported to support means for storing the second command and its QoS information in the array. In some instances, the VM scheduler 550 may be configured or otherwise supported to support means for prioritizing the transfer of the second command to volatile memory based at least in part on the QoS information of the second command.

[0107] In some instances, decoder 530 may be configured or otherwise supported as means for determining an identifier of a second command based at least in part on a second plurality of bits included in the first command, the second plurality of bits indicating the identifier.

[0108] In some instances, bus interface 525 may be configured or otherwise supported for means of receiving a first command from a host device via a command bus during a set of clock cycles, the command bus including a command select pin configured for double data rate signaling. In some instances, decoder 530 may be configured or otherwise supported for means of decoding the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles.

[0109] In some instances, decoder 530 may be configured or otherwise supported for means of determining QoS information of a read command received via the command bus after the first command, based at least in part on decoding the first command and a plurality of bits included in the first command. TCQ circuitry 535 may be configured or otherwise supported for means of prioritizing the transmission of data associated with the read command to the host device, based at least in part on the QoS information of the read command.

[0110] In some instances, the first command is decoded at least in part based on the state of the command select pin during at least one rising edge and one falling edge of at least one clock cycle. In some instances, the scheduling component 540 may be configured or otherwise support means for prioritizing the transfer of read commands to non-volatile or volatile memory based at least in part on QoS information of the read command.

[0111] In some instances, scheduling component 540 may be configured or otherwise supported for means of prioritizing the transfer of read commands to non-volatile or volatile memory based at least in part on the amount of time read commands are queued at the interface controller. In some instances, decoder 530 may be configured or otherwise supported for means of determining the identifier of the read command based at least in part on a second plurality of bits included in the first command.

[0112] In some instances, the NVM scheduler 545 may be configured or otherwise supported to provide means for storing read commands and QoS information of the read commands in the array. In some instances, the NVM scheduler 545 may be configured or otherwise supported to provide means for prioritizing the transfer of read commands to non-volatile memory based at least in part on the QoS information of the read commands.

[0113] In some instances, the VM scheduler 550 may be configured or otherwise supported to support means for storing read commands and QoS information of the read commands in the array. In some instances, the VM scheduler 550 may be configured or otherwise supported to support means for prioritizing the transfer of read commands to volatile memory based at least in part on the QoS information of the read commands, the logic being configured to receive read commands and QoS information of the read commands from the array.

[0114] In some instances, bus interface 525 may be configured or otherwise supported for receiving a first command from a host device via a command bus during a set of clock cycles, the command bus including a command select pin configured for double data rate signaling. In some instances, decoder 530 may be configured or otherwise supported for decoding the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles. In some instances, decoder 530 may be configured or otherwise supported for determining QoS information for write commands received via the command bus after the first command, based at least in part on decoding the first command and multiple bits included in the first command. Scheduling component 540 may be configured or otherwise supported for prioritizing write command transfers to non-volatile or volatile memory based at least in part on the QoS information of the write commands.

[0115] In some instances, the first command is decoded at least in part based on the state of the command select pin during at least one rising edge and one falling edge of at least one clock cycle.

[0116] In some instances, the scheduling component 540 may be configured or otherwise supported as means for prioritizing the transfer of write commands to non-volatile or volatile memory based at least in part on the amount of time the write commands are queued at the interface controller.

[0117] Figure 6 A flowchart is shown of a method 600 for supporting quality of service information for a multi-memory system, according to an example disclosed herein. The operation of method 600 can be implemented by a memory device or its components as described herein. For example, the operation of method 600 can be implemented by, as referenced... Figures 1 to 5 The memory device described is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described function. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0118] At 605, the method may include receiving a first command from a host device during a set of clock cycles via a command bus, the command bus including a command select pin configured for double data rate signaling. The operation at 605 may be performed according to examples as disclosed herein. In some examples, aspects of the operation at 605 may be as described in references... Figure 5 The bus interface 525 described is used for execution.

[0119] At 610, the method may include decoding a first command based at least in part on the state of the command selection pin during at least one clock cycle of the set of clock cycles. The operation at 610 may be performed according to examples as disclosed herein. In some examples, aspects of the operation at 610 may be as described in references... Figure 5 The decoder 530 described is used for execution.

[0120] At 615, the method may include determining QoS information of a second command, including a read command or a write command, based at least in part on decoding a first command and a plurality of bits included in the first command. The operation at 615 may be performed according to examples as disclosed herein. In some instances, aspects of the operation at 615 may be as described in references... Figure 5 The decoder 530 described is used for execution.

[0121] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a first command from a host device during a set of clock cycles via a command bus including a command select pin configured for double data rate signaling, decoding the first command at least in part based on the state of the command select pin during at least one clock cycle of the set of clock cycles, and determining QoS information for a second command, including a read command or a write command, at least in part based on the decoding of the first command and a plurality of bits included in the first command.

[0122] In some instances of the method 600 and device described herein, the plurality of bits indicate the QoS category of the second command. In some instances of the method 600 and device described herein, the first command can be decoded at least in part based on the state of the command selection pin during at least one rising edge and one falling edge of at least one clock cycle.

[0123] Some examples of the method 600 and device described herein may further include operations, features, circuit systems, logic, means, or instructions for prioritizing the transmission of the second command to non-volatile memory or volatile memory based at least in part on QoS information of the second command.

[0124] Some examples of the methods 600 and devices described herein may further include operations, features, circuit systems, logic, devices, or instructions that prioritize the transfer of a second command to non-volatile or volatile memory based at least in part on the amount of time the second command is queued at the interface controller.

[0125] In some instances of the method 600 and device described herein, the second command includes a read command, and the method, device, and non-transitory computer-readable medium may further include operations, features, circuitry, logic, means, or instructions for prioritizing the transmission of data associated with the second command to a host device based at least in part on QoS information of the second command.

[0126] Some examples of the method 600 and device described herein may further include operations, features, circuit systems, logic, means, or instructions for storing a second command and its QoS information in an array, and prioritizing the transfer of the second command to non-volatile memory based at least in part on the QoS information of the second command.

[0127] Some examples of the method 600 and device described herein may further include operations, features, circuit systems, logic, means, or instructions for storing a second command and its QoS information in an array, and prioritizing the transfer of the second command to volatile memory based at least in part on the QoS information of the second command.

[0128] Some examples of the method 600 and device described herein may further include operations, features, circuitry, logic, apparatus, or instructions for determining an identifier of a second command based at least in part on a second plurality of bits included in the first command, the second plurality of bits indicating the identifier.

[0129] Figure 7 A flowchart is shown of a method 700 for supporting quality of service information for a multi-memory system, according to an example disclosed herein. The operation of method 700 can be implemented by a memory device or its components as described herein. For example, the operation of method 700 can be implemented by, as referenced... Figures 1 to 5 The memory device described is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described function. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0130] At 705, the method may include receiving a first command from a host device during a set of clock cycles via a command bus, the command bus including a command select pin configured for double data rate signaling. Operation at 705 may be performed according to examples as disclosed herein. In some examples, aspects of operation at 705 may be as described in references... Figure 5 The bus interface 525 described is used for execution.

[0131] At 710, the method may include decoding a first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles. The operation at 710 may be performed according to examples as disclosed herein. In some instances, aspects of the operation at 710 may be as described in references... Figure 5 The decoder 530 described is used for execution.

[0132] At 715, the method may include determining QoS information for a read command received via the command bus after the first command, at least in part based on (e.g., in response to) decoding the first command and a plurality of bits included in the first command. The operation at 715 may be performed according to examples as disclosed herein. In some instances, aspects of the operation at 715 may be as described in references... Figure 5 The decoder 530 described is used for execution.

[0133] At 720, the method may include prioritizing the transmission of data associated with a read command to the host device, at least in part based on (e.g., according to) QoS information of the read command. The operation at 720 may be performed according to examples as disclosed herein. In some instances, aspects of the operation at 720 may be as described in references... Figure 5 The TCQ circuit system 535 is described and executed.

[0134] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a first command from a host device during a set of clock cycles via a command bus including a command select pin configured for double data rate signaling, decoding the first command at least in part based on the state of the command select pin during at least one clock cycle of the set of clock cycles, determining QoS information for a read command received via the command bus after the first command based at least in part on the decoding of the first command and multiple bits included in the first command, and prioritizing the transmission of data associated with the read command to the host device based at least in part on the QoS information of the read command.

[0135] In some instances of the method 700 and device described herein, the first command can be decoded at least in part based on the state of the command select pin during at least one rising edge and one falling edge of at least one clock cycle.

[0136] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, means, or instructions for prioritizing the transfer of read commands to non-volatile or volatile memory based at least in part on QoS information of the read command.

[0137] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, devices, or instructions that prioritize the transfer of read commands to non-volatile or volatile memory based at least in part on the amount of time that read commands can be queued at the interface controller.

[0138] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, means, or instructions for determining an identifier of a read command based at least in part on a second plurality of bits included in a first command.

[0139] Some examples of the methods 700 and devices described herein may further include operations, features, circuit systems, logic, means, or instructions for storing read commands and QoS information of read commands in an array, and prioritizing the transfer of read commands to non-volatile memory based at least in part on the QoS information of the read commands.

[0140] Some examples of the method 700 and device described herein may further include operations, features, circuitry, logic, means, or instructions for storing read commands and QoS information of read commands in an array, and prioritizing the transfer of read commands to volatile memory based at least in part on the QoS information of read commands, the logic being configured to receive read commands and QoS information of read commands from the array.

[0141] Figure 8 A flowchart is shown of a method 800 for supporting quality of service information for a multi-memory system, according to an example disclosed herein. The operation of method 800 can be implemented by a memory device or its components as described herein. For example, the operation of method 800 can be implemented by, as referenced herein... Figures 1 to 5 The memory device described is used for execution. In some instances, the memory device may execute a set of instructions to control the functional elements of the device to perform the described function. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0142] At 805, the method may include receiving a first command from a host device during a set of clock cycles via a command bus, the command bus including a command select pin configured for double data rate signaling. Operation at 805 may be performed according to examples as disclosed herein. In some examples, aspects of operation at 805 may be as described in references... Figure 5 The bus interface 525 described is used for execution.

[0143] At 810, the method may include decoding a first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles. The operation at 810 may be performed according to examples as disclosed herein. In some examples, aspects of the operation at 810 may be as described in references... Figure 5 The decoder 530 described is used for execution.

[0144] At 815, the method may include determining QoS information for a write command received via the command bus after the first command, at least in part based on (e.g., in response to) decoding the first command and a plurality of bits included in the first command. The operation at 815 may be performed according to examples as disclosed herein. In some instances, aspects of the operation at 815 may be as described in references... Figure 5 The decoder 530 described is used for execution.

[0145] At 820, the method may include prioritizing the transfer of write commands to non-volatile or volatile memory based at least in part on (e.g., according to) QoS information of the write command. The operation at 820 may be performed according to examples as disclosed herein. In some instances, aspects of the operation at 820 may be as described in references... Figure 5 The described scheduling component 540 is used for execution.

[0146] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a first command from a host device via a command bus including a command select pin configured for double data rate signaling during a set of clock cycles, decoding the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles, determining QoS information for a write command received via the command bus after the first command based at least in part on the decoding of the first command and multiple bits included in the first command, and prioritizing the transfer of write commands to non-volatile or volatile memory based at least in part on the QoS information of the write commands.

[0147] In some instances of the method 800 and device described herein, the first command can be decoded at least in part based on the state of the command select pin during at least one rising edge and one falling edge of at least one clock cycle.

[0148] Some examples of the methods 800 and devices described herein may further include operations, features, circuitry, logic, means, or instructions for prioritizing the transfer of write commands to non-volatile or volatile memory based at least in part on the amount of time that write commands can be queued at the interface controller.

[0149] It should be noted that the methods described herein describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0150] A device is described. The device may include non-volatile memory; volatile memory configured to serve as a cache memory for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller is operable to cause the device to receive a first command from a host device via a command bus during a set of clock cycles, the command bus including a command select pin configured for double data rate signaling; to decode the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles; and to determine QoS information of a second command, including a read command or a write command, based at least in part on the decoding of the first command and a plurality of bits included in the first command.

[0151] In some instances of the device, the plurality of bits indicate the QoS category of the second command. In some instances of the device, the first command may be decoded at least in part based on the state of the command selection pin during at least one rising edge and one falling edge of the at least one clock cycle. In some instances, the device may include prioritizing the transfer of the second command to the non-volatile memory or the volatile memory based at least in part on the QoS information of the second command.

[0152] In some instances, the device may include prioritizing the transmission of the second command to the non-volatile memory or the volatile memory based at least in part on the amount of time the second command can be queued at the interface controller. In some instances, the device may include prioritizing the transmission of data associated with the second command to the host device based at least in part on the QoS information of the second command.

[0153] In some instances, the device may include an array configured to store the second command and the QoS information of the second command; and logic coupled to the array and the non-volatile memory and configured to prioritize the transmission of the second command to the non-volatile memory based at least in part on the QoS information of the second command, the logic being configured to receive the second command and the QoS information of the second command from the array.

[0154] In some instances, the device may include an array configured to store the second command and the QoS information of the second command; and logic coupled to the array and the volatile memory and configured to prioritize the transmission of the second command to the volatile memory based at least in part on the QoS information of the second command, the logic being configured to receive the second command and the QoS information of the second command from the array.

[0155] In some instances, the device may include an identifier for the second command determined at least in part based on a second plurality of bits included in the first command, the second plurality of bits indicating the identifier.

[0156] In some instances of the device, the volatile memory includes DRAM cells, and the interface controller may be operable to interface with the host device via a DRAM interface.

[0157] Another device is described. The device may include non-volatile memory; volatile memory configured to serve as a cache memory for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller is operable to cause the device to receive a first command from a host device via a command bus during a set of clock cycles, the command bus including a command select pin configured for double data rate signaling; to decode the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles; to determine QoS information for a read command received via the command bus after the first command based at least in part on the decoding of the first command and a plurality of bits included in the first command; and to prioritize the transmission of data associated with the read command to the host device based at least in part on the QoS information of the read command.

[0158] In some instances of the device, the first command may be decoded at least in part based on the state of the command selection pin during at least one rising edge and one falling edge of the at least one clock cycle. In some instances, the device may include prioritizing the transfer of the read command to the non-volatile memory or the volatile memory based at least in part on the QoS information of the read command.

[0159] In some instances, the device may include prioritizing the transfer of the read command to the non-volatile memory or the volatile memory based at least in part on the amount of time the read command can be queued at the interface controller. In some instances, the device may include determining the identifier of the read command based at least in part on a second plurality of bits included in the first command.

[0160] In some instances, the device may include an array configured to store the read command and the QoS information of the read command; and logic coupled to the array and the non-volatile memory and configured to prioritize the transmission of the read command to the non-volatile memory based at least in part on the QoS information of the read command, the logic being configured to receive the read command and the QoS information of the read command from the array.

[0161] In some instances, the device may include an array configured to store the read command and the QoS information of the read command; and logic coupled to the array and the volatile memory and configured to prioritize the transmission of the read command to the volatile memory based at least in part on the QoS information of the read command, the logic being configured to receive the read command and the QoS information of the read command from the array.

[0162] Another device is described. The device may include non-volatile memory; volatile memory configured to serve as a cache memory for the non-volatile memory; and an interface controller coupled to the non-volatile memory and the volatile memory. The interface controller is operable to cause the device to receive a first command from a host device via a command bus during a set of clock cycles, the command bus including a command select pin configured for double data rate signaling; to decode the first command based at least in part on the state of the command select pin during at least one clock cycle of the set of clock cycles; to determine QoS information of a write command received via the command bus after the first command based at least in part on the decoding of the first command and a plurality of bits included in the first command; and to prioritize the transmission of the write command to the non-volatile memory or the volatile memory based at least in part on the QoS information of the write command.

[0163] In some instances of the device, the first command may be decoded at least in part based on the state of the command select pin during at least one rising edge and one falling edge of the at least one clock cycle. In some instances, the device may include prioritizing the transfer of the write command to the non-volatile memory or the volatile memory based at least in part on the amount of time the write command can be queued at the interface controller.

[0164] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, wherein the bus can have various bit widths.

[0165] A protocol can define one or more communication procedures and one or more communication parameters supported for use by a device or component. For example, a protocol can define various operations, the timing and frequency for those operations, the meaning of various commands or signals or both, one or more addressing schemes for one or more memories, the type of communication where pins are reserved, the size of data processed at various components such as interfaces, the data rates or bandwidths supported by various components such as interfaces, and other parameters and metrics, or any combination thereof. The use of shared protocols enables interaction between devices because each device can operate in a way that another device expects, recognizes, and understands. For example, two devices supporting the same protocol can interact according to the policies, procedures, and parameters defined by the protocol, while two devices supporting different protocols may be incompatible.

[0166] To illustrate, two devices supporting different protocols may be incompatible because the protocols define different addressing schemes (e.g., different numbers of address bits). As another illustration, two devices supporting different protocols may be incompatible because the protocols define different transmission procedures for responding to a single command (e.g., the burst length or number of bytes allowed in response to the command may be different). Simply translating a command into an action should not be interpreted as the use of two different protocols. In fact, protocols can be considered different if the corresponding procedures or parameters defined by the two protocols change. For example, if a device supports different addressing schemes or different transmission procedures for responding to commands, then the device can be said to support two different protocols.

[0167] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. If there is any conductive path between components that allows the flow of signals between them at any time, then the components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other). At any given time, based on or in response to the operation of a device including the connected components, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the flow of signals between the connected components for a period of time.

[0168] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path, while in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0169] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0170] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0171] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. These terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may contain heavily doped, for example, degenerate, semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of the carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of the carriers are holes), then the FET may be called a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0172] The description herein, taken in conjunction with the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," and not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be implemented without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0173] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, components of the same type can be distinguished by a dash following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0174] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0175] As used herein, the term “substantially” means that the modified feature (e.g., a verb or adjective modified by the term “substantially”) need not be absolute but must be close enough to obtain the advantage of the feature. As used herein, the term “in parallel” means that the described actions or phenomena occur during a period of time that at least partially overlap in time; they may occur substantially simultaneously or may be offset in time.

[0176] The various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, it may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, a combination of one or more microprocessors with a DSP core, or any other such configuration).

[0177] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functions can be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the above-described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed such that portions of the functions are implemented in different physical locations. And, as used herein, including in the claims, the use of "or" in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0178] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compressed optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs use lasers to reproduce data optically. Combinations of these are also included within the scope of computer-readable media.

[0179] The description provided herein enables those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Non-volatile memory; A volatile memory configured to serve as a cache memory for the non-volatile memory; and An interface controller, coupled to the non-volatile memory and the volatile memory, is operable to enable the device to: During a set of clock cycles, a set of bits is received from the host device via a command bus, the command bus including a command select pin configured for double data rate signaling; Whether the set of bits represents metadata of a first command or a second command is determined at least in part based on the state of the command selection pin during at least one clock cycle of the set of clock cycles. and The metadata of the second command is represented by a set of bits indicating the state of the command selection pin, which is at least partially based on the set of bits. The quality of service (QoS) information of the second command is determined at least partially based on a plurality of bits included in the set of bits. The second command includes a read command or a write command.

2. The device of claim 1, wherein the plurality of bits indicate the QoS category of the second command.

3. The device of claim 1, wherein the set of bits is decoded at least in part based on the state of the command selection pin during at least one rising edge and one falling edge of the at least one clock cycle.

4. The device of claim 1, wherein the interface controller is further operable to cause the device to: The transmission of the second command to the non-volatile memory or the volatile memory is prioritized at least in part based on the QoS information of the second command.

5. The device of claim 4, wherein the interface controller is further operable to cause the device to: The transmission of the second command to the non-volatile memory or the volatile memory is prioritized at least in part based on the amount of time the second command is queued at the interface controller.

6. The device of claim 1, wherein the second command comprises the read command, and wherein the interface controller is further operable to cause the device to: The transmission of data associated with the second command to the host device is prioritized, at least in part, based on the QoS information of the second command.

7. The device according to claim 1, further comprising: An array configured to store the second command and the QoS information of the second command; and A logic, coupled to the array and the non-volatile memory and configured to prioritize the transmission of the second command to the non-volatile memory based at least in part on the QoS information of the second command, the logic being configured to receive the second command and the QoS information of the second command from the array.

8. The device according to claim 1, further comprising: An array configured to store the second command and the QoS information of the second command; and A logic, coupled to the array and the volatile memory and configured to prioritize the transmission of the second command to the volatile memory based at least in part on the QoS information of the second command, the logic being configured to receive the second command and the QoS information of the second command from the array.

9. The device of claim 1, wherein the interface controller is further operable to cause the device to: The identifier of the second command is determined at least in part based on a second plurality of bits included in the set of said bits, the second plurality of bits indicating said identifier.

10. The device of claim 1, wherein the volatile memory comprises dynamic random access memory (DRAM) cells, and the interface controller is operable to interface with the host device via a DRAM interface.

11. An apparatus comprising: Non-volatile memory; A volatile memory configured to serve as a cache memory for the non-volatile memory; and An interface controller, coupled to the non-volatile memory and the volatile memory, is operable to enable the device to: During a set of clock cycles, a set of bits is received from the host device via a command bus, the command bus including a command select pin configured for double data rate signaling; Whether the set of bits represents metadata of a first command or a second command is determined at least in part based on the state of the command selection pin during at least one clock cycle of the set of clock cycles. The Quality of Service (QoS) information of a read command received via the command bus after the set of bits is determined based at least in part on the set of bits indicating the metadata of the second command and multiple bits included in the set of bits, in relation to the state of the command selection pin. and The transmission of data associated with the read command to the host device is prioritized, at least in part, based on the QoS information of the read command.

12. The device of claim 11, wherein the set of bits is decoded at least in part based on the state of the command selection pin during at least one rising edge and one falling edge of the at least one clock cycle.

13. The device of claim 11, wherein the interface controller is further operable to cause the device to: The transmission of the read command to the non-volatile memory or the volatile memory is prioritized at least in part based on the QoS information of the read command.

14. The device of claim 11, wherein the interface controller is further operable to cause the device to: The transmission of the read command to the non-volatile memory or the volatile memory is prioritized at least in part based on the amount of time the read command is queued at the interface controller.

15. The device of claim 11, wherein the interface controller is further operable to cause the device to: The identifier of the read command is determined at least in part based on a second plurality of bits included in the set of bits.

16. The device of claim 11, further comprising: An array configured to store the read command and the QoS information of the read command; and A logic, coupled to the array and the non-volatile memory and configured to prioritize the transmission of the read command to the non-volatile memory based at least in part on the QoS information of the read command, the logic being configured to receive the read command and the QoS information of the read command from the array.

17. The apparatus of claim 11, further comprising: An array configured to store the read command and the QoS information of the read command; and A logic, coupled to the array and the volatile memory and configured to prioritize the transmission of the read command to the volatile memory based at least in part on the QoS information of the read command, the logic being configured to receive the read command and the QoS information of the read command from the array.

18. An apparatus comprising: Non-volatile memory; A volatile memory configured to serve as a cache memory for the non-volatile memory; and An interface controller, coupled to the non-volatile memory and the volatile memory, is operable to enable the device to: During a set of clock cycles, a set of bits is received from the host device via a command bus, the command bus including a command select pin configured for double data rate signaling; Whether the set of bits represents metadata of a first command or a second command is determined at least in part based on the state of the command selection pin during at least one clock cycle of the set of clock cycles. Based at least in part on the state of the command selection pin indicating the set of bits representing the metadata of the second command and multiple bits included in the set of bits, determine the Quality of Service (QoS) information of the write command received via the command bus after the set of bits; and The transmission of the write command to the non-volatile memory or the volatile memory is prioritized at least in part based on the QoS information of the write command.

19. The device of claim 18, wherein the set of bits is decoded at least in part based on the state of the command select pin during at least one rising edge and one falling edge of the at least one clock cycle.

20. The device of claim 18, wherein the interface controller is further operable to cause the device to: The transmission of write commands to the non-volatile memory or the volatile memory is prioritized at least in part based on the amount of time the write commands are queued at the interface controller.

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