Display motherboard, detection method thereof, display substrate and display device

Abstract

A display motherboard, a display substrate and a display device. The display motherboard comprises at least one substrate area, the substrate area comprises at least one detection pad area, at least one detection trace area and at least two display substrates, the detection pad area comprises a plurality of pads, the detection trace area comprises a plurality of signal traces, the first end of the plurality of signal traces is connected with the plurality of pads in correspondence, the second end of the plurality of signal traces extends to the display substrate in the substrate area and is connected with the detection circuit of the display substrate, the plurality of pads are configured to enable an external detection device to provide a detection signal to the detection circuit of the display substrate in the substrate area through the plurality of pads, and the display substrates in the substrate area are simultaneously subjected to a lighting detection or an aging procedure. The present disclosure realizes a group unit detection lighting mode, effectively improves the efficiency of ET lighting detection and aging procedure, reduces the process time, and effectively improves the production capacity.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular to a display mother board, a detection method thereof, a display substrate and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] The technical problem to be solved by the present disclosure is to provide a display mother board, a detection method thereof, a display substrate and a display device to improve the efficiency of lighting detection and aging process.

[0005] In one aspect, the present disclosure provides a display mother board, comprising at least one substrate area, the substrate area comprising at least one detection pad area, at least one detection trace area, and at least two display substrates, the display substrate comprising a display area and a binding area located on one side of the display area, the display area comprising a plurality of sub-pixels, and the binding area comprising at least a detection circuit and a plurality of detection pins, the detection circuit being connected to the plurality of detection pins and the plurality of sub-pixels; the detection pad area comprising a plurality of pads, and the detection trace area comprising a plurality of signal traces, the first end of the plurality of signal traces being connected to the plurality of pads in correspondence, and the second end of the plurality of signal traces extending to the binding area of the display substrate in the substrate area and being connected to the plurality of detection pins of the display substrate in correspondence, the plurality of pads being configured to enable an external detection device to provide a detection signal to the detection circuit of each display substrate in the substrate area through the plurality of pads, and to simultaneously perform lighting detection or aging process on each display substrate in the substrate area.

[0006] In an example embodiment, the substrate region comprises at least a first display substrate and a second display substrate arranged in sequence along a first direction, the detection trace region is arranged on one side of the first display substrate and the second display substrate in a second direction, and the detection pad region is arranged on a side of the second display substrate away from the first display substrate, or the detection pad region is arranged on a side of the first display substrate away from the second display substrate, and the first direction intersects the second direction.

[0007] In an example embodiment, the detection pad region comprises at least a first pad, a second pad, a third pad, and a fourth pad, and the detection trace region comprises at least a first power supply trace, a second power supply trace, a third power supply trace, and a fourth power supply trace; a first end of the first power supply trace is connected to the first pad, and a second end of the first power supply trace extends to the first display substrate and is connected to a detection pin of the first display substrate; the first pad is configured to enable an external detection device to provide a first power supply signal to the first display substrate through the first pad; a first end of the second power supply trace is connected to the second pad, and a second end of the second power supply trace extends to the second display substrate and is connected to a detection pin of the second display substrate; the second pad is configured to enable the external detection device to provide the first power supply signal to the second display substrate through the second pad; a first end of the third power supply trace is connected to the third pad, and a second end of the third power supply trace extends to the first display substrate and is connected to a detection pin of the first display substrate; the third pad is configured to enable the external detection device to provide a second power supply signal to the first display substrate through the third pad; and a first end of the fourth power supply trace is connected to the fourth pad, and a second end of the fourth power supply trace extends to the second display substrate and is connected to a detection pin of the second display substrate; the fourth pad is configured to enable the external detection device to provide the second power supply signal to the second display substrate through the fourth pad.

[0008] In an example embodiment, at least one signal trace of the detection trace region is a single-layer trace structure, or a double-layer trace structure, or a three-layer or more trace structure.

[0009] In an example embodiment, the first power supply trace and the third power supply trace are arranged on a side of the second power supply trace and the fourth power supply trace away from the display substrate.

[0010] In an example embodiment, a width of the first power supply trace is greater than a width of the second power supply trace, and a width of the third power supply trace is greater than a width of the fourth power supply trace, and the widths are minimum dimensions of the first power supply trace, the second power supply trace, the third power supply trace, and the fourth power supply trace in the second direction, respectively.

[0011] In an example embodiment, the detection pad area further comprises a fifth pad and a sixth pad, and the detection trace area further comprises a fifth power supply trace and a sixth power supply trace; a first end of the fifth power supply trace is connected with the fifth pad, and a second end of the fifth power supply trace extends to the back of the first display substrate and the second display substrate and is connected with the detection pin of the first display substrate and the second display substrate respectively, and the fifth pad is configured to enable an external detection device to provide a high-level signal to the first display substrate and the second display substrate through the fifth pad; a first end of the sixth power supply trace is connected with the sixth pad, and a second end of the sixth power supply trace extends to the back of the first display substrate and the second display substrate and is connected with the detection pin of the first display substrate and the second display substrate respectively, and the sixth pad is configured to enable an external detection device to provide a low-level signal to the first display substrate and the second display substrate through the sixth pad.

[0012] In an example embodiment, the fifth power supply trace and the sixth power supply trace are arranged on the side of the second power supply trace close to the display substrate.

[0013] In an example embodiment, the detection pad area further comprises an eleventh pad, a twelfth pad, a thirteenth pad and a fourteenth pad, and the detection trace area further comprises an eleventh power supply trace, a twelfth power supply trace, a thirteenth power supply trace and a fourteenth power supply trace; a first end of the eleventh power supply trace is connected with the eleventh pad, and a second end of the eleventh power supply trace extends to the first display substrate and is connected with the detection pin of the first display substrate, and the eleventh pad is configured to enable an external detection device to provide a first initial signal to the first display substrate through the eleventh pad; a first end of the twelfth power supply trace is connected with the twelfth pad, and a second end of the twelfth power supply trace extends to the second display substrate and is connected with the detection pin of the second display substrate, and the twelfth pad is configured to enable an external detection device to provide a first initial signal to the second display substrate through the twelfth pad; a first end of the thirteenth power supply trace is connected with the thirteenth pad, and a second end of the thirteenth power supply trace extends to the first display substrate and is connected with the detection pin of the first display substrate, and the thirteenth pad is configured to enable an external detection device to provide a second initial signal to the first display substrate through the thirteenth pad; a first end of the fourteenth power supply trace is connected with the fourteenth pad, and a second end of the fourteenth power supply trace extends to the second display substrate and is connected with the detection pin of the second display substrate, and the fourteenth pad is configured to enable an external detection device to provide a second initial signal to the second display substrate through the fourteenth pad.

[0014] In an exemplary embodiment, the eleventh power supply wire, the twelfth power supply wire and the fourteenth power supply wire are arranged on a side of the second power supply wire close to the display substrate, and the thirteenth power supply wire is arranged on a side of the third power supply wire away from the display substrate.

[0015] In an exemplary embodiment, a width of the eleventh power supply wire is greater than a width of the twelfth power supply wire, and a width of the thirteenth power supply wire is greater than a width of the fourteenth power supply wire, the widths being minimum dimensions of the eleventh power supply wire, the twelfth power supply wire, the thirteenth power supply wire and the fourteenth power supply wire in the second direction, respectively.

[0016] In an example embodiment, the detection pad area further comprises a first pad group, a second pad group, a third pad group, a fourth pad group and a fifth pad group, and the detection trace area further comprises a first trace group, a second trace group, a third trace group, a fourth trace group and a fifth trace group; the first ends of the plurality of signal traces in the first trace group are connected to the plurality of pads in the first pad group in correspondence, the second ends of the plurality of signal traces in the first trace group extend to the second display substrate and are connected to the plurality of detection pins of the second display substrate in correspondence, and the first pad group is configured to enable an external detection device to provide detection signals to the second display substrate through the first pad group; the first ends of the plurality of signal traces in the second trace group are connected to the plurality of pads in the second pad group in correspondence, the second ends of the plurality of signal traces in the second trace group extend to the first display substrate and are connected to the plurality of detection pins of the first display substrate in correspondence, and the second pad group is configured to enable an external detection device to provide detection signals to the first display substrate through the second pad group; the first ends of the plurality of signal traces in the third trace group are connected to the plurality of pads in the third pad group in correspondence, the second ends of the plurality of signal traces in the third trace group extend to the first display substrate and the second display substrate and are connected to the plurality of detection pins of the first display substrate and the second display substrate in correspondence, and the third pad group is configured to enable an external detection device to provide selection signals to the first display substrate and the second display substrate through the third pad group; the first ends of the plurality of signal traces in the fourth trace group are connected to the plurality of pads in the fourth pad group in correspondence, the second ends of the plurality of signal traces in the fourth trace group extend to the first display substrate and the second display substrate and are connected to the plurality of detection pins of the first display substrate and the second display substrate in correspondence, and the fourth pad group is configured to enable an external detection device to provide gate drive signals to the first display substrate and the second display substrate through the fourth pad group; and the first ends of the plurality of signal traces in the fifth trace group are connected to the plurality of pads in the fifth pad group in correspondence, the second ends of the plurality of signal traces in the fifth trace group extend to the first display substrate and the second display substrate and are connected to the plurality of detection pins of the first display substrate and the second display substrate in correspondence, and the fifth pad group is configured to enable an external detection device to provide detection switch signals to the first display substrate and the second display substrate through the fifth pad group.

[0017] In an example embodiment, the second trace group is disposed on a side of the first trace group away from the display substrate, the third trace group is disposed on a side of the second trace group away from the display substrate, the fourth trace group is disposed on a side of the third trace group away from the display substrate, and the fifth trace group is disposed between the fifth power supply trace and the sixth power supply trace.

[0018] In an exemplary embodiment, the detection pad area further comprises a plurality of electrostatic protection units, first ends of the plurality of electrostatic protection units are respectively connected to a plurality of pads in the first pad group, the second pad group, the third pad group, the fourth pad group and the fifth pad group, and second ends of the plurality of electrostatic protection units are respectively connected to first ends of a plurality of signal traces in the first trace group, the second trace group, the third trace group, the fourth trace group and the fifth trace group.

[0019] In an exemplary embodiment, the shape of the at least one pad is rectangular, the length L of the pad is 300 μm to 1200 μm, the width of the pad is 80 μm to 1200 μm, and the spacing between adjacent pads is 150 μm to 1500 μm, wherein the length and the spacing are average dimensions in the arrangement direction of the plurality of pads, and the width is an average dimension perpendicular to the arrangement direction of the plurality of pads.

[0020] In an exemplary embodiment, the pad comprises a probe type pad, the length of the probe type pad is 400 μm to 1200 μm, the width of the probe type pad is 400 μm to 1200 μm, and the spacing between adjacent probe type pads is 100 μm to 1500 μm.

[0021] In an exemplary embodiment, the pad comprises a crimp type pad, the length of the crimp type pad is 300 μm to 1000 μm, the width of the crimp type pad is 80 μm to 250 μm, and the spacing between adjacent crimp type pads is 50 μm to 300 μm.

[0022] In another aspect, the exemplary embodiments of the present disclosure also provide a detection method of a display mother board, the display mother board comprising the aforementioned display mother board, the detection method comprising:

[0023] The external detection device is connected to the plurality of pads of the at least one substrate area, and provides a lighting detection signal or an aging program signal to the detection circuit of the plurality of display substrates in the substrate area through the plurality of pads, and simultaneously performs lighting detection or an aging program on the plurality of display substrates in the substrate area.

[0024] In another aspect, the exemplary embodiments of the present disclosure also provide a display substrate configured to be cut from the aforementioned display mother board.

[0025] In another aspect, the exemplary embodiments of the present disclosure also provide a display device comprising the aforementioned display substrate.

[0026] The display motherboard, the display substrate and the display device provided by the present disclosure realize the unit detection lighting mode by arranging the detection pad area and the detection trace area in the substrate area, effectively improve the efficiency of the ET lighting detection and the aging procedure, reduce the process time, and effectively improve the production capacity.

[0027] Other aspects can become apparent from the following detailed description, when considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0029] Figure 1 FIG. 1 is a structural schematic diagram of a display device;

[0030] Figure 2 FIG. 2 is a structural schematic diagram of a display substrate;

[0031] Figure 3 FIG. 3 is a plan structural schematic diagram of a display area in a display substrate;

[0032] Figure 4 FIG. 4 is a sectional structural schematic diagram of a display area in a display substrate;

[0033] Figure 5 FIG. 5 is an equivalent circuit diagram of a pixel driving circuit;

[0034] Figure 6 FIG. 6 is a plan structural schematic diagram of a binding area in a display substrate;

[0035] Figure 7 FIG. 7 is a schematic diagram of a unit detection and aging procedure of a display substrate;

[0036] Figure 8 FIG. 8 is a schematic diagram of arrangement of multiple display substrates on a display motherboard;

[0037] Figure 9 FIG. 9 is a structural schematic diagram of a display motherboard according to an exemplary embodiment of the present disclosure;

[0038] Figure 10 FIG. 10 is a structural schematic diagram of a substrate area according to an exemplary embodiment of the present disclosure;

[0039] Figure 11 FIG. 11 is a structural schematic diagram of a detection pad area according to an exemplary embodiment of the present disclosure;

[0040] Figure 12A structure diagram of a fourth pad group for an exemplary embodiment of the present disclosure;

[0041] Figure 13 A structure diagram of a junction area between a detection pad area and a detection trace area for an embodiment of the present disclosure;

[0042] Figure 14 A structure diagram of a three-layer trace for an exemplary embodiment of the present disclosure;

[0043] Figure 15 A structure diagram of a detection trace area for an exemplary embodiment of the present disclosure;

[0044] Figure 16 Another structure diagram of a detection trace area for an exemplary embodiment of the present disclosure.

[0045] Explanation of reference signs:

[0046] 10 - detection unit; 11 - first insulating layer; 12 - second insulating layer;

[0047] 20 - control line; 21 - first gate metal layer; 22 - second gate metal layer;

[0048] 23 - first source-drain metal layer; 30 - detection line; 40 - electrostatic protection unit;

[0049] 100 - display area; 101 - substrate; 102 - driving circuit layer;

[0050] 103 - light-emitting structure layer; 104 - encapsulation structure layer; 200 - binding area;

[0051] 300 - frame area; 400 - display motherboard; 500 - display substrate;

[0052] 510 - first display substrate; 520 - second display substrate; 530 - detection pin;

[0053] 600 - cutting area; 700 - substrate area; 701 - detection circuit;

[0054] 702 - detection pin; 710 - detection pad area; 720 - detection trace area;

[0055] 800 - pad; 801 - first pad; 802 - second pad;

[0056] 803 - third pad; 804 - fourth pad; 805 - fifth pad;

[0057] 806 - sixth pad; 811 - eleventh pad; 812 - twelfth pad;

[0058] 813 - thirteenth pad; 814 - fourteenth pad; 810 - first pad group;

[0059] 820 - second pad group; 830 - third pad group; 840 - fourth pad group;

[0060] 850 - fifth pad group; 900 - signal line; 901 - first power supply line;

[0061] 902 - second power supply line; 903 - third power supply line; 904 - fourth power supply line;

[0062] 905 - fifth power supply line; 906 - sixth power supply line; 911 - eleventh power supply line;

[0063] 912 - twelfth power supply line; 913 - thirteenth power supply line; 914 - fourteenth power supply line;

[0064] 910 - first line group; 920 - second line group; 930 - third line group;

[0065] 940 - fourth line group; 950 - fifth line group. DETAILED DESCRIPTION

[0066] In order to make the objects, technical solutions and advantages of the present disclosure clearer, below will be a detailed description of the embodiments of the present disclosure in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. One of ordinary skill in the art can easily understand that the means and content can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0067] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0068] The ordinal numbers "first", "second", "third", etc. in the specification are set to avoid confusion of the constituent elements, and are not intended to be limited in terms of quantity.

[0069] In this specification, terms of "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicating the positional or directional relationship of the components are used to describe the positional relationship of the components with reference to the drawings for the convenience of explanation and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0070] In this specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or connected; it can be directly connected, or indirectly connected through an intermediate piece, or communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0071] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0072] In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in this specification, "source electrode" and "drain electrode" can be exchanged with each other.

[0073] In this specification, "connection" includes the case where components are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having a certain electrical action include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0074] In this specification, "parallel" means a state where an angle formed by two straight lines is -10° or more and 10° or less, and thus, an angle of -5° or more and 5° or less is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is 80° or more and 100° or less, and thus, a state where an angle of 85° or more and 95° or less is also included.

[0075] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be sometimes interchanged with "a conductive film". Similarly, "an insulating film" can be sometimes interchanged with "an insulating layer".

[0076] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, or deformation.

[0077] In this specification, "about" means not strict limitation of a boundary and allows a value within a range of process and measurement error.

[0078] Figure 1 FIG. 1 is a schematic view of a structure of a display device. As shown in FIG. 1, a display device 100 includes a display panel 110, a driver circuit 120, and a control circuit 130. Figure 1As shown, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller being connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver being connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver being connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver being connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit being connected to the scan signal line, the light emitting signal line, and the data signal line, respectively. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in such a manner that the scan start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, o can be a natural number.

[0079] Figure 2 is a schematic view of a structure of a display substrate. As shown, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller being connected to the data driver, the scan driver, and the light emitting driver, respectively, the data driver being connected to a plurality of data signal lines (D1 to Dn), respectively, the scan driver being connected to a plurality of scan signal lines (S1 to Sm), respectively, the light emitting driver being connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit being connected to the scan signal line, the light emitting signal line, and the data signal line, respectively. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data driver can sample the gray scale value using the clock signal, and apply data voltages corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row, n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in such a manner that the scan start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal, o can be a natural number. Figure 2As shown, the display substrate can include a display area 100, a binding area 200 located at one side of the display area 100, and a frame area 300 located at the other side of the display area 100. In an exemplary embodiment, the display area 100 can be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display dynamic pictures or still images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display substrate can adopt a flexible substrate, and thus the display substrate can be deformable, for example, rolled, bent, folded, or rolled up.

[0080] In an exemplary embodiment, the frame area 300 can include, in sequence along a direction away from the display area 100, a circuit region, a power line region, a crack dam region, and a cutting region. The circuit region is connected to the display area 100 and can include at least a plurality of cascaded gate driving circuits connected to a plurality of scan lines of the pixel driving circuit in the display area 100. The power line region is connected to the circuit region and can include at least a low-level power line extending along a direction parallel to an edge of the display area and connected to a cathode in the display area 100. The crack dam region is connected to the power line region and can include at least a plurality of cracks provided on a composite insulating layer. The cutting region is connected to the crack dam region and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0081] In an exemplary embodiment, the binding area and the frame area 300 can be provided with a first isolation dam and a second isolation dam, the first isolation dam and the second isolation dam can extend along a direction parallel to an edge of the display area, forming a ring structure surrounding the display area 100, the edge of the display area being an edge of the display area on the side of the binding area or the frame area.

[0082] Figure 3 A schematic diagram of a planar structure of a display area in a display substrate. As shown, the display substrate can include a display area 100, a binding area 200 located at one side of the display area 100, and a frame area 300 located at the other side of the display area 100. In an exemplary embodiment, the display area 100 can be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display dynamic pictures or still images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display substrate can adopt a flexible substrate, and thus the display substrate can be deformable, for example, rolled, bent, folded, or rolled up. Figure 3As shown, the display region can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first color light emitting sub-pixel P1, a second color light emitting sub-pixel P2, and a third color light emitting sub-pixel P3. Each sub-pixel can include a circuit unit and a light emitting unit, and the circuit unit can include at least a pixel driving circuit connected with a scanning signal line, a data signal line, and a light emitting signal line, and configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light emitting signal line, and output a corresponding current to the light emitting device. Each sub-pixel can include a light emitting unit, and the light emitting unit can include at least a light emitting device connected with the pixel driving circuit of the sub-pixel, and configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0083] In an example embodiment, the first sub-pixel P1 can be a green sub-pixel (G) emitting green light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 can be a red sub-pixel (R) emitting red light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0084] In an example embodiment, the pixel unit can include four sub-pixels, and the four sub-pixels can be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure.

[0085] Figure 4 A cross-sectional structure schematic diagram of a display region in a display substrate is shown, which illustrates the structure of three sub-pixels in the display region. As shown, Figure 4 In a plane perpendicular to the display substrate, the display region can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, which is not limited in the present disclosure.

[0086] In an example embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, and the circuit units can include at least a pixel driving circuit, which can include a plurality of transistors and a storage capacitor, Figure 4The example shown uses only one pixel driving circuit, including one transistor and one storage capacitor. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving force of the anode and cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which ensures that external moisture cannot enter the light-emitting structure layer 103.

[0087] In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all light-emitting units may be common layers that are connected together, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.

[0088] Figure 5 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 5 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit is connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, first power supply line VDD, initial signal line INIT and second power supply line VSS).

[0089] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0090] In an example embodiment, a first terminal of the storage capacitor C is connected to the second node N2, and a second terminal of the storage capacitor C is connected to the first power supply line VDD.

[0091] In an example embodiment, a gate electrode of the first transistor T1 is connected to the second scan signal line S2, a first electrode of the first transistor T1 is connected to the initial signal line INIT, and a second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the first initial voltage to the gate electrode of the third transistor T3 to initialize the amount of charge of the gate electrode of the third transistor T3.

[0092] In an example embodiment, a gate electrode of the second transistor T2 is connected to the first scan signal line S1, a first electrode of the second transistor T2 is connected to the second node N2, and a second electrode of the second transistor T2 is connected to the third node N3. When an on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode and the second electrode of the third transistor T3.

[0093] The gate electrode of the third transistor T3 is connected to the second node N2, i.e., the gate electrode of the third transistor T3 is connected to the first terminal of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between its gate electrode and the first electrode.

[0094] The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, a scan transistor, or the like, and when an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit.

[0095] The gate electrode of the fifth transistor T5 is connected to the emission signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When an on-level emission signal is applied to the emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0096] The gate electrode of the seventh transistor T7 is connected with the first scan signal line S1, the first electrode of the seventh transistor T7 is connected with the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected with the first electrode of the light emitting device. When the turn-on level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light emitting device, so as to initialize the amount of charge accumulated in the first electrode of the light emitting device or release the amount of charge accumulated in the first electrode of the light emitting device.

[0097] In an exemplary embodiment, the light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer and a second electrode (cathode) stacked.

[0098] In an exemplary embodiment, the second electrode of the light emitting device EL is connected with the second power supply line VSS, and the signal of the second power supply line VSS is a low level signal continuously provided. The signal of the first power supply line VDD is a high level signal continuously provided.

[0099] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0100] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low temperature poly-silicon thin film transistors, or can be oxide thin film transistors, or can be low temperature poly-silicon thin film transistors and oxide thin film transistors. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-crystalline oxide (LTPO) display substrate, which can take advantage of both, can realize low frequency driving, can reduce power consumption, and can improve display quality.

[0101] In an exemplary embodiment, the first scan signal line S1 is connected with the first electrode of the first transistor T1, the second electrode of the first transistor T1 is connected with the first electrode of the second transistor T2, the second electrode of the second transistor T2 is connected with the first electrode of the third transistor T3, the second electrode of the third transistor T3 is connected with the first electrode of the fourth transistor T4, the second electrode of the fourth transistor T4 is connected with the first electrode of the fifth transistor T5, the second electrode of the fifth transistor T5 is connected with the first electrode of the sixth transistor T6, and the second electrode of the sixth transistor T6 is connected with the first electrode of the seventh transistor T7. Figure 5The seven transistors in the pixel driving circuit shown are all P-type transistors. The working process of the pixel driving circuit can include:

[0102] In the first stage t1, referred to as a reset stage, the signal of the second scan signal line S2 is a low-level signal, and the signals of the first scan signal line S1 and the emission signal line E are high-level signals. The signal of the second scan signal line S2 is a low-level signal, so that the first transistor T1 is turned on, and the signal of the initial signal line INIT is provided to the second node N2, so as to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scan signal line S1 and the emission signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off, and the OLED does not emit light in this stage.

[0103] In the second stage t2, referred to as a data writing stage or a threshold compensation stage, the signal of the first scan signal line S1 is a low-level signal, the signals of the second scan signal line S2 and the emission signal line E are high-level signals, and the data signal line D outputs a data voltage. In this stage, the first end of the storage capacitor C is a low-level signal, so that the third transistor T3 is turned on. The signal of the first scan signal line S1 is a low-level signal, so that the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned on. The second transistor T2 and the fourth transistor T4 are turned on, so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage in the first electrode is emptied, the initialization is completed, and it is ensured that the OLED does not emit light. The signal of the second scan signal line S2 is a high-level signal, so that the first transistor T1 is turned off. The signal of the emission signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.

[0104] In the third stage t3, referred to as an emission stage, the signal of the emission signal line E is a low-level signal, and the signals of the first scan signal line S1 and the second scan signal line S2 are high-level signals. The signal of the emission signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD is provided to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the turned-on sixth transistor T6, so as to drive the OLED to emit light.

[0105] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the gate electrode and the first electrode thereof. Since the voltage of the second node N2 is Vd-|Vth|, the driving current of the third transistor T3 is:

[0106] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0107] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power voltage output by the first power supply line VDD.

[0108] Figure 6 Fig. 1 is a schematic diagram of a planar structure of a binding area in a display substrate. As shown in Fig. 1, the display substrate includes a plurality of pixel driving circuits 10, a plurality of data signal lines D, a plurality of first power supply lines VDD, and a plurality of second power supply lines VSS. Figure 6As shown, in the exemplary embodiment, in the plane parallel to the display substrate, the binding area 200 can be located at one side of the display area 100, along the direction away from the display area 100, the binding area 200 can include the fan-out area B1, the bending area B2, the detection circuit area B3, the driving chip area B4 and the binding pin area B5 arranged in sequence. The fan-out area B1 is connected to the display area 100, and can at least include a first power line VDD, a second power line VSS and a plurality of data transmission lines, the plurality of data transmission lines are configured to connect the data signal lines of the display area 100 in a fan-out wiring manner, the first power line VDD is configured to connect the high-level power line of the display area 100, and the second power line VSS is configured to connect the low-level power line of the frame area. The bending area B2 is connected to the fan-out area B1, and can include a composite insulating layer provided with a groove, the groove is configured to bend the binding area 200 to the back of the display area 100. The detection circuit area B3 is connected to the bending area B2, and can at least be provided with a detection circuit (Cell Test, referred to as CT) for detecting the display substrate, the detection circuit CT can be connected with the corresponding signal lines of the display area, and can realize the light-on detection and aging program of the display substrate. The driving chip area B4 is connected to the detection circuit area B3, and can at least be provided with a driving chip (Integrated Circuit, referred to as IC), the driving chip is connected with the data signal lines of the display area through the data transmission lines in the fan-out area B1, and is configured to generate the driving signal required for driving the sub-pixel, and provide the driving signal to the data signal lines of the display area. For example, the driving signal can be a data signal for driving the luminance of the sub-pixel. The binding pin area B5 is connected to the driving chip area B4, and can at least be provided with a plurality of pins (PIN), the plurality of pins are configured to be bound and connected with the external flexible circuit board (Flexible Printed Circuit, referred to as FPC). In the exemplary embodiment, the binding area can include other circuits and signal lines, such as anti-static circuit, multiplexing circuit (MUX), etc., which are not limited in the present disclosure.

[0109] In an exemplary embodiment, a plurality of detections need to be performed in a display substrate preparation process, one of which is a cell test (ET) light-on, also referred to as ET light-on detection. The ET light-on detection is performed before a display substrate is bonded with a driving chip (IC) and a flexible circuit board (FPC) for inputting a display signal, and a detection signal is input to the display substrate to make the pixels present colors, and a defect detection device is used to check whether each pixel is good or not, so as to confirm whether the display substrate has defects. Since the prepared light emitting device has an interface not stable, etc., another important process of the display substrate is an aging procedure. The aging procedure is a necessary process before a display device is shipped, and the interface not stable can be aged by lighting the light emitting device with a certain size of current for a period of time, so as to reduce the brightness attenuation of the light emitting device and increase the service life of the light emitting device.

[0110] Figure 7 A schematic diagram of a display substrate performing a cell test and an aging procedure. As shown in Figure 7 The display substrate can include a display area 100 and a bonding area 200 located at one side of the display area 100. The display area 100 can include a plurality of sub-pixels constituting a plurality of pixel rows and a plurality of pixel columns, and a plurality of data signal lines D, and the sub-pixels can at least include a pixel driving circuit and a light emitting device. The plurality of data signal lines D can extend along a second direction Y and be sequentially arranged at a set interval along a first direction X, each data signal line D is electrically connected with the pixel driving circuit of the plurality of sub-pixels of one pixel column, and the second direction Y and the first direction X intersect each other. In an exemplary embodiment, the second direction Y can be a pixel column direction, the first direction X can be a pixel row direction, and the second direction Y and the first direction X can be perpendicular to each other.

[0111] In an exemplary embodiment, the binding area 200 may include a detection circuit, which may include at least a plurality of detection units 10, a control line 20, and a detection line 30. The plurality of detection units 10 may be arranged sequentially along a first direction X at predetermined intervals, and the positions of the plurality of detection units 10 may correspond one-to-one with the positions of a plurality of data signal lines D in the display area 100. Each detection unit 10 may include a control terminal, an input terminal, and an output terminal. One end of the control line 20 is connected to a detection pin in the binding pin area, and the other end of the control line 20 may be connected to the control terminal of the plurality of detection units 10. The control line 20 is configured to control the conduction or disconnection of the plurality of detection units 10. One end of the detection line 30 is connected to the detection pin of the bonding pin area, and the other end of the detection line 30 can be connected to the input terminal of multiple detection units 10. The output terminal of multiple detection units 10 can be connected to multiple data signal lines D of the display area 100. The detection unit 10 is configured to output the signal output by the detection line 30 to the data signal line D of the display area 100 under the control of the control line 20, so as to realize the aging process and lamp detection of the display substrate.

[0112] In an exemplary embodiment, the lamp detection and aging process of the detection circuit is as follows: before bonding the driver chip and the flexible circuit board to the display substrate, an external detection device is connected to the detection pin of the bonding area. The external detection device outputs control signals and detection signals to the detection circuit through the detection pin. The control signals control multiple detection units to conduct. The multiple detection units output detection signals to multiple data signal lines of the display area to perform lamp detection and aging procedures on the red sub-pixel, blue sub-pixel and green sub-pixel respectively.

[0113] Currently, the process of manufacturing OLED display devices involves first preparing a display motherboard, then cutting the motherboard into multiple display substrates, each of which can be used to form a single OLED display device. Figure 8 This is a schematic diagram showing the arrangement of multiple display substrates on a display motherboard. For example... Figure 8 As shown, multiple display substrates 500 on the display motherboard 400 are arranged in a regular pattern. Each display substrate 500 may include at least a display area and a bonding area. The cutting area 600 is located on the outer side of each display substrate 500. A cutting channel is provided within the cutting area 600. After all film layers of the display motherboard are prepared, the cutting equipment cuts along the cutting channel to form multiple display substrates 500. Currently, existing OLED display devices use a single-substrate (Cell) lamp-lighting method. After cutting to form multiple display substrates, each display substrate undergoes ET lamp-lighting detection and an aging process. The qualified products are then sent to the next process.

[0114] The display mother board provided by the exemplary embodiments of the present disclosure comprises at least one substrate area, the substrate area comprises at least one detection pad area, at least one detection trace area, and at least two display substrates, the display substrate comprises a display area and a binding area located at one side of the display area, the display area comprises a plurality of sub-pixels, the binding area comprises at least a detection circuit and a plurality of detection pins, the detection circuit is connected with the plurality of detection pins and the plurality of sub-pixels; the detection pad area comprises a plurality of pads, the detection trace area comprises a plurality of signal traces, the first end of the plurality of signal traces is connected with the plurality of pads in correspondence, the second end of the plurality of signal traces extends to the binding area of the display substrate in the substrate area, and is connected with the plurality of detection pins of the display substrate in correspondence, the plurality of pads are configured to enable an external detection device to provide a detection signal to the detection circuit of each display substrate in the substrate area through the plurality of pads, and simultaneously perform a light-on detection or an aging procedure on each display substrate in the substrate area.

[0115] The display mother board provided by the exemplary embodiments of the present disclosure can realize a group unit detection (Group CT) light-on mode, effectively improve the efficiency of ET light-on detection and aging procedure, reduce the process time, and effectively improve the production capacity.

[0116] Figure 9 FIG. 1 is a structural schematic diagram of a display mother board according to an exemplary embodiment of the present disclosure, which shows that the display mother board comprises three substrate areas, and each substrate area comprises two display substrates. Figure 9 As shown in FIG. 1, the display mother board can comprise three substrate areas 700 arranged in sequence along a second direction Y, each substrate area 700 can comprise two display substrates 500 arranged in sequence along a first direction X, and the first direction X and the second direction Y are perpendicular to each other.

[0117] In the exemplary embodiments, at least one substrate area 700 can further comprise at least one detection pad area 710 and at least one detection trace area 720. In the at least one substrate area 700, the detection pad area 710 can be located at the edge of the substrate area 700 in the first direction X, or can be located at the edge of the substrate area 700 in the opposite direction of the first direction X, and the detection trace area 720 can be located at the edge of the substrate area 700 in the second direction Y, or can be located at the edge of the substrate area 700 in the opposite direction of the second direction Y.

[0118] In an example embodiment, the display substrate 500 can include at least a display area and a binding area, the display area can include at least a plurality of sub-pixels arranged in a matrix, the binding area can be arranged on one side of the display area in the second direction Y, the binding area can include at least a detection circuit area and a binding pin area, the detection circuit area can be arranged with a detection circuit CT, the binding pin area can be arranged with a plurality of detection pins, the detection circuit CT can be connected to the plurality of detection pins of the binding pin area and the plurality of sub-pixels in the display area through a plurality of signal lines, and the detection circuit CT is configured to perform light-on detection and aging program on the display substrate.

[0119] In an example embodiment, the detection pad area 710 can include at least a plurality of pads arranged in sequence along the second direction Y, and each pad can have a rectangular shape. The plurality of pads are configured to be connected to an external detection device, so that the external detection device provides a detection signal to each display substrate 500 in the substrate area 700 through the plurality of pads.

[0120] In an example embodiment, the detection trace area 720 can include at least a plurality of signal traces, the first ends of the plurality of signal traces are connected to the plurality of pads of the detection pad area 710 respectively, and the second ends of the plurality of signal traces extend to the binding area of each display substrate 500 in the substrate area 700 and are connected to the plurality of detection pins of each display substrate 500 respectively, so that the external detection device provides a detection signal to the detection circuit CT of each display substrate 500 in the substrate area 700 through the plurality of pads and the plurality of signal traces.

[0121] In an example embodiment, the display motherboard can include m substrate areas 700 arranged in sequence along the second direction Y, each substrate area 700 can include n display substrates 500 arranged in sequence along the first direction X, forming an n(V)*m(H) arrangement, m can be a positive integer greater than or equal to 1, and n can be a positive integer greater than or equal to 2. For example, the display motherboard can be a 2(V)*4(H) arrangement, including 4 substrate areas, and each substrate area includes 2 substrate areas. For another example, the display motherboard can be a 3(V)*4(H) arrangement, including 4 substrate areas, and each substrate area includes 3 substrate areas. For another example, the display motherboard can be a 3(V)*3(H) arrangement, including 3 substrate areas, and each substrate area includes 3 substrate areas. For another example, the display motherboard can be a 2(V)*5(H) or 2(V)*3(H) arrangement, and the present disclosure does not limit it here.

[0122] In some possible example embodiments, each substrate region 700 can include two detection pad regions 710. For a substrate region 700 including one detection pad region 710, the detection pad region 710 can be disposed at an edge of the substrate region 700 in the first direction X, or can be disposed at an edge of the substrate region 700 in the opposite direction of the first direction X. For a substrate region 700 including two detection pad regions 710, the two detection pad regions 710 can be respectively disposed at edges of the substrate region 700 in the first direction X.

[0123] In some possible example embodiments, each substrate region 700 can include two detection trace regions 720. For a substrate region 700 including one detection trace region 720, the detection trace region 720 can be disposed at an edge of the substrate region 700 in the second direction Y, or can be disposed at an edge of the substrate region 700 in the opposite direction of the second direction Y. For a substrate region 700 including two detection trace regions 720, the two detection trace regions 720 can be respectively disposed at edges of the substrate region 700 in the second direction Y.

[0124] Figure 10 FIG. 7 shows a schematic view of a structure of a substrate region according to an example embodiment of the present disclosure, which schematically shows Figure 9 FIG. 7 shows a schematic view of a structure of a substrate region according to an example embodiment of the present disclosure, which schematically shows Figure 10 As shown in FIG. 7, the substrate region 700 can include at least a first display substrate 510, a second display substrate 520, a detection pad region 710, and a detection trace region 720. The first display substrate 510 and the second display substrate 520 can be sequentially disposed along the first direction X. The detection pad region 710 can be located at a side of the second display substrate 520 away from the first display substrate 510 (an edge of the substrate region 700 in the first direction X). The detection trace region 720 can be located at a side of the first display substrate 510 and the second display substrate 520 in the second direction Y.

[0125] In some possible example embodiments, the detection pad region 710 can be located at a side of the first display substrate 510 away from the second display substrate 520, and the detection trace region 720 can be located at a side of the first display substrate 510 and the second display substrate 520 in the opposite direction of the second direction Y.

[0126] In example embodiments, the detection pad region 710 can include at least a plurality of pads 800 sequentially disposed along the second direction Y. The detection trace region 720 can include at least a plurality of signal traces 900. First ends of the plurality of signal traces 900 are respectively connected to the plurality of pads 800 in correspondence. Second ends of the plurality of signal traces 900 extend toward the first display substrate 510 and the second display substrate 520, and are respectively connected to a plurality of detection pins in a bonding region of the first display substrate 510 and a plurality of detection pins in a bonding region of the second display substrate 520 in correspondence.

[0127] In the exemplary embodiments, the signals required for each display substrate ET light-on detection and aging procedure can include at least a detection signal (CT signal), a gate drive signal (GOA signal), a multiplexing signal (MUX signal), and a direct current power supply signal.

[0128] In the exemplary embodiments, the detection signal (CT signal) can include at least any one or more of a detection switch signal SW, a red sub-pixel detection signal DR_L of the first display substrate, a green sub-pixel detection signal DG_L of the first display substrate, a blue sub-pixel detection signal DB_L of the first display substrate, a red sub-pixel detection signal DR_R of the second display substrate, a green sub-pixel detection signal DG_R of the second display substrate, and a blue sub-pixel detection signal DB_R of the second display substrate.

[0129] In the exemplary embodiments, the detection switch signal wire of the first display substrate and the detection switch signal wire of the second display substrate can be connected together, i.e., the first display substrate and the second display substrate can share a detection switch signal wire for transmitting the detection switch signal SW, so as to save the detection signal channel.

[0130] In the exemplary embodiments, the detection signals of the same color sub-pixels in the first display substrate and the second display substrate adopt separate signal wires, so as to control and adjust the voltage values of the detection signals respectively. By providing the detection signals to the same color sub-pixels in the two display substrates respectively through separate signal wires, the present disclosure can control and adjust the light-on brightness and color coordinates of the two display substrates respectively, can avoid the brightness difference and color coordinate difference caused by the different lengths of the signal wires of the two display substrates, and can realize the aging procedure and ET light-on detection of the two display substrates under the same gray scale and brightness.

[0131] In the exemplary embodiments, the gate drive signal (GOA signal) can include at least any one or more of a scan start signal GSTV, a scan first clock signal GCK, a scan second clock signal GCB, an emission start signal ESTV, an emission first clock signal ECK, and an emission second clock signal ECB. In the exemplary embodiments, the plurality of gate drive signal wires of the first display substrate and the plurality of gate drive signal wires of the second display substrate can be connected together one-to-one, i.e., the first display substrate and the second display substrate can share the gate drive signal wires for transmitting the gate drive signals, so as to save the detection signal channel.

[0132] In an example embodiment, the multiplexing signals (MUX signals) can include at least any one or more of a first selection signal MUX1, a second selection signal MUX2, a third selection signal MUX3, a fourth selection signal MUX4, a fifth selection signal MUX5, and a sixth selection signal MUX6. In an example embodiment, the plurality of selection signal traces of the first display substrate and the plurality of selection signal traces of the second display substrate can be connected together one-to-one, i.e., the first display substrate and the second display substrate can share the selection signal traces for transmitting the multiplexing signals, so as to save the detection signal channels.

[0133] In an example embodiment, the direct current power supply signals can include at least any one or more of a high level signal VGH, a low level signal VGL, a first initial signal VINIT1_L of the first display substrate, a second initial signal VINIT2_L of the first display substrate, a first initial signal VINIT1_R of the second display substrate, a second initial signal VINIT2_R of the second display substrate, a first power supply signal VDD_L of the first display substrate, a second power supply signal VSS_L of the first display substrate, a first power supply signal VDD_R of the second display substrate, and a second power supply signal VSS_R of the second display substrate.

[0134] In an example embodiment, the first initial signal VINIT1, the second initial signal VINIT2, the first power supply signal VDD, and the second power supply signal VSS in the first display substrate and the second display substrate adopt separate power supply traces to control and adjust the voltage drop of the power supply signals respectively. By providing the power supply signals to the two display substrates respectively through separate power supply traces, the disclosure can eliminate the resistance difference caused by the different lengths of the power supply traces of the two display substrates through a resistance compensation method, can make the resistances of the power supply traces of the two display substrates as close as possible, so as to ensure that the power supply voltages of the two display substrates are close, and can effectively avoid the situation that one group of voltages is small and the other group of voltages exceeds the output capability of the device, so as to realize that the two display substrates can perform the aging program and the ET point lighting detection under the same power supply voltage.

[0135] In an example embodiment, the high level signal line of the first display substrate and the high level signal line of the second display substrate can be connected together, and the low level signal line of the first display substrate and the low level signal line of the second display substrate can be connected together, i.e., the first display substrate and the second display substrate can share the high level signal line for transmitting the high level signals, and the first display substrate and the second display substrate can share the low level signal line for transmitting the low level signals, so as to save the detection signal channels.

[0136] Figure 11 A structure schematic diagram for detecting the pad area is shown in an example embodiment of the disclosure, which shows Figure 10A planar structure of the detection pad area in the substrate area is shown. As shown Figure 11 The detection pad area can include at least a plurality of pads which can be sequentially arranged along the second direction Y.

[0137] In an exemplary embodiment, the plurality of pads of the detection pad area can include at least a first pad group 810, a second pad group 820, a third pad group 830, a fourth pad group 840, a fifth pad group 850, and a plurality of power pads.

[0138] In an exemplary embodiment, the plurality of pads in the first pad group 810 are configured to provide a red sub-pixel detection signal DR_R, a green sub-pixel detection signal DG_R, and a blue sub-pixel detection signal DB_R to the second display substrate respectively, the plurality of pads in the second pad group 820 are configured to provide a red sub-pixel detection signal DR_L, a green sub-pixel detection signal DG_L, and a blue sub-pixel detection signal DB_L to the first display substrate respectively, the plurality of pads in the third pad group 830 are configured to provide a first selection signal MUX1, a second selection signal MUX2, a third selection signal MUX3, a fourth selection signal MUX4, a fifth selection signal MUX5, and a sixth selection signal MUX6 to the first display substrate and the second display substrate respectively, the plurality of pads in the fourth pad group 840 are configured to provide a scan start signal GSTV, a scan first clock signal GCK, a scan second clock signal GCB, an emission start signal ESTV, an emission first clock signal ECK, and an emission second clock signal ECB to the first display substrate and the second display substrate respectively, and the plurality of pads in the fifth pad group 850 are configured to provide a detection switch signal SW to the first display substrate and the second display substrate respectively.

[0139] In an exemplary embodiment, the plurality of power pads can include at least a first pad 801, a second pad 802, a third pad 803, a fourth pad 804, a fifth pad 805, a sixth pad 806, an eleventh pad 811, a twelfth pad 812, a thirteenth pad 813, and a fourteenth pad 814.

[0140] In the example embodiment, the first pad 801 is configured to provide a first power signal VDD_L to the first display substrate, the second pad 802 is configured to provide a first power signal VDD_R to the second display substrate, the third pad 803 is configured to provide a second power signal VSS_L to the first display substrate, the fourth pad 804 is configured to provide a second power signal VSS_R to the second display substrate, the fifth pad 805 is configured to provide a high-level signal VGH to the first display substrate and the second display substrate respectively, the sixth pad 806 is configured to provide a low-level signal VGL to the first display substrate and the second display substrate respectively, the eleventh pad 811 is configured to provide a first initial signal VINIT1_L to the first display substrate, the twelfth pad 812 is configured to provide a first initial signal VINIT1_R to the second display substrate, the thirteenth pad 813 is configured to provide a second initial signal VINIT2_L to the first display substrate, and the fourteenth pad 814 is configured to provide a second initial signal VINIT2_R to the second display substrate.

[0141] In the example embodiment, the first pad group 810, the second pad group 820, the third pad group 830 and the fourth pad group 840 can be sequentially arranged along the second direction Y, the twelfth pad 812 can be arranged on one side of the fourth pad group 840 in the second direction Y, the eleventh pad 811 can be arranged on one side of the twelfth pad 812 in the second direction Y, the fourteenth pad 814 can be arranged on one side of the eleventh pad 811 in the second direction Y, the sixth pad 806 can be arranged on one side of the fourteenth pad 814 in the second direction Y, the fifth pad group 850 can be arranged on one side of the sixth pad 806 in the second direction Y, the fifth pad 805 can be arranged on one side of the fifth pad group 850 in the second direction Y, the second pad 802 can be arranged on one side of the fifth pad 805 in the second direction Y, the fourth pad 804 can be arranged on one side of the second pad 802 in the second direction Y, the first pad 801 can be arranged on one side of the fourth pad 804 in the second direction Y, the third pad 803 can be arranged on one side of the first pad 801 in the second direction Y, and the thirteenth pad 813 can be arranged on one side of the third pad 803 in the second direction Y.

[0142] In the example embodiment, at least one dummy pad can be arranged between some adjacent pads, which is not limited in the present disclosure.

[0143] Figure 12 FIG. 8 shows a structure diagram of a fourth pad group in an example embodiment of the present disclosure, which illustrates Figure 11 the planar structure of the fourth pad group in the detection pad area. As shown in FIG. 8, the fourth pad group includes a first pad 801, a second pad 802, a third pad 803, a fourth pad 804, a fifth pad 805, a sixth pad 806, an eleventh pad 811, a twelfth pad 812, a thirteenth pad 813 and a fourteenth pad 814. Figure 12As shown, the fourth pad group can at least include: a forty-first pad 841 configured to provide a scan start signal GSTV to the first display substrate and the second display substrate respectively, a forty-second pad 842 configured to provide a light emission start signal ESTV to the first display substrate and the second display substrate respectively, a forty-third pad 843 configured to provide a light emission second clock signal ECB to the first display substrate and the second display substrate respectively, a forty-fourth pad 844 configured to provide a light emission first clock signal ECK to the first display substrate and the second display substrate respectively, a forty-fifth pad 845 configured to provide a scan second clock signal GCB to the first display substrate and the second display substrate respectively, and a forty-sixth pad 846 configured to provide a scan first clock signal GCK to the first display substrate and the second display substrate respectively.

[0144] As shown in FIGS. 11 and Figure 12 As shown, the detection pad area can further include a plurality of electrostatic discharge (ESD) units 40 arranged on the side of the plurality of pads close to the second display substrate, and the ESD units 40 are configured to prevent electrostatic introduction.

[0145] In the exemplary embodiments, the pads providing the CT signal, the GOA signal and the MUX signal need to be provided with the ESD units 40, and thus the plurality of pads in the first pad group 810, the second pad group 820, the third pad group 830, the fourth pad group 840 and the fifth pad group 850 are provided with the ESD units 40, the first ends of the plurality of ESD units 40 are connected to the plurality of pads in the first pad group 810, the second pad group 820, the third pad group 830, the fourth pad group 840 and the fifth pad group 850 respectively, and the second ends of the plurality of ESD units 40 are connected to the first ends of the plurality of signal lines respectively. In the exemplary embodiments, the first pad 801 to the sixth pad 806 and the eleventh pad 811 to the fourteenth pad 814 providing the direct current power supply signal are not provided with the ESD units 40.

[0146] In the exemplary embodiments, the ESD units 40 can adopt a thin film transistor structure, and the plurality of thin film transistor structures are connected to at least one electrostatic discharge line, so that the electrostatic conduction to the electrostatic discharge line is directly released to the ground end through the ground pad.

[0147] In the exemplary embodiments, in the existing display substrate adopting the single-substrate lighting mode, the external detection device connects a plurality of detection pins in the pin area to realize signal input. In order to prevent static electricity from being introduced, a corresponding static protection unit is usually arranged at the corresponding position of the plurality of detection pins. The present inventors have found that, in the display substrate reliability process, the plurality of static protection units have corrosion phenomenon, which causes the risk of connection failure between the detection pins and the signal lines in the binding area of the display substrate. The present disclosure sets the static protection unit in the detection pad area of the display motherboard by adopting the group unit detection (Group CT) lighting mode, so that the plurality of detection pins of the display substrate do not need to be provided with the static protection unit, thereby effectively avoiding the problem of connection failure between the detection pins and the signal lines in the binding area caused by the corrosion of the static protection unit, and effectively improving the yield.

[0148] In the exemplary embodiments, the static protection unit arranged in the detection pad area is cut off after the group unit detection is completed, which is not limited in the present disclosure.

[0149] Figure 13 The structure of the junction area between the detection pad area and the detection trace area in the exemplary embodiments of the present disclosure is shown in the structure diagram. Figure 13 As shown in the exemplary embodiments, since the first pad 801, the third pad 803 and the thirteenth pad 813 are all pads for providing a direct-current power supply signal to the first display substrate, the static protection unit is arranged at the end of the second direction Y of the detection pad area, so that the power supply trace for providing the direct-current power supply signal to the first display substrate is located outside the detection trace area, thereby simplifying the trace layout.

[0150] In the exemplary embodiments, the shape of the pads in the detection pad area can be rectangular, and the shapes and sizes of the plurality of pads can be substantially the same. The length L of the pad can be about 300 μm to 1200 μm, the width M of the pad can be about 80 μm to 1200 μm, and the spacing W between adjacent pads can be about 150 μm to 1500 μm. The length L and the spacing W can be the average size along the arrangement direction of the plurality of pads, and the width M can be the average size perpendicular to the arrangement direction of the plurality of pads.

[0151] In the exemplary embodiments, the pads can include probe-type pads and crimp-type pads. The probe-type pads are configured to be connected with probes, and the crimp-type pads are configured to be connected with FPC gold fingers.

[0152] In an example embodiment, for the probe-type pads, the length L of the probe-type pads can be about 400 pm to 1200 pm, the width M of the probe-type pads can be about 400 pm to 1200 pm, and the spacing W between adjacent probe-type pads can be about 100 pm to 1500 pm. For example, the length L of the probe-type pads can be about 700 pm, the width M of the probe-type pads can be about 700 pm, and the spacing W between adjacent probe-type pads can be about 200 pm.

[0153] In an example embodiment, for the crimp-type pads, the length L of the crimp-type pads can be about 300 pm to 1000 pm, the width M of the crimp-type pads can be about 80 pm to 250 pm, and the spacing W between adjacent crimp-type pads can be about 50 pm to 300 pm. For example, the length L of the crimp-type pads can be about 440 pm, the width M of the crimp-type pads can be about 120 pm, and the spacing W between adjacent crimp-type pads can be about 80 pm.

[0154] In an example embodiment, the plurality of signal traces in the detection trace area can include at least a first trace group 910, a second trace group 920, a third trace group 930, a fourth trace group 940, a fifth trace group 950, and a plurality of power supply traces for transmitting direct current power supply signals.

[0155] In an example embodiment, the first ends of the plurality of signal traces in the first trace group 910 are connected to the plurality of pads in the first pad group 810, the second ends of the plurality of signal traces in the first trace group 910 extend to the back of the second display substrate and are connected to the plurality of detection pins of the second display substrate, and the plurality of signal traces in the first trace group 910 are configured to provide a red sub-pixel detection signal DR_R, a green sub-pixel detection signal DG_R, and a blue sub-pixel detection signal DB_R to the second display substrate, respectively.

[0156] In an example embodiment, the first ends of the plurality of signal traces in the second trace group 920 are connected to the plurality of pads in the second pad group 820, the second ends of the plurality of signal traces in the second trace group 920 extend to the back of the first display substrate and are connected to the plurality of detection pins of the first display substrate, and the plurality of signal traces in the second trace group 920 are configured to provide a red sub-pixel detection signal DR_L, a green sub-pixel detection signal DG_L, and a blue sub-pixel detection signal DB_L to the first display substrate, respectively.

[0157] In an example embodiment, the first ends of the plurality of signal wires in the third wire group 930 are connected to the plurality of pads in the third pad group 830 in correspondence, and the second ends of the plurality of signal wires in the third wire group 930 extend to the first display substrate and the second display substrate and are connected to the plurality of detection pins of the first display substrate and the second display substrate in correspondence respectively, and the plurality of signal wires in the third wire group 930 are configured to provide the first selection signal MUX1, the second selection signal MUX2, the third selection signal MUX3, the fourth selection signal MUX4, the fifth selection signal MUX5 and the sixth selection signal MUX6 to the first display substrate and the second display substrate respectively.

[0158] In an example embodiment, the first ends of the plurality of signal wires in the fourth wire group 940 are connected to the plurality of pads in the fourth pad group 840 in correspondence, and the second ends of the plurality of signal wires in the fourth wire group 940 extend to the first display substrate and the second display substrate and are connected to the plurality of detection pins of the first display substrate and the second display substrate in correspondence respectively, and the plurality of signal wires in the fourth wire group 940 are configured to provide the scan start signal GSTV, the scan first clock signal GCK, the scan second clock signal GCB, the emission start signal ESTV, the emission first clock signal ECK and the emission second clock signal ECB to the first display substrate and the second display substrate respectively.

[0159] In an example embodiment, the first ends of the plurality of signal wires in the fifth wire group 950 are connected to the plurality of pads in the fifth pad group 850 in correspondence, and the second ends of the plurality of signal wires in the fifth wire group 950 extend to the first display substrate and the second display substrate and are connected to the plurality of detection pins of the first display substrate and the second display substrate in correspondence respectively, and the plurality of signal wires in the fifth wire group 950 are configured to provide the detection switch signal SW to the first display substrate and the second display substrate respectively. In an example embodiment, the fifth wire group 950 can include a first control line, a second control line and a third control line.

[0160] In an example embodiment, the plurality of power supply wires can at least include: a first power supply wire 901, a second power supply wire 902, a third power supply wire 903, a fourth power supply wire 904, a fifth power supply wire 905, a sixth power supply wire 906, an eleventh power supply wire 911, a twelfth power supply wire 912, a thirteenth power supply wire 913 and a fourteenth power supply wire 914.

[0161] In the example embodiment, a first end of the first power supply wire 901 is connected with the first pad 801, and a second end of the first power supply wire 901 extends to the back of the first display substrate and is connected with a corresponding detection pin of the first display substrate, and the first power supply wire 901 is configured to provide a first power supply signal VDD_L to the first display substrate. A first end of the second power supply wire 902 is connected with the second pad 802, and a second end of the second power supply wire 902 extends to the back of the second display substrate and is connected with a corresponding detection pin of the second display substrate, and the second power supply wire 902 is configured to provide a first power supply signal VDD_R to the second display substrate. A first end of the third power supply wire 903 is connected with the third pad 803, and a second end of the third power supply wire 903 extends to the back of the first display substrate and is connected with a corresponding detection pin of the first display substrate, and the third power supply wire 903 is configured to provide a second power supply signal VSS_L to the first display substrate. A first end of the fourth power supply wire 904 is connected with the fourth pad 804, and a second end of the fourth power supply wire 904 extends to the back of the second display substrate and is connected with a corresponding detection pin of the second display substrate, and the fourth power supply wire 904 is configured to provide a second power supply signal VSS_R to the second display substrate. A first end of the fifth power supply wire 905 is connected with the fifth pad 805, and a second end of the fifth power supply wire 905 extends to the back of the first display substrate and the second display substrate and is connected with a corresponding detection pin of the first display substrate and the second display substrate, respectively, and the fifth power supply wire 905 is configured to provide a high-level signal VGH to the first display substrate and the second display substrate. A first end of the sixth power supply wire 906 is connected with the sixth pad 806, and a second end of the sixth power supply wire 906 extends to the back of the first display substrate and the second display substrate and is connected with a corresponding detection pin of the first display substrate and the second display substrate, respectively, and the sixth power supply wire 906 is configured to provide a low-level signal VGL to the first display substrate and the second display substrate.

[0162] In the example embodiment, a first end of the eleventh power line 911 is connected with the eleventh pad 811, a second end of the eleventh power line 911 extends to the back of the first display substrate and is connected with the corresponding detection pin of the first display substrate, and the eleventh power line 911 is configured to provide the first initial signal VINIT1_L to the first display substrate. A first end of the twelfth power line 912 is connected with the twelfth pad 812, a second end of the twelfth power line 912 extends to the back of the second display substrate and is connected with the corresponding detection pin of the second display substrate, and the twelfth power line 912 is configured to provide the first initial signal VINIT1_R to the second display substrate. A first end of the thirteenth power line 913 is connected with the thirteenth pad 813, a second end of the thirteenth power line 913 extends to the back of the first display substrate and is connected with the corresponding detection pin of the first display substrate, and the thirteenth power line 913 is configured to provide the second initial signal VINIT2_L to the first display substrate. A first end of the fourteenth power line 914 is connected with the fourteenth pad 814, a second end of the fourteenth power line 914 extends to the back of the second display substrate and is connected with the corresponding detection pin of the second display substrate, and the fourteenth power line 914 is configured to provide the second initial signal VINIT2_R to the second display substrate.

[0163] In the example embodiment, the twelfth power line 912, the eleventh power line 911, the fourteenth power line 914, the sixth power line 906, the fifth power line 905, the second power line 902, the fourth power line 904, the first power line 901, the third power line 903 and the thirteenth power line 913 can be sequentially arranged along the second direction Y, that is, the first power line 901 and the third power line 903 can be arranged on one side of the second power line 902 and the fourth power line 904 in the second direction Y, the fifth power line 905 and the sixth power line 906 can be arranged on the side opposite to the second power line 902 in the second direction Y, the eleventh power line 911, the twelfth power line 911 and the fourteenth power line 914 can be arranged on the side opposite to the second power line 902 in the second direction Y, and the thirteenth power line 913 is arranged on the side of the third power line 903 in the second direction Y.

[0164] In the example embodiment, the first width M1 of the first power line 901 can be greater than the second width M2 of the second power line 902, the third width M3 of the third power line 903 can be greater than the fourth width M4 of the fourth power line 904, and the first width M1, the second width M2, the third width M3 and the fourth width M4 are all the minimum dimensions of the lines extending along the first direction X in the second direction Y.

[0165] In the example embodiment, the first power supply line 901 and the second power supply line 902 are both used to transmit the first power supply signal, and the third power supply line 903 and the fourth power supply line 904 are both used to transmit the second power supply signal. However, the first power supply line 901 and the third power supply line 903 are configured to transmit the power supply signal to the first display substrate, and the second power supply line 902 and the fourth power supply line 904 are configured to transmit the power supply signal to the second display substrate. Therefore, the extension length of the first power supply line 901 is greater than that of the second power supply line 902, the extension length of the third power supply line 903 is greater than that of the fourth power supply line 904, and there is a difference in the length of the power supply lines between the first power supply line 901 and the second power supply line 902 and between the third power supply line 903 and the fourth power supply line 904. The disclosure can achieve resistance compensation by adjusting the width of the power supply line, so that the resistance of the first power supply line 901 and the resistance of the second power supply line 902 are as close as possible, and the resistance of the third power supply line 903 and the resistance of the fourth power supply line 904 are as close as possible. In order to achieve a better aging effect, a higher cross voltage is usually required when performing the aging program. Therefore, the resistance design of the power supply line is very necessary, and the equal resistance design can ensure that the input voltage of each display substrate is close, avoiding the situation that one group of voltage is small and the other group of voltage exceeds the output capacity of the device.

[0166] In the example embodiment, the resistance calculation formula is R=PL / S, where p is the resistivity of the line, which is determined by the material itself, L is the length of the line, and S is the cross-sectional area of the line. When the resistance is close, the cross-sectional area of the two power supply lines can be calculated according to the resistance calculation formula during design, so as to obtain the corresponding power supply line width.

[0167] In the example embodiment, the width of the eleventh power supply line 911 can be greater than the width of the twelfth power supply line 912. Through resistance compensation, the resistance of the eleventh power supply line 911 and the resistance of the twelfth power supply line 912 are as close as possible, and the input voltage of each display substrate is close.

[0168] In the example embodiment, the width of the thirteenth power supply line 913 can be greater than the width of the fourteenth power supply line 914. Through resistance compensation, the resistance of the thirteenth power supply line 913 and the resistance of the fourteenth power supply line 914 are as close as possible, and the input voltage of each display substrate is close.

[0169] In one exemplary embodiment, at least one signal trace in the detection trace area can be a single-layer trace structure, a double-layer trace structure, or a trace structure with three or more layers. For example, multiple power traces providing DC power signals can be a single-layer trace structure, and the power traces can be disposed in the first source-drain metal layer (SD1). Alternatively, multiple power traces providing DC power signals can be a double-layer trace structure or a trace structure with three or more layers. The multiple power traces can be disposed in the first gate metal layer (GATE1) and the second gate metal layer (GATE2), or in the first gate metal layer and the first source-drain metal layer (SD1), or in the second gate metal layer and the first source-drain metal layer, or in the first gate metal layer, the second gate metal layer, and the first source-drain metal layer.

[0170] Figure 14 This is a schematic diagram of a three-layer wiring structure as an exemplary embodiment of this disclosure. Figure 14 As shown, on a plane perpendicular to the display substrate, the display substrate may include at least a substrate 101, a first gate metal layer 21 disposed on the substrate 101, a first insulating layer 11 disposed on the side of the first gate metal layer 21 away from the substrate, a second gate metal layer 22 disposed on the side of the first insulating layer 11 away from the substrate, a second insulating layer 12 disposed on the side of the second gate metal layer 22 away from the substrate, and a first source / drain metal layer 23 disposed on the side of the second insulating layer 12 away from the substrate. The first gate metal layer 21 may include a first sub-line, the second gate metal layer 22 may include a second sub-line, and the first source / drain metal layer 23 may include a third sub-line. The third sub-line is connected to the first sub-line through multiple first vias and to the second sub-line through multiple second vias, so that the first sub-line, the second sub-line, and the third sub-line are interconnected, and the interconnected first sub-line, the second sub-line, and the third sub-line constitute a three-layer wiring structure.

[0171] In an exemplary embodiment, one or more of the first power trace 901, the second power trace 902, the third power trace 903, the fourth power trace 904, the fifth power trace 905, the sixth power trace 906, the eleventh power trace 911, the twelfth power trace 912, the thirteenth power trace 913, and the fourteenth power trace 914 may be arranged in a double-layer or triple-layer or higher wiring structure, which is not limited herein.

[0172] Figure 15 This is a schematic diagram of a detection wiring area as an exemplary embodiment of the present disclosure, showing the wiring structure of the detection wiring area corresponding to the area of ​​the second display substrate. For example... Figure 15As shown, in the exemplary embodiment, the detection trace area 720 can be located on one side of the second display substrate 520 in the second direction Y in the substrate area, and the detection trace area 720 can include a plurality of trace groups and a plurality of power supply traces. The plurality of trace groups can include at least a first trace group 910, a second trace group 920, a third trace group 930, a fourth trace group 940, and a fifth trace group 950, and a plurality of signal traces in the plurality of trace groups extend along the first direction X. The plurality of power supply traces can include at least a first power supply trace 901, a second power supply trace 902, a third power supply trace 903, a fourth power supply trace 904, a fifth power supply trace 905, a sixth power supply trace 906, an eleventh power supply trace 911, a twelfth power supply trace 912, a thirteenth power supply trace 913, and a fourteenth power supply trace 914, which respectively extend along the first direction X.

[0173] In the exemplary embodiment, the first trace group 910, the second trace group 920, the third trace group 930, the fourth trace group 940, and the fifth trace group 950 can be sequentially arranged along a direction away from the second display substrate 520, the second trace group 920 can be arranged on one side of the first trace group 910 in the second direction Y, the third trace group 930 can be arranged on one side of the second trace group 920 in the second direction Y, the fourth trace group 940 can be arranged on one side of the third trace group 930 in the second direction Y, and the fifth trace group 950 can be arranged between the fifth power supply trace 905 and the sixth power supply trace 906.

[0174] In the exemplary embodiment, the twelfth power supply trace 912, the eleventh power supply trace 911, the fourteenth power supply trace 914, the sixth power supply trace 906, the fifth power supply trace 905, the second power supply trace 902, the fourth power supply trace 904, the first power supply trace 901, the third power supply trace 903, and the thirteenth power supply trace 913 can be sequentially arranged along a direction away from the second display substrate 520, and the twelfth power supply trace 912 can be arranged on one side of the fourth trace group 940 away from the second display substrate 520.

[0175] In the exemplary embodiment, the first ends of the second power supply trace 902, the fourth power supply trace 904, the twelfth power supply trace 912, and the fourteenth power supply trace 914 are connected to corresponding pads of the detection pad area, and the second ends respectively extend to corresponding areas of the second display substrate and are connected to the plurality of detection pins 530 of the second display substrate in correspondence.

[0176] In the example embodiment, the fourth power supply line 904 can be connected to the plurality of detection pins 530 of the second display substrate through at least two fourth connection lines 904-1. The at least two fourth connection lines 904-1 can be respectively arranged on two sides of the first direction X of the second display substrate. The first ends of the two fourth connection lines 904-1 are respectively connected to the fourth power supply line 904. The second ends of the two fourth connection lines 904-1 extend towards the direction close to the second display substrate 520 (the opposite direction of the second direction Y) and are respectively connected to the detection pins 530 on the two sides of the first direction X of the second display substrate 520, forming a "U" shaped connection structure.

[0177] In the example embodiment, the second power supply line 902 can be connected to the plurality of detection pins 530 of the second display substrate through at least two second connection lines 902-1. The at least two second connection lines 902-1 can be respectively arranged on the inner sides of the two fourth connection lines 904-1. The first ends of the two second connection lines 902-1 are respectively connected to the second power supply line 902. The second ends of the two second connection lines 902-1 extend towards the direction close to the second display substrate 520 and are respectively connected to the detection pins 530 on the two sides of the first direction X of the second display substrate 520, forming a "U" shaped connection structure. The "U" shaped connection structure formed by the second power supply line 902 and the two second connection lines 902-1 is nested in the "U" shaped connection structure formed by the fourth power supply line 904 and the two fourth connection lines 904-1.

[0178] In the example embodiment, the shapes of the second power supply line 902 and the fourth power supply line 904 can be linear shapes extending along the first direction X. The shapes of the second connection line 902-1 and the fourth connection line 904-1 can be linear shapes extending along the second direction Y. The second power supply line 902 and the second connection line 902-1 can be arranged in the same layer and form an integrated structure connected to each other. The fourth power supply line 904 and the fourth connection line 904-1 can be arranged in the same layer and form an integrated structure connected to each other.

[0179] In the example embodiment, since the second power supply line 902 is located on the side of the fourth power supply line 904 close to the second display substrate 520, the second power supply line 902 needs to adopt a bridging structure to avoid the fourth connection line 904-1. In the example embodiment, the second power supply line 902 can include at least one bridging portion 902A, the second power supply line 902 can be arranged in one conductive layer, and the bridging portion 902A can be arranged in another conductive layer. The two ends of the bridging portion 902A in the first direction X are connected to the second power supply line 902 through vias K respectively, to form a complete second power supply line 902. For example, the bridging portion 902A can be arranged in the second gate metal layer (GATE2), and the second power supply line 902 can be arranged in the first source-drain metal layer (SD1).

[0180] In the example embodiment, the twelfth power supply line 912 can be connected to the detection pin 530 of the second display substrate through at least one twelfth connection line 912-1. The at least one twelfth connection line 912-1 can be arranged in the middle of the second display substrate in the first direction X. The first end of the twelfth connection line 912-1 is connected to the twelfth power supply line 912, and the second end of the twelfth connection line 912-1 extends towards the direction close to the second display substrate 520 and is connected to the detection pin 530 in the middle of the second display substrate 520 in the first direction X.

[0181] In the example embodiment, the fourteenth power supply line 914 can be connected to the detection pin 530 of the second display substrate through at least one fourteenth connection line 914-1. The at least one fourteenth connection line 914-1 can be arranged in the middle of the second display substrate in the first direction X. The first end of the fourteenth connection line 914-1 is connected to the fourteenth power supply line 914, and the second end of the fourteenth connection line 914-1 extends towards the direction close to the second display substrate 520 and is connected to the detection pin 530 in the middle of the second display substrate 520 in the first direction X.

[0182] In the example embodiment, since the twelfth power supply line 912 and the fourteenth power supply line 914 are located on the side of the second power supply line 902 close to the second display substrate 520, the twelfth power supply line 912 and the fourteenth power supply line 914 need to adopt a bridging structure to avoid the second connection line 902-1, the fourth connection line 904-1 and other connection lines. In the example embodiment, the twelfth power supply line 912 and the fourteenth power supply line 914 can each include a plurality of bridging portions, and the complete twelfth power supply line 912 and the complete fourteenth power supply line 914 are formed by the bridging portions.

[0183] In the example embodiment, the first ends of the fifth power supply wires 905 and the sixth power supply wires 906 are connected with the corresponding pads of the detection pad area, and the second ends of the fifth power supply wires 905 and the sixth power supply wires 906 continue to extend to the corresponding areas of the first display substrate after passing through the corresponding areas of the second display substrate. In the corresponding areas of the second display substrate, the fifth power supply wires 905 and the sixth power supply wires 906 are respectively connected with the detection pins 530 of the second display substrate.

[0184] In the example embodiment, the fifth power supply wires 905 can be connected with the detection pins 530 of the second display substrate through at least two fifth connection lines 905-1 respectively, forming a "U" shaped connection structure. The sixth power supply wires 906 can be connected with the detection pins 530 of the second display substrate through at least two sixth connection lines 906-1 respectively, and the "U" shaped connection structure formed by the sixth power supply wires 906 and the two sixth connection lines 906-1 is nested in the "U" shaped connection structure formed by the fifth power supply wires 905 and the two fifth connection lines 905-1.

[0185] In the example embodiment, since the fifth power supply wires 905 and the sixth power supply wires 906 are located on the side of the second power supply wires 902 close to the second display substrate 520, and the sixth power supply wires 906 are located on the side of the fifth power supply wires 905 close to the second display substrate 520, the fifth power supply wires 905 need to adopt a bridging structure to avoid the second connection lines 902-1 and the fourth connection lines 904-1, and the sixth power supply wires 906 need to adopt a bridging structure to avoid the second connection lines 902-1, the fourth connection lines 904-1 and the fifth connection lines 905-1. In the example embodiment, the fifth power supply wires 905 and the sixth power supply wires 906 can each include a plurality of bridging portions to form complete fifth power supply wires 905 and sixth power supply wires 906.

[0186] In the example embodiment, the first ends of the first power supply wires 901, the third power supply wires 903, the eleventh power supply wires 911 and the thirteenth power supply wires 913 are connected with the corresponding pads of the detection pad area, and the second ends continue to extend to the corresponding areas of the first display substrate after passing through the corresponding areas of the second display substrate, without being connected with the detection pins of the second display substrate.

[0187] In the example embodiment, since the eleventh power supply wires 911 are located on the side of the fourteenth power supply wires 914 close to the second display substrate 520, the eleventh power supply wires 911 need to adopt a bridging structure to avoid the corresponding second connection lines 902-1, the fourth connection lines 904-1, the fifth connection lines 905-1, the sixth connection lines 906-1 and the fourteenth connection lines 914-1, and the eleventh power supply wires 911 can include at least a plurality of bridging portions to form complete eleventh power supply wires 911.

[0188] In an example embodiment, the first wiring group 910 can include at least two signal wires extending along the first direction X, the first ends of the two signal wires being connected to the two pads of the first pad group in the detection pad area, and the second ends of the two signal wires being connected to the detection pins 530 of the second display substrate through the connection wires respectively. One of the two signal wires is configured to provide detection signals to the plurality of sub-pixels in the red and blue pixel columns of the second display substrate, and the other of the two signal wires is configured to provide detection signals to the plurality of sub-pixels in the green pixel column of the second display substrate, i.e., the red sub-pixel detection signal DR_R and the blue sub-pixel detection signal DB_R of the second display substrate adopt one of the two signal wires, and the green sub-pixel detection signal DG_R of the second display substrate adopts the other of the two signal wires. In an example embodiment, the two signal wires in the first wiring group 910 adopt a bridging structure to avoid the corresponding connection wires.

[0189] In an example embodiment, the second wiring group 920 can include at least two signal wires extending along the first direction X, the first ends of the two signal wires being connected to the two pads of the second pad group in the detection pad area, and the second ends of the two signal wires extending to the corresponding area of the first display substrate after passing through the corresponding area of the second display substrate, without being connected to the detection pins of the second display substrate.

[0190] In an example embodiment, the third wiring group 930, the fourth wiring group 940, and the fifth wiring group 950 can each include a plurality of signal wires extending along the first direction X, the first ends of the plurality of signal wires being connected to the plurality of pads of the third pad group, the fourth pad group, and the fifth pad group in the detection pad area, and the second ends of the plurality of signal wires extending to the corresponding area of the first display substrate after passing through the corresponding area of the second display substrate. In the corresponding area of the second display substrate, the plurality of signal wires are connected to the detection pins 530 of the second display substrate through the connection wires respectively. In an example embodiment, the plurality of signal wires in the third wiring group 930, the fourth wiring group 940, and the fifth wiring group 950 need to adopt a bridging structure to avoid the corresponding connection wires, which will not be described herein.

[0191] Figure 16 Another structure diagram of a detection wiring area for an example embodiment of the present disclosure is shown in FIG. 9B, which is a structure diagram of a wiring in the detection wiring area and the corresponding area of the first display substrate. As shown in FIG. 9B, the detection wiring area can include a first wiring group 910, a second wiring group 920, a third wiring group 930, a fourth wiring group 940, and a fifth wiring group 950. Figure 16As shown, in the exemplary embodiment, the detection trace area 720 can be located on one side of the substrate area in the second direction Y of the first display substrate 510, and the detection trace area 720 can include a plurality of trace groups and a plurality of power supply traces. The plurality of trace groups can include at least a second trace group 920, a third trace group 930, a fourth trace group 940, and a fifth trace group 950, and a plurality of signal traces in the plurality of trace groups extend along the first direction X. The plurality of power supply traces can include at least a first power supply trace 901, a third power supply trace 903, a fifth power supply trace 905, a sixth power supply trace 906, an eleventh power supply trace 911, and a thirteenth power supply trace 913, which extend along the first direction X.

[0192] In the exemplary embodiment, the second trace group 920, the third trace group 930, the fourth trace group 940, and the fifth trace group 950 can be sequentially arranged along a direction away from the second display substrate 520, and the eleventh power supply trace 911, the sixth power supply trace 906, the fifth power supply trace 905, the first power supply trace 901, the third power supply trace 903, and the thirteenth power supply trace 913 can be sequentially arranged along a direction away from the second display substrate 520. The eleventh power supply trace 911 can be arranged on a side of the fourth trace group 940 away from the second display substrate 520, and the fifth trace group 950 can be arranged between the fifth power supply trace 905 and the sixth power supply trace 906.

[0193] In the exemplary embodiment, the second ends of the first power supply trace 901, the third power supply trace 903, the fifth power supply trace 905, the sixth power supply trace 906, the eleventh power supply trace 911, and the thirteenth power supply trace 913 extend to the corresponding areas of the first display substrate after passing through the corresponding areas of the second display substrate, and are connected to the plurality of detection pins 530 of the first display substrate correspondingly.

[0194] In the exemplary embodiment, the third power supply trace 903 can be connected to the plurality of detection pins 530 of the first display substrate correspondingly through at least two third connection lines 903-1. The at least two third connection lines 903-1 can be arranged on both sides of the first direction X of the first display substrate respectively, the first ends of the two third connection lines 903-1 are connected to the third power supply trace 903 respectively, and the second ends of the two third connection lines 903-1 extend towards the direction close to the first display substrate 510 (the opposite direction of the second direction Y) and are connected to the detection pins 530 on both sides of the first direction X of the first display substrate 510 respectively, forming a "U" shaped connection structure.

[0195] In the example embodiment, the first power supply line 901 can be connected to the plurality of detection pins 530 of the first display substrate through at least two first connecting lines 901-1. The at least two first connecting lines 901-1 can be respectively arranged on the inner sides of the two third connecting lines 903-1. The first ends of the two first connecting lines 901-1 are respectively connected to the first power supply line 901. The second ends of the two first connecting lines 901-1 extend towards the first display substrate 510, and are respectively connected to the detection pins 530 on both sides of the first display substrate 510 in the first direction X, forming a "U" shaped connection structure. The "U" shaped connection structure formed by the first power supply line 901 and the two first connecting lines 901-1 is nested in the "U" shaped connection structure formed by the third power supply line 903 and the two third connecting lines 903-1.

[0196] In the example embodiment, the first power supply line 901 and the third power supply line 903 can have a linear shape extending along the first direction X. The first connecting line 901-1 and the third connecting line 903-1 can have a linear shape extending along the second direction Y. The first power supply line 901 and the first connecting line 901-1 can be arranged in the same layer and form an integrated structure. The third power supply line 903 and the third connecting line 903-1 can be arranged in the same layer and form an integrated structure.

[0197] In the example embodiment, the first power supply line 901 is arranged on the side of the third power supply line 903 close to the first display substrate 510. Therefore, the first power supply line 901 needs to adopt a bridging structure to avoid the third connecting line 903-1. In the example embodiment, the first power supply line 901 can include at least one bridging portion. The first power supply line 901 can be arranged in one conductive layer, and the bridging portion can be arranged in another conductive layer. The two ends of the bridging portion in the first direction X are respectively connected to the first power supply line 901 through vias K, forming a complete first power supply line 901. For example, the bridging portion can be arranged in the second gate metal layer (GATE2), and the first power supply line 901 can be arranged in the first source / drain metal layer (SD1).

[0198] In the example embodiment, the eleventh power supply line 911 can be connected to the detection pin 530 of the first display substrate through at least one eleventh connecting line 911-1. The at least one eleventh connecting line 911-1 can be arranged in the middle of the first display substrate in the first direction X. The first end of the eleventh connecting line 911-1 is connected to the eleventh power supply line 911. The second end of the eleventh connecting line 911-1 extends towards the first display substrate 510 and is connected to the detection pin 530 in the middle of the first display substrate 510 in the first direction X.

[0199] In the example embodiment, the eleventh power supply line 911 needs to adopt a bridging structure to avoid the first connection line 901-1, the third connection line 903-1 and other connection lines, because the eleventh power supply line 911 is located on the side of the first power supply line 901 close to the first display substrate 510.

[0200] In the example embodiment, the thirteenth power supply line 913 can be connected to the detection pin 530 of the first display substrate through at least one thirteenth connection line 913-1. The at least one thirteenth connection line 913-1 can be arranged in the middle of the first direction X of the first display substrate, the first end of the thirteenth connection line 913-1 is connected to the thirteenth power supply line 913, and the second end of the thirteenth connection line 913-1 extends towards the direction close to the first display substrate 510 and is connected to the detection pin 530 in the middle of the first direction X of the first display substrate 510.

[0201] In the example embodiment, the thirteenth connection line 913-1 adopts a bridging structure to avoid the first power supply line 901 and the third power supply line 903, because the thirteenth power supply line 913 is located on the side of the third power supply line 903 away from the first display substrate 510.

[0202] In the example embodiment, the first end of the fifth power supply line 905 and the sixth power supply line 906 is connected to the corresponding pad of the detection pad area, and the second end of the fifth power supply line 905 and the sixth power supply line 906 extends to the corresponding area of the first display substrate after passing through the corresponding area of the second display substrate. In the corresponding area of the second display substrate, the fifth power supply line 905 and the sixth power supply line 906 are respectively connected to the detection pin 530 of the second display substrate, and in the corresponding area of the first display substrate, the fifth power supply line 905 and the sixth power supply line 906 are respectively connected to the detection pin 530 of the first display substrate.

[0203] In the example embodiment, the fifth power supply line 905 can be connected to the detection pin 530 of the first display substrate through at least two fifth connection lines 905-1, forming a "U" shaped connection structure. The sixth power supply line 906 can be connected to the detection pin 530 of the first display substrate through at least two sixth connection lines 906-1, and the "U" shaped connection structure formed by the sixth power supply line 906 and the two sixth connection lines 906-1 is nested in the "U" shaped connection structure formed by the fifth power supply line 905 and the two fifth connection lines 905-1.

[0204] In the example embodiment, since the fifth power supply wire 905 and the sixth power supply wire 906 are located on the side of the first power supply wire 901 close to the first display substrate 510, and the sixth power supply wire 906 is located on the side of the fifth power supply wire 905 close to the first display substrate 510, the fifth power supply wire 905 needs to adopt a bridging structure to avoid the first connection line 901-1 and the third connection line 903-1, and the sixth power supply wire 906 needs to adopt a bridging structure to avoid the first connection line 901-1, the third connection line 903-1 and the fifth connection line 905-1.

[0205] In the example embodiment, the second wire group 920 can include at least two signal wires extending along the first direction X, the first ends of the two signal wires are connected to the 2 pads of the second pad group in the detection pad area, and the second ends of the two signal wires extend to the corresponding area of the first display substrate through the corresponding area of the second display substrate and are connected to the detection pins of the first display substrate, one signal wire is configured to provide a detection signal to the plurality of sub-pixels in the red and blue pixel column of the first display substrate, and the other signal wire is configured to provide a detection signal to the plurality of sub-pixels in the green pixel column of the first display substrate, that is, the red sub-pixel detection signal DR_R and the blue sub-pixel detection signal DB_R in the first display substrate adopt one signal wire, and the green sub-pixel detection signal DG_R in the first display substrate adopts another signal wire. In the example embodiment, the two signal wires in the second wire group 920 adopt a bridging structure to avoid the corresponding connection line.

[0206] In the example embodiment, the third wire group 930, the fourth wire group 940 and the fifth wire group 950 can each include a plurality of signal wires extending along the first direction X, the first ends of the plurality of signal wires are connected to a plurality of pads of the third pad group, the fourth pad group and the fifth pad group in the detection pad area, and the second ends of the plurality of signal wires continue to extend to the corresponding area of the first display substrate after extending through the corresponding area of the second display substrate. In the corresponding area of the second display substrate, the plurality of signal wires are connected to the detection pins 530 of the second display substrate through the connection lines, respectively, and in the corresponding area of the first display substrate, the plurality of signal wires are connected to the detection pins 530 of the first display substrate through the connection lines, respectively. In the example embodiment, the plurality of signal wires in the third wire group 930, the fourth wire group 940 and the fifth wire group 950 need to adopt a bridging structure to avoid the corresponding connection line, which will not be described here.

[0207] In the example embodiment, the display motherboard detection method of the Group CT mode for the light-on detection or the aging program can include:

[0208] The external detection device is connected with a plurality of pads of the substrate area, and provides a lighting detection signal or an aging program signal to a detection circuit of a plurality of display substrates in the substrate area through the plurality of pads, and performs lighting detection or an aging program on the plurality of display substrates in the substrate area.

[0209] In the example embodiment, the lighting detection signal or the aging program signal can at least include a detection signal, a gate driving signal, a multiplexing signal and a direct current power supply signal.

[0210] As can be seen from the structure and detection method of the display mother board in the example embodiment of the present disclosure, the present disclosure can realize a group CT lighting mode by arranging a detection pad area and a detection trace area in the substrate area, effectively improving the efficiency of the ET lighting detection and the aging program, reducing the process time, and effectively improving the production capacity.

[0211] In the example embodiment, the example embodiment of the present disclosure further provides a display substrate formed by cutting the aforementioned display mother board.

[0212] The example embodiment of the present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

[0213] Those skilled in the art should understand that the technical solutions of the present disclosure can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be covered in the scope of the claims of the present disclosure.

Claims

1. A display motherboard, characterized in that, The system includes multiple substrate regions arranged sequentially along a second direction. Each substrate region includes at least one detection pad area, at least one detection trace area, and at least two display substrates. Each display substrate includes a display area and a bonding area located on one side of the display area. The display area includes multiple sub-pixels. The bonding area includes at least a detection circuit and multiple detection pins. The detection circuit is connected to the multiple detection pins and the multiple sub-pixels. The detection pad area includes multiple pads, and the detection trace area includes multiple signal traces. The first ends of the multiple signal traces are connected to the multiple pads, and the second ends of the multiple signal traces extend to the bonding area of ​​the display substrate in the substrate region and are connected to the multiple detection pins of the display substrate. The multiple pads are configured to allow an external detection device to provide detection signals to the detection circuit of each display substrate in the substrate region through the multiple pads, and to simultaneously perform lamp detection or aging procedures on each display substrate in the substrate region. The substrate region includes at least a first display substrate and a second display substrate arranged sequentially along a first direction. The detection trace area is located on one side of the first display substrate and the second display substrate in a second direction. The detection pad area is located on the side of the second display substrate away from the first display substrate. Alternatively, the detection pad area is located on the side of the first display substrate away from the second display substrate. The first direction intersects the second direction. The detection signals of sub-pixels of the same color in the first display substrate and the second display substrate use separate signal traces to control and adjust the voltage value of the detection signal respectively.

2. The display motherboard according to claim 1, characterized in that, The detection pad area includes at least a first pad, a second pad, a third pad, and a fourth pad; the detection trace area includes at least a first power trace, a second power trace, a third power trace, and a fourth power trace. The first end of the first power trace is connected to the first pad, and the second end of the first power trace extends to the first display substrate and is connected to the detection pin of the first display substrate. The first pad is configured to allow an external detection device to provide a first power signal to the first display substrate through the first pad. The first end of the second power trace is connected to the second pad, and the second end of the second power trace extends to the second display substrate and is connected to the detection pin of the second display substrate. The second pad is configured to allow an external detection device to provide a first power signal to the second display substrate through the second pad. The first end of the third power trace is connected to the third pad, and the second end of the third power trace extends to the first display substrate and is connected to the detection pin of the first display substrate. The third pad is configured to allow an external detection device to provide a second power signal to the first display substrate through the third pad. The first end of the fourth power trace is connected to the fourth pad, and the second end of the fourth power trace extends to the second display substrate and is connected to the detection pin of the second display substrate. The fourth pad is configured to allow an external detection device to provide a second power signal to the second display substrate through the fourth pad.

3. The display motherboard according to claim 2, characterized in that, At least one signal trace in the detection trace area is a single-layer trace structure, or a double-layer trace structure, or a trace structure with three or more layers.

4. The display motherboard according to claim 2, characterized in that, The first power trace and the third power trace are disposed on the side of the second power trace and the fourth power trace away from the display substrate.

5. The display motherboard according to claim 2, characterized in that, The width of the first power trace is greater than the width of the second power trace, and the width of the third power trace is greater than the width of the fourth power trace. The widths are the minimum dimensions of the first power trace, the second power trace, the third power trace, and the fourth power trace in the second direction, respectively.

6. The display motherboard according to claim 2, characterized in that, The detection pad area also includes a fifth pad and a sixth pad, and the detection trace area also includes a fifth power trace and a sixth power trace; The first end of the fifth power trace is connected to the fifth pad, and the second end of the fifth power trace extends to the first display substrate and the second display substrate and is connected to the detection pins of the first display substrate and the second display substrate respectively. The fifth pad is configured to enable an external detection device to provide a high-level signal to the first display substrate and the second display substrate through the fifth pad. The first end of the sixth power trace is connected to the sixth pad, and the second end of the sixth power trace extends to the first display substrate and the second display substrate and is connected to the detection pins of the first display substrate and the second display substrate, respectively. The sixth pad is configured to allow an external detection device to provide a low-level signal to the first display substrate and the second display substrate through the sixth pad.

7. The display motherboard according to claim 6, characterized in that, The fifth power trace and the sixth power trace are located on the side of the second power trace closest to the display substrate.

8. The display motherboard according to claim 2, characterized in that, The detection pad area also includes the eleventh pad, the twelfth pad, the thirteenth pad, and the fourteenth pad; the detection trace area also includes the eleventh power trace, the twelfth power trace, the thirteenth power trace, and the fourteenth power trace. The first end of the eleventh power trace is connected to the eleventh pad, and the second end of the eleventh power trace extends to the first display substrate and is connected to the detection pin of the first display substrate. The eleventh pad is configured to allow an external detection device to provide a first initial signal to the first display substrate through the eleventh pad. The first end of the twelfth power trace is connected to the twelfth pad, and the second end of the twelfth power trace extends to the second display substrate and is connected to the detection pin of the second display substrate. The twelfth pad is configured to allow an external detection device to provide a first initial signal to the second display substrate through the twelfth pad. The first end of the thirteenth power trace is connected to the thirteenth pad, and the second end of the thirteenth power trace extends to the first display substrate and is connected to the detection pin of the first display substrate. The thirteenth pad is configured to allow an external detection device to provide a second initial signal to the first display substrate through the thirteenth pad. The first end of the fourteenth power trace is connected to the fourteenth pad, and the second end of the fourteenth power trace extends to the second display substrate and is connected to the detection pin of the second display substrate. The fourteenth pad is configured to allow an external detection device to provide a second initial signal to the second display substrate through the fourteenth pad.

9. The display motherboard according to claim 8, characterized in that, The eleventh, twelfth, and fourteenth power traces are located on the side of the second power trace closer to the display substrate, and the thirteenth power trace is located on the side of the third power trace farther from the display substrate.

10. The display motherboard according to claim 8, characterized in that, The width of the eleventh power trace is greater than the width of the twelfth power trace, and the width of the thirteenth power trace is greater than the width of the fourteenth power trace. The widths are the minimum dimensions of the eleventh, twelfth, thirteenth, and fourteenth power traces in the second direction, respectively.

11. The display motherboard according to claim 2, characterized in that, The detection pad area further includes a first pad group, a second pad group, a third pad group, a fourth pad group, and a fifth pad group; the detection trace area further includes a first trace group, a second trace group, a third trace group, a fourth trace group, and a fifth trace group. The first ends of multiple signal traces in the first trace group are connected to multiple pads in the first pad group, and the second ends of multiple signal traces in the first trace group extend to the second display substrate and are connected to multiple detection pins of the second display substrate. The first pad group is configured to enable an external detection device to provide detection signals to the second display substrate through the first pad group. The first ends of multiple signal traces in the second trace group are connected to multiple pads in the second pad group, and the second ends of multiple signal traces in the second trace group extend to the first display substrate and are connected to multiple detection pins of the first display substrate. The second pad group is configured to enable an external detection device to provide detection signals to the first display substrate through the second pad group. The first ends of the multiple signal traces in the third trace group are connected to the multiple pads in the third pad group, and the second ends of the multiple signal traces in the third trace group extend to the first display substrate and the second display substrate, respectively, and are connected to the multiple detection pins of the first display substrate and the second display substrate. The third pad group is configured to enable an external detection device to provide a selection signal to the first display substrate and the second display substrate through the third pad group. The first ends of the multiple signal traces in the fourth trace group are connected to the multiple pads in the fourth pad group, and the second ends of the multiple signal traces in the fourth trace group extend to the first display substrate and the second display substrate, respectively, and are connected to the multiple detection pins of the first display substrate and the second display substrate. The fourth pad group is configured to enable an external detection device to provide gate drive signals to the first display substrate and the second display substrate through the fourth pad group. The first ends of multiple signal traces in the fifth trace group are connected to multiple pads in the fifth pad group, and the second ends of multiple signal traces in the fifth trace group extend to the first display substrate and the second display substrate, respectively, and are connected to multiple detection pins of the first display substrate and the second display substrate. The fifth pad group is configured to enable an external detection device to provide detection switch signals to the first display substrate and the second display substrate through the fifth pad group.

12. The display motherboard according to claim 11, characterized in that, The second trace group is disposed on the side of the first trace group away from the display substrate, the third trace group is disposed on the side of the second trace group away from the display substrate, the fourth trace group is disposed on the side of the third trace group away from the display substrate, and the fifth trace group is disposed between the fifth power trace and the sixth power trace.

13. The display motherboard according to claim 11, characterized in that, The detection pad area also includes multiple electrostatic discharge (ESD) protection units. The first end of each ESD protection unit is connected to multiple pads in the first pad group, the second pad group, the third pad group, the fourth pad group, and the fifth pad group, respectively. The second end of each ESD protection unit is connected to the first end of multiple signal traces in the first trace group, the second trace group, the third trace group, the fourth trace group, and the fifth trace group, respectively.

14. The display motherboard according to any one of claims 1 to 13, characterized in that, At least one pad is rectangular in shape, the length L of the pad is 300 μm to 1200 μm, the width of the pad is 80 μm to 1200 μm, the spacing between adjacent pads is 150 μm to 1500 μm, the length and spacing are average dimensions in the multiple pad arrangement directions, and the width is the average dimension in the multiple pad arrangement directions perpendicular to the multiple pad arrangement directions.

15. The display motherboard according to claim 14, characterized in that, The pads include probe pads, the length of which is 400μm to 1200μm, the width of which is 400μm to 1200μm, and the spacing between adjacent probe pads is 100μm to 1500μm.

16. The display motherboard according to claim 14, characterized in that, The pads include press-fit pads, the length of which is 300μm to 1000μm, the width of which is 80μm to 250μm, and the spacing between adjacent press-fit pads is 50μm to 300μm.

17. A method for detecting a display motherboard, characterized in that, The display motherboard includes the display motherboard as described in any one of claims 1 to 16, and the detection method includes: An external testing device is connected to multiple pads in at least one substrate area, and provides lamp detection signals or aging program signals to the detection circuits of multiple display substrates in the substrate area through the multiple pads, while performing lamp detection or aging programs on the multiple display substrates in the substrate area.

18. A display substrate, characterized in that, The display substrate is configured to be formed by cutting a display motherboard as described in any one of claims 1 to 16.

19. A display device, characterized in that, Includes the display substrate as described in claim 18.

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