A PXIe data acquisition module with multi-channel isolation supporting multiple acquisition functions

Abstract

The present invention is a PXIe data acquisition module with multi-channel isolation that supports multiple acquisition functions. The present invention relates to the field of PXIe data acquisition technology. A plurality of analog signal channels with inter-channel isolation are used to connect ports to be measured. Signal conditioning and analog-to-digital conversion are performed on the port signals to generate analog signals. The output analog signals are processed and stored using an FPGA, and the processed signals are output to a data transmission interface via a PCIe interface. The FPGA performs corresponding on-chip digital signal processing and stores the signals in a DDR. The main controller can read the data stored in the DDR via the PXIe bus. The main controller configures the different measurement functions of each channel by accessing register configurations in the FPGA. The PXIe interface used in the present invention can achieve a data transmission rate of up to 16 Gbps via the PCIe 2.0x4 bus.

Description

Technical Field

[0001] The present invention relates to the technical field of PXIe data acquisition, in particular to a PXIe data acquisition module with isolation between multiple channels supporting multiple acquisition functions. Background Art

[0002] Existing PXIe multi-channel data acquisition modules, both domestically and internationally, not only fail to support simultaneous data acquisition of multiple analog channels with different functions, but also fail to balance parameters such as sampling accuracy, input bandwidth, and sampling rate. For example, NI's PXIe-4481 analog input module supports six analog channels, has a 24-bit ADC resolution, a ±10V voltage input range, and a sampling rate of no more than 20MSa / s. ADLINK's PXIe-9852 high-speed PXIe digitizer supports two analog channels, has a 14-bit ADC resolution, a ±10V voltage input range, a 3dB bandwidth of 90MHz, and lacks channel-to-channel isolation.

[0003] However, with the increasing demand for electronic measurement and testing products, existing data acquisition modules cannot achieve measurement capabilities for different signal types by simply replacing the analog signal conditioning circuit. This fails to meet the needs of companies for reducing the difficulty of modular product development and design, and users' needs for diverse signal acquisition scenarios. At the same time, isolation between multiple acquisition channels ensures the safe use of measurement instruments in complex scenarios and improves product stability.

[0004] Data acquisition modules based on the PXIe bus benefit from the PCIe transmission protocol, enabling higher data acquisition rates. High-speed signal testing and measurement require data acquisition with higher sampling rates and bandwidth. Furthermore, the digital data transmission and storage units must support real-time processing, transmission, and storage of high-speed waveform data, delivering multi-channel waveform data to the host controller.

[0005] In summary, existing multi-channel isolated PXIe data acquisition cannot meet the bandwidth, sampling speed and sampling accuracy requirements when measuring high-speed signals, and cannot flexibly achieve simultaneous measurement of multiple types of signals in complex systems. Summary of the Invention

[0006] To address the above-mentioned shortcomings or improvement needs of the existing technology and the design deficiencies of the existing multi-channel isolated PXIe data acquisition modules, a multi-channel isolated PXIe data acquisition module supporting multiple signal acquisition functions is proposed, featuring wide input range, high sampling rate, and high data transmission rate. The present invention proposes a multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions.

[0007] The present invention provides a PXIe data acquisition module with multi-channel isolation that supports multiple acquisition functions. The present invention provides the following technical solutions:

[0008] A PXIe data acquisition module with multi-channel isolation that supports multiple acquisition functions, comprising: multiple isolated analog signal channels, a data buffer, a programmable logic FPGA, a clock system, a PCIe interface, and a data transmission interface;

[0009] The multiple inter-channel isolated analog signal channels output isolated signals to a programmable logic FPGA, the programmable logic FPGA is respectively connected to a data buffer area and a clock system, the programmable logic FPGA is connected to a PCIe interface, and the PCIe interface is connected to a data transmission interface;

[0010] The analog signal channels isolated between the multiple channels include a signal conditioning circuit, an analog-to-digital conversion circuit and a signal isolation unit. The signal isolation unit adopts an independent board-to-board connector. The signal conditioning circuit of each channel is connected to the analog-to-digital conversion circuit through an independent board-to-board connector. The board-to-board connector is responsible for providing isolated power supply and transmission switch control signals for the signal conditioning circuit.

[0011] Preferably, the programmable logic FPGA includes an acquisition control unit, a digital signal processing unit, a storage control unit and a PCIe module;

[0012] The acquisition control unit controls the acquisition of analog signals from multiple isolated analog signal channels and transmits the signals to the digital signal processing unit and the storage control unit. The digital signal processing unit and the storage control unit exchange data, and the signal output ends of the digital signal processing unit and the storage control unit are both connected to the PCIe module.

[0013] Preferably, the data buffer area adopts a high-speed cache unit, and the DDR3L chips are grouped to store waveform data of different channels. The storage depth of each data acquisition channel supports storing waveform data of a certain time length at a certain sampling rate;

[0014] The programmable logic FPGA receives a data read command from the main controller through the PCIe interface, and sends the stored data in the data buffer area to the main controller through the PCIe link through the PCIe interface.

[0015] Preferably, the analog-to-digital conversion circuit configures the sampling rate and resolution working parameters by the SPI configuration signal sent by the programmable logic FPGA through the signal isolation unit, and sends the sampling data signal and data receiving clock to the programmable logic FPGA through the signal isolation unit. Through the synchronization control signal, the programmable logic can control the synchronous data acquisition of multiple channels.

[0016] Preferably, the clamp-type sensor, thermocouple and acceleration sensor on the current clamp are used to respectively realize the measurement of different functions, including voltage, current, temperature, strain force and acceleration measurement.

[0017] Preferably, the isolation degree of each part is 500V; the analog-to-digital conversion of the analog signals of N channels is achieved through N high-speed analog-to-digital conversion circuits that support a maximum sampling rate of 200MSa / s.

[0018] Preferably, the clock system consists of two phase-locked loops. One phase-locked loop provides the working clock for the programmable logic FPGA and multiple groups of DDR3L memory, and the other phase-locked loop provides multiple homologous sampling clocks for the analog-to-digital conversion circuits of multiple channels. At the same time, the phase-locked loop has a clock source switching function. According to the working requirements of the data acquisition module, it can be configured to use the crystal oscillator clock on the module or the high-precision differential clock from the PXIe backplane.

[0019] A PXIe data acquisition method supporting multiple acquisition functions and isolating multiple channels, the method comprising the following steps:

[0020] Connect the ports to be tested through multiple isolated analog signal channels, and convert the port signals into analog signals through signal conditioning and analog-to-digital conversion operations respectively;

[0021] The output analog signal is processed and stored through the programmable logic FPGA, and the processed signal is output to the data transmission interface through the PCIe interface;

[0022] The corresponding on-chip digital signal processing is performed in the programmable logic FPGA and stored in the DDR. The main controller can read the data stored in the DDR through the PXIe bus; the main controller configures the different measurement functions of each channel by accessing the register configuration in the FPGA.

[0023] A computer-readable storage medium stores a computer program, which is executed by a processor to implement a PXIe data acquisition method with isolation between multiple channels and supporting multiple acquisition functions.

[0024] A computer device includes a memory and a processor. The memory stores a computer program. When the processor runs the computer program stored in the memory, the processor executes a PXIe data acquisition method with isolation between multiple channels that supports multiple acquisition functions.

[0025] The present invention has the following beneficial effects:

[0026] The present invention combines low-speed and high-speed isolation devices with modular isolated power supplies to achieve mutual isolation between multiple analog channels and digital departments. The 500V inter-channel isolation ensures that the input analog signal of each analog channel will not affect the circuit and working status of other channels and digital systems in the event of an abnormality.

[0027] Analog module cards with different signal acquisition functions can be connected to the digital control and data transmission module through board-to-board connectors. The acquisition control of different channels can be realized through FPGA, and different measurement functions of each channel can be realized by relying on reconfigurable configuration. This method does not require replacing the entire module and is much less expensive than designing different PXIe measurement modules.

[0028] This invention uses an FPGA as the control unit for data acquisition and data transmission, leveraging abundant I / O and logic resources to implement multi-channel data measurement control and data transmission. Furthermore, the FPGA enables efficient digital signal processing and waveform measurement, significantly faster than the processor in the main control computer.

[0029] The present invention addresses the problem of slow data transmission rate of PXI measurement boards. The PXIe interface adopted by the present invention can achieve a data transmission rate of up to 16Gbps through the PCIe 2.0 x4 bus. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 This is the overall block diagram of the data acquisition module;

[0032] Figure 2 This is the basic structure diagram of a single analog channel. DETAILED DESCRIPTION

[0033] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0036] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] The present invention is described in detail below with reference to specific embodiments. Specific embodiment one:

[0039] according to Figures 1 to 2 As shown, the specific optimization technical solution adopted by the present invention to solve the above technical problems is: the present invention relates to a PXIe data acquisition module with isolation between multiple channels that supports multiple acquisition functions.

[0040] A PXIe data acquisition module with multi-channel isolation that supports multiple acquisition functions, comprising: multiple isolated analog signal channels, a data buffer, a programmable logic FPGA, a clock system, a PCIe interface, and a data transmission interface;

[0041] The multiple inter-channel isolated analog signal channels output isolated signals to a programmable logic FPGA, the programmable logic FPGA is respectively connected to a data buffer area and a clock system, the programmable logic FPGA is connected to a PCIe interface, and the PCIe interface is connected to a data transmission interface;

[0042] The analog signal channels isolated between the multiple channels include a signal conditioning circuit, an analog-to-digital conversion circuit and a signal isolation unit. The signal isolation unit adopts an independent board-to-board connector. The signal conditioning circuit of each channel is connected to the analog-to-digital conversion circuit through an independent board-to-board connector. The board-to-board connector is responsible for providing isolated power supply and transmission switch control signals for the signal conditioning circuit. Specific embodiment two:

[0044] The difference between the second embodiment of the present application and the first embodiment is that:

[0045] The programmable logic FPGA includes an acquisition control unit, a digital signal processing unit, a storage control unit and a PCIe module;

[0046] The acquisition control unit controls the acquisition of analog signals from multiple isolated analog signal channels and transmits the signals to the digital signal processing unit and the storage control unit. The digital signal processing unit and the storage control unit exchange data, and the signal output ends of the digital signal processing unit and the storage control unit are both connected to the PCIe module. Specific embodiment three:

[0048] The only difference between the third embodiment of the present application and the second embodiment is that:

[0049] The data buffer area uses a high-speed cache unit. By grouping DDR3L chips to store waveform data of different channels, the storage depth of each data acquisition channel supports storing waveform data of a certain time length at a certain sampling rate.

[0050] The programmable logic FPGA receives a data read command from the main controller through the PCIe interface, and sends the stored data in the data buffer area to the main controller through the PCIe link through the PCIe interface. Specific embodiment four:

[0052] The only difference between the fourth embodiment of the present application and the third embodiment is that:

[0053] The analog-to-digital conversion circuit uses the SPI configuration signal sent by the programmable logic FPGA through the signal isolation unit to configure the sampling rate and resolution working parameters, and sends the sampled data signal and data receiving clock to the programmable logic FPGA through the signal isolation unit. Through the synchronization control signal, the programmable logic can control the synchronous data acquisition of multiple channels. Specific embodiment five:

[0055] The only difference between the fifth embodiment of the present application and the fourth embodiment is that:

[0056] The clamp-type sensor, thermocouple and accelerometer on the current clamp are used to measure different functions, including voltage, current, temperature, strain and acceleration. Specific embodiment six:

[0058] The only difference between the sixth embodiment of the present application and the fifth embodiment is that:

[0059] The isolation degree of each part is 500V; the analog-to-digital conversion of the analog signals of N channels is realized through N high-speed analog-to-digital conversion circuits that support a maximum sampling rate of 200MSa / s. Specific embodiment seven:

[0061] The only difference between the seventh embodiment of the present application and the sixth embodiment is that:

[0062] The clock system consists of two phase-locked loops. One phase-locked loop provides the operating clock for the programmable logic FPGA and multiple groups of DDR3L memory, and the other phase-locked loop provides multiple identical sampling clocks for the analog-to-digital conversion circuits of multiple channels. The phase-locked loop also has a clock source switching function. According to the working requirements of the data acquisition module, it can be configured to use the crystal oscillator clock on the module or the high-precision differential clock from the PXIe backplane. Specific embodiment eight:

[0064] The only difference between the eighth embodiment of the present application and the seventh embodiment is that:

[0065] The present invention provides a PXIe data acquisition method with isolation between multiple channels supporting multiple acquisition functions, the method comprising the following steps:

[0066] Connect the ports to be tested through multiple isolated analog signal channels, and convert the port signals into analog signals through signal conditioning and analog-to-digital conversion operations respectively;

[0067] The output analog signal is processed and stored through the programmable logic FPGA, and the processed signal is output to the data transmission interface through the PCIe interface;

[0068] The corresponding on-chip digital signal processing is performed in the programmable logic FPGA and stored in the DDR. The main controller can read the data stored in the DDR through the PXIe bus; the main controller configures the different measurement functions of each channel by accessing the register configuration in the FPGA. Specific embodiment nine:

[0070] The only difference between the ninth embodiment of the present application and the eighth embodiment is that:

[0071] The present invention provides a computer-readable storage medium having a computer program stored thereon. The program is executed by a processor to implement a PXIe data acquisition method supporting multiple acquisition functions and isolating multiple channels. Specific embodiment ten:

[0073] The only difference between the tenth embodiment of the present application and the ninth embodiment is that:

[0074] The present invention provides a computer device, including a memory and a processor. The memory stores a computer program. When the processor runs the computer program stored in the memory, the processor executes a PXIe data acquisition method that supports isolation between multiple channels and multiple acquisition functions. Specific embodiment eleven:

[0076] The only difference between the eleventh embodiment of the present application and the tenth embodiment is that:

[0077] like Figure 2 As shown, taking voltage measurement module 1 as an example, its working method is as follows:

[0078] When starting work, the analog voltage signal is input into the analog channel through the BNC terminal, which connects the gas discharge tube and the housing. When the input exceeds the rated voltage, it absorbs most of the voltage through its own breakdown, protecting the analog circuit connected in parallel with it at the back end from damage by overvoltage. In the present invention, a 500V gas discharge tube is selected, which is connected to the housing and can release overvoltage exceeding 500V to the ground. After passing through the input terminal, the analog signal first passes through an RC parallel network. The main function of this part of the circuit is to constitute the signal voltage division attenuation together with the attenuation control. Low-frequency and DC signals are attenuated through the resistor network, while higher-frequency signals are attenuated through capacitor voltage division. The signal is then input into the coupling switch circuit. This project requires that the data acquisition module can realize DC coupling, AC coupling and GND coupling. Therefore, in the present invention, a method of controlling the relay switch to access different couplings through FPGA signals is adopted to realize the switching of coupling modes.

[0079] DC coupling allows both DC and AC components of the signal to pass through. AC coupling, by connecting a DC-blocking capacitor in series with the link, allows only AC signals to pass through, filtering out the DC component of the input signal. GND coupling connects the entire analog channel directly to ground and observes whether the output shows 0V. If it is not 0V, it indicates that the acquisition module has an unreasonable voltage offset in the channel and requires calibration before measurement.

[0080] The signal attenuation section primarily consists of relays and a resistor-capacitor network. The FPGA adjusts the required attenuation coefficient of the signal input by changing the relay state. Passing through the attenuation network, the signal can be attenuated to 1 / 4 or 1 / 400 of the original signal. By combining the attenuation network and the pre-coupling resistor, the calculated input impedance is approximately 1 MΩ.

[0081] After passing through the first stage of signal attenuation, the signal is input into the op amp follower. This device has an input impedance of approximately infinite and an output impedance of approximately zero, providing excellent drive capability. This ensures that the output voltage remains unaffected by changes in load impedance at the op amp's rated output power. After passing through the op amp follower, the output signal is isolated from the input signal, providing a buffering effect and protecting the circuit against overvoltage inputs.

[0082] After passing through the op amp follower, the analog signal enters the second-stage attenuation network, which consists of a resistor divider network. In the present invention, three signals are used to control the switches of different channels of the analog multiplexer to achieve the switching of the attenuation coefficient, with a total of six attenuation coefficients. Based on the first-stage attenuation, the second-stage attenuation network can attenuate the input signal to 1 / 2, 1 / 4, 1 / 10, 1 / 20, 1 / 40, or no attenuation.

[0083] After passing through the attenuation network, it enters the signal amplification module which can achieve 10 times amplification. In the present invention, the operational amplifier adopts a negative feedback amplifier structure, and the output signal is in phase with the input signal.

[0084] After amplification, the analog signal passes through a low-pass filter network controlled by three FPGA signals. Eight cutoff frequencies are selectable based on measurement requirements, effectively filtering out most frequency components in the stopband. Finally, at the end of the analog signal conditioning circuit, the analog signal passes through a negative feedback amplifier circuit composed of op amps, which achieves a two-fold gain. Because the ADC's analog signal input requires a differential signal, a differential operational amplifier (OPA) with a bandwidth of 350MHz is used after the amplifier to convert the single-channel signal into a differential signal.

[0085] After the analog signal is conditioned to meet the ADC's input voltage requirements, it is quantized and converted to a digital output by the ADC. The present invention uses a 14-bit ADC capable of up to 1Gsps. This ADC has 14 pairs of differential data outputs and one pair of differential clock outputs, which the FPGA uses to receive data.

[0086] Control signals from the FPGA are serially input and output in parallel on two cascaded shift registers, which are used to control the relays and analog switches of the analog channels. Because the inverted output of the last bit in the cascaded process serves as the input to the other shift register, some input data is logically opposite to the actual relay state control requirements.

[0087] like Figure 1 As shown, the various analog channels and digital circuit parts of the data acquisition system are isolated from each other, the data signals are transmitted through different isolation devices, and the power supply is transmitted through the isolated power supply module. The ADC requires FPGA to configure it through the SPI bus, and this bus is transmitted through two isolators of a domestic company in the present invention. One of them is an I2C dedicated chip with two bidirectional channels, which supports an I2C clock of up to 2MHz. Because the present invention has low requirements for the ADC configuration speed, the SDIO and SCLK in the SPI bus use this isolator. The other is a four-channel unidirectional isolator that supports a maximum communication rate of 150MHz. The control signals of the functional modules of the analog channel and the CSN signals of the SPI are transmitted through this isolator.

[0088] When transmitting high-speed ADC data and clock signals, the present invention currently uses differential high-speed isolators to achieve channel-to-channel isolation and data transmission. This isolator product has four channels, each allowing data signals up to 2.5Gbps, for a total bandwidth of 10Gbps across all four channels. In the present invention, four of these isolators are used per channel to transmit the ADC differential data signal and differential clock.

[0089] After the ADC transmits the waveform data to the FPGA, the FPGA performs on-chip digital signal processing and stores it in the DDR memory. The host controller can then access the data stored in the DDR memory via the PXIe bus. Simultaneously, the host controller accesses register configurations in the FPGA to configure the different measurement functions for each channel. Specific embodiment 12:

[0091] The difference between the twelfth embodiment of the present application and the eleventh embodiment is that:

[0092] The technical principles of the present invention include: utilizing high-speed differential digital signal isolation devices and isolated power supplies with high isolation, designing N isolated analog signal channels in a PXIe data acquisition module to ensure mutual isolation between digital signals and the N analog signal channels, with an overall isolation of approximately 500V; achieving analog-to-digital conversion of the analog signals of the N channels through N high-speed analog-to-digital converters supporting a maximum sampling rate of 200MSa / s; connecting the analog signal conditioning circuit of each channel to the above-mentioned digital circuit board through a board-to-board connector, enabling flexible replacement, and configuring the acquisition function of each channel through an FPGA; finally, using multiple groups of DDR memories and high-performance FPGAs to meet PCIe high-speed data transmission and waveform data storage requirements.

[0093] According to the technical principles of the present invention, the functions and working modes of the various parts of the multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions are as follows:

[0094] The digital control and data transmission module mainly includes four parts: data cache, programmable logic, clock system and PCIe interface. Communication between the PCIe interface and the data cache is achieved through programmable logic.

[0095] The data buffer is a high-speed cache unit. By grouping DDR3L chips to store waveform data for different channels, the storage depth of each data acquisition channel can support storing waveform data for a certain duration at a certain sampling rate. The programmable logic receives data read commands from the main controller via the PCIe interface and transmits the stored data in the data buffer to the main controller via the PCIe link. This method not only enables real-time waveform data upload and display, but also allows data to be stored on external storage media such as solid-state drives, enabling long-term waveform data recording. By parsing the data acquisition control commands sent by the main controller, the programmable logic in the module can also configure functional units such as the sampling rate of the analog-to-digital converters, analog signal conditioning circuits, and clock systems for different channels. The programmable logic includes functions such as waveform parameter measurement and triggering, enabling real-time calculation and analysis of waveform data. The clock system consists of two phase-locked loops. One phase-locked loop provides the operating clock for the programmable logic and multiple groups of DDR3L memory, and the other phase-locked loop provides multiple identical sampling clocks for the analog-to-digital converters of multiple channels. At the same time, the phase-locked loop has a clock source switching function. According to the working requirements of the data acquisition module, it can be configured to use the crystal clock on the module or the high-precision differential clock from the PXIe backplane.

[0096] Power and data signal isolation primarily consists of two components: data signal isolation and power supply isolation. Each data acquisition channel group uses a combination of high-speed differential signal isolators and low-speed isolators to isolate different signal types. The isolated power supply for each analog channel is generated using a transformer and linear regulator. The 12V power supply from the PXIe backplane is converted to +12V and -12V power using an isolation transformer. A linear regulator then converts the -12V power supply to the -5.6V required by the analog-to-digital converter. A single high-speed differential signal isolator chip can support up to four unidirectional differential signals. Five of these isolators are required between the analog-to-digital converter and the programmable logic of each data acquisition channel, transmitting waveform data signals, differential clock, and synchronization signals. Each data acquisition channel requires two low-speed isolators: one that transmits the analog-to-digital converter's SPI configuration signals, supporting unidirectional digital signals up to 150Mbps. Another dual-port isolator, supporting up to 2Mbps, transmits the switch control signals for the serial analog signal conditioning circuit.

[0097] The data acquisition analog channel consists of two components: signal conditioning circuitry and analog-to-digital conversion circuitry. Each channel's signal conditioning circuit is connected to the analog-to-digital conversion circuit via a separate board-to-board connector. The board-to-board connector provides isolated power and transmits switch control signals. Two 8-bit shift registers convert the serial analog signal conditioning circuit's switch control signals into parallel control signals, which are used to control the relays and analog switches within the signal conditioning circuitry. After input, the analog signal passes through the signal conditioning circuitry's signal attenuation, signal amplification, and analog filtering circuits before being adjusted to the input range of the analog-to-digital converter. Signal attenuation and amplification are controlled by switch control signals, which control the relay state and the connection state of the resistor-capacitor network to switch the amplification or attenuation factor. The analog filter circuitry uses analog switches to change the low-pass filter's cutoff frequency. An RC low-pass filter network allows for switching between eight filter frequencies. The signal conditioning circuit supports three input coupling modes: DC coupling, AC coupling, and GND coupling. This switching of coupling modes allows for measuring different analog signals and performing zero calibration. Each analog channel input port is connected to a gas discharge tube, which can ensure that the subsequent circuit will not be damaged by input voltage exceeding 500V, further improving the safety of the module in complex environments.

[0098] The analog-to-digital converter (ADC) uses SPI configuration signals sent by the programmable logic through the isolator to configure operating parameters such as sampling rate and resolution. The programmable logic also transmits the sampled data signal and data receive clock to the programmable logic via the high-speed isolator. Synchronous control signals enable the programmable logic to control the simultaneous data acquisition of multiple channels.

[0099] The present invention supports a total of five data acquisition analog channels operating simultaneously, covering voltage, current, temperature, strain, and acceleration measurement functions. Among them, the maximum input voltage that can be measured by voltage measurement module one is 400V, and the maximum sampling rate of the analog-to-digital converter is 200MSa / s; voltage measurement module two supports measuring 30Vrms and DC 60V voltages with a measurement resolution of 11 bits; the current, temperature, and strain measurement modules are all implemented based on voltage measurement module two, and the clamp-type sensor, thermocouple, and acceleration sensor on the current clamp are used to achieve different measurement functions.

[0100] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in an appropriate manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless otherwise clearly defined. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, "N" means at least two, such as two, three, etc., unless otherwise clearly defined. Any process or method description in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code comprising one or more executable instructions for implementing a custom logic function or process, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may be performed in a different order than shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which the embodiments of the present invention pertain. The logic and / or steps shown in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logic function, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or for use in conjunction with such instruction execution systems, apparatuses, or devices. For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by an instruction execution system, apparatus, or device, or in conjunction with such instruction execution systems, apparatuses, or devices. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or N wirings (electronic devices), a portable computer disk cartridge (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM).In addition, the computer-readable medium may even be paper or other suitable medium on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, then editing, interpreting, or processing in other suitable ways as necessary, and then storing it in a computer memory. It should be understood that the various parts of the present invention can be implemented with hardware, software, firmware, or a combination thereof. In the above embodiment, the N steps or methods can be implemented with software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented with hardware, as in another embodiment, any one of the following technologies known in the art or their combination can be used to implement: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0101] Those skilled in the art will appreciate that all or part of the steps carried out in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment. In addition, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0102] The above description is merely a preferred embodiment of a multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions. The scope of protection for a multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions is not limited to the aforementioned embodiment; all technical solutions based on this concept fall within the scope of protection of the present invention. It should be noted that improvements and variations readily apparent to those skilled in the art without departing from the principles of the present invention are also within the scope of protection of the present invention.

Claims

1. A PXIe data acquisition module with multi-channel isolation supporting multiple acquisition functions, characterized by: The module includes: multiple analog signal channels with isolation between channels, data buffer area, programmable logic FPGA, clock system, PCIe interface and data transmission interface; The multiple inter-channel isolated analog signal channels output isolated signals to a programmable logic FPGA, the programmable logic FPGA is respectively connected to a data buffer area and a clock system, the programmable logic FPGA is connected to a PCIe interface, and the PCIe interface is connected to a data transmission interface; The analog signal channels isolated between the multiple channels include a signal conditioning circuit, an analog-to-digital conversion circuit and a signal isolation unit. The signal isolation unit adopts an independent board-to-board connector. The signal conditioning circuit of each channel is connected to the analog-to-digital conversion circuit through an independent board-to-board connector. The board-to-board connector is responsible for providing isolated power supply and transmission switch control signals for the signal conditioning circuit.

2. The multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions according to claim 1, wherein: The programmable logic FPGA includes an acquisition control unit, a digital signal processing unit, a storage control unit and a PCIe module; The acquisition control unit controls the acquisition of analog signals from multiple isolated analog signal channels and transmits the signals to the digital signal processing unit and the storage control unit. The digital signal processing unit and the storage control unit exchange data, and the signal output ends of the digital signal processing unit and the storage control unit are both connected to the PCIe module.

3. The multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions according to claim 2, wherein: The data buffer area uses a high-speed cache unit. By grouping DDR3L chips to store waveform data of different channels, the storage depth of each data acquisition channel supports storing waveform data of a certain time length at a certain sampling rate. The programmable logic FPGA receives a data read command from the main controller through the PCIe interface, and sends the stored data in the data buffer area to the main controller through the PCIe link through the PCIe interface.

4. The multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions according to claim 3, wherein: The analog-to-digital conversion circuit uses the SPI configuration signal sent by the programmable logic FPGA through the signal isolation unit to configure the sampling rate and resolution working parameters, and sends the sampled data signal and data receiving clock to the programmable logic FPGA through the signal isolation unit. Through the synchronization control signal, the programmable logic can control the synchronous data acquisition of multiple channels.

5. The PXIe data acquisition module with multi-channel isolation supporting multiple acquisition functions according to claim 4, characterized in that: The clamp-type sensor, thermocouple and accelerometer on the current clamp are used to measure different functions, including voltage, current, temperature, strain and acceleration.

6. The multi-channel isolated PXIe data acquisition module supporting multiple acquisition functions according to claim 5, wherein: The isolation degree of each part is 500V; the analog-to-digital conversion of the analog signals of N channels is realized through N high-speed analog-to-digital conversion circuits that support a maximum sampling rate of 200MSa / s.

7. The PXIe data acquisition module with multi-channel isolation supporting multiple acquisition functions according to claim 6, characterized in that: The clock system consists of two phase-locked loops. One phase-locked loop provides the operating clock for the programmable logic FPGA and multiple groups of DDR3L memory, and the other phase-locked loop provides multiple identical sampling clocks for the analog-to-digital conversion circuits of multiple channels. The phase-locked loop also has a clock source switching function. According to the working requirements of the data acquisition module, it can be configured to use the crystal oscillator clock on the module or the high-precision differential clock from the PXIe backplane.

8. A PXIe data acquisition method with multi-channel isolation supporting multiple acquisition functions, characterized by: The method comprises the following steps: Connect the ports to be tested through multiple isolated analog signal channels, and convert the port signals into analog signals through signal conditioning and analog-to-digital conversion operations respectively; The output analog signal is processed and stored through the programmable logic FPGA, and the processed signal is output to the data transmission interface through the PCIe interface; The corresponding on-chip digital signal processing is performed in the programmable logic FPGA and stored in the DDR. The main controller can read the data stored in the DDR through the PXIe bus; the main controller configures the different measurement functions of each channel by accessing the register configuration in the FPGA.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement a PXIe data acquisition method supporting isolation between multiple channels and multiple acquisition functions as claimed in claim 8.

10. A computer device, characterized in that: The method comprises a memory and a processor, wherein a computer program is stored in the memory. When the processor runs the computer program stored in the memory, the processor executes the PXIe data acquisition method with isolation between multiple channels supporting multiple acquisition functions according to claim 8.

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