An asymmetric write dual voltage magnetic random access memory structure

Abstract

The application discloses a kind of asymmetric write dual-voltage magnetic random access memory (MRAM) structure, including magnetic random access array, write drive circuit, readout circuit, write bit line selection circuit, read bit line selection circuit, word line drive circuit and control circuit.The application is designed using two voltage domains transistor, to guarantee that memory can work normally under dual power supply voltage.When writing, control part works in low voltage domain, and write circuit part works in high voltage domain, which can shorten write delay and improve write yield;When reading, readout circuit and control part work in low voltage domain, which can reduce read power consumption and reduce read damage.At the same time, for the asymmetry of MRAM memory cell structure, the application proposes an asymmetric write mode, which effectively reduces the power waste in the writing process.Compared with the traditional MRAM memory, the application effectively improves the write yield and reduces the write delay while considering the area and energy efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and particularly relates to an array structure based on magnetic random access memory (MRAM) and a dual-voltage circuit design method for asymmetric writing. Background Technology

[0002] In recent years, with the continuous development of the Internet of Things (IoT), higher requirements have been placed on the power consumption and reliability of storage. Among the new non-volatile memories (NVMs), massive ramified RAM (MRAM) has attracted widespread attention both domestically and internationally due to its non-volatility, high density, and near-zero static power consumption. Compared to other non-volatile memories, MRAM has lower write power consumption and higher storage density. Furthermore, MRAM also has significant advantages in read efficiency, read speed, and endurance. Therefore, MRAM is more suitable for low-voltage, low-power applications compared to other non-volatile memories.

[0003] Magnetic random access memory (MRAM) offers advantages such as non-volatility, fast read / write speeds, low static power consumption, and compatibility with complementary metal-oxide-semiconductor (CMOS) processes, making it suitable for edge devices in IoT. MRAM stores data by using current to change the magnetization direction of the free layer metal in a magnetic tunnel junction (MTJ). When the magnetization direction of the free layer in the MTJ is the same as that of the fixed layer, the magnetoresistance is low (P); conversely, when the magnetization direction of the free layer is opposite to that of the fixed layer, the magnetoresistance is high (AP). Due to the asymmetry of the 1-transistor 1-MTJ (1T1M) memory cell, the transition from low-resistance to high-resistance state (P2AP) during the write process is more difficult to achieve than the transition from high-resistance to low-resistance state (AP2P). To achieve high yield in the P2AP write process, a higher write voltage is required, which leads to wasted power in the AP2P case. Furthermore, the voltage and current requirements of the power supply differ significantly between write and read operations, making a single power supply insufficient for the storage needs of MRAM. Summary of the Invention

[0004] The purpose of this invention is to provide an asymmetric write dual-voltage magnetic random access memory structure to solve the write problem caused by the asymmetry of storage cells in MRAM memory, as well as the problem of different power requirements for read and write operations.

[0005] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0006] A dual-voltage magnetic random access memory structure with asymmetric writing includes a magnetic random access array, a write drive circuit, a write bit line selection circuit, a read bit line selection circuit, a readout circuit, a word line drive circuit, and a control circuit.

[0007] The control circuit is connected to the write drive circuit, the write bit line selection circuit, the read bit line selection circuit, the read circuit, and the word line drive circuit, respectively.

[0008] The control circuit is used for the timing function and logic control of the entire memory. It latches the externally input data, address, control signals and internally output data on the rising edge of the clock, and outputs the read enable signal ReadEN and the write enable signal WriteEN to the word line driver circuit. The read enable signal ReadEN is also input to the read bit line selection circuit and the read circuit, and the output write enable signal WriteEN is also input to the write driver circuit and the write bit line selection circuit.

[0009] The write driver circuit is connected to the write bit line selection circuit and is used for write operation control, data input, and to provide write drive capability to the write bit line selection circuit. The write driver circuit includes two voltage domains: a low voltage domain and a high voltage domain. The low voltage domain is used to control the write operation and data input, and the high voltage domain is used to provide write drive capability.

[0010] The write bit line selection circuit is connected to the magnetic random access memory array, and selects the corresponding bit line and source line according to the low-order address during the write operation;

[0011] The magnetic random access memory array is responsible for storing data and can realize data writing and reading at any address. Its magnetic tunnel junction changes the magnetization direction according to the direction of the writing current to form different magnitudes of magnetoresistance to store data.

[0012] The read bit line selection circuit is connected to the magnetic random access memory array. During the read operation, it selects the corresponding bit line according to the low-order address and grounds the corresponding source line.

[0013] The readout circuit is connected to the read bit selection circuit and is used to read data from the storage array. The output data is generated by judging the resistance of the magnetic tunnel junction in the two storage cells.

[0014] The word line driving circuit is responsible for decoding the high-order address and driving the word lines. It has two output voltages: a lower voltage for read operations and a higher voltage for write operations.

[0015] Furthermore, write and read operations use different power supply voltages to ensure high write yield and low memory access power consumption.

[0016] Furthermore, the write bit selection circuit for writing "0" and writing "1" is asymmetrical, which can better match the writing requirements of a 1-transistor 1-magnetic tunnel junction memory cell and reduce power consumption waste.

[0017] Furthermore, the magnetic random access memory array includes a memory cell array, where each memory cell consists of a transistor and a magnetic tunnel junction. Each column of memory cells shares a word line WL, and each row of memory cells shares a bit line BL and a source line SL; the memory cell array is divided into n subarrays according to the number of bits of stored data n.

[0018] Furthermore, each subarray is responsible for storing one bit of data, including several storage units determined by the number of data bits and the array size, as well as ports for several bit lines, source lines, and word lines.

[0019] Furthermore, the write driver circuit includes multiple write driver circuit groups, with the same number of write driver circuit groups and the same number of data bits. Each write driver circuit group includes an inverter and two 1-bit write driver circuits, with the two 1-bit write driver circuits having identical structures. The input terminals of each 1-bit write driver circuit include a data input terminal DIN and a write enable signal WriteEN. The output terminals of each 1-bit write driver circuit include write bit lines WBL and WBLB, and write source lines WSL and WSLB. The two power supply terminals of the 1-bit write driver circuit are connected to power supply VDDH and power supply VDDL, respectively. The ground terminal is connected to ground VSS. The inverter INV0 is connected between the data input terminals DIN of the two 1-bit write driver circuits.

[0020] Furthermore, the 1-bit write drive circuit includes: a first inverter INV1, whose input is connected to the write enable signal WriteEN and whose output is connected to node NW; a second inverter INV2, whose input is connected to the data input DIN and whose output is connected to node NDIN; a first NOR gate NOR1, which is a dual-input single-output circuit, whose first input is connected to the data input DIN, whose second input is connected to node NW and whose output is connected to node IN[0]; a second NOR gate NOR2, which is a dual-input single-output circuit, whose first input is connected to node NW, whose second input is connected to node NDIN and whose output is connected to node IN[1]; a first level converter LS[1], whose input is connected to node IN[0] and whose output is connected to node WBL, whose two power supply terminals are connected to power supply VDDH and power supply VDDL respectively, and whose ground terminal is connected to ground VSS; a second level converter LS[2], whose input is connected to node IN[1] and whose output is connected to node WBL, whose two power supply terminals are connected to power supply VDDH and power supply VDDL respectively, and whose ground terminal is connected to ground VSS.

[0021] Furthermore, the first level converter LS[1] and the second level converter LS[2] have the same structure, both including: a first PMOS transistor P1, whose gate is connected to the first node NET1, the source is connected to the power supply VDDH, and the drain is connected to the second node NET2; a second PMOS transistor P2, whose gate is connected to the second node NET2, the source is connected to the power supply VDDH, and the drain is connected to the first node NET1; a third PMOS transistor P3, whose gate is connected to the second node NET2, the source is connected to the power supply VDDH, and the drain is connected to the output terminal OUT; a first NMOS transistor N1, whose gate is connected to the input terminal IN, the source is connected to ground VSS, and the drain is connected to the second node NET2; a second NMOS transistor N2, whose gate is connected to node NIN, the source is connected to ground VSS, and the drain is connected to the first node NET1; a second NMOS transistor N3, whose gate is connected to the second node NET2, the source is connected to ground VSS, and the drain is connected to the output terminal OUT; a first inverter INV, whose input terminal is connected to the input terminal IN, the output terminal is connected to node NIN, the power supply terminal is connected to the power supply VDDL, and the ground terminal is connected to ground VSS.

[0022] The write bit line selection circuit includes a decoding circuit, a level shifter group, and multiple write transmission transistor groups. The number of write transmission transistor groups is the same as the number of data bits. The decoding circuit is responsible for decoding the low-order address bits and generating drive signals for the write transmission transistor groups. The level shifter group is responsible for converting the signals generated by the decoding circuit into higher voltage signals to drive the corresponding write transmission transistor groups. The write transmission transistor groups are responsible for connecting the bit lines WBL and WBLB of the write drive circuit and the bit line BL of the array, as well as connecting the source lines WSL and WSLB of the write drive and the source line SL of the array.

[0023] Furthermore, the transmission tube group includes m write transmission tubes;

[0024]

[0025] Where n represents the number of bits for storing data, and N represents the total number of bit lines (BL).

[0026] Each write transmission transistor includes a first PMOS transistor P1, whose gate is connected to the second node NET2, its source is connected to the write source line WSL, and its drain is connected to the source line SL[0].

[0027] The second PMOS transistor P2 has its gate connected to the second node NET4, its source connected to the write source line WSLB, and its drain connected to the source line SL[1].

[0028] The first NMOS transistor N1 has its gate connected to the first node NET3, its source connected to the write bit line WBL, and its drain connected to the bit line BL[0].

[0029] The second NMOS transistor N2 has its gate connected to the first node NET3, its source connected to the write source line WSL, and its drain connected to the source line SL[0].

[0030] The third NMOS transistor N3 has its gate connected to the first node NET3, its source connected to the write bit line WBLB, and its drain connected to the bit line BL[1].

[0031] The fourth NMOS transistor N4 has its gate connected to the first node NET3, its source connected to the write source line WSLB, and its drain connected to the source line SL[1].

[0032] The first inverter INV has its input connected to the first node NET3 and its output connected to the second node NET4.

[0033] Furthermore, the readout circuit includes multiple 1-bit readout circuits, the number of which is the same as the number of data bits. The input terminals of the 1-bit readout circuit include two bit lines RBL and RBLB, and a read enable signal ReadEN; its output terminal is the data output terminal DOUT; the power supply terminal is connected to the power supply VDDL; and the ground terminal is connected to ground VSS.

[0034] Furthermore, the read bit line selection circuit includes a decoding circuit and multiple read transmission transistor groups. The decoding circuit is responsible for decoding the low-order address bits and generating drive signals for the read transmission transistor groups. The read transmission transistor groups are responsible for connecting the bit lines RBL and RBLB of the readout circuit and the bit line BL of the array, as well as connecting the source lines RSL and RSLB of the readout circuit and the source line SL of the array.

[0035] Furthermore, the read transfer transistor group consists of multiple groups of read transfer transistors, each group of read transfer transistors including: a first NMOS transistor N1, whose gate is connected to the first node NET1, whose source is connected to the read bit line RBL, and whose drain is connected to the bit line BL[0]; a second NMOS transistor N2, whose gate is connected to the first node NET1, whose source is connected to ground VSS, and whose drain is connected to the source line SL[0]; a third NMOS transistor N3, whose gate is connected to the first node NET1, whose source is connected to the read bit line RBLB, and whose drain is connected to the bit line BL[1]; and a fourth NMOS transistor N4, whose gate is connected to the first node NET1, whose source is connected to ground VSS, and whose drain is connected to the source line SL[1].

[0036] Furthermore, the word line driving circuit includes: a word line decoder, a level shifter group, and a read / write selection circuit. The word line decoder is responsible for decoding the high-order address bits, generating the word line driving signal RWL during read operations. The level shifter group is responsible for converting the low-voltage signal RWL generated by the word line decoder into a high-voltage signal WWL to drive the word lines during write operations. The read / write selection circuit selects the word line drive of the array based on the read enable signal ReadEN and the write enable signal WriteEN.

[0037] Furthermore, the control circuit includes a set of flip-flops and a logic circuit. The flip-flop set is controlled by a clock signal CLK and is responsible for latching externally input data, address, and enable signals, as well as internally output data, on the rising edge of the clock signal. The logic circuit is responsible for generating a read enable signal ReadEN and a write enable signal WriteEN based on the latched enable signal.

[0038] Furthermore, the logic circuit includes:

[0039] The first inverter INV has its input connected to the read / write enable WEB and its output connected to the node WE.

[0040] The first NOR gate NOR1 is a dual-input single-output circuit. Its first input is connected to the chip select enable CEB, its second input is connected to the node WE, and its output is connected to the read enable signal ReadEN.

[0041] The second NOR gate, NOR2, is a dual-input single-output circuit. Its first input is connected to the chip select enable (CEB), its second input is connected to the node read / write enable (WEB), and its output is connected to the write enable signal (WriteEN).

[0042] The asymmetric write dual-voltage magnetic random access memory of the present invention has the following advantages:

[0043] (1) The present invention adopts a dual-voltage circuit design. The higher power supply voltage is used in the drive part of the write circuit to provide higher write drive capability, reduce write delay and improve write yield; the lower power supply voltage is used in the read circuit to reduce read power consumption and reduce read damage.

[0044] (2) The present invention uses a level converter to solve the matching problem of dual voltage circuits. The digital logic part uses a lower power supply voltage and controls the write circuit through the level converter, which effectively reduces the power consumption and area overhead of the control circuit.

[0045] (3) The present invention utilizes an asymmetric writing circuit structure to reduce the voltage across the MTJ during AP2P while ensuring the P2AP write yield and write delay, thereby reducing the risk of MTJ breakdown and reducing AP2P write power consumption without affecting normal writing. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the following description is only some embodiments of the present invention. For those skilled in the art, they can obtain more information based on these drawings without creative effort.

[0047] Figure 1This is a block diagram of an asymmetric write dual-voltage magnetic random access memory structure provided in an embodiment of the present invention;

[0048] Figure 2 This is a structural diagram of a magnetic random access memory array provided in an embodiment of the present invention;

[0049] Figure 3 This is a structural diagram of the write driver circuit provided in an embodiment of the present invention;

[0050] Figure 4 This is a structural diagram of a 1-bit write driver circuit provided in an embodiment of the present invention;

[0051] Figure 5 This is a circuit diagram of a level converter provided in an embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of the readout circuit structure provided in an embodiment of the present invention;

[0053] Figure 7 This is a structural diagram of the write bit line selection circuit provided in an embodiment of the present invention;

[0054] Figure 8 This is a structural diagram of the read line selection circuit provided in an embodiment of the present invention;

[0055] Figure 9 This is a structural diagram of the word line driving circuit provided in an embodiment of the present invention;

[0056] Figure 10 This is a control circuit structure diagram provided in an embodiment of the present invention;

[0057] Figure 11 This is a schematic diagram of the connection between the subarray and the column selection transmission tube provided in an embodiment of the present invention;

[0058] Figure 12 This is a comparison chart of simulation results showing the impact of different power supply voltages on write yield and write latency, provided in an embodiment of the present invention.

[0059] Figure 13 This is a comparison chart of simulation results between the asymmetric writing method provided in this embodiment of the invention and the traditional method. Detailed Implementation

[0060] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0061] To better understand the purpose, structure, and function of this invention, the following detailed description of an analog domain-in-memory computing array structure based on magnetic random access memory is provided in conjunction with the accompanying drawings.

[0062] The present invention describes an asymmetric write dual-voltage magnetic random access memory structure as follows: Figure 1 As shown, the system includes: a magnetic random access memory (MRM) array, a write drive circuit, a read circuit, a write bit line selection circuit, a read bit line selection circuit, a word line drive circuit, and a control circuit. The MLM array is responsible for storing data and can write and read data from any address. Its magnetic tunnel junction changes its magnetization direction according to the direction of the write current, forming different resistance values ​​to store data. In this embodiment, the M×N size of the memory array is used, where M is the total number of word lines (WL) and N is the total number of bit lines (BL).

[0063] Magnetic random access array structure such as Figure 2 As shown, the array can be divided into n subarrays according to the number of bits of data stored, where n is the number of bits of data stored. Each subarray has 2m bit lines and 2m source lines, where m is expressed as:

[0064]

[0065] The "2" in the formula indicates that this array uses 2 transistors and 2 magnetic tunnel junctions to store 1 bit of data.

[0066] Figure 3 This is a schematic diagram of the write drive circuit provided in an embodiment of the present invention. It consists of 2n 1-bit write drive circuits and n inverters. Each group of write drive circuits is responsible for writing 1 bit of data. Two 1-bit write drive circuits write two opposite data, causing the corresponding MTJs in the array to form opposite magnetization states. When reading data, the difference between high and low resistance can be used to determine the magnetization state.

[0067] The specific structure of the 1-bit write driver circuit is as follows: Figure 4 As shown, it consists of two inverters, two NOR gates, and two level shifters. The digital logic section uses a lower operating voltage VDDL, while the level shifters convert the write voltage to a higher voltage VDDH, providing stronger write drive capability. In this embodiment, VDDL is 1.2V and VDDH is 2V. DIN is the data to be written, and WriteEN is the write enable signal. When WriteEN is 1, it is enabled, and different write voltages are generated depending on the DIN input data. When DIN is 1, WBL is low and WSL is high, and MTJ is in the AP state after writing; when DIN is 0, BL is high and WSL is low, and MTJ is in the P state after writing.

[0068] Figure 5The level shifter structure used in this embodiment consists of three P-type transistors (PMOS), three N-type transistors (NMOS), and one inverter. Only the inverter operates at the VDDL power supply voltage; the others use transistors with higher operating voltages. Its working principle is as follows: low-voltage control signals IN and NIN control the gates of N1 and N2 respectively. If IN is 1.2V, N1 is turned on and N2 is turned off, creating a voltage difference between NET1 and NET2. P1 and P2 form a latch structure, which uses positive feedback to amplify the voltage difference between NET1 and NET2, ultimately making NET2 low. After passing through the inverter composed of P3 and N3, the OUT output is 2V. Adjusting the dimensions of P3 and N3 strengthens the write drive capability.

[0069] Readout circuit such as Figure 6 As shown, there are n 1-bit readout circuits, all powered by VDDL, which reduces readout power consumption and minimizes read corruption. The input signals for each 1-bit readout circuit include two bit lines, RBL and RBLB, and a read enable signal, ReadEN. RBL and RBLB are connected to two different bit lines, and data is obtained by comparing the magnetoresistive strength of two different memory cells.

[0070] Figure 7 The write bit line selection circuit connects the write bit lines WBL and WBLB, the write source lines WSL and WSLB, and the array's bit lines BL and SL. A decoding circuit decodes the bit address to select different bit lines for writing data. Based on the number of bits n to be written, the transmission transistors can be divided into n groups, with each group responsible for writing one bit of data. The write transmission transistor groups can be further divided into m groups based on whether they are simultaneously selected. The transmission transistors and logic section of each group are as follows... Figure 7 As shown in the lower right corner, it includes: 1 inverter, 4 NMOS and 2 PMOS. N2 and P1, N4 and P2 form transmission gates to connect the source lines WSL and WSLB of the write driver and the source lines SL[0] and SL[1] of the array, while only N1 and N2 are used as single NMOS to connect the bit lines of the write driver and the bit lines of the array. The asymmetric circuit design can ensure that the voltage across the MTJ is within a reasonable range when writing "1" and writing "0", so as to solve the problems of power consumption waste and MTJ breakdown during the writing process of the memory cell.

[0071] The structure of the read line selection circuit is as follows: Figure 8As shown, it consists of a decoding circuit and transmission transistors. The decoding circuit is responsible for decoding the low-order address bits and selecting the corresponding transmission transistor. The division of the read transmission transistor is similar to that of the write transmission transistor, the difference being that it does not use a transmission gate structure, but only NMOS transmission transistors, which can reduce area and read power consumption. The read transmission transistor adopts a symmetrical design to reduce the impact of the circuit on the read data.

[0072] Figure 9 This is a block diagram of the word line driver circuit, consisting of a word line decoder, a level shifter group, and a read / write selection circuit. The word line decoder converts the high-order address bits into the corresponding word line drive signals. CEB is the chip select enable signal, active low. When CEB is "0", the word line decoder is active. The level shifter group converts 1.2V to 2V, providing word line drive during write operations. The read / write selection circuit is controlled by the read enable signal ReadEN and the write enable signal WriteEN. When WriteEN is enabled, WWL and WL are connected, providing 2V word line drive; when ReadEN is enabled, RWL and WL are connected, providing 1.2V word line drive.

[0073] The structure of the control circuit is as follows Figure 10 As shown, the memory can be divided into a flip-flop group and a logic control section. The flip-flop group is responsible for latching data, address, and various enable signals on the rising edge of the clock signal CLK, ensuring that the signals inside the memory remain unchanged throughout the entire clock cycle. The logic control section consists of one inverter and two NOR gates, generating read / write enable signals ReadEN and WriteEN from the latched chip select enable CEB and read / write signal WEB.

[0074] Figure 11 This is a schematic diagram showing the connection between the subarray and the read / write transmission transistor. A single subarray contains M×2m ​​storage cells, where two cells at the same position in odd and even rows share 1 bit of data. During each write or read operation, the higher-order address is decoded by the word line to select one word line, and the lower-order address is decoded by the bit line to select the bit line transmission transistor. The write drive circuit or read circuit then writes or reads data from the designated storage cell. It is important to note that because this invention employs a dual-voltage design, the write transmission transistor, the drive section of the write drive module, and the word line drive during write operations all use transistors with higher operating voltages; while the read transmission transistor, the read circuit, and the word line drive during read operations use normal transistors.

[0075] Figure 12 This demonstrates the impact of different power supply voltages on write yield and write latency. The simulation was conducted in a test environment of 25°C, SS process corner, and the results in the figure represent the average values ​​for AP2P and P2AP. Figure 12As can be seen, the higher the power supply voltage, the higher the write yield and the shorter the write latency of the magnetic random access memory (RAM). When the write voltage reaches 2V, the write yield can reach 99.8%, and the write latency is 7.37ns. The read circuit can operate normally at 1.2V, meaning the write circuit requires a higher voltage to achieve high yield and high speed write operations.

[0076] Simulation results for asymmetric writing and traditional methods are as follows: Figure 13 As shown. Traditional writing methods refer to the use of a symmetrical write transfer transistor design, meaning that both BL and SL have transfer gate structures. From... Figure 13 It can be observed that in the P2AP case, there is essentially no difference between the two methods; however, in the AP2P case, the asymmetric write method reduces write power consumption by 66% compared to the traditional method without a significant change in write yield. Simultaneously, the number of transmission transistors in the asymmetric write method is reduced by 25% compared to the traditional method.

[0077] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A dual-voltage magnetic random access memory structure with asymmetric writing capability, characterized in that, It includes a magnetic random access memory array, a write driver circuit, a write bit line selection circuit, a read bit line selection circuit, a readout circuit, a word line driver circuit, and a control circuit; the source lines WSL and WSLB of the write driver and the source line SL of the array are connected through transmission gates composed of NMOS and PMOS, and the bit lines WBL and WBLB of the write driver and the bit line BL of the array are connected through NMOS. The control circuit is connected to the write drive circuit, the write bit line selection circuit, the read bit line selection circuit, the read circuit, and the word line drive circuit, respectively. The control circuit is used to latch externally input data, address, control signals and internally output data on the rising edge of the clock, and outputs the read enable signal ReadEN and the write enable signal WriteEN to the word line driver circuit; the read enable signal ReadEN is also input to the read bit line selection circuit and the read circuit, and the output write enable signal WriteEN is also input to the write driver circuit and the write bit line selection circuit. The write driver circuit is connected to the write bit line selection circuit and is used for write operation control, data input, and to provide write drive capability for write operations. The write driver circuit includes two voltage domains: a low voltage domain and a high voltage domain. The low voltage domain is used to control write operations and data input, while the high voltage domain is used to provide write drive capability. The write bit line selection circuit is connected to the magnetic random access memory array, and selects the corresponding bit line and source line according to the low-order address during the write operation; The magnetic random access memory array is responsible for storing data and is used to write and read data from any address. The read bit line selection circuit is connected to the magnetic random access memory array. During the read operation, it selects the corresponding bit line according to the low-order address and grounds the corresponding source line. The readout circuit is connected to the read bit selection circuit and is used to read data from the storage array. The output data is generated by judging the resistance of the magnetic tunnel junction in the two storage cells. The word line driving circuit is responsible for decoding the high-order address and driving the word lines. It has two output voltages: a lower voltage for read operations and a higher voltage for write operations.

2. The asymmetric write dual-voltage magnetic random access memory structure according to claim 1, characterized in that, The magnetic random access memory array includes a memory cell array, where each memory cell consists of a transistor and a magnetic tunnel junction; each column of memory cells shares a word line WL, and each row of memory cells shares a bit line BL and a source line SL; the memory cell array is divided into n subarrays according to the number of bits of stored data n. Each subarray is responsible for storing one bit of data. A subarray includes several storage units, as well as several bit lines, source lines, and word lines, determined by the number of data bits and the array size.

3. The asymmetric write dual-voltage magnetic random access memory structure according to claim 1, characterized in that, The write driver circuit includes multiple write driver circuit groups, and the number of write driver circuit groups is the same as the number of data bits; The write driver circuit group includes an inverter and two 1-bit write driver circuits, and the two 1-bit write driver circuits have the same structure. The input terminals of the 1-bit write driver circuit all include the data input terminal DIN and the write enable signal WriteEN; the output terminals all include the write bit lines WBL and WBLB, and the write source lines WSL and WSLB; the two power supply terminals of the 1-bit write driver circuit are connected to power supply VDDH and power supply VDDL respectively; the ground terminal is connected to ground VSS; the inverter INVO is connected between the data input terminals DIN of the two 1-bit write driver circuits.

4. The asymmetric write dual-voltage magnetic random access memory structure according to claim 3, characterized in that, The 1-bit write drive circuit includes: The first inverter INV1 has its input connected to the write enable signal WriteEN and its output connected to node NW. The second inverter INV2 has its input terminal connected to the data input terminal DIN and its output terminal connected to the node NDIN. The first NOR gate NOR1 is a dual-input single-output circuit. Its first input terminal is connected to the data input terminal DIN, its second input terminal is connected to node NW, and its output terminal is connected to node IN[0]. The second NOR gate NOR2 is a dual-input single-output circuit. Its first input terminal is connected to node NW, its second input terminal is connected to node NDIN, and its output terminal is connected to node IN[1]. The first level converter LS[1] has its input terminal connected to node IN[0], its output terminal connected to node WBL, its two power supply terminals connected to power supply VDDH and power supply VDDL respectively, and its ground terminal connected to ground VSS; The second level converter LS[2] has its input terminal connected to node IN[1], its output terminal connected to node WBL, its two power supply terminals connected to power supply VDDH and power supply VDDL respectively, and its ground terminal connected to ground VSS.

5. The asymmetric write dual-voltage magnetic random access memory structure according to claim 1, characterized in that, The write bit selection circuit includes a decoding circuit, a level converter group, and multiple write transmission transistor groups; the number of write transmission transistor groups is the same as the number of data bits. The decoding circuit is responsible for decoding the low-order address bits and generating the drive signal for the write transmission transistor group. The level converter group is responsible for converting the signal generated by the decoding circuit into a higher voltage signal to drive the corresponding write transmission transistor group. The write transmission transistor group is responsible for connecting the bit lines WBL and WBLB of the write driver circuit and the bit line BL of the array, as well as connecting the source lines WSL and WSLB of the write driver and the source line SL of the array.

6. The asymmetric write dual-voltage magnetic random access memory structure according to claim 5, characterized in that, The transmission tube group includes m write transmission tubes; （1）； Where n represents the number of bits for storing data, and N represents the total number of bit lines (BL). Each write transmission transistor includes a first PMOS transistor P1, whose gate is connected to the second node NET4, its source is connected to the write source line WSL, and its drain is connected to the source line SL[0]. The second PMOS transistor P2 has its gate connected to the second node NET4, its source connected to the write source line WSLB, and its drain connected to the source line SL[1]. The first NMOS transistor N1 has its gate connected to the first node NET3, its source connected to the write bit line WBL, and its drain connected to the bit line BL[0]. The second NMOS transistor N2 has its gate connected to the first node NET3, its source connected to the write source line WSL, and its drain connected to the source line SL[0]. The third NMOS transistor N3 has its gate connected to the first node NET3, its source connected to the write bit line WBLB, and its drain connected to the bit line BL[1]. The fourth NMOS transistor N4 has its gate connected to the first node NET3, its source connected to the write source line WSLB, and its drain connected to the source line SL[1]. The first inverter INV has its input connected to the first node NET3 and its output connected to the second node NET4.

7. The asymmetric write dual-voltage magnetic random access memory structure according to claim 1, characterized in that, The readout circuit includes multiple 1-bit readout circuits, with the number of 1-bit readout circuits being the same as the number of data bits; the input terminals of the 1-bit readout circuits include two bit lines RBL and RBLB, and a read enable signal ReadEN; its output terminal is the data output terminal DOUT; the power supply terminal is connected to the power supply VDDL; and the ground terminal is connected to ground VSS.

8. The asymmetric write dual-voltage magnetic random access memory structure according to claim 1, characterized in that, The read bit line selection circuit includes: a decoding circuit and multiple read transmission transistor groups; the decoding circuit is responsible for decoding the low-order address and generating drive signals for the read transmission transistor groups; the read transmission transistor groups are responsible for connecting the bit lines RBL and RBLB of the read circuit and the bit line BL of the array, as well as connecting the source lines RSL and RSLB of the read circuit and the source line SL of the array.

9. The asymmetric write dual-voltage magnetic random access memory structure according to claim 1, characterized in that, The word line driving circuit includes: a word line decoder, a level converter group, and a read / write selection circuit; the word line decoder is responsible for decoding the high-order address bits and generating the word line driving signal RWL during read operations; the level converter group is responsible for converting the low-voltage signal RWL generated by the word line decoder into a high-voltage signal WWL to drive the word lines during write operations; the read / write selection circuit selects the word line driving of the array according to the read enable signal ReadEN and the write enable signal WriteEN.

10. The asymmetric write dual-voltage magnetic random access memory structure according to claim 1, characterized in that, The control circuit includes: a set of flip-flops and a logic circuit; the set of flip-flops is controlled by a clock signal CLK and is responsible for latching externally input data, address and enable signal, as well as internally output data on the rising edge of the clock signal; the logic circuit is responsible for generating a read enable signal ReadEN and a write enable signal WriteEN based on the latched enable signal.

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