Methods, apparatus and systems for driving transistors

Abstract

Methods, apparatus, and systems for driving transistors are described. An example apparatus includes a regulator (505) comprising a first input terminal (522), a first output terminal (524), and a second output terminal (528) adapted to be coupled to a control terminal (172) of a transistor (150); a first stage (510) comprising a first input terminal (530) coupled to the first output terminal of the regulator and an output terminal (534) adapted to be coupled to the control terminal of the transistor; and a second stage (515) comprising an input terminal (536) coupled to the second output terminal of the regulator and an output terminal (538) adapted to be coupled to the control terminal of the transistor.

Description

Technical Field

[0001] This description generally relates to transistors, and more specifically to methods, apparatus, and systems for driving transistors. Background Technology

[0002] In some applications, transistors such as field-effect transistors (FETs) or metal-oxide-semiconductor field-effect transistors (MOSFETs) are connected to a load via an inductor. The transistor can be controlled to supply current to the load using a pulse-width modulation (PWM) signal provided to its gate. Summary of the Invention

[0003] One aspect of this disclosure relates to an apparatus for driving a transistor, comprising: a regulator including: a first input terminal adapted to be coupled to a control terminal of the transistor; a first output terminal; a second output terminal; and a comparator circuit including an input terminal adapted to be coupled to an output terminal of a linear regulator circuit, a first output terminal coupled to a second output terminal of the regulator, and a second output terminal coupled to a logic gate; a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal coupled to the first input terminal of the regulator; and a second stage including an input terminal coupled to the second output terminal of the regulator and an output terminal coupled to the first input terminal of the regulator.

[0004] Another aspect of this disclosure relates to an apparatus for driving a transistor, comprising: a first stage including an input terminal and an output terminal adapted to be coupled to a control terminal of the transistor, the first stage being adapted to enable the transistor using a first voltage from a first voltage source; a second stage including an input terminal and an output terminal adapted to be coupled to the control terminal of the transistor, the second stage being adapted to enable the transistor using a second voltage from a second voltage source, the first voltage having a greater potential than the second voltage; and a regulator including a first input terminal and a second input terminal adapted to be coupled to the control terminal of the transistor, a first output terminal coupled to the input terminal of the first stage, and a second output terminal coupled to the input terminal of the second stage, the regulator being adapted to: enable the first stage based on an activation signal obtained at the second input terminal of the regulator exceeding a first threshold voltage level; and enable the second stage based on a voltage signal at the first input terminal of the regulator exceeding a second threshold voltage level for a period of time; and wherein the regulator is adapted to be coupled to a clamping voltage source, and the regulator is configurable to disable the first stage based on the voltage signal at the first input terminal of the regulator exceeding a voltage of the clamping voltage source.

[0005] Another aspect of this disclosure relates to an electrical system comprising: a transistor including a control terminal; and a driver including: an input terminal adapted to receive an activation signal; an output terminal coupled to the control terminal of the transistor; a first stage including an input terminal and an output terminal coupled to the control terminal of the transistor; a second stage including an input terminal and an output terminal coupled to the control terminal of the transistor; and a regulator including: a first input terminal coupled to the control terminal of the transistor; a second input terminal; a first output terminal coupled to the input terminal of the first stage; and a second output terminal coupled to the input terminal of the second stage, wherein the regulator is configurable to: enable the first stage based on an activation signal obtained at the second input terminal of the regulator exceeding a first threshold voltage level; and enable the second stage based on a voltage signal at the first input terminal of the regulator exceeding a second threshold voltage level for a period of time; and wherein the regulator is adapted to be coupled to a clamping voltage source, and the regulator is configurable to disable the first stage based on the voltage signal at the first input terminal of the regulator exceeding a voltage of the clamping voltage source. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an example power converter including a first example driver and a second example driver.

[0007] Figure 2 This is a first schematic diagram of the first driver of the power converter.

[0008] Figure 3 This is a second schematic diagram of the second driver of the power converter.

[0009] Figure 4 This is the third schematic diagram of the third driver of the power converter.

[0010] Figure 5 yes Figure 1 A block diagram of an example implementation of a first driver adapted to enable a transistor in response to an input signal at an input terminal.

[0011] Figure 6 yes Figure 1 and / or Figure 5 A schematic diagram illustrating an example implementation of the first driver.

[0012] Figure 7A and Figure 7B yes Figure 1 , Figure 5 and / or Figure 6A schematic diagram of an example implementation of the first driver, including Figure 6 The additional logic circuit system described in the implementation method.

[0013] Figure 8 yes Figure 1 , Figure 5 and / or Figure 6 A schematic diagram of an example implementation of the first driver, including Figure 6 The additional logic circuit system described in the implementation method.

[0014] Figure 9 It is a flowchart representing a sample process that can be implemented using logic or machine-readable instructions that can be executed to implement the sample driver.

[0015] Figure 10 This is a schematic diagram of an example analog stand for the driver in an example power converter.

[0016] Figure 11 It is a signal diagram depicting the first current signal of the first transistor enabled by the first driver and the second current signal of the second transistor enabled by the second driver in a power conversion system under various voltage offsets.

[0017] Figure 12 It is a signal diagram depicting the first slew rate of a transistor enabled by a first driver and the second slew rate of a transistor enabled by a second driver in a power conversion system under various voltage offsets.

[0018] Figure 13 It is a signal diagram depicting the first current signal of a transistor enabled by a first driver and the second current signal of a second transistor enabled by a second driver in a power conversion system with various driver resistors.

[0019] Figure 14 It is a signal diagram depicting the first conversion rate of a transistor enabled by a first driver and the second conversion rate of a transistor enabled by a second driver in a power conversion system with various driver resistors.

[0020] Figure 15 It is a description Figure 1 The example power converter shows the control signals and output signals during the operation of the driving transistor. Detailed Implementation

[0021] The accompanying drawings are not to scale. Generally, the same reference numerals will be used throughout the drawings and the accompanying written description to refer to the same or similar workpieces. As used herein, references to connections (e.g., attachment, coupling, connection, and link) will be interpreted in accordance with the language of the specification and the relevant claims. The interpretation of connection references in this application should be consistent with the language of the claims and the context of the specification describing the purpose of connecting various elements. Therefore, connection references do not necessarily imply that two elements are directly connected or connected to each other in a fixed relationship.

[0022] When identifying multiple elements or parts that can be referenced separately, descriptors such as “first,” “second,” “third,” etc., are used herein. Unless otherwise specified or understood based on the context in which these descriptors are used, such descriptors do not imply any priority, physical order, or arrangement or chronological order in a list, but are merely labels used to refer to multiple elements or parts separately for ease of understanding of the described examples. In some examples, the descriptor “first” may be used to refer to an element in a detailed description, while the same element may be referred to in the claims using different descriptors such as “second” or “third.” In such cases, such descriptors are used solely for ease of reference to multiple elements or parts.

[0023] Some examples described herein include methods, apparatus, and systems for driving transistors at a controlled conversion rate. Transistors are used, for example, in power conversion circuits, electrical or power adapters, electric vehicle charging units, and electric vehicle components (e.g., battery charging circuits, traction inverters, etc.). Signals (e.g., voltage and / or current) can be applied to the transistor gate (e.g., a control terminal) to enable another signal to pass through another pair of transistor terminals (e.g., from the transistor's source terminal to its drain terminal). Power conversion circuits or power converters are used in applications where a reliable power source may be beneficial. Power converters can be boost converters (e.g., boost converters that produce an output voltage greater than the input voltage), buck converters (e.g., buck converters that produce an output voltage less than the input voltage), and / or combinations thereof.

[0024] To ensure the power converter is an efficient and reliable power source, one or more currents flowing through various parts of the power converter circuit (e.g., inductor current, transistor current, load current, etc.) are regulated by a controller to turn switches on and / or off. The controller monitors these currents to regulate the output voltage, thereby providing a reliable power source. For example, the controller can regulate the load current by adjusting the current through the inductor to ensure the output voltage is within the desired range. The controller can regulate the output voltage by changing the operation of the transistor to regulate the current through the inductor.

[0025] Transistors can be controlled by a driver (e.g., a driver circuit). The driver or driver circuit can enable (e.g., turn on) and disable (e.g., turn off) the transistor in response to a PWM signal generated by a controller (e.g., a control circuit). As described herein, examples of drivers (e.g., driver circuits) include one or more transistors, such as FETs, MOSFETs, or any other switching device, such as bipolar junction transistors (BJTs). However, other switching types or technologies can be used.

[0026] The driver can be configured by the controller to enable and disable the transistor. A power conversion circuit including one or more such drivers can switch between high-side control using a first driver (e.g., enabling the first transistor and disabling the second transistor) and low-side control using a second driver (e.g., disabling the first transistor and enabling the second transistor) to provide a substantially stable or otherwise regulated output voltage.

[0027] In some applications (e.g., power conversion circuits, power conversion systems, etc.), the voltage at the transistor gate (e.g., gate voltage) may not exceed a voltage threshold while remaining in the on-state for extended periods (e.g., linear mode) to ensure reliable transistor operation. When the gate voltage exceeds the normal operating voltage (e.g., 6 volts, 7 volts, etc.) for a short period, the transistor may exceed its normal operating conditions. Transistors operating under normal conditions may have a slew rate. As used herein, the phrase "slew rate" and its variations encompass the change in the amount of electrical quantity (e.g., voltage or current) of a signal per unit time. For example, when a transistor is enabled by a driver, the voltage change at the transistor drain terminal has a slew rate (e.g., 20 volts per nanosecond, 100 volts per nanosecond, etc.). The slew rate of a transistor controls how quickly a signal at the transistor terminals changes to a desired value (e.g., how quickly the transistor is enabled and begins to conduct).

[0028] The slew rate of a transistor can be affected by the signal (e.g., current, voltage, etc.) supplied to the transistor's control terminals. For example, a higher current at the transistor gate can correspond to a higher slew rate, which in turn corresponds to a faster change in the signal at the transistor terminals. Therefore, applications such as power converter circuit systems can benefit from the relatively fast and controlled slew rate of a transistor. In some examples, a transistor with a maximum rated voltage (e.g., 6 volts, 7 volts, etc.) can transition from an off state (e.g., a cutoff mode where no signal flows between the two transistor terminals) to an on state using a signal exceeding the maximum rated voltage (e.g., a linear mode where the signal flows between the two terminals). Because the signal activating the transistor exceeds the maximum rated voltage at the moment the transistor transitions to the on state, the signal slew rate at the two terminals can be controlled to a greater extent. For example, if a transistor has a maximum rated voltage of 6 volts, and a 12-volt signal is applied to the transistor gate until the transistor reaches linear mode, the transistor's slew rate may be greater than that of a transistor enabled with a 6-volt signal. In some examples, because the transistor's control terminals are driven (e.g., a driver holds the transistor's gate terminals at a certain voltage) above the rated voltage for a relatively short period of time (e.g., tens of nanoseconds) to drive the transistor during the switching period, the transistor may not degrade and / or suffer from reduced reliability. Furthermore, the voltage at the transistor's gate can be adjusted (e.g., maintained between 6 and 12 volts, or a clamping voltage of 8 volts, etc.) to achieve higher switching rates and prevent damage to the transistor caused by the enabling transistor (powered by a 12-volt source).

[0029] Some examples described herein include transistors manufactured using gallium nitride (GaN). Furthermore, some examples described herein include the use of GaN transistors and include methods, apparatus, and systems for driving transistors at a controlled slew rate. Some examples described herein include the ability to use current to drive a transistor (e.g., at the transistor gate) to set the transistor's slew rate, and the slew rate can be enabled by a margin higher than the conduction margin (e.g., a voltage of 12 volts at the gate terminal) to prevent damage to the transistor. Some examples described herein include driving the terminal gate with a constant current source based on a voltage level exceeding the normal operating voltage level while the transistor is in the conduction state. Some examples described herein include clamping (e.g., regulating) a higher gate signal during the transistor's transition to the conduction state to protect the transistor from stress. For example, the driver may include a regulator to enable and / or disable control signals (e.g., current signals) provided to the gate terminal in response to the voltage at the gate terminal exceeding a clamping voltage (e.g., 8 volts). Some examples described herein include a relatively weak pull-up transistor to maintain the transistor's gate signal at its maximum rated voltage (e.g., 6 volts) to prevent stress on the transistor after it has been enabled by a current source. In some of the examples described herein, the gate drive current and / or the current supplied by the driver to the terminal gate is programmable over a wide range.

[0030] In some examples, the regulator may provide a first trigger signal to a first stage in the driver to enable the transistor under the current supplied by a first voltage source node. In response to a signal at the transistor control terminal exceeding a threshold voltage value, the regulator may disable the first stage after a delay and provide a second trigger signal to a second stage in the driver to enable the transistor (e.g., keep it in the on state) under the current supplied by a second voltage source node. The first voltage source node may include a potential greater than that of the second voltage source node (e.g., 6 volts, 7 volts, etc., e.g., a potential of 12 volts, etc.).

[0031] Figure 1 This is a schematic diagram of an example power converter 100 including a first example driver 105 and a second example driver 110. The power converter 100 includes a first driver 105, a second driver 110, a controller 120, and an inverter 125. The power converter 100 is adapted to be coupled to an example bus voltage node 140, an example ground node 145, and an example load 146. Figure 1In the topology, power converter 100 is adapted and / or otherwise configured to drive load 146 (e.g., to power load 146 and / or provide it with an output signal). For example, load 146 may correspond to an electric vehicle, one or more batteries in the electric vehicle, an electronic control unit (ECU), an electric motor in the electric vehicle, a traction inverter included in the electric vehicle, and / or combinations thereof. Power converter 100 includes an example capacitor 147, an example inductor 148, a first example transistor 150, and a second example transistor 151.

[0032] Controller 120 has an output coupled to example output terminal 154. First driver 105 has a first input coupled to example input terminal 156. Input terminal 156 is configured to be coupled to output terminal 154 to obtain an activation signal (IN) from controller 120. First driver 105 has a first output coupled to example output terminal 158. Second driver 110 has a second input coupled to example input terminal 160. Input terminal 160 is configured to be coupled to the output of inverter 125 to obtain an inverted activation signal (nIN). Second driver 110 has a second output coupled to example output terminal 162. First transistor 150 has a control terminal 172 (e.g., a gate terminal), a source terminal 174 (e.g., a first current terminal) coupled to ground node 145, and a drain terminal 176 (e.g., a second current terminal) coupled to inductor 148. The control terminal 172 is coupled to output terminal 158 to switch to an on state in response to obtaining one or more control signals from first driver 105. The second transistor 151 has a control terminal 186 coupled to the output terminal 162 of the second driver 110, a source terminal 188 coupled to the inductor 148, and a drain terminal 190 coupled to the bus voltage node 140. Figure 1 In the topology, bus voltage node 140 provides voltage signals (such as signal VIN).

[0033] Inverter 125 is coupled between output terminal 154 and input terminal 160 of second driver 110. Inductor 148 is coupled to source terminal 188 of second transistor 151 and to drain terminal 176 of first transistor 150. Capacitor 147 is coupled between inductor 148 and ground node 145. Load 146 (e.g., an electronic device to be powered, industrial terminal equipment, etc.) is coupled between inductor 148 and ground node 145.

[0034] exist Figure 1In the example, the first driver 105 controls the on state (e.g., on or off) of the first transistor 150, and the second driver 110 controls the on state of the second transistor 151. However, drivers 105 and 110 can control the on state of any number of transistors or switches. Furthermore, any number of drivers can control the on state of transistors. For example, the first driver 105 can switch the first transistor 150 from a non-conducting state to a conducting state, and the second driver can be coupled to control terminal 172 to switch the first transistor 150 from a conducting state to a non-conducting state.

[0035] The first transistor 150 is an n-channel metal-oxide-semiconductor (NMOS) field-effect transistor. Alternatively, the first transistor 150 may be a p-channel metal-oxide-semiconductor (PMOS) field-effect transistor, a bipolar junction transistor (BJT), or any other three-terminal device. Similarly, the second transistor 151 is an NMOS field-effect transistor. Alternatively, the second transistor 151 may be a PMOS field-effect transistor, a BJT, or any other three-terminal device. As used herein, the phrase "NMOS transistor" and variations thereof include NMOS field-effect transistors (FETs), GaN transistors, silicon carbide (SiC) transistors, etc. Similarly, as used herein, the phrase "PMOS transistor" and variations thereof include PMOS field-effect transistors, GaN transistors, SiC transistors, etc.

[0036] In operation, controller 120 generates an activation signal (e.g., a PWM signal, voltage signal IN, etc.) at output terminal 154. Controller 120 regulates the load voltage of the power converter at load 146. In some examples, controller 120 regulates the load voltage to maintain a maximum or minimum allowable voltage, regulates the load current, and / or limits the maximum positive current and / or minimum negative current of inductor 148 to avoid damage to load 146 and / or more generally, to avoid damage to power converter 100. Furthermore, controller 120 controls the on / off state (e.g., on or off) of first transistor 150 and second transistor 151 by providing an activation signal (IN) to drivers 105, 110. Controller 120 can be implemented using a state machine, microcontroller, multiple discrete components, or any other suitable device in a hardware implementation manner.

[0037] Inverter 125 responds to changes in the control signal provided by controller 120 and generates an inverted signal (e.g., a voltage signal nIN). As used herein, an inverter (e.g., inverter 125) includes a control circuitry to respond to an activation signal and provide (e.g., output) an inverted signal to second driver 110. For example, if controller 120 generates a 5-volt activation signal (IN) voltage at the input terminal of inverter 125, inverter 125 can provide a 0-volt activation signal (nIN) voltage to second driver 110.

[0038] In some examples, other components, such as level-shifting circuitry or digital buffers, may be coupled to the output terminal 154 of controller 120 and / or to the input terminal of first driver 105 or second driver 110. For example, a level-shifting circuitry may be coupled to the output terminal 154 of controller 120 to shift the voltage of a control signal (such as signal IN) to a higher voltage amplitude. In some examples, inverter 125 may be additionally or alternatively coupled to the input terminal 156 of first driver 105.

[0039] Any other method of providing signals (e.g., activation signals, signal IN, etc.) at input terminal 156 of the first driver 105 and / or input terminal 160 of the second driver 110 may be used additionally or alternatively. For example, controller 120 may include a control circuitry (such as an inverter) to generate activation signals (such as signal IN or signal nIN), and controller 120 may include a first output terminal to be coupled to input terminal 156 and a second output terminal to be coupled to input terminal 160.

[0040] In some examples described herein, the first driver 105 and the second driver 110 enable and / or disable transistors (such as the first transistor 150 or the second transistor 151) in response to changes in an activation signal (IN) generated by the controller 120. In some examples, when the first driver 105 disables the first transistor 150, the second driver 110 enables the second transistor 151, and when the second driver 110 disables the second transistor 151, the first driver 105 enables the first transistor 150. Drivers 105 and 110 may be configured to enable and / or disable transistors 150 and 151 to regulate the power signal supplied to the load 146 (e.g., the current through the inductor 148).

[0041] The first driver 105 responds to a change in an activation signal obtained at input terminal 156 by providing at least one control signal to the first transistor 150. In some examples described herein, the first driver 105 provides (e.g., pass, output, transmit, etc.) a first control signal to switch the first transistor 150 from a non-conducting state to a conducting state, and provides a second control signal to the first transistor 150 for maintaining it in the conducting state. Similarly, the second driver 110 responds to a change in an activation signal (e.g., signal nIN) modified by inverter 125 by providing at least one control signal to the second transistor 151.

[0042] In some examples, the first driver 105 and / or the second driver 110 include a first stage and a second stage driven by different voltage levels to enable transistors 150, 151. For example, the first driver 105 may include a first stage adapted to be coupled to a 12-volt power supply and a second stage adapted to be coupled to a 6-volt power supply. The first driver 105 may include a regulator for enabling the first stage, and the first stage may provide a gate drive current supplied by the 12-volt power supply to control terminal 172. The regulator may then disable the first stage and enable the second stage, and the second stage may provide a gate drive current supplied by the 6-volt power supply to control terminal 172. Any number of control signals may be additionally or alternatively provided by any of the drivers 105, 110 to any of the transistors 150, 151. For example, the first driver 105 may provide a third control signal to the first transistor 150 to switch the first transistor 150 from a conducting state to a non-conducting state.

[0043] exist Figure 1 In the illustrated example, the first driver 105 responds to an activation signal exceeding a threshold voltage level (such as a logic high level, a voltage corresponding to logic "1", etc.) by enabling the first transistor 150. In some examples, the first driver 105 disables the first transistor 150 when the signal IN does not exceed the threshold voltage level. Similarly, the second driver 110 responds to a signal change at input terminal 160. The second driver 110 responds to a signal provided by inverter 125 by enabling the second transistor 151 in response to a signal nIN exceeding a threshold voltage level. In some examples, the second driver 110 disables the second transistor 151 when the signal nIN does not exceed the threshold voltage level. In some examples, the power converter 100 may include more than two drivers and / or more than two transistors to regulate the power signal supplied to load 146.

[0044] Ground node 145 provides a reference voltage (e.g., 0 volts) for power converter 100. In some examples, ground node 145 may be coupled to earth, digital ground, or analog ground. In other examples, ground node 145 may be coupled to the source node voltage to provide a reference voltage (such as 1 volt).

[0045] Inductor 148 is an electrical component with two ends that stores energy in a magnetic field when current flows through it. During high-level operation, energy is stored in inductor 148 when second transistor 151 is turned on (e.g., enabled) and first transistor 150 is not turned on (e.g., disabled). During low-level operation, energy is discharged from inductor 148 to ground through first transistor 150 when first transistor 150 is turned on and second transistor 151 is not turned on.

[0046] Capacitor 147 is an electrical component with two ends that stores energy in an electric field. During high-level operation, energy is stored in capacitor 147 when second transistor 151 is turned on and first transistor 150 is not turned on. During low-level operation (e.g., when first transistor 150 is turned on), energy is discharged from capacitor 147 to load 146.

[0047] Figure 2 This is a first schematic diagram 200 of a driver 205 in a power converter. The first schematic diagram 200 includes a driver 205, a first transistor 210, a first voltage source node 215, a second voltage source node 220, a third voltage source node 225, and a ground node 230. The driver 205 includes an inverting level shifter 235, a second transistor 240, an inverter driver 245, and a third transistor 250. The first transistor 210 is an NMOS transistor, the second transistor 240 is a PMOS transistor, and the third transistor 250 is an NMOS transistor. The first transistor includes a control terminal 260 and a source terminal 262. The source terminal 262 is coupled to the ground node 230.

[0048] Inverter driver 245 inverts signal IN and sends the inverted voltage signal to second transistor 240. When the voltage of signal IN is 5 volts, inverter driver 245 provides a 0-volt signal. When the voltage of signal IN is IN, inverter driver 245 provides a 5-volt signal. Inverter driver 245 enables and disables third transistor 250 in response to changes in signal IN.

[0049] During the on-state (e.g., when the signal IN has 5 volts), the second transistor 240 is enabled (e.g., turned on) and the third transistor 250 is disabled (e.g., not turned on). As a result, the first transistor 210 is enabled during the on-state. During the off-state (e.g., when the signal IN has 0 volts), the second transistor 240 is disabled and the third transistor 250 is enabled. As a result, the first transistor 210 is disabled during the off-state.

[0050] Figure 2 The driver 205 is configured to transmit a control signal to the first transistor 210, which is provided by the first voltage source node 215 (e.g., by the voltage of VDRV, 6 volts). Furthermore, in Figure 2 In the circuit, the PMOS pull-up (e.g., the second transistor 240) has a large and therefore inefficient die area. Because the driver 205 is powered by VDRV (e.g., 6 volts), the gate of the first transistor 210 (e.g., the voltage at the control terminal 260) reaches the maximum voltage of VDRV (e.g., 6 volts).

[0051] When driving transistors, an example formula for calculating the margin is shown in Formula 1 below:

[0052] Formula 1

[0053] In the example of Formula 1, This indicates a margin (e.g., threshold voltage) for the control terminal (such as control terminal 260) of a transistor (such as transistor 210) having a finite switching rate. This indicates the voltage at the first voltage source node 215 (such as VDRV, 6 volts, etc.), and This represents the difference between the voltage at the gate terminal (such as control terminal 260) and the voltage at the source terminal (such as source terminal 262). As used herein and as shown in Formula 1 above, the phrase "transistor margin" or variations thereof includes (1) the voltage driving the transistor (e.g., VDRV) and (2) the difference between the voltage at the gate terminal and the voltage at the source terminal. In some examples, a larger voltage driving the transistor, such as 12 volts compared to 6 volts, results in a larger transistor margin and thus allows the transistor to turn on at a greater slew rate. In some examples, the transistor margin controls the current (e.g., gate current, gate drive current, output current, etc.) that the driver can provide when driving (e.g., transitioning) the transistor to an enabled state. Therefore, the driver margin controls the slew rate of the transistor when it transitions to the enabled phase. In some examples, such as the following combination Figures 5 to 8In the described example, the first transistor can be enabled by a first voltage source (such as 12 volts) at the control terminal, and the second transistor can be enabled by a second voltage source (such as 6 volts) at the control terminal. Because the first transistor is powered at the control terminal by a first voltage source having a larger potential than the second transistor, the first transistor includes a larger margin than the second transistor. Therefore, when transitioning to the enabled state, the slewing rate of the first transistor can be greater than that of the second transistor.

[0054] exist Figure 2 In the example, driver 205 provides transistor 210 with a control signal (such as a current signal) provided by the voltage (VDRV) supplied by the first voltage source node 215, and the voltage (VDRV) is the maximum rated voltage of transistor 210, such as 6 volts. Therefore, the gate of the second transistor 210 is limited to VDRV while transitioning to the enabled state, thus limiting the slewing rate of the second transistor 210. Furthermore, in Figure 2 In the example, the area of ​​transistor 240 may be larger than... Figure 3 , Figure 4 and / or Figure 8 The topology has a large area, and therefore the efficiency is low in terms of die area, as described below.

[0055] Figure 3 This is a second schematic diagram 300 of the driver 305 in the power converter. The second schematic diagram 300 includes the driver 305, a first transistor 310, a first voltage source node 315, a second voltage source node 320, a third voltage source node 325, and a ground node 330. The driver 305 includes an inverting level shifter 335, a buffer 340, a second transistor 342, a first inverter 344, a third transistor 346, a fourth transistor 348, a second inverter 350, and a fifth transistor 352. The first transistor 310 is an NMOS transistor, the second transistor 342 is a PMOS transistor, the third transistor 346 is an NMOS transistor, the fourth transistor 348 is an NMOS transistor, and the fifth transistor 352 is an NMOS transistor. The first transistor 310 includes a control terminal 353.

[0056] Inverting level shifter 335 amplifies the signal IN, inverts the shifted voltage signal, and provides the inverted voltage signal to buffer 340. Buffer 340 removes glitches (e.g., unwanted signal transitions) from the inverted voltage signal obtained from inverting level shifter 335 and provides the voltage signal to a coupling component (e.g., second transistor 342) at an output impedance level lower than the output impedance level of buffer 340. Inverting level shifter 335 and buffer 340 enable and disable second transistor 342 in response to changes in signal IN. First inverter 344 inverts a voltage signal (e.g., voltage signal IN) and provides the inverted voltage signal to third transistor 346. First inverter 344 enables and disables third transistor 346 in response to changes in signal IN. Second transistor 342 and third transistor 346 enable and disable fourth transistor 348 in response to changes in the signals provided by buffer 340 and first inverter 344.

[0057] The second inverter 350 inverts a voltage signal (e.g., signal IN) and provides the inverted voltage signal to the fifth transistor 352. The second inverter 350 enables and disables the fifth transistor 352 in response to changes in signal IN. During the on-state (e.g., signal IN has a voltage of 5 volts), the second transistor 342 is on, while the third transistor 346 is off. As a result, the fourth transistor 348 is on. Furthermore, the fifth transistor 352 is off. Because the fourth transistor 348 is on and the fifth transistor 352 is off, the first transistor 310 is on.

[0058] During the off state (e.g., when the signal IN has 0 volts), the second transistor 342 is not turned on, while the third transistor 346 is turned on. As a result, the fourth transistor 348 is not turned on. Furthermore, the fifth transistor 352 is turned on. Because the fourth transistor 348 is not turned on and the fifth transistor 352 is turned on, the first transistor 310 is not turned on.

[0059] Figure 3 The driver 305 shown enables the first transistor 310 via a first voltage source node 315 (e.g., powered by VDRV). Therefore, the voltage at the gate of the first transistor 310 (e.g., the maximum gate voltage) is limited by the voltage signal VDRV, thereby limiting the slewing rate of the first transistor 310.

[0060] exist Figure 3In the example, driver 305 provides a control signal (such as a current signal) to first transistor 310 based on the voltage (VDRV) provided by first voltage source node 315, and the voltage (VDRV) is the maximum rated voltage of first transistor 310, such as 6 volts. Therefore, the gate of first transistor 310 is limited to VDRV while transitioning to the enabled state, thus limiting the transistor's slewing rate. Furthermore, in Figure 3 In the example, the control terminals of transistors 310 and 348 are limited to VDRV. Therefore, the drive current supplied to the first transistor 310 can decrease as the control terminal of the first transistor 310 increases. When the first transistor 310 supplies a large current, the slewing rate of the first transistor 310 may be limited because the voltage at the first transistor 310 ( (Higher due to high current)

[0061] Figure 4 This is a third schematic diagram 400 of a driver 402 in a power converter. Driver 402 is adapted to receive an input signal (e.g., a voltage signal IN), and driver 402 enables and disables a first transistor 404 in response to changes in the signal IN. Driver 402 includes a single-pulse generator 412, a first buffer 414, a second transistor 416, a second buffer 418, a third transistor 420, a current source 422, a first current mirror circuit 424, and a second current mirror circuit 426. The third schematic diagram 400 includes a first voltage source node 428, a second voltage source node 430, and a ground node 432. The first transistor 404 and the third transistor 420 are NMOS transistors, while the second transistor 416 is a PMOS transistor. The first transistor 404 includes a control terminal 436, a drain terminal 438, and a source terminal 440 coupled to the ground node 432.

[0062] A single-pulse generator 412 and a first buffer 414 enable and disable a second transistor 416 in response to changes in the signal IN. The second transistor 416 enables the first transistor 404. When the signal IN transitions to an on state (e.g., from 0 volts to 5 volts), the single-pulse generator 412 generates a pulse signal. The first buffer 414 receives the pulse signal, modifies the pulse signal (e.g., removes glitches from the pulse signal), and transmits the modified pulse signal to the second transistor 416. In response to the modified pulse signal, the second transistor 416 becomes disabled (e.g., initially not conducting). When the second transistor 416 is not conducting, the first transistor 404 may be turned on (e.g., enabled by the second current mirror circuit 426, as described below) or not turned on (e.g., not enabled by the second current mirror circuit 426).

[0063] The first current mirror circuit 424 includes a first terminal 454 coupled to the third transistor 420 and a second terminal 456. The second current mirror circuit 426 includes a first terminal 458 coupled to the second terminal 456 of the first current mirror circuit 424. The second current mirror circuit 426 includes a second terminal 460 coupled to the first transistor 404. In operation, when the signal IN transitions to an on state (e.g., from 0 volts to 5 volts), the single-pulse generator 412 generates a pulse signal. The second buffer 418 receives the pulse signal, modifies the pulse signal (e.g., removes glitches from the pulse signal), and provides the modified pulse signal to the third transistor 420. As a result, in response to receiving the modified pulse signal, the third transistor 420 is enabled (e.g., begins to conduct).

[0064] When the third transistor 420 is enabled, the current source 422 supplies current to the first current mirror circuit 424. The first current mirror circuit 424 mirrors the current from the first terminal 454 to the second terminal 456. The second current mirror circuit 426 receives the current at the first terminal 458 and mirrors the current at the second terminal 460 (and the control terminal 436). As a result, the first transistor 404 is enabled and begins to conduct.

[0065] During operation, the single-pulse generator 412 generates a pulse in response to the voltage of the signal IN exceeding a threshold. The first buffer 414 provides an output signal to the second transistor 416, thus de-energizing the second transistor 416. The second buffer 418 receives the output signal from the single-pulse generator 412 and generates an output signal to enable the third transistor 420 (e.g., turning on the third transistor 420). In response to the third transistor 420 turning on, a current signal is generated by the current source node 422 at the first terminal 454 of the first current mirror circuit 424. Therefore, the first current mirror circuit 424 generates a current signal at the second terminal 456. The second current mirror circuit 426 receives the current signal at the first terminal 458 and generates an output signal at the second terminal 460 (e.g., the control terminal 436 of the first transistor 404). In response to the output signal of the second current mirror circuit 426, the first transistor 404 is enabled by the first voltage source node 428 (e.g., a node coupled to the first current mirror circuit 424) and by the second voltage source node 430 (e.g., a node coupled to the second current mirror circuit 426).

[0066] After the single-pulse generator 412 has generated an output signal pulse (e.g., the voltage generated by the single-pulse generator 412 is 0 volts), the third transistor 420 is disabled (e.g., not turned on). As a result, the first current mirror circuit 424 does not generate an output signal at the second terminal 456, and the second current mirror circuit 426 does not generate an output signal at the second terminal 460. Since the output of the first buffer 414 is low (preferably around 0 volts), the second transistor 416 begins to turn on. As a result, the first transistor 404 is enabled by the second voltage source node 430 (e.g., the node coupled to the second transistor 416).

[0067] Under certain operating conditions, the second current mirror circuit 426 generates a current signal based on a current signal obtained from the first current mirror circuit 424 (e.g., from a circuit operating at a potential of 12 volts). As a result, the control terminal 436 of the first transistor 404 is limited to VDRV (e.g., 6 volts) during the transition to the conduction phase. However, the maximum voltage of the gate of the first transistor 404 is limited because the second current mirror circuit 426 (e.g., transistor 482 included in the second current mirror circuit 426) is coupled to the second voltage source node 430 (e.g., 6 volts). Therefore, the gate terminal (e.g., control terminal 436) of the first transistor 404 is limited and cannot provide a large slewing rate.

[0068] exist Figure 4 In the example, the second terminal 460 of the second current mirror circuit 426 is limited to VDRV. Therefore, the maximum voltage of the control terminal 436 is limited when transitioning to the enable state. Because the first transistor 404 may require a voltage greater than VDRV (e.g., the maximum rated voltage of the first transistor 404) during state transitions to maintain a high slew rate, the second current mirror circuit 426 (e.g., the transistor coupled between the second voltage source node 430 and the second terminal 460) and / or the first transistor 404 may deplete the margin provided by VDRV, thus failing to maintain a high slew rate (e.g., due to weak and / or thermal corners).

[0069] Figure 5 yes Figure 1 A block diagram of an example implementation 500 of a first driver 105, the driver 105 being adapted to respond to an input terminal (e.g., Figure 1 The input signal (e.g., signal IN) at the input terminal 156 enables the transistor (e.g., Figure 1 Transistor 150). Implementation method 500 includes Figure 1 The device includes a driver 105, a ground node 145, an input terminal 156, an output terminal 158, and a transistor 150. The transistor 150 includes... Figure 1The control terminal 172, source terminal 174, and drain terminal 176. Figure 5 In the example shown, the first driver 105 includes an example regulator 505, a first example stage 510, and a second example stage 515. Figure 5 In the topology, the first driver 105 is adapted to couple to a first example voltage source node 516 and a second example voltage source node 518. In some examples described herein, the first voltage source node 516 is coupled to a first voltage source, while the second voltage source node 518 is coupled to a second voltage source. The first voltage source may have a first potential higher than the second potential of the second voltage source. For example, the first voltage source node 516 may be coupled to a first voltage source having a 12-volt potential, while the second voltage source node 518 may be coupled to a second voltage source having a VDRV (e.g., 6 volts). Voltage source nodes 516, 518 may include voltage sources. For example, the first voltage source node 516 may include a voltage source configured to deliver a 10-volt potential.

[0070] Figure 5 The first driver 105 can respond to a change in the activation signal (e.g., signal IN exceeding a voltage threshold) by providing a first control signal to the output terminal 158 and the control terminal 172 to enable the transistor 150 (e.g., transistor 150 begins to conduct). The first control signal can be provided by the first stage 510 as a voltage and / or current from the first voltage source node 516. In response to the voltage at the output terminal 158, the first driver 105 can provide a second control signal instead of the first control signal to enable the transistor 150. The second control signal can be provided by the second stage 515 as a voltage and / or current from the second voltage source node 518, and the first voltage source node 516 (e.g., a first voltage source) can include a higher potential (e.g., electrical potential) than the second voltage source node 518 (e.g., a second voltage source). For example, the first voltage source node 516 can provide a voltage of 12 volts, while the second voltage source node 518 can provide a voltage of 6 volts. In some examples, the first driver 105 may include additional and / or alternative circuitry based on... Figure 1 The controller 120 provides a change in the activation signal (such as a decrease) to disable the transistor 150.

[0071] In operation, regulator 505 may be adapted to enable first stage 510 by providing a first trigger signal to first stage 510. First stage 510 may be adapted to enable transistor 150 by current from a first voltage source (e.g., a first control signal, gate drive current, current signal) (e.g., current from first voltage source node 516). First stage 510 may be adapted to enable transistor 150 by providing a first control signal to control terminal 172 of transistor 150 in response to the first trigger signal provided by regulator 505 exceeding a threshold voltage level (e.g., logic high, 3 volts, etc.). Regulator 505 may be adapted to regulate the output of first stage 510 (e.g., the first control signal, gate drive current, etc.) by providing a regulation signal to first stage 510 in response to the voltage at control terminal 172 exceeding a voltage threshold. For example, if the voltage at control terminal 172 exceeds the clamping voltage provided by a clamping voltage source (e.g., 8 volts), regulator 505 may provide a regulation signal at second output terminal 526 to regulate the voltage at control terminal 172 to the clamping voltage. The regulator 505 may be adapted to disable the first stage 510 by providing a logic output signal at the first input terminal 530 in response to a signal (e.g., current and / or voltage) at the second input terminal 522 exceeding the clamping voltage for a certain amount of time (e.g., a period of time after the voltage exceeds the clamping voltage by 50 nanoseconds).

[0072] In operation, regulator 505 can be configured to enable second stage 515 by transmitting and / or otherwise delivering a second trigger signal to second stage 515. Second stage 515 can be adapted to enable transistor 150 by providing current from a second source (e.g., second voltage source node 518). Second stage 515 can be adapted to enable transistor 150 by providing a second control signal to control terminal 172 of transistor 150 in response to a first trigger signal provided by regulator 505 exceeding a threshold voltage level (e.g., logic high, 2 volts).

[0073] In some examples described herein, the first voltage source node 516 may provide a higher voltage (e.g., 12 volts) than the second voltage source node 518 to increase the margin of transistor 150 during switching, such as during transition to an enable state. In some examples described herein, the first driver 105 may include a fast current source pull-up (e.g., a transistor and / or a first stage) to set, determine, and / or otherwise regulate the switching rate of transistor 150 while limiting the voltage at control terminal 172. Advantageously, the first driver 105 may limit the voltage at control terminal 172 to prevent damage to transistor 150 during transition to an enable state. In some examples described herein, the first driver 105 may disable the fast pull-up (e.g., a transistor and / or a first stage) after the voltage at control terminal 172 reaches a plateau voltage (e.g., a clamping voltage). In some examples described herein, the first driver 105 may include a weak pull-up (e.g., a transistor and / or a second stage) to hold control terminal 172 at a DC operating voltage, such as the transistor's maximum rated voltage, VDRV, 6 volts, etc.

[0074] During operation, because the first driver 105 provides the transistor 150 with a control signal supplied by the first voltage source node 516, which includes a potential greater than that of the second voltage source node 518, the output stage margin (the margin of transistor 150 provided by the first driver 105) is not limited to VDRV during transition to the enable state. Furthermore, during operation, the first driver 105 can limit the control terminal 172 to an operating voltage (e.g., 6 volts, VDRV, etc.) to keep transistor 150 in a stable state without damaging it. In some examples described herein, a significant portion of the charge (e.g., voltage) at the control terminal 172 may be supplied by the first voltage source node 516 rather than the second voltage source node 518. Therefore, the second voltage source node 518 may not need to supply a large current during operation.

[0075] Advantageously, by driving (e.g., enabling) control terminal 172 supplied by a current source (e.g., IDRV) from the high-voltage rail (e.g., first voltage source node 516), more margin can be provided to transistor 150 to achieve a high slew rate. Furthermore, a fast voltage regulation loop (e.g., regulator 505) can be included in the first driver 105 to limit the gate voltage (e.g., the voltage at control terminal 172) transiently (e.g., during transition to an enabled state). A gate voltage detector (e.g., regulator 505, linear regulator, and / or comparator circuitry) can be included in the first driver 105 to turn off (e.g., disable) the fast pull-up drive (e.g., first stage 510) and enable the weak pull-up (e.g., second stage 515) to achieve long-term reliability and low power consumption. Advantageously, in some examples described herein, the first driver 105 can provide a constant and / or consistent slew rate at process corners and / or temperatures.

[0076] In some examples, transistor 150 may transition to an enabled state in response to a first control signal for a shorter time period than in response to a second control signal. For example, transistor 150 may transition at a first slew rate in response to a first control signal, and then transistor 150 may transition at a second slew rate in response to a second control signal, and the first slew rate may be greater than the second slew rate. In some examples, transistor 150 may be damaged and / or destroyed if driven by the first control signal (such as enabling) for an extended period of time. Because the first driver 105 modulates the first control signal (e.g., disables the first control signal) and enables the second control signal, keeping transistor 150 in an enabled state, the first driver 105 enables transistor 150 to begin conducting at a slew rate provided by the first voltage source node 516 that is greater than the slew rate provided by the second voltage source node 518 and / or to enable transistor 150 for a period of time without reducing the operability of transistor 150 (e.g., without damaging transistor 150 during operation).

[0077] exist Figure 5In the illustrated example, regulator 505 has and / or otherwise includes a first input terminal 520, a second input terminal 522, a first output terminal 524, a second output terminal 526, and a third output terminal 528. The first input terminal 520 is configured to couple to input terminal 156 of driver 105 to receive an activation signal (IN). Regulator 505 is adapted to receive the activation signal (e.g., the signal IN provided by controller 120). In some examples, regulator 505 enables first stage 510 by transmitting a first trigger signal at first output terminal 524 and enables second stage 515 by transmitting a second trigger signal at third output terminal 528. Regulator 505 enables first stage 510 to enable transistor 150 in response to the activation signal exceeding a threshold voltage level (such as a logic high threshold). In some examples, regulator 505 provides an adjustment signal to first stage 510 at second output terminal 526, and first stage 510 can change a first control signal provided to output terminal 158 in response to the adjustment signal.

[0078] Regulator 505 enables second stage 515 in response to a signal (e.g., a voltage signal) obtained at second input terminal 522. For example, if the voltage obtained at second input terminal 522 (such as at output terminal 158 and / or control terminal 172) exceeds a voltage threshold provided by a clamping voltage source node, regulator 505 may clamp the voltage at control terminal 172 and provide a second trigger signal to second stage 515. In some examples, regulator 505 provides a second trigger signal in response to a voltage obtained at second input terminal 522 exceeding a voltage threshold (such as VCLAMP) for a period of time. In some examples, regulator 505 may change (e.g., terminate) the provision of a first trigger signal, and instead additionally and / or alternatively provide a second trigger signal.

[0079] The first stage 510 has and / or otherwise includes a first input terminal 530 coupled to a first output terminal 524 of the regulator 505 to obtain a first trigger signal, a second input terminal 532 coupled to a second output terminal 526 of the regulator 505 to obtain a regulation signal, and an output terminal 534 coupled to an output terminal 158 of the first driver 105 (e.g., a control terminal 172 coupled to the transistor 150) to provide a first control signal. Figure 5In this configuration, the first stage 510 is adapted to couple to the first voltage source node 516 and the ground node 145. The first stage 510 provides (e.g., outputs) a first control signal at the output terminal 534 (e.g., provided to the output terminal 158 of the first driver 105 and / or to the control terminal 172 of the transistor 150) in response to a first trigger signal obtained at the first input terminal 530 exceeding a threshold voltage level. Therefore, the first stage 510 enables the transistor 150. In some examples, the first stage 510 changes and / or otherwise modifies the first control signal (e.g., disables the first control signal) in response to the first trigger signal not exceeding a voltage threshold such as a logic high voltage threshold. In some examples, the first stage 510 changes the first control signal in response to an adjustment signal obtained at the second input terminal 532.

[0080] The second stage 515 has and / or otherwise includes a third output terminal 528 coupled to the regulator 505 to obtain an input terminal 536 for a second trigger signal and an output terminal 538 coupled at example node 539 to the first stage 510 to provide a second control signal. Figure 5 In this configuration, node 539 is coupled to the second input terminal 522 of regulator 505, the output terminal 158 of first driver 105, and the control terminal 172 of transistor 150. Second stage 515 is adapted to be coupled to a second voltage source node 518 and to ground node 145. Second stage 515 provides a second control signal at output terminal 538 (e.g., provided to output terminal 158 of driver 105 and / or to control terminal 172 of transistor 150) in response to a second trigger signal obtained at input terminal 536 exceeding a threshold voltage level (such as a logic high value). Therefore, second stage 515 can enable transistor 150 in response to a second trigger signal provided by regulator 505 at third output terminal 528 and obtained at input terminal 536. In some examples, second stage 515 provides the second control signal in response to a second trigger signal not exceeding a threshold voltage level such as a logic low value.

[0081] In operation, regulator 505 receives an activation signal at first input terminal 520. In response to the activation signal exceeding a threshold voltage level (such as a logic high level, 5 volts, etc.), regulator 505 transmits and / or otherwise adapts to transmit a first trigger signal to first stage 510 at first output terminal 524. In response to the first trigger signal exceeding the threshold voltage level, first stage 510 provides and / or otherwise adapts to generate a first control signal at output terminal 534 (e.g., provided to node 539, provided to output terminal 158 of driver 105, provided to control terminal 172, etc.) to enable transistor 150 using current supplied by first voltage source node 516. In some examples, regulator 505 provides an adjustment signal to first stage 510 at first output terminal 524 in response to a change in the signal received at second input terminal 522. For example, if the voltage at node 539 exceeds a threshold (such as a clamping voltage threshold), regulator 505 may modify (e.g., reduce and / or disable) the adjustment signal. The first stage 510 can then change (e.g., reduce and / or disable) the first control signal of the enabling transistor 150 in response to a change in the adjustment signal obtained at the second input terminal 532.

[0082] In response to a signal (e.g., a voltage value) at node 539, such as a voltage exceeding a voltage threshold (e.g., a clamping voltage) for a period of time, regulator 505 may provide a second trigger signal to second stage 515 at third output terminal 528. In response to the second trigger signal, second stage 515 may provide and / or otherwise adapt to output a second control signal (e.g., provided to control terminal 172) at output terminal 538 to the driver's output terminal 158, the signal carrying current supplied by the second voltage source node 518. Therefore, transistor 150 is first enabled by the current supplied by first voltage source node 516, and then enabled by the current supplied by second voltage source node 518 (e.g., kept on, held in enabled mode).

[0083] Figure 6 yes Figure 1 and / or Figure 5 A schematic diagram of an example implementation 600 of the first driver 105, which is adapted to respond to an example input terminal (e.g., Figure 1 Example input signal (e.g., activation signal, signal IN, etc.) at example input terminal 156) to enable transistor (e.g., Figure 1 Transistor 150). Figure 6 The implementation methods 600 include Figure 1 and / or Figure 5 The system includes a first driver 105, a ground node 145, an input terminal 156, an output terminal 158, and a transistor 150. The transistor 150 includes... Figure 1 and / or Figure 5The control terminal 172, source terminal 174, and drain terminal 176. Figure 6 In the example, the first driver 105 includes Figure 5 The regulator 505, the first stage 510, the second stage 515, the first voltage source node 516, and the second voltage source node 518.

[0084] exist Figure 6 In the example shown, regulator 505 includes logic gate 601, comparator, delay and latch circuitry 602 (hereinafter referred to as "comparator 602"), linear regulator circuitry 603, and transistor 604. Regulator 505 is adapted to be coupled to example clamp voltage source node 605. In the example described herein, clamp voltage source node 605 is configured to be coupled to voltage sources to (1) drive transistor 150 at a higher slew rate and (2) provide a potential greater than that of a voltage source (such as VDRV) coupled to a second voltage source node 518 and less than that of a first voltage source node 516 (such as 12 volts) (such as VCLAMP). For example, a first voltage source coupled to the first voltage source node 516 may provide 12 volts, a second voltage source coupled to the second voltage source node 518 may provide 6 volts, and a third voltage source coupled to the clamp voltage source node 605 may provide 8 volts. However, any one of the clamping voltage source node 605, the first voltage source node 516, and / or the second voltage source node 518 can be coupled to a voltage source that provides any suitable voltage, such as 0 volts, 10 volts, 100 volts, etc.

[0085] exist Figure 6 In the illustrated example, logic gate 601 includes a first input terminal 616 coupled to a first input terminal 520 of regulator 505 to obtain an activation signal (IN), a second input terminal 617 for obtaining a signal (e.g., a logic low value) from comparator circuit 602, and an output terminal 619 coupled to a first output terminal 524 of regulator 505 to provide a first trigger signal. Figure 6In the illustrated topology, logic gate 601 is an example complementary AND gate. In some examples, logic gate 601 may be implemented using any suitable combination of logic gates and / or circuitry. Logic gate 601 provides and / or is otherwise adapted to output a first trigger signal at output terminal 619 (e.g., at the first output terminal 524 of the regulator and / or provided to the first input terminal 530 of the first stage 510). For example, logic gate 601 may provide the first trigger signal in response to (1) the voltage of a signal (such as an activation signal, signal IN, etc.) obtained at the first input terminal 616 and (2) the voltage at the second input terminal 617 exceeding a threshold voltage level, such as a logic high threshold of 5 volts. In other examples, logic gate 601 may modify (e.g., reduce) the first trigger signal in response to the activation signal and / or a third trigger signal not exceeding a threshold voltage level. Logic gate 601 is configured to enable the first stage 510 by transmitting the first trigger signal to the first input terminal 530 of the first stage 510.

[0086] The linear regulator circuit 603 includes an output terminal 620 for regulating transistor 604, a first input terminal 621 (such as a non-inverting input) adapted to be coupled to clamp voltage source 605, and a second input terminal 622 (such as an inverting input) coupled to regulator 505 to obtain a signal (e.g., voltage) at control terminal 172. Figure 6In the illustrated topology, the linear regulator circuit 603 is an example linear amplifier, such as a comparator. However, any suitable combination of circuitry and / or logic gates can be used to implement the linear regulator circuit 603. In operation, the linear regulator circuit 603 is adapted to regulate the voltage at the second input terminal 622 (e.g., at node 539, the control terminal 172 of transistor 150, etc.) via transistor 604 in response to a comparison of a signal obtained at the first input terminal 621 (e.g., the voltage threshold level VCLAMP provided by the clamping voltage source 605) with a signal obtained at the second input terminal 622 (e.g., the voltage at the control terminal 172 of transistor 150). In some examples, the linear regulator circuit 603 regulates (e.g., adjusts) the current through transistor 604. Therefore, because transistor 604 is coupled to first stage 510 (e.g., to switching circuit 633 coupled to current source 632), linear regulator circuit 603 regulates the current supplied to current mirror circuit 634 at first terminal 640, and thus regulates the current supplied to control terminal 172 by current mirror circuit 634 at second terminal 642. In some examples, linear regulator circuit 603 regulates the voltage at second input terminal 622 such that this voltage substantially tracks (e.g., equals) the voltage at first input terminal 621, such as the voltage VCLAMP provided by clamp voltage source node 605. For example, if the voltage at second input terminal 622 is greater than the voltage at first input terminal 621, linear regulator circuit 603 can reduce the output at output terminal 620, thereby increasing the current flow from source terminal 623 to drain terminal 624 of transistor 604. Because transistor 604 and current mirror circuit 634 are adapted to be coupled to current source node 632 via switching circuit 633, linear regulator circuit 603 and / or transistor 604 thus reduce the current supplied to the first terminal 640 of current mirror circuit 634.

[0087] Transistor 604 includes a source terminal 623 (e.g., a first current terminal) adapted to be coupled to a first voltage source node 516, a drain terminal 624 (e.g., a second current terminal) coupled to a second output terminal 526 of regulator 505 to provide a regulation signal, and a control terminal 625 (e.g., a gate terminal) coupled to an output terminal 620 to obtain an output from linear regulator circuit 603. In operation, transistor 604 provides a regulation signal (e.g., current) to first stage 510 at second output terminal 526 in response to a signal provided by linear regulator circuit 603 at control terminal 625. For example, if the voltage at second input terminal 522 is higher than the voltage (VCLAMP) at first input terminal 621, linear regulator circuit 603 may increase the current provided to control terminal 625 of transistor 604. Therefore, the first stage 510 can drive transistor 150 with a lower control signal (e.g., with a smaller current), and the voltage at node 539 (e.g., control terminal 172, second input terminal 522) is reduced to the voltage VCLAMP provided by the clamping voltage source node 605. In response to an adjustment signal, the first stage 510 can increase or decrease the first control signal (e.g., current signal, control current) at output terminal 534, thereby adjusting the control terminal 172 of transistor 150, such as the voltage at control terminal 172.

[0088] Comparator circuit 602 (e.g., comparator, delay, and / or latch circuitry) includes an input terminal 629 coupled to output terminal 620 to obtain the output from linear regulator circuit 603, a first output terminal 630 coupled to a third output terminal 528 of regulator 505 to enable second stage 515 (e.g., input terminal 536 coupled to second stage 515), and a second output terminal 631 coupled to a second input terminal 617 to provide a signal (e.g., a logic low value) to logic gate 601. Comparator circuit 602 enables second stage 515 (e.g., a transistor included in second stage 515 and coupled to input terminal 536) in response to a change in the output of linear regulator circuit 603 by providing a second trigger signal at first output terminal 630. In some examples, comparator circuit 602 obtains a signal (e.g., an analog voltage value) provided by linear regulator circuit 603 at input terminal 629. Comparator circuit 602 converts an analog signal into a digital signal (e.g., a logic high value, a logic low value, etc.) and outputs a logic low value at output terminals 630, 631 in response to the signal at input terminal 629 not exceeding a voltage threshold for a period of time (e.g., a delay). Comparator circuit 602 may include filtering circuitry (e.g., resistors and capacitors) to respond to the signal obtained at input terminal 629 after a period of time (e.g., 20 nanoseconds). Comparator circuit 602 may include and / or be adapted to be coupled to a reference voltage node.

[0089] In operation, if the signal at input terminal 629 exceeds a threshold (e.g., a logic high voltage threshold, 2 volts, 3 volts, etc.) for a period of time, comparator circuit 602 can provide a first voltage signal (e.g., a logic high value) at output terminals 630, 631. In operation, if the signal at input terminal 629 does not exceed a threshold (e.g., a logic high voltage threshold, 2 volts, 3 volts, etc.) for a period of time, comparator circuit 602 can provide a second voltage signal (e.g., a logic low value) at output terminals 630, 631. Therefore, by providing the second voltage signal, comparator circuit 602 can disable logic gate 601, thereby disabling the first stage 510. Furthermore, by providing the second voltage signal (e.g., a second control signal) to the second stage 515, comparator circuit 602 can enable the second stage 515, thereby enabling transistor 150.

[0090] exist Figure 6 In the example shown, the first stage 510 is adapted to be coupled to the current source 632 and to the first voltage source node 516. The first stage 510 includes an example switching circuit 633 and an example current mirror circuit 634. The second stage 515 includes a transistor 635. Figure 6 In the topology depicted, the second stage 515 is adapted to be coupled to the second voltage source node 518. Figure 6 In the topology depicted, the first voltage source node 516 has a higher potential than the second voltage source node 518. For example, the first voltage source node 516 may have a potential of 12 volts, while the second voltage source node 518 may have a potential of 6 volts. The current source 632 may supply current (e.g., a mirror signal, a current mirror signal, a signal IDRV, a signal Iref, etc.) to the current mirror circuit 634 and / or the first stage 510.

[0091] The switching circuit 633 includes: a first terminal 636 coupled to a first input terminal 530 of the first stage 510 to obtain a first trigger signal; a second terminal 637 adapted to be coupled to a current source node 632; and a third terminal 638 for providing a current signal to the current mirror circuit 634. In response to a logic high value being obtained at the first terminal 636, the switching circuit 633 electrically connects the second terminal 637 to the third terminal 638. The switching circuit 633 can be implemented by any suitable switching device (e.g., MOSFET, BJT, double-pole single-throw (DPST) switch, etc.). In some examples, the switching circuit 633 can be implemented using one or more NMOS transistors. In response to a signal obtained at the first terminal 636 (e.g., a first control signal provided by logic gate 601) exceeding a voltage threshold, the switching circuit 633 electrically connects the second terminal 637 to the third terminal 638.

[0092] The current mirror circuit 634 includes a first terminal 640, which is coupled to a third terminal 638 of the switching circuit 633 and to a second input terminal 532 of the first stage 510 to obtain a current signal. The current mirror circuit 634 also includes a second terminal 642 coupled to the output terminal 534 of the first stage 510 to provide a control signal to the control terminal 172. Figure 6 In one example, the current mirror circuit 634, in response to receiving a signal (such as a mirror signal, current mirror signal, etc.) at the first terminal 640, provides a first control signal to the control terminal 172 of the transistor 150 at the second terminal 642. For example, the switching circuit 633 and the transistor 604 can be enabled to provide a mirrored current (such as the signal IDRV) provided by the current source node 632 to the first terminal 640, and then the current mirror circuit 634 can provide the first control signal to the control terminal. For example, the current mirror circuit 634 can receive the signal IDRV at the first terminal 640 in response to the switching circuit 633 being enabled, and provide the signal to the control terminal 172 at the second terminal 642. In some examples, a second current mirror circuit or any number of current mirror circuits can be coupled between the second terminal 642 and node 539 to provide additional current to enable the transistor 150. In some examples, regulator 505, such as linear regulator circuit 603 and / or transistor 604, can enable and / or disable current mirror circuit 634 to provide a first control signal in response to the voltage at the second input terminal 522 of regulator 505.

[0093] The second stage 515 includes a transistor 635. The transistor 635 includes a control terminal 644 coupled to an input terminal 536 of the second stage 515 to obtain a second trigger signal, a source terminal 646 adapted to be coupled to a second voltage source node 518, and a drain terminal 648 coupled to an output terminal 538 of the second stage 515 to provide a second control signal. The transistor 635 provides the second control signal at the output terminal 538 of the second stage 515 to enable transistor 150 in response to the second trigger signal obtained at the control terminal 644 (e.g., provided by comparator circuitry 602 at the input terminal 536).

[0094] In operation, in response to the voltage at control terminal 172 exceeding clamp voltage source node 605, linear regulator circuit 603 regulates and / or clamps the voltage through transistor 604 by providing an adjustment signal to first stage 510. Therefore, the voltage at control terminal 172 is regulated to not exceed a maximum voltage (e.g., VCLAMP). In response to the voltage at control terminal 172 (e.g., at second input terminal 522, at node 539, at second input terminal 622) reaching voltage VCLAMP over a period of time (e.g., after a delay), comparator circuit 602 provides a second trigger signal (e.g., a logic low value) to second stage 515 at output terminal 620. In some examples, comparator circuit 602 delays and / or otherwise waits to provide the second trigger signal until the voltage at input terminal 629 does not exceed a threshold (such as a logic low value) over a period of time. As a result, transistor 635 is enabled, and thus transistor 150 is enabled using the current provided by second voltage source node 518. In some examples, logic gate 601 can change the first control signal in response to a change in the second trigger signal (e.g., reduce the signal to 0 volts), and thus disable switching circuit 633.

[0095] Figure 7A yes Figure 1 , Figure 5 and / or Figure 6 A schematic diagram of an example implementation 700 of the first driver 105, including Figure 6 The additional logic circuit system of implementation method 600. Implementation method 700 includes... Figure 1 The driver 105, ground node 145, transistor 150, input terminal 156, and output terminal 158 are included. Figure 7A In the example, the first driver 105 includes Figure 5 The regulator 505, the first stage 510, the second stage 515, the first voltage source node 516, and the second voltage source node 518. Figure 7A In the topology, the first driver 105 includes Figure 6 The clamping voltage source node 605 and current source node 632.

[0096] Regulator 505 includes logic gate 601, comparator circuit 602, and linear regulator circuit 603. In operation, logic gate 601 provides a first trigger signal at the first output terminal 524 of the regulator and / or provides a first trigger signal to the first input terminal 530 of the first stage 510. In some examples, logic gate 601 may provide the first trigger signal in response to an activation signal (IN) and a signal obtained at the second input terminal 617 exceeding a voltage threshold (such as a logic high value). Logic gate 601 enables the switching circuit 633 of the first stage 510 by providing the first trigger signal to the first input terminal 530 of the first stage 510.

[0097] The linear regulator circuit 603 includes a first transistor 702, a second transistor 704, a third transistor 706, a first resistor 708, a second resistor 710, and a third resistor 712. Figure 7A In the topology, the first transistor 702 and the second transistor 704 are both PMOS transistors, while the third transistor 706 is an NMOS transistor. The first transistor 702 includes a source terminal 714 coupled to a first input terminal 621 of the linear regulator circuit 603 (e.g., adapted to be coupled to a clamping voltage source node 605), a control terminal 716, and a drain terminal 718 coupled to the control terminal 716. A first resistor 708 is coupled between the drain terminal 718 of the first transistor 702 and a ground node 145. The second transistor 704 includes a control terminal 720 coupled to the drain terminal 718 of the first transistor 702, a source terminal 722 coupled to a second input terminal 622 of the linear regulator circuit 603 (e.g., coupled to node 539) to obtain a signal at the control terminal 172, and a drain terminal 724 adapted to be coupled to the ground node 145 (e.g., through a resistor).

[0098] The third transistor 706 includes a control terminal 726 coupled to the drain terminal 724 of the second transistor 704, a drain terminal 728 coupled to the output terminals 620A, 620B of the linear regulator circuit 603 to provide the output of the linear regulator circuit 603, and a source terminal 730 adapted to be coupled to the ground node 145. A second resistor 710 is coupled between the control terminal 726 of the third transistor 706 and the ground node 145. A third resistor 712 is coupled and / or adapted to be coupled between the first voltage source node 516 and the drain terminal 728 of the third transistor 706. The linear regulator circuit 603, in response to a voltage at the second input terminal 622 (e.g., at node 539, at control terminal 172) exceeding the voltage (VCLAMP) provided by the clamping voltage source node 605, regulates the voltage at node 539 (e.g., at control terminal 172) by changing the regulation signal (e.g., current) through the transistor 604. Therefore, the linear regulator circuit 603 regulates the first control signal (e.g., current) provided by the first stage 510 such that the voltage at the control terminal 172 is regulated and / or does not exceed a certain voltage. Thus, advantageously, transistor 150 can be prevented from being damaged by the first stage 510 driving (e.g., enabling) transistor 150.

[0099] Comparator circuit 602 (e.g., comparator, delay, and / or latch circuitry) is coupled to logic gate 601, linear regulator circuit 603, and the third output terminal 528 of regulator 505. Input terminal 629 of comparator circuit 602 is coupled to control terminal 625 of transistor 604 (e.g., coupled to output terminal 620A of linear regulator circuit 603) to obtain an output signal from linear regulator circuit 603. Comparator circuit 602 is adapted to provide a second trigger signal to second stage 515 (e.g., enable transistor 635) in response to the voltage at input terminal 629 exceeding a voltage threshold (e.g., a reference voltage of comparator circuit 602) for a period of time. Comparator circuit 602 can also provide a logic low value at second output terminal 631 (e.g., to logic gate 601 at second input terminal 617) to change the first trigger signal and / or disable first stage 510.

[0100] Transistor 604 includes a drain terminal 624 coupled to a second output terminal 526 (e.g., coupled to a second input terminal 532 and a third terminal 638), a source terminal 623 adapted to be coupled to a first voltage source node 516, and a control terminal 625 coupled to an output terminal 620B of linear regulator circuit 603. Transistor 604 can respond to the output from linear regulator circuit 603 (e.g., at control terminal 625) by providing a regulation signal to first stage 510 at the second output terminal 526. In operation, if the voltage at the second input terminal 522 exceeds the voltage VCLAMP (e.g., if the voltage at the second input terminal 622 exceeds the voltage at the first input terminal 621), linear regulator circuit 603 increases the current through transistor 604 (e.g., from source terminal 623 to drain terminal 624). Therefore, the current obtained by current mirror circuit 634 at first terminal 640 is lower than the previously obtained current, and thus, the current provided by current mirror circuit 634 at second terminal 642 is reduced. As a result, the voltage at the second input terminal 522 decreases and begins to approach the voltage VCLAMP.

[0101] Level 510 includes Figure 6 The switching circuit 633 and the current mirror circuit 634. In Figure 7A In the topology, the switching circuit 633 is implemented as an NMOS transistor. For example, the control terminal of the NMOS transistor may be coupled to the first terminal 636, the source terminal of the NMOS transistor may be coupled to the second terminal 637, and the drain terminal of the NMOS transistor may be coupled to the third terminal 638. However, any other circuitry may be additionally or alternatively included to implement the switching circuit 633. The switching circuit 633 includes a first terminal 636 coupled to the first input terminal 530, a third terminal 638 coupled to the first terminal 640 of the current mirror circuit 634, and a second terminal 637 adapted to be coupled to the current source node 632.

[0102] The current mirror circuit 634 includes a fourth transistor 732 and a fifth transistor 734. Figure 7AIn the topology, both the fourth transistor 732 and the fifth transistor 734 are PMOS transistors. The fourth transistor 732 includes a source terminal 736 adapted to be coupled to the first voltage source node 516, a drain terminal 738 coupled to the first terminal 640 of the current mirror circuit 634, and a control terminal 740 coupled to the first terminal 640. The fifth transistor 734 includes a control terminal 742 coupled to the control terminal 740 of the fourth transistor 732, a source terminal 744 adapted to be coupled to the first voltage source node 516, and a drain terminal 746 coupled to the second terminal 642 of the current mirror circuit 634. In operation, the current mirror circuit 634, in response to receiving a signal (such as a mirror signal, current mirror signal) at the first terminal 640, provides a first control signal at the second terminal 642 to the output terminal 158 (e.g., to node 539, to transistor 150, etc.). For example, switching circuit 633 and transistor 604 can be enabled to provide a mirrored current (such as the signal IDRV) supplied by current source 632 to first terminal 640, and then current mirror circuit 634 can provide a first control signal to control terminal 172. In some examples, a second current mirror circuit can be coupled between second terminal 642 of first stage 510 and output terminal 534 (such as between second terminal 642 and node 539) to provide additional current to enable transistor 150.

[0103] Level 2 515 includes Figure 6 Transistor 635. Transistor 635 is coupled to input terminal 536 of the second stage 515 (e.g., coupled to the third output terminal 528 of the regulator 505) and to output terminal 538 (e.g., coupled to node 539, coupled to output terminal 158, coupled to transistor 150, etc.). In response to receiving a second trigger signal at input terminal 536, transistor 635 can enable transistor 150 by providing a second control signal (such as current provided by the second voltage source node 518).

[0104] Figure 7B yes Figure 6 A schematic diagram of an example implementation 760 of a comparator circuit 602 (e.g., a comparator, delay, and latch circuit). Implementation 760 includes... Figure 1 Grounding node 145 Figure 5 The first voltage source node 516 and the supply voltage node (V5V) 762 (e.g., a digital supply voltage node). In Figure 7B In one example, comparator circuit 602 includes a first transistor 764, a first resistor 766, a capacitor 768, a second transistor 770, a second resistor 772, a latch circuit 774, and a buffer circuit 776. In some examples, comparator circuit 602 may be adapted to couple to supply voltage node 762 and / or first voltage source node 516. Figure 7B In the example, supply voltage node 762 provides a voltage of 5 volts. However, supply voltage node 762 can provide any suitable supply voltage (e.g., 3.3 volts) to comparator circuit 602.

[0105] The first transistor 764 includes an input terminal 629 coupled to the comparator circuit 602 to obtain an output from the linear regulator circuit 603, a source terminal 780 adapted to be coupled to the first voltage source node 516, and a drain terminal 782. Figure 7B In the topology, the first transistor 764 is a PMOS transistor. In operation, the first transistor 764 provides a signal (e.g., current) at the drain terminal 782 in response to a signal at control terminal 778 (e.g., input terminal 629). For example, if the linear regulator circuit 603 reduces the output signal provided at output terminal 620 in response to the voltage at the second input terminal 622 exceeding the voltage VCLAMP at the first input terminal 621, the first transistor 764 can use the first voltage source node 516 to increase the current signal provided at the drain terminal 728.

[0106] exist Figure 7B In the illustrated example, the first resistor 766 and capacitor 768 are each coupled between drain terminal 782 and ground node 145. In operation, the first resistor 766 and capacitor 768 can form a filter circuit (e.g., a low-pass filter circuit), and the filter circuit can delay the enabling of the second transistor 770 in response to a current signal provided by the first transistor 764. For example, once the first transistor 764 is enabled, the second transistor 770 can be enabled in response to the first transistor 764 being enabled, and the second transistor 770 can be enabled after a delay based on the impedance of the first resistor 766 and capacitor 768.

[0107] The second transistor 770 includes a control terminal 784 coupled to the drain terminal 782 of the first transistor 764, a source terminal 786 adapted to be coupled to the ground node 145, and a drain terminal 788 adapted to be coupled to the supply voltage node 762 (e.g., via a resistor). Figure 7BIn the topology depicted, the second transistor 770 is an NMOS transistor. A second resistor 772 is coupled between the drain terminal 788 and the supply voltage node 762. The latch circuit 774 includes an input terminal 790 coupled to the drain terminal 788 of the second transistor 770 and an output terminal 792 for providing an output signal (e.g., a logic low value) to the logic gate 601. The latch circuit 774 sets (e.g., latches) the voltage signal at the output terminal 792 in response to a voltage obtained at the input terminal 790. For example, if the voltage at the input terminal 790 decreases (e.g., changes from a logic high value to a logic low value), the latch circuit 774 can maintain the voltage (e.g., a logic low value) at the output terminal 792 until the next cycle. The output terminal 792 of the latch circuit 774 is coupled to the second output terminal 631 of the comparator circuit 602.

[0108] The buffer circuit 776 is coupled between the output terminal 792 of the latch circuit 774 and the first output terminal 630 of the comparator circuit 602. Figure 7B In the example, buffer circuit 776 removes glitches (e.g., unwanted signal transitions) from the voltage signal obtained from the output terminal 792 of latch circuit 774 and provides the voltage signal to the coupling element at the output terminal 630 of comparator circuit 602 (e.g., transistor 635 of second stage 515) at an output impedance level lower than the output impedance level of latch circuit 774. Although Figure 7B The topology includes a buffer circuit, but any number of buffer circuits can be additionally or alternatively included in the comparator circuit 602 and / or more generally, the driver 105. For example, the buffer circuit can be coupled between the output terminal 792 of the latch circuit 774 and the output terminal 631 of the comparator circuit 602.

[0109] In operation, in the initial state (e.g., when the first driver 105 is commanded to turn on in response to the signal IN obtained at input terminal 156), comparator circuit 602 provides a first voltage signal (e.g., a logic high value) at the first output terminal 630 and the second output terminal 631. In response to a change in the signal obtained at input terminal 629 (e.g., the linear regulator circuit 603 reduces the voltage signal at output terminal 620 in response to the voltage at the second input terminal 622 exceeding the voltage at the first input terminal 621), the first transistor 764 is enabled. Therefore, the second transistor 770 is enabled after a delay controlled by a filter circuit (e.g., the first resistor 766 and capacitor 768). As a result, a low voltage signal is provided to latch circuit 774 at input terminal 790, and latch circuit 774 changes the output at output terminal 792 (e.g., providing a logic low value). In response to a change at output terminal 792, and consequently at first output terminal 630 and second output terminal 631, second stage 515 is enabled, while first stage 510 is disabled. Latch circuit 774 ensures that driver 105 remains in this state (e.g., when second stage 515 is enabled and first stage 510 is disabled) until first driver 105 is commanded to be disabled in response to a change (e.g., a decrease) in the signal IN obtained at input terminal 156.

[0110] Figure 8 yes Figure 1 , Figure 5 and / or Figure 6 A schematic diagram of an example implementation 800 of the driver 105, including Figure 6 The additional logic circuit system for the implementation method. Implementation method 800 includes... Figure 1 The driver 105, ground node 145, transistor 150, input terminal 156, and output terminal 158 are included. Figure 8 In the example, drive 105 includes Figure 5 The regulator 505, the first stage 510, the second stage 515, the first voltage source node 516, and the second voltage source node 518. Figure 8 In the topology, driver 105 includes Figure 6 The clamping voltage source node 605 and current source node 632.

[0111] exist Figure 8 In the example shown, regulator 505 includes logic gate 601, comparator circuit 602, linear regulator circuit 603, and transistor 604. Figure 8In the example, the linear regulator circuit 603 includes a transistor 802 and a resistor 804. The transistor 802 includes a drain terminal 806 coupled to the output terminals 620 (e.g., output terminals 620A, 620B) of the linear regulator circuit 603 (e.g., coupled to the input terminal 629 of the comparator circuit 602), a source terminal 808 coupled to the first input terminal 621 (e.g., adapted to be coupled to the clamp voltage source node 605), and a control terminal 810 coupled to the second input terminal 622. The resistor 804 is coupled and / or adapted to be coupled between the drain terminal 806 of the transistor 802 and the first voltage source node 516. In operation, the linear regulator circuit 603 adjusts the voltage at node 539 (e.g., at the output terminal 534 of the first stage 510, at the second input terminal 522, etc.) to approximate the voltage VCLAMP provided by the clamp voltage source node 605.

[0112] exist Figure 8 In the example shown, the first level 510 includes Figure 6 The switching circuit 633 and the current mirror circuit 634. In Figure 8 In the topology, the switching circuit 633 is implemented as an NMOS transistor. However, any other circuitry may be added or alternatively included to implement the switching circuit 633. Figure 8 In the example, the first stage 510 includes a second current mirror circuit 812. The second current mirror circuit 812 includes a first terminal 814 coupled to a second terminal 642 of the current mirror circuit 634 and coupled to a second input terminal 522 of the regulator 505 to obtain a signal (e.g., current) from the current mirror circuit 634, and the second current mirror circuit 812 includes a second terminal 816 coupled to an output terminal 534 of the first stage (e.g., coupled to an output terminal 158 and / or coupled to a control terminal 172 of the transistor 150) to provide a control signal to the transistor 150 and thus enable the transistor 150.

[0113] The second current mirror circuit 812 includes a first transistor 818 and a second transistor 819. The first transistor 818 includes a drain terminal 820 coupled to a first terminal 814 to obtain a current signal from the first current mirror circuit 634, a control terminal 822 coupled to the drain terminal 820, and a source terminal 824 coupled to a second terminal 816 of the second current mirror circuit 812 to provide a control signal to the control terminal 172. The second transistor 819 includes a control terminal 826 coupled to the control terminal 822 of the first transistor 818 to obtain a current signal from the first current mirror circuit 634, a drain terminal 828 adapted to be coupled to the first voltage source node 516, and a source terminal 830 coupled to the second terminal 816 of the second current mirror circuit 812 to provide a control signal to the control terminal 172. In some examples, the current mirror circuit 634 may, in response to a signal obtained at the first terminal 640, such as the signal IDRV when the switching circuit 633 is enabled by the regulator 505, provide a current signal at the second terminal 642 (e.g., at the first terminal 814 of the second current mirror circuit 812). The second current mirror circuit 812 may then, in response to a signal obtained at the first terminal 814, provide a second control signal at the second terminal 816 (e.g., provide a second control signal to the transistor 150 at the output terminal 534). In some examples, the second current mirror circuit 812 may provide additional current to enable the transistor 150 compared to the current mirror circuit 634, and / or the second current mirror circuit 812 may stabilize the current signal provided by the current mirror circuit 634 at the second terminal 642.

[0114] Level 2 515 includes Figure 6 Transistor 635. Transistor 635 is coupled to input terminal 536 and to output terminal 538 of the second stage 515. In response to receiving a second trigger signal at input terminal 536, transistor 635 enables transistor 150 by providing a second control signal (such as current provided by the second voltage source node 518).

[0115] Although Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 The diagram illustrates the implementation. Figure 1 The example method of controller 105, but Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 One or more of the elements, processes, and / or devices illustrated in the diagrams may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other way. Furthermore, example regulator 505, example first stage 510, example second stage 515, and / or more generally, Figure 1 , Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 The example driver 105 can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Therefore, for example, any one of the example regulator 505, the first example stage 510, the second example stage 515, and / or more generally, the example driver 105 can be implemented by one or more analog or digital circuits, logic circuits, one or more programmable processors, one or more programmable controllers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more programmable logic devices (PLDs), and / or one or more field-programmable logic devices (FPLDs). When reading any of the device or system claims of this patent to cover purely software and / or firmware implementations, at least one of the example regulator 505, the first example stage 510, the second example stage 515, and / or more generally, the example driver 105 is hereby expressly defined as including non-transitory computer-readable storage devices or disks with software and / or firmware, such as memory, digital universal disk (DVD), optical disk (CD), Blu-ray disc, etc. Furthermore, Figure 1 Example driver 105 may include, except Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 One or more elements, processes, and / or devices other than (or in place of) those shown, and / or may include any or all of more than one of the elements, processes, and devices shown. As used herein, the phrase “in communication” includes variations thereof, covering direct communication and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-off events.

[0116] Figure 9 A representative is shown for implementation. Figure 1The example driver 105 includes example hardware logic, machine-readable instructions, a hardware-implemented state machine, and / or any combination thereof flowcharts. Machine-readable instructions can be one or more executable programs or one or more portions of an executable program that are executed by a computer processor, such as a processor. The program may be embodied in software stored on a non-transitory computer-readable storage medium (such as a CD-ROM, floppy disk, hard disk drive, DVD, Blu-ray disc, or processor-associated memory), but the entire program and / or portions thereof may alternatively be executed by a device other than a processor and / or embodied in firmware or dedicated hardware. Furthermore, although references... Figure 9 The flowcharts shown depict an example program, but many other methods for implementing example driver 105 can be used alternatively. For example, the execution order of the blocks can be changed, and / or some of the blocks described can be changed, eliminated, or combined. Additionally or alternatively, any or all blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0117] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, packaged format, etc. The machine-readable instructions described herein can be stored as data (e.g., a portion of an instruction, code, a representation of code, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, machine-readable instructions can be segmented and stored on one or more storage devices and / or computing devices (e.g., servers). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, reassigned, compiled, etc., to make them directly readable, interpretable, and / or executable by computing devices and / or other machines. For example, machine-readable instructions can be stored in multiple parts, which are separately compressed, encrypted, and stored on separate computing devices, wherein these parts, after decryption, decompression, and combination, form a set of executable instructions that implement programs such as those described herein.

[0118] In another example, machine-readable instructions may be stored in a state where they can be read by a computer but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the instructions on a specific computing device or other device. In another example, the machine-readable instructions (e.g., stored settings, data input, recorded network addresses, etc.) may need to be configured before they can be fully or partially executed. Therefore, the described machine-readable instructions and / or corresponding one or more programs include such machine-readable instructions and / or one or more programs, regardless of their specific format or state at storage or otherwise shelved or en route.

[0119] The machine-readable instructions described in this article can be represented using any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0120] As mentioned above, Figure 9 The example process can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on non-transitory computer and / or machine-readable media, such as hard disk drives, flash memory, read-only memory, optical disks, digital universal disks, caches, random access memory, and / or any other storage device or disk that stores information for any duration (e.g., extended time periods, permanently, for transient instances, for temporary caching and / or cached information). As used herein, the term "non-transitory computer-readable media" is explicitly defined to include any type of computer-readable storage device and / or disk, excluding propagation signals and transmission media.

[0121] This document uses “comprising” and “including” (and all forms and tenses thereof) as open-ended terms. Therefore, whenever a claim uses any form of “comprising” or “including” (e.g., including, comprising, having, etc.) as a preamble or in any kind of claim statement, other elements, terms, etc., may be present without exceeding the scope of the corresponding claim or statement. As used herein, when the phrase “at least” is used, for example, as a transitional term in the preamble of a claim, it is open-ended in the same way as the terms “comprising” and “including” are open-ended. When the term “and / or” is used, for example, in the form of A, B, and / or C, it refers to any combination or subset of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, and (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A and B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase “at least one of A or B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, and / or steps, the phrase “at least one of A and B” means an implementation that includes any one of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities and / or steps, the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, and (3) at least one A and at least one B.

[0122] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude multiple entities. As used herein, the term "a" or "an" refers to one or more of those entities. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple devices, elements, or method actions can be implemented by, for example, a single unit or processor. Additionally, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that the combination of features is unfeasible and / or advantageous.

[0123] Figure 9This is a flowchart representing an example process 900 that can be implemented using logic or machine-readable instructions that can be executed to implement the example driver (e.g., Figure 1 , Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 Drive 105). Figure 9 In example process 900, regulator 505 receives an activation signal (such as signal IN) and determines whether the activation signal exceeds a voltage threshold level (such as a logic high voltage threshold, a 5-volt threshold, or a 3-volt threshold). If regulator 505 determines that the activation signal does not exceed the voltage threshold level (e.g., block 905 returns a "No" result), control returns to block 905, and regulator 505 receives the activation signal.

[0124] If regulator 505 determines that the activation signal exceeds (e.g., meets, reaches, or is greater than) a voltage threshold level (e.g., block 905 returns a "yes" result), then regulator 505 enables and regulates the first stage 510 (block 910). In some examples, regulator 505 provides a first trigger signal at the first output terminal 524 (e.g., to the first terminal 636 of switching circuit 633) to enable the first stage 510. The first stage 510 receives the first trigger signal. In response to the first trigger signal, the first stage 510 provides a first control signal at the output terminal 534. Therefore, transistor 150 is enabled (e.g., turned on) by the current supplied through the first voltage source node 516.

[0125] In some examples, regulator 505 may be adapted to regulate the first stage 510 in response to a voltage signal obtained at node 539 by providing and / or changing an adjustment signal at the second output terminal 526. For example, if linear regulator circuit 603 determines that the voltage at the second input terminal 522 (such as at node 539, control terminal 172) exceeds a voltage threshold (such as VCLAMP provided by clamp voltage source node 605), then linear regulator circuit 603 and / or transistor 604 may regulate the voltage at node 539. Therefore, the signal provided to current mirror circuit 634 may be varied (e.g., reduced). In some examples, regulator 505 may be adapted to regulate the voltage at control terminal 172, second input terminal 522, etc., by providing an adjustment signal at the second output terminal 526. Regulator 505 may adjust the output provided by the first stage 510 (e.g., a first control signal) such that the output from node 539 to control terminal 172 does not exceed normal operating conditions for an extended period and / or damage transistor 150.

[0126] Regulator 505 receives a voltage signal at second input terminal 522 (e.g., the voltage at node 539 and / or the voltage at control terminal 172). If regulator 505 determines that the voltage signal exceeds a threshold for a period of time (e.g., VCLAMP provided by clamp voltage source node 605) (e.g., block 925 returns a "yes" result), regulator 505 disables first stage 510 (block 930). Regulator 505 then enables second stage 515 (block 940). For example, if comparator circuit 602 determines that the output of linear regulator circuit 603 is activated for a period of time (e.g., enabled, providing output), comparator circuit 602 may provide a logic low value to second input terminal 617 of logic gate 601 and provide a second trigger signal to second stage 515 at third output terminal 528.

[0127] Therefore, logic gate 601 alters (e.g., reduces) the first trigger signal provided to the first input terminal 530 of the first stage 510, and switching circuit 633 is disabled. Therefore, current mirror circuit 634 alters (e.g., reduces, stops providing) the first control signal. Furthermore, in response to the second trigger signal, transistor 635 of the second stage 515 is enabled and provides a second control signal to control terminal 172. Therefore, transistor 150 is enabled by the second stage 515. If regulator 505 determines that the voltage signal (e.g., the voltage at control terminal 172) has not exceeded a threshold voltage level for a period of time (e.g., block 925 returns a "no" result), regulator 505 enables and regulates the first stage 510 (block 910).

[0128] Figure 10 It is a driver in a power converter (e.g., Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 Drive 105 Figure 2 Drive 205, Figure 3 Drive 305, Figure 4 A schematic diagram of an example simulation stand 1000 (e.g., a test bench, circuit, etc.) for drivers such as 402. The simulation stand 1000 can be used to verify drivers (such as...) Figure 1 The function of the driver 105) enables the use of multiple levels (such as Figure 5 The transistor model (510 for the first stage and 515 for the second stage). In some examples, the analog bench 1000 can demonstrate... Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 The driver 105 relative to Figure 2 Drive 205, Figure 3Drive 305 and / or Figure 4 The advantages of the 402 driver are as follows: Figures 11-14 The analog stage 1000 includes a capacitor 1005, a first voltage source node 1010, a resistor (Rdrv) 1012, a second voltage source 1015, and a driver 1020 (e.g., Figure 1 , Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 Drive 105 Figure 2 Drive 205, Figure 3 Drive 305, Figure 4 The driver 1020 includes a driver 402), a third voltage source 1035, a first inductor 1040, a transistor model 1045, a diode 1050, a second inductor 1055, a current source 1060, a fourth voltage source (VBUS) 1065, and a ground node 1070. The driver 1020 includes an output terminal 1072. Figure 10 In the example, first voltage source node 1010 provides 12 volts to represent first voltage source node 516, and second voltage source node 1015 provides 6 volts to represent second voltage source node 518. However, any of the voltage source / voltage source nodes 1010, 1015, 1035, and 1065 can provide any suitable voltage. Figure 10 In the example, the clamping voltage source is generated within the driver 1020, therefore, the clamping voltage source node 605 is included within the driver 1020.

[0129] Capacitor 1005 is coupled between the first voltage source node 1010 and the first inductor 1040. Resistor (Rdrv) 1012 is coupled between the driver 1020 and the first inductor 1040. In some examples, the impedance of resistor 1012 may affect the impedance of current sources in the driver (such as...). Figure 6 The magnitude of the current provided by the current source 632 in the driver 105. In some examples, resistor (Rdrv) 1012 may adjust the fast pull-up gate drive current (e.g., IDRV, the current provided by the first stage 510) to set the slew rate of transistor 1074 included in transistor model 1045. Second voltage source 1015 is coupled between driver 1020 and first inductor 1040. First inductor 1040 is coupled between driver 1020 and ground node 1070. Driver 1020 is adapted to be coupled to first voltage source node 1010 and to second voltage source 1015. Driver 1020 is adapted to receive an activation signal (e.g., signal IN) and provide (e.g., output) one or more control signals to enable transistor model 1045. In some examples, first voltage source node 1010 may be Figure 5 The first voltage source node 516, and the second voltage source 1015 can be Figure 5 The second voltage source node 518.

[0130] A third voltage source node 1035 is coupled between the driver 1020 and the transistor model 1045. In some examples, the third voltage source node 1035 may represent the voltage applied to the gate of a transistor (such as the control terminal of a transistor included in transistor model 1045). In some examples, the third voltage source node 1035 may shift the gate voltage (e.g., the voltage at the control terminal of transistor 1074) to change the margin provided by the driver 1020 and determine the effect of the margin on the gate current and slew rate of transistor 1074, as described below. Figure 11 , Figure 12 , Figure 13 and / or Figure 14 As described. In some examples, a more negative voltage shift of the third voltage source node 1035 reduces the voltage required to drive transistor 1074 ( Therefore, as shown in Formula 1 above, the driver 1020 can be a transistor 1074 (such as the first voltage source node 1010, ...). Figure 5 The first voltage source node 516 provides more margin with a constant supply source voltage. Voltage shifting of the third voltage source 1035 (e.g., a method to obtain margin for transistor 1074) may be difficult to achieve (it may be impossible); however, voltage shifting can be achieved through analog testing on analog bench 1000 to demonstrate example performance of driver 1020.

[0131] Example transistor model 1045 includes transistor 1074, third inductor 1075, fourth inductor 1076, and fifth inductor 1078. Figure 10 In the example, transistor 1074 is an NMOS transistor. Transistor 1074 includes a control terminal 1080, a drain terminal 1082, and a source terminal 1084. A third inductor 1075 is coupled between a third voltage source node 1035 and the control terminal 1080, a fourth inductor 1076 is coupled between the drain terminal 1082 and the diode 1050, and a fifth inductor 1078 is coupled between the source terminal 1084 and the ground node 1070. In some examples, transistor model 1045 may represent, for example, Figure 1 The transistor 150 is a transistor. Therefore, inductors 1075, 1076, and 1078 can represent the internal inductance in transistor 150. For example, the third inductor 1075 can represent the gate inductance of transistor 1074, the fourth inductor 1076 can represent the drain inductance of transistor 1074, and the fifth inductor 1078 can represent the source inductance of transistor 1074.

[0132] exist Figure 10 In the example shown, diode 1050 is coupled between fourth inductor 1076 and second inductor 1055. In some examples, diode 1050 may limit the current flowing to drain terminal 1082. Current source node 1060 is coupled between fourth inductor 1076 and ground node 1070. Second inductor 1055 is coupled between diode 1050 and fourth voltage source node 1065. Fourth voltage source node 1065 is coupled between second inductor 1055 and ground node 1070. In some examples, fourth voltage source node 1065 may provide a signal (such as voltage VBUS) to represent the voltage supplied to the power converter including driver 1020, such as... Figure 1 Bus voltage node 140.

[0133] Figure 11 Figure 1100 is a signal diagram depicting the first current signal of the first transistor enabled by the first driver and the second current signal of the second transistor enabled by the second driver in a power conversion system under various voltage offsets (e.g., transistor margins). Figure 11 Signal diagram 1100 includes a first example current signal (line 1105) and a second example current signal (line 1110). Figure 11 In the middle, the first current signal (line 1105) can represent the current signal generated by... Figure 2 , Figure 3 and / or Figure 4 The drivers 205, 305, and 402 provide control terminals (such as those provided by transistors 210, 310, and 404) to transistors 210 and 404. Figure 4 The driver 402 provides current to the control terminal 436 of the transistor 404, and the second current signal (line 1110) can represent the current supplied by the transistor. Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 The driver 105 provides current to the control terminal 172 of the transistor 150.

[0134] Signal diagram 1100 illustrates the current that can be applied to (e.g., adapted to enable, be supplied to, be obtained from, etc.) the control terminals of transistors under various voltage margins provided at the control terminals. For example, the second current signal (line 1110) illustrates the voltage at the control terminal 172 of transistor 150, at which current can be supplied to the control terminal 172 to enable transistor 150. A voltage offset can be applied to a transistor (e.g., transistor 1074) having a source voltage (e.g., a voltage provided by a third voltage source 1035). Therefore, the voltage offset provided at the control terminals determines the margin of the transistor. Figure 11In the example, a larger negative margin value (e.g., voltage offset) indicates an additional margin provided to the transistor compared to a smaller negative margin value.

[0135] At a first example voltage offset of -3.48 volts at 1120, the first current signal (line 1105) is 750 mA, while the second current signal (line 1110) is 800 mA. At a second example voltage offset of -2.4 volts at 1130, the first current signal (line 1105) is 650 mA, while the second current signal (line 1110) is 800 mA. At a third example voltage offset of -1.2 volts at 1140, the first current signal (line 1105) is 500 mA, while the second current signal (line 1110) is 725 mA. Therefore, signal diagram 1100 shows that the current applied to the control terminal of the transistor (e.g., transistor 150) associated with the second current signal (line 1110) may be greater than the current applied to the control terminal of the transistor associated with the first current signal (line 1105) having the same voltage margin. Therefore, a driver (such as driver 105) associated with the second current signal (line 1110) can provide a larger gate drive current to the coupled transistor than the driver associated with the first current signal (line 1105), such as when the transistor's voltage offset is 0 volts. Furthermore, signal diagram 1100 shows that the gate current that driver 105 can provide to transistor 150 has a less sensitive margin than that of the drivers (such as drivers 205, 305, 402) represented by the first current signal (line 1105).

[0136] Figure 12 Figure 1200 is a signal diagram depicting the first conversion rate of a transistor enabled by a first driver and the second conversion rate of a transistor enabled by a second driver in a power conversion system under various voltage offsets (e.g., transistor margins). Figure 12 Signal diagram 1200 includes a first example slew rate (line 1205) and a second example slew rate (line 1210). In Figure 12 In the diagram, the first slew rate (line 1205) can represent the slew rate associated with the transistor, such as when transistor 404 is switched by... Figure 4 The voltage change at the drain terminal 438 of transistor 404 when the driver 402 is enabled. Furthermore, the first slew rate (line 1205) can be represented by the voltage change when transistor 210 is... Figure 2 When the driver 205 is enabled and / or when the transistor 310 is Figure 3 The associated conversion rate when the driver 305 is enabled. Similarly, in Figure 12 In the diagram, the second conversion rate (line 1210) can be represented when transistor 150 is... Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 When the driver 105 is enabled, the switching rate associated with the transistor, such as the voltage change at the drain terminal 176 of the transistor 150.

[0137] Signal diagram 1200 illustrates the slew rates that can be associated with the control terminals of a transistor under various voltage offsets provided at the control terminals. For example, a second slew rate (line 1210) can illustrate the change in voltage over time at the drain terminal 176 of transistor 150 when the transistor is enabled by driver 105 (e.g., activated, switched to an on state, etc.). Voltage offsets can be applied to the transistor (e.g., transistor 1074) through a voltage source node (e.g., a third voltage source 1035). Therefore, the voltage offset provided at the control terminals determines the transistor's margin. Figure 12 In the example, a larger negative margin value (e.g., voltage offset) indicates an additional margin provided to the transistor compared to a smaller negative margin value.

[0138] At a first example voltage offset of -3.6 volts at 1220, the first slew rate (line 1205) is 142.5 volts / nanosecond, while the second slew rate (line 1210) is 130 volts / nanosecond. At a second example voltage offset of -2.8 volts at 1230, the first slew rate (line 1205) is 130 volts / nanosecond, and the second slew rate (line 1210) is 133 volts / nanosecond. At a third example voltage offset of -1 volt at 1240, the first slew rate (line 1205) is 105 volts / nanosecond, while the second slew rate (line 1210) is 127 volts / nanosecond. Therefore, signal diagram 1200 shows that the slew rate (e.g., the change in voltage at the drain terminal over a period of time) of the transistor associated with the second slew rate (line 1210) (e.g., transistor 150) can be greater than the slew rate of the transistor associated with the first slew rate (line 1205) having the same voltage margin. Therefore, the driver associated with the second slew rate (line 1210) can make the slew rate of the coupled transistor greater than that associated with the first slew rate (line 1205) by providing a larger gate drive current to the transistor, such as when the transistor voltage offset is 0 volts. Furthermore, signal diagram 1200 illustrates that the slew rate of driver 105 is less sensitive to margins than drivers (such as drivers 205, 305, 402) represented by the first slew rate (line 1205).

[0139] Figure 13 Figure 1300 depicts the first current signal of a transistor enabled by a first driver and the second current signal of a second transistor enabled by a second driver in a power conversion system under various driver resistors. Figure 13 Signal diagram 1300 includes a first example current signal (line 1305) and a second example current signal (line 1310). Figure 13 In the middle, the first current signal (line 1305) can represent the current signal generated by... Figure 2 , Figure 3 and / or Figure 4 The drivers 205, 305, and 402 provide control terminals (such as those provided by transistors 210, 310, and 404) to transistors 210 and 404. Figure 4 The driver 402 provides current to the control terminal 436 of the transistor 404, and the second current signal (line 1310) can represent the current supplied by the transistor. Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8 The driver 105 provides current to the control terminal 172 of the transistor 150.

[0140] Signal diagram 1300 illustrates the current that can be applied to the control terminals of a transistor at various impedances (e.g., resistances) of a resistor (Rdrv) coupled to the driver. The resistor (e.g., Figure 10 The resistor 1012 can proportionally affect the current source in the driver (e.g., Figure 6 The current is supplied by the current source 632. For example, the second current signal (line 1310) can indicate the current supplied to the control terminal 172 to enable the transistor 150. In another example, the resistor impedance can be... Figure 10 The resistor 1012 controls the value of the current supplied by the current source node (IDRV) included in the driver 1020. In some examples, adjusting the resistor (Rdrv) 1012 can adjust a control signal provided by the driver 1020 (such as a control current, a first control signal provided by the first stage 510) and / or can adjust the slewing rate of the transistor 1074.

[0141] With a first example resistor 1320 of 20 kΩ, the first current signal (line 1305) is 175 mA, while the second current signal (line 1310) is 410 mA. With a second example resistor 1330 of 60 kΩ, the first current signal (line 1305) is 150 mA, while the second current signal (line 1310) is 225 mA. With a third example resistor 1340 of 90 kΩ, the first current signal (line 1305) is 120 mA, while the second current signal (line 1310) is 150 mA. Therefore, signal diagram 1300 shows that the current applied to the control terminal of the transistor (e.g., transistor 150) associated with the second current signal (line 1310) may be greater than the current applied to the control terminal of the transistor associated with the first current signal (line 1305) having the same resistance (e.g., driver resistance value). Therefore, at lower resistance impedances, the driver associated with the second current signal (line 1310) has unrestricted margin and can provide a higher gate drive current than the driver associated with the first current signal (line 1305). Furthermore, signal diagram 1300 shows that, compared to drivers associated with the first current signal (line 1305) such as drivers 205, 305, and 402, driver 105 can supply a larger gate current when a high slew rate is required (e.g., as the impedance of resistor 1012 decreases with increasing demand on driver 105).

[0142] Figure 14 Figure 1400 shows the signal diagrams depicting the first conversion rate of a transistor enabled by a first driver and the second conversion rate of a transistor enabled by a second driver in a power conversion system with various drive resistors. Figure 14 Signal diagram 1400 includes a first example slew rate (line 1405) and a second example slew rate (line 1410). Figure 14 In the diagram, the first slew rate (line 1405) can represent the slew rate associated with the transistor, such as when transistor 404 is switched by... Figure 4 The voltage change at the drain terminal 438 of transistor 404 when the driver 402 is enabled. Furthermore, the first slew rate (line 1205) can be represented by the voltage change when transistor 210 is... Figure 2 When the driver 205 is enabled and / or when the transistor 310 is Figure 3 The associated conversion rate when the driver 305 is enabled. Similarly, in Figure 14 In the diagram, the second conversion rate (line 1410) can be represented when transistor 150 is... Figure 5 , Figure 6 , Figure 7A , Figure 7B and / or Figure 8When the driver 105 is enabled, the switching rate associated with the transistor (such as the voltage change at the drain terminal 176 of the transistor 150).

[0143] Signal diagram 1400 illustrates the slew rate associated with the drain terminal at various impedances (e.g., resistances) of the resistor (Rdrv) coupled to the driver. The resistor (e.g., Figure 10 The resistor 1012 can proportionally affect the current source in the driver (e.g., Figure 6 The current supplied by the current source 632. For example, the second slew rate (line 1410) can illustrate the change in voltage at the drain terminal 176 of transistor 150 over time as the transistor is enabled. In another example, the resistor impedance can be... Figure 10 The resistor 1012 has an impedance, and the resistor 1012 controls the value of the current supplied by the current source node (IDRV) included in the driver 1020.

[0144] At a first example resistor 1420 of 20 kΩ, the first slew rate (line 1405) is 70 V / NDS, while the second slew rate (line 1410) is 100 V / NDS. At a second example resistor 1430 of 63 kΩ, the first slew rate (line 1405) is 52 V / NDS, while the second slew rate (line 1410) is 63 V / NDS. At a third example resistor 1440 of 90 kΩ, the first slew rate (line 1405) is 43 V / NDS, while the second slew rate (line 1410) is 50 V / NDS. Therefore, signal diagram 1400 indicates that the current applied to the control terminal of the transistor (e.g., transistor 150) associated with the second slew rate (line 1410) may be greater than the current applied to the control terminal of the transistor associated with the first slew rate (line 1405) having the same resistance (e.g., driver resistance value). Therefore, the driver associated with the second slew rate (line 1410) can make the slew rate of the coupled transistor greater than that associated with the first slew rate (line 1405), such as when the transistor's voltage offset is 0 volts. Furthermore, signal diagram 1400 shows that, compared to the drivers associated with the first slew rate (line 1405), such as drivers 205, 305, 402, driver 105 can make the slew rate of transistor 150 higher when needed (e.g., as the demand on driver 105 increases, the impedance of resistor 1012 decreases).

[0145] Figure 15 It is a description Figure 1 Example power converter 100 in driving such as Figure 1 Example signals of control signals and output signals during the operation of transistor 150 are shown in Figure 1500. Figure 15 Signal diagram 1500 includes a first depiction 1502, a second depiction 1504, a third depiction 1506, a fourth depiction 1508, a fifth depiction 1510, and a sixth depiction 1512. The first depiction 1502 includes an activation signal (line 1520), which can represent... Figure 1 and / or Figures 5-8 The voltage at input terminal 156 of driver 105. The second depiction 1504 includes a first trigger signal (line 1522) that may represent the voltage at the first output terminal 524 of regulator 505. The third depiction 1506 includes a regulation signal (line 1524) that may represent the current supplied by regulator 505 at the second output terminal 526 (e.g., the current through transistor 604). The fourth depiction 1508 includes a second trigger signal (line 1526) that may represent the voltage at the third output terminal 528 of regulator.

[0146] The fifth depiction 1510 includes an output signal (line 1528) that may represent the voltage at the output terminal 158 of the regulator and / or the voltage at the control terminal 172 of the transistor 150. Furthermore, the output signal (line 1528) may represent a first control signal provided by the first stage 510 at the output terminal 534 and / or a second control signal provided by the second stage 515 at the output terminal 538. The sixth depiction 1512 includes a drain signal (line 1530) that may represent the voltage at the drain terminal 176 of the transistor 150. Figure 15 In the example signal diagram 1500, the voltage or current amplitude of any signal (lines 1520, 1522, 1524, 1526, 1528, 1530) can be any suitable value.

[0147] At the first example time 1550, controller 120 increases the activation voltage signal (line 1520) to a logic high value of 5 volts. However, the logic high value can be any suitable amplitude, such as 6 volts. In response to the increase in the activation voltage signal (line 1520), regulator 505 increases the first trigger signal (line 1522) to 5 volts. In response to the increase in the first trigger signal (line 1522), first stage 510 provides a first control signal at output terminal 534, resulting in an increase in the output signal at output terminal 158. In response to the increase in voltage of the output signal (line 1528) (e.g., in response to the increase in voltage signal obtained at the second input terminal 522), regulator 505 provides an adjustment signal (line 1524) at the second output terminal 526.

[0148] At the second example time 1560, the first stage 510 increases the output signal (line 1528) to the voltage of the clamp voltage source node (VCLAMP) 605, and the regulator 505 increases the regulation signal (line 1524) to the value I_REG. Therefore, the regulator 505 regulates the first control signal (e.g., the output signal (line 1528)) by providing the regulation signal (line 1524). The regulation signal value I_REG can be any suitable current value, such as 1 ampere. In response to the output signal (line 1528) at control terminal 172 exceeding a threshold voltage (e.g., exceeding the voltage of VDRV and / or the voltage of VCLAMP), transistor 150 switches to the enable stage. Therefore, the source terminal 174 and the drain terminal 176 are electrically connected, and the drain signal (line 1530) decreases from the value of VBUS. Figure 15 In the example, the magnitude of VBUS can be any suitable voltage. For example, VBUS could represent the voltage value at bus voltage node (VIN) 140, or VBUS could represent a voltage of 10 volts.

[0149] In response to an increase in the output signal (line 1528) and thus an increase in the voltage signal obtained at the second input terminal 522, the linear regulator circuit 603 decreases the output signal at the output terminal 620. As a result, the comparator circuit 602 obtains the output signal of the linear regulator circuit 603 at the input terminal 629 and delays it by an example time period (t_delay) 1565. The length of the time period 1565 can be any suitable time period (e.g., 10 nanoseconds), and a filter circuit including resistor 766 and capacitor 768 controls the length of the time period 1565. Figure 15 In the example, the drain signal (line 1530) drops to 0 volts during time period 1565. However, the drain signal (line 1530) can drop to any suitable voltage, such as 1 volt. Furthermore, the drain signal (line 1530) can drop to a suitable voltage (e.g., 0 volts, 1 volt) before or after time period 1565.

[0150] After a period of time 1565 controlled by comparator circuit 602 (e.g., controlled by resistor 766 and capacitor 768), and at a third example time 1570, regulator 505 reduces the first trigger signal (line 1522) and the adjustment signal (line 1524) to 0 volts respectively, and regulator 505 reduces the second trigger signal (line 1526) to the value of VDRV-5V. In some examples, the voltage of the second voltage source node (VDRV) 518 may be 6 volts, and therefore the value of VDRV-5V may be 1 volt. In response to the reduction of the first trigger signal (line 1522), first stage 510 reduces the first control signal at output terminal 534 (e.g., stops supplying), and in response to the reduction of the second trigger signal (line 1526), ​​second stage 515 increases the second control signal at output terminal 538. As a result, the output signal (line 1528) at the output terminal 158 and control terminal 172 of transistor 150 reduces the voltage of the clamping voltage source node (VCLAMP) 605 to the voltage of the second voltage source node (VDRV) 518. As a result of the reduction in the output signal (line 1528), transistor 150 is enabled, and therefore, the drain signal (line 1530) remains at 0 volts.

[0151] At the fourth example time 1580, controller 120 reduces the activation signal (IN) (line 1520) to 0 volts. In response to the reduction of the activation signal (line 1520), regulator 505 increases the second trigger signal (line 1526) to the voltage of VDRV. As a result, second stage 515 reduces the second control signal, and therefore the output signal (line 1528) decreases to 0 volts. As a result, transistor 150 is disabled, and the drain signal (line 1530) increases to the voltage of VBUS.

[0152] This article describes example methods, apparatuses, systems, and articles of art for driving transistors. Other examples and combinations thereof include the following:

[0153] Example 1 includes an apparatus comprising a regulator including a first input terminal, a first output terminal, and a second output terminal adapted to be coupled to a control terminal of a transistor; a first stage including a first input terminal coupled to the first output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor; and a second stage including an input terminal coupled to the second output terminal of the regulator and an output terminal adapted to be coupled to the control terminal of the transistor.

[0154] Example 2 includes the apparatus described in Example 1, wherein the regulator includes a second input terminal and a logic gate, the logic gate including a first input terminal coupled to the second input terminal of the regulator, a second input terminal coupled to a comparator circuit, and an output terminal coupled to the first output terminal of the regulator.

[0155] Example 3 includes the apparatus described in Example 1, wherein the regulator includes a comparator circuit that includes an input terminal coupled to a linear regulator circuit, a first output terminal coupled to a second output terminal of the regulator, and a second output terminal coupled to a logic gate.

[0156] Example 4 includes the apparatus described in Example 1, wherein the transistor is a first transistor and the regulator includes a third output terminal; a linear regulator circuit including an output terminal, a first input terminal adapted to be coupled to a voltage source, and a second input terminal coupled to the first input terminal of the regulator; and a second transistor including a control terminal coupled to the output terminal of the linear regulator circuit, a first current terminal adapted to be coupled to a voltage source, and a second current terminal coupled to the third output terminal of the regulator.

[0157] Example 5 includes the apparatus described in Example 4, wherein the first stage includes a second input terminal coupled to the third output terminal of the regulator.

[0158] Example 6 includes the apparatus of Example 4, wherein the linear regulator circuit includes a second transistor including a control terminal, a first current terminal coupled to the first input terminal of the linear regulator circuit, and a second current terminal coupled to the control terminal of the second transistor; a third transistor including a control terminal coupled to the control terminal of the second transistor and adapted to be coupled to a ground node, a first current terminal coupled to the second input terminal of the linear regulator circuit, and a second current terminal; and a fourth transistor including a control terminal coupled to the second current terminal of the third transistor and adapted to be coupled to the ground node, a first current terminal adapted to be coupled to the ground node, and a second current terminal coupled to the output terminal of the linear regulator circuit.

[0159] Example 7 includes the apparatus described in Example 4, wherein the linear regulator circuit includes a second transistor, the second transistor including a control terminal coupled to a second input terminal of the linear regulator circuit, a first current terminal coupled to a first input terminal of the linear regulator circuit, and a second current terminal coupled to the output terminal of the linear regulator circuit.

[0160] Example 8 includes the apparatus of Example 1, wherein the transistor is a first transistor, and the first stage includes a switching circuit including a first terminal coupled to the input terminal of the first stage, a second terminal adapted to be coupled to a current source, and a third terminal; and a first current mirror circuit adapted to be coupled to a voltage source node, the first current mirror circuit including a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage.

[0161] Example 9 includes the apparatus of Example 8, wherein the first stage includes a second current mirror circuit coupled between the second terminal of the first current mirror circuit and the control terminal of the first transistor, the second current mirror circuit including a first terminal coupled to the second terminal of the first current mirror circuit and a second terminal adapted to be coupled to the control terminal of the first transistor.

[0162] Example 10 includes the apparatus of Example 9, wherein the second current mirror circuit includes a third transistor including a control terminal coupled to the first terminal of the second current mirror circuit, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal coupled to the first terminal of the second current mirror circuit; and a fourth transistor including a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal adapted to be coupled to the voltage source node.

[0163] Example 11 includes the apparatus of Example 8, wherein the current mirror circuit includes a third transistor including a control terminal coupled to a first terminal of the current mirror circuit, a first current terminal adapted to be coupled to the voltage source node, and a second current terminal coupled to the first terminal of the current mirror circuit; and a fourth transistor including a control terminal coupled to the control terminal of the third transistor, a first current terminal adapted to be coupled to the voltage source node, and a second current terminal coupled to the second terminal of the current mirror circuit.

[0164] Example 12 includes the apparatus of Example 8, wherein the switching circuit includes a third transistor, a first terminal of the switching circuit is coupled to a first output terminal of the regulator, a second terminal of the switching circuit is coupled to a first current terminal of the third transistor, and a third terminal of the switching circuit is coupled to a second current terminal of the third transistor.

[0165] Example 13 includes the apparatus described in Example 1, wherein the transistor is a first transistor, and the second stage includes a second transistor, the second transistor including a control terminal coupled to the input terminal of the second stage, a first current terminal adapted to be coupled to a voltage source node, and a second current terminal coupled to the output terminal of the second stage.

[0166] Example 14 includes an apparatus comprising: a first stage including an input terminal and an output terminal adapted to be coupled to a control terminal of a transistor, the first stage being adapted to enable the transistor using a first voltage from a first voltage source; a second stage including an input terminal and an output terminal adapted to be coupled to the control terminal of the transistor, the second stage being adapted to enable the transistor using a second voltage from a second voltage source, the first voltage having a greater potential than the second voltage; and a regulator including a first input terminal and a second input terminal adapted to be coupled to the control terminal of the transistor, a first output terminal coupled to the input terminal of the first stage, and a second output terminal coupled to the input terminal of the second stage, the regulator being adapted to enable the first stage based on an activation signal obtained at the second input terminal of the regulator exceeding a first threshold voltage level, and to enable the second stage based on a voltage signal at the first input terminal of the regulator exceeding a second threshold voltage level for a period of time.

[0167] Example 15 includes the apparatus described in Example 14, wherein the regulator includes a third output terminal, and the regulator is adapted to regulate the voltage at the first input terminal by providing a regulation signal at the third output terminal of the regulator.

[0168] Example 16 includes the apparatus described in Example 14, wherein the regulator is adapted to enable the first stage by providing a first trigger signal at the first output terminal of the regulator.

[0169] Example 17 includes the apparatus of Example 16, wherein the first stage is adapted to enable the transistor by providing a first control signal at the output terminal of the first stage based on the first trigger signal exceeding a third threshold voltage level.

[0170] Example 18 includes the apparatus of Example 14, wherein the regulator is adapted to be coupled to a clamping voltage source, and the regulator is adapted to disable the first stage based on a voltage signal at the first input terminal exceeding the voltage of the clamping voltage source.

[0171] Example 19 includes the apparatus described in Example 14, wherein the regulator is adapted to enable the second stage by providing a second trigger signal at the second output terminal of the regulator.

[0172] Example 20 includes the apparatus of Example 19, wherein the second stage is adapted to enable the transistor by providing a second control signal at the output terminal of the second stage based on the second trigger signal exceeding a third threshold voltage level.

[0173] Example 21 includes the apparatus of Example 14, wherein the transistor is a first transistor, and the first stage includes a switching circuit including a first terminal coupled to the first input terminal of the first stage, a second terminal adapted to be coupled to a current source, and a third terminal, wherein the switching circuit provides a mirror signal at the third terminal of the switching circuit based on a first trigger signal exceeding a third threshold voltage level.

[0174] Example 22 includes the apparatus of Example 21, wherein the transistor is a first transistor, and the first stage includes a current mirror circuit adapted to be coupled to a voltage source node, the current mirror circuit including a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage, the current mirror circuit being adapted to provide a first control signal at the second terminal of the current mirror circuit based on the mirror signal.

[0175] Example 23 includes the apparatus of Example 14, wherein the regulator is adapted to output a first trigger signal at a first output terminal in response to the activation signal exceeding a first threshold voltage level; and to output a second trigger signal at a second output terminal in response to the voltage signal exceeding a second threshold voltage level for a period of time.

[0176] Example 24 includes a system comprising a driver and a transistor, the driver including an input terminal adapted to receive an activation signal and an output terminal, the transistor including a control terminal coupled to the output terminal of the driver, the driver being adapted to output a first control signal to the control terminal of the transistor having a first voltage, and output a second control signal to the control terminal of the transistor having a second voltage, wherein the first voltage has a potential greater than the second voltage.

[0177] Example 25 includes the system described in Example 24, wherein the driver includes a regulator having a first input terminal coupled to the input terminal of the driver, a second input terminal coupled to the control terminal of the transistor, a first output terminal, and a second output terminal. The regulator is adapted to output a first trigger signal at the first output terminal of the regulator based on an activation signal obtained at the first input terminal of the regulator exceeding a first threshold voltage level, and to output a second trigger signal at the second output terminal of the regulator based on a voltage signal obtained at the second input terminal of the regulator exceeding a second threshold voltage level.

[0178] Example 26 includes the system described in Example 25, wherein the regulator includes a third output terminal, and the regulator is adapted to regulate the voltage at the input terminal of the regulator by providing a regulation signal at the third output terminal of the regulator.

[0179] Example 27 includes the system described in Example 24, wherein the driver includes a first stage, the first stage including an input terminal and an output terminal coupled to the control terminal of the transistor, the first stage being adapted to output the first control signal at the output terminal of the first stage based on a trigger signal obtained at the input terminal of the first stage exceeding a threshold voltage level.

[0180] Example 28 includes the system described in Example 24, wherein the driver includes a second stage, the second stage including an input terminal and an output terminal coupled to the control terminal of the transistor, the second stage being adapted to output the second control signal at the output terminal of the second stage based on a trigger signal obtained at the input terminal of the second stage exceeding a threshold voltage level.

[0181] From the foregoing, it should be understood that example methods, apparatuses, and articles of manufacture for driving transistors have been described. The described methods, apparatuses, and articles of manufacture improve the efficiency of using computing devices by enabling a driver in a power conversion system to drive the transistor gate from a turn-off state to a turn-on state with a signal higher than the turn-on gate signal. The described methods, apparatuses, and articles of manufacture are accordingly modified with respect to the functionality of a computer.

[0182] Although certain example methods, apparatuses, and articles have been described herein, the scope of this patent is not limited thereto. Rather, this patent covers all methods, apparatuses, and articles that fall fully within the scope of the claims of this patent.

[0183] The appended claims are hereby incorporated by reference into this detailed description, wherein each claim is an independent embodiment of the present description.

Claims

1. An apparatus for driving a transistor, comprising: Regulator, the regulator comprising: A first input terminal suitable for coupling to the control terminal of a transistor; First output terminal; Second output terminal; and A comparator circuit, the comparator circuit including an input terminal adapted to be coupled to the output terminal of a linear regulator circuit, a first output terminal coupled to the second output terminal of the regulator, and a second output terminal coupled to a logic gate; A first stage, comprising a first input terminal coupled to the first output terminal of the regulator and an output terminal coupled to the first input terminal of the regulator; and The second stage includes an input terminal coupled to the second output terminal of the regulator and an output terminal coupled to the first input terminal of the regulator.

2. The apparatus according to claim 1, wherein, The regulator includes a second input terminal and a logic gate, the logic gate having a first input terminal coupled to the second input terminal of the regulator, a second input terminal coupled to the second output terminal of the comparator circuit, and an output terminal coupled to the first output terminal of the regulator.

3. The apparatus according to claim 1, wherein, The regulator includes the linear regulator circuit having a first input terminal adapted to be coupled to a voltage source and a second input terminal coupled to the first input terminal of the regulator, wherein the comparator circuit is configurable to disable the first stage and enable the second stage in response to a signal at the input terminal of the comparator circuit not exceeding a threshold for a period of time.

4. The apparatus according to claim 3, wherein, The transistor is a first transistor, and the regulator includes: Third output terminal; and The second transistor includes a control terminal coupled to the output terminal of the linear regulator circuit, a first current terminal adapted to be coupled to a voltage source, and a second current terminal coupled to the third output terminal of the regulator.

5. The apparatus according to claim 4, wherein, The first stage includes a second input terminal coupled to the third output terminal of the regulator.

6. The apparatus according to claim 4, wherein, The linear regulator circuit includes: The second transistor includes a control terminal, a first current terminal coupled to the first input terminal of the linear regulator circuit, and a second current terminal coupled to the control terminal of the second transistor. A third transistor, the third transistor including a control terminal coupled to the control terminal of the second transistor and adapted to be coupled to a ground node, a first current terminal coupled to the second input terminal of the linear regulator circuit, and a second current terminal; and A fourth transistor includes a control terminal coupled to the second current terminal of the third transistor and adapted to be coupled to the ground node, a first current terminal adapted to be coupled to the ground node, and a second current terminal coupled to the output terminal of the linear regulator circuit.

7. The apparatus according to claim 4, wherein, The linear regulator circuit includes: The second transistor includes a control terminal coupled to the second input terminal of the linear regulator circuit, a first current terminal coupled to the first input terminal of the linear regulator circuit, and a second current terminal coupled to the output terminal of the linear regulator circuit.

8. The apparatus according to claim 1, wherein, The transistor is a first transistor, and the first stage includes: A switching circuit, the switching circuit including a first terminal coupled to the input terminal of the first stage, a second terminal adapted to be coupled to a current source, and a third terminal; and A first current mirror circuit adapted to be coupled to a voltage source node, the first current mirror circuit including a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage.

9. The apparatus according to claim 8, wherein, The first stage includes a second current mirror circuit coupled between the second terminal of the first current mirror circuit and the output terminal of the first stage. The second current mirror circuit includes a first terminal coupled to the second terminal of the first current mirror circuit and a second terminal coupled to the output terminal of the first stage.

10. The apparatus according to claim 9, wherein, The second current mirror circuit includes: A third transistor, the third transistor including a control terminal coupled to the first terminal of the second current mirror circuit, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal coupled to the first terminal of the second current mirror circuit; and The fourth transistor includes a control terminal coupled to the control terminal of the third transistor, a first current terminal coupled to the second terminal of the second current mirror circuit, and a second current terminal adapted to be coupled to the voltage source node.

11. The apparatus according to claim 8, wherein, The current mirror circuit includes: A third transistor, the third transistor including a control terminal coupled to the first terminal of the current mirror circuit, a first current terminal adapted to be coupled to the voltage source node, and a second current terminal coupled to the first terminal of the current mirror circuit; and The fourth transistor includes a control terminal coupled to the control terminal of the third transistor, a first current terminal adapted to be coupled to the voltage source node, and a second current terminal coupled to the second terminal of the current mirror circuit.

12. The apparatus according to claim 8, wherein: The switching circuit includes a third transistor; The first terminal of the switching circuit is coupled to the first output terminal of the regulator; The second terminal of the switching circuit is coupled to the first current terminal of the third transistor; as well as The third terminal of the switching circuit is coupled to the second current terminal of the third transistor.

13. The apparatus according to claim 1, wherein, The transistor is a first transistor, and the second stage includes a second transistor, the second transistor including a control terminal coupled to the input terminal of the second stage, a first current terminal adapted to be coupled to a voltage source node, and a second current terminal coupled to the output terminal of the second stage.

14. An apparatus for driving a transistor, comprising: A first stage, the first stage including an input terminal and an output terminal adapted to be coupled to a control terminal of a transistor, the first stage being adapted to enable the transistor using a first voltage from a first voltage source; The second stage includes an input terminal and an output terminal adapted to be coupled to the control terminal of the transistor. The second stage is adapted to enable the transistor using a second voltage from a second voltage source, wherein the first voltage has a greater potential than the second voltage. as well as A regulator, comprising a first input terminal and a second input terminal adapted to be coupled to the control terminal of the transistor, a first output terminal coupled to the input terminal of the first stage, and a second output terminal coupled to the input terminal of the second stage, the regulator being adapted to: The first stage is enabled based on the activation signal obtained at the second input terminal of the regulator exceeding the first threshold voltage level; as well as The second stage is enabled based on the voltage signal at the first input terminal of the regulator exceeding the second threshold voltage level for a period of time. as well as The regulator is adapted to be coupled to a clamping voltage source, and the regulator is configurable to disable the first stage based on the voltage signal at the first input terminal of the regulator exceeding the voltage of the clamping voltage source.

15. The apparatus according to claim 14, wherein, The regulator includes a third output terminal, and the regulator is adapted to adjust the voltage at the first input terminal of the regulator by providing an adjustment signal at the third output terminal of the regulator.

16. The apparatus according to claim 14, wherein, The regulator is adapted to enable the first stage by providing a first trigger signal at the first output terminal of the regulator.

17. The apparatus according to claim 16, wherein, The first stage is adapted to enable the transistor by providing a first control signal at the output terminal of the first stage based on the first trigger signal exceeding a third threshold voltage level.

18. The apparatus according to claim 14, wherein, The regulator is adapted to enable the second stage by providing a second trigger signal at the second output terminal of the regulator.

19. The apparatus according to claim 18, wherein, The second stage is adapted to enable the transistor by providing a second control signal at the output terminal of the second stage based on the second trigger signal exceeding a third threshold voltage level.

20. The apparatus according to claim 14, wherein, The transistor is a first transistor, and the first stage includes a switching circuit comprising a first terminal coupled to the input terminal of the first stage, a second terminal adapted to be coupled to a current source, and a third terminal, the switching circuit being adapted to provide a mirror signal at the third terminal of the switching circuit based on a first trigger signal exceeding a third threshold voltage level.

21. The apparatus according to claim 20, wherein, The transistor is a first transistor, and the first stage includes a current mirror circuit adapted to be coupled to a voltage source node. The current mirror circuit includes a first terminal coupled to the third terminal of the switching circuit and a second terminal coupled to the output terminal of the first stage. The current mirror circuit is adapted to provide a first control signal at the second terminal of the current mirror circuit based on the mirror signal.

22. The apparatus according to claim 14, wherein, The regulator is adapted to: In response to the activation signal exceeding the first threshold voltage level, a first trigger signal is output at the first output terminal; as well as In response to the voltage signal exceeding the second threshold voltage level within the specified time period, a second trigger signal is output at the second output terminal.

23. An electrical system comprising: A transistor, the transistor including a control terminal; as well as The driver includes: An input terminal, adapted to receive an activation signal; An output terminal, which is coupled to the control terminal of the transistor; The first stage includes an input terminal and an output terminal coupled to the control terminal of the transistor; The second stage includes an input terminal and an output terminal coupled to the control terminal of the transistor; Regulator, the regulator comprising: The first input terminal coupled to the control terminal of the transistor; Second input terminal; The first output terminal coupled to the input terminal of the first stage; and The second output terminal is coupled to the input terminal of the second stage. The regulator can be configured to: The first stage is enabled based on an activation signal obtained at the second input terminal of the regulator exceeding a first threshold voltage level; and The second stage is enabled based on the voltage signal at the first input terminal of the regulator exceeding the second threshold voltage level for a period of time; and The regulator is adapted to be coupled to a clamping voltage source, and the regulator is configurable to disable the first stage based on the voltage signal at the first input terminal of the regulator exceeding the voltage of the clamping voltage source.

24. The system according to claim 23, wherein, The regulator is adapted to: Based on the activation signal obtained at the first input terminal of the regulator exceeding the first threshold voltage level, a first trigger signal is output at the first output terminal of the regulator; as well as Based on the voltage signal obtained at the second input terminal of the regulator exceeding the second threshold voltage level, a second trigger signal is output at the second output terminal of the regulator.

25. The system according to claim 23, wherein, The regulator includes a third output terminal, and the regulator is adapted to regulate the voltage at the input terminal of the regulator by providing a regulation signal at the third output terminal of the regulator.

26. The system according to claim 23, wherein, The first stage is adapted to output a first control signal at the output terminal of the first stage based on a trigger signal obtained at the input terminal of the first stage exceeding a threshold voltage level.

27. The system according to claim 23, wherein, The second stage is adapted to output a second control signal at the output terminal of the second stage based on a trigger signal obtained at the input terminal of the second stage exceeding a threshold voltage level.

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