Generation method and device, verification method and device, electronic device and storage medium

Abstract

A method for generating path information for an object path in an integrated circuit design, a verification method, a generation device, a verification device, an electronic device, and a computer-readable storage node. The object path includes at least one buffer, and the generation method includes: extracting buffer information for at least one buffer in the object path from a buffer description file for the integrated circuit design; extracting path description information for the object path from a chip logic design file for the integrated circuit design based on the buffer information; and generating path information for the object path based on the path description information. This path information generation method can automatically generate path information for the object path, significantly reducing the time required to generate path information, thereby facilitating reduced verification time for integrated circuit design verification and improving verification efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method and device for generating path information, a method and device for verifying path information, an electronic device, and a storage medium. Background Art

[0002] Verification is the work of simulating and testing chip functional design and chip technology before chip production. As the scale of chips continues to increase, verification has become an important part of the chip research and development and design industry. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a method for generating path information of an object path in an integrated circuit design, where the object path includes at least one buffer. The method includes: extracting buffer information of at least one buffer in the object path from a buffer description file used for the integrated circuit design; extracting path description information of the object path from a chip logic design file of the integrated circuit design based on the buffer information; and generating path information of the object path based on the path description information.

[0004] For example, in the generating method provided by an embodiment of the present disclosure, the buffer information includes the name of the input signal of at least one buffer in the object path and the name of the output signal of at least one buffer.

[0005] For example, in the generation method provided in an embodiment of the present disclosure, path description information of the object path is extracted from the chip logic design file of the integrated circuit design based on the buffer information, including: determining the starting point and the end point of the object path from the chip logic design file of the integrated circuit design based on the name of the input signal of at least one buffer and the name of the output signal of at least one buffer; and extracting the starting point information of the starting point and the end point information of the end point from the chip logic design file of the integrated circuit design, the path description information including the starting point information and the end point information.

[0006] For example, in the generation method provided in one embodiment of the present disclosure, the starting point and the end point of the object path are determined from the chip logic design file of the integrated circuit design according to the name of the input signal of at least one buffer and the name of the output signal of at least one buffer, including: determining the first line network signal connected to the input port of the input signal of at least one buffer from the chip logic design file of the integrated circuit design, and using the other port connected to the first line network signal as the starting point of the object path; and determining the second line network signal connected to the output port of the output signal of at least one buffer from the chip logic design file of the integrated circuit design, and using the other port connected to the second line network signal as the end point of the object path.

[0007] For example, in the generation method provided in one embodiment of the present disclosure, the starting point information of the starting point and the end point information of the end point are extracted from the chip logic design file of the integrated circuit design, including: extracting the name of the starting point and the name of the end point from the chip logic design file of the integrated circuit design; and determining the first circuit module where the starting point is located according to the name of the starting point, and determining the second circuit module where the end point is located according to the name of the end point.

[0008] For example, the generation method provided in one embodiment of the present disclosure also includes: extracting an input circuit module connected to the input port of the input signal of at least one buffer and an output circuit module connected to the output port of the output signal of at least one buffer from the buffer description file of the integrated circuit design; judging whether the first circuit module and the second circuit module are respectively consistent with the input circuit module and the output circuit module; generating path information of the object path according to the path description information, including: in response to the first circuit module and the second circuit module being respectively consistent with the input circuit module and the output circuit module, generating path information of the object path according to the path description information.

[0009] For example, the generation method provided in one embodiment of the present disclosure also includes: obtaining clock path information of the clock signal of at least one buffer and the number of levels of at least one buffer from the buffer description file of the integrated circuit design; generating path information of the object path based on the path description information, including: generating path information of the object path based on the path description information and further based on the clock path information and the number of levels of at least one buffer.

[0010] For example, in a generation method provided in an embodiment of the present disclosure, clock path information of a clock signal of at least one buffer is obtained from a buffer description file of an integrated circuit design, including: extracting an instance name and a name of a clock signal of at least one buffer from the buffer description file of the integrated circuit design; and generating clock path information of the clock signal based on the instance name and the name of the clock signal.

[0011] For example, in the generation method provided in one embodiment of the present disclosure, path information of the object path is generated based on the path description information and further based on the clock path information and the number of levels of at least one buffer, including: establishing a correspondence between the name of the input signal of at least one buffer, the name of the output signal of at least one buffer, the clock path information, the number of levels of at least one buffer, and the path description information; and generating the path information of the object path based on the correspondence.

[0012] For example, in a generation method provided in an embodiment of the present disclosure, the path information is used to verify the object path using a verification device, and the method further includes: generating a path information file containing the path information according to a file format recognized by the verification device.

[0013] At least one embodiment of the present disclosure provides a verification method for verifying an object path in an integrated circuit design, comprising: obtaining path information of the object path according to the generation method provided in any embodiment of the present disclosure; obtaining a black box file of the integrated circuit design, the black box file including module information of multiple circuit modules included in the integrated circuit design and circuit modules that are not related to the verification of the object path; and verifying the object path based on the path information and the black box file to generate a verification result.

[0014] At least one embodiment of the present disclosure provides a device for generating path information of an object path in an integrated circuit design, where the object path includes at least one buffer. The generating device includes: a first extraction unit configured to extract buffer information of at least one buffer in the object path from a buffer description file used for the integrated circuit design; a second extraction unit configured to extract path description information of the object path from a chip logic design file of the integrated circuit design based on the buffer information; and a generation unit configured to generate path information of the object path based on the path description information.

[0015] For example, in a generation device provided in an embodiment of the present disclosure, the second extraction unit includes a determination subunit and a first extraction subunit. The determination subunit is configured to determine the start point and end point of the object path from a chip logic design file of the integrated circuit design based on the name of the input signal of at least one buffer and the name of the output signal of at least one buffer. The first extraction subunit is configured to extract starting point information of the start point and end point information of the end point from the chip logic design file of the integrated circuit design, where the path description information includes the starting point information and the end point information.

[0016] For example, in a generation device provided in an embodiment of the present disclosure, the determination subunit includes a start point determination subunit and an end point determination subunit. The start point determination subunit is configured to determine, from a chip logic design file of the integrated circuit design, a first net signal connected to an input port of an input signal of at least one buffer, and use the other port connected to the first net signal as the start point of the object path. The end point determination subunit is configured to determine, from the chip logic design file of the integrated circuit design, a second net signal connected to an output port of an output signal of at least one buffer, and use the other port connected to the second net signal as the end point of the object path.

[0017] For example, in the generation device provided in one embodiment of the present disclosure, the first extraction subunit includes a name extraction subunit and a module extraction subunit. The name extraction subunit is configured to extract the name of the starting point and the name of the end point from the chip logic design file of the integrated circuit design. The module extraction subunit is configured to determine the first circuit module in which the starting point is located based on the name of the starting point, and to determine the second circuit module in which the end point is located based on the name of the end point.

[0018] For example, in the generation device provided in one embodiment of the present disclosure, a third extraction unit and a judgment unit are further included. The third extraction unit is configured to extract an input circuit module connected to an input port of an input signal of at least one buffer and an output circuit module connected to an output port of an output signal of at least one buffer from the buffer description file of the integrated circuit design. The judgment unit is configured to judge whether the first circuit module and the second circuit module are consistent with the input circuit module and the output circuit module, respectively. The generation unit includes a first generation sub-unit, which is configured to generate path information of the object path according to the path description information in response to the first circuit module and the second circuit module being consistent with the input circuit module and the output circuit module, respectively.

[0019] For example, a generation device provided in an embodiment of the present disclosure further includes an acquisition unit configured to acquire clock path information of a clock signal of at least one buffer and the number of stages of at least one buffer from a buffer description file of an integrated circuit design. The generation unit includes a second generation sub-unit configured to generate path information of an object path based on the path description information and further based on the clock path information and the number of stages of at least one buffer.

[0020] For example, in a generation device provided in an embodiment of the present disclosure, the acquisition unit includes a second extraction subunit and a clock information generation subunit. The second extraction subunit is configured to extract the instance name and clock signal name of at least one buffer from a buffer description file of an integrated circuit design. The clock information generation subunit is configured to generate clock path information for the clock signal based on the instance name and the clock signal name.

[0021] For example, in a generation device provided in an embodiment of the present disclosure, the second generation subunit includes an establishment subunit and a path information generation subunit. The establishment subunit is configured to establish a correspondence between the name of the input signal of at least one buffer, the name of the output signal of at least one buffer, clock path information, the number of stages of at least one buffer, and path description information. The path information generation subunit is configured to generate path information for the object path based on the correspondence.

[0022] For example, in a generation device provided in an embodiment of the present disclosure, the path information is used to verify the object path using a verification device. The generation device also includes a file generation unit configured to generate a path information file containing path information according to a file format recognized by the verification device.

[0023] At least one embodiment of the present disclosure provides a verification device for verifying an object path in an integrated circuit design, comprising: a path information acquisition unit configured to acquire path information of the object path according to a generation method provided in any embodiment of the present disclosure; a black box file acquisition unit configured to acquire a black box file of the integrated circuit design, the black box file including module information of multiple circuit modules included in the integrated circuit design that are not related to the verification of the object path; and a verification unit configured to verify the object path based on the path information and the black box file and generate a verification result.

[0024] At least one embodiment of the present disclosure provides an electronic device, comprising a processor; a memory comprising one or more computer program instructions; the one or more computer program instructions are stored in the memory and, when executed by the processor, implement the generation method or verification method provided by any embodiment of the present disclosure.

[0025] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions. When the computer-readable instructions are executed by a processor, the generation method or verification method provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0027] Figure 1A A flowchart of a method for generating path information of an object path in integrated circuit design provided by at least one embodiment of the present disclosure is shown;

[0028] Figure 1B A schematic diagram illustrating a file format of a buffer description file provided by at least one embodiment of the present disclosure is shown;

[0029] Figure 1C A schematic diagram showing the file format of a chip logic design file provided by at least one embodiment of the present disclosure is shown;

[0030] Figure 2 At least one embodiment of the present disclosure provides Figure 1A Flowchart of the method of step S20;

[0031] Figure 3 A flowchart showing another generation method provided by at least one embodiment of the present disclosure is shown;

[0032] Figure 4 A schematic diagram showing the file format of a path information file provided by at least one embodiment of the present disclosure is shown;

[0033] Figure 5 A flowchart showing another generation method provided by at least one embodiment of the present disclosure is shown;

[0034] Figure 6A A flowchart of a verification method for verifying an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown;

[0035] Figure 6B A flowchart of another verification method for verifying an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown;

[0036] Figure 7A A schematic block diagram of a device for generating path information of an object path in integrated circuit design provided by at least one embodiment of the present disclosure is shown;

[0037] Figure 7B A schematic block diagram of a verification device for verifying an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown;

[0038] Figure 8 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0039] Figure 9 A schematic block diagram showing another electronic device provided by at least one embodiment of the present disclosure; and

[0040] Figure 10 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0041] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0043] In the system-on-a-chip (SoC) design verification, dynamic simulation verification or static formal verification can usually be used to verify the SoC design (for example, verification of SoC connectivity). Dynamic simulation verification may, for example, include extracting verification function points, applying stimuli to the SoC design, and verifying whether the SoC design complies with the design specifications by observing the output results of the SoC design. It is difficult to describe the timing logic and gating logic with functional coverage in dynamic simulation verification, and if the number of interconnected signals is large, it is necessary to separately construct a large number of use cases to check connectivity and process intermediate signals, which is difficult to maintain once changes occur. Static formal verification may, for example, include mathematically completely proving or verifying whether the circuit implementation scheme actually implements the functions described by the SoC design. Static formal verification requires model extraction of the SoC design, which requires the verifier to have very high mathematical skills and experience.

[0044] In current ultra-large-scale SoCs, the physical implementation of the layout needs to be divided into multiple circuit modules, each of which is then completed through top-level design. As chip size continues to increase, the area increases, and the connections between circuit modules increase accordingly. This line delay inevitably leads to timing issues. To address this issue, buffers (for example, flip-flops) are inserted into the connection between two circuit modules to converge timing. As chip size increases, the number of buffers required in the entire physical design also increases. For example, in large-scale designs, hundreds of thousands of buffers are often required to achieve timing convergence.

[0045] In order to make the verification of integrated circuit designs simpler, some verification tools have emerged. The use of verification tools can simplify the difficulty of verifying SoC designs. Verification tools include, for example, connection checking tools for checking the connectivity of paths. The connection checking tool provides a script format specifically used to describe the path information of the path to be tested. The script contains information such as the source point, destination point, selection signal, clock signal, signal delay, etc. on the path. The verifier can describe the path information of the path to be checked in the corresponding script according to the script format defined by the connection checking tool, and then read the design file and the script including the path information through commands to check the connectivity of the path and give a report. However, when faced with a huge number of signals, writing a script for path information is undoubtedly a huge project.

[0046] At least one embodiment of the present disclosure provides a method for generating path information of an object path in an integrated circuit design, wherein the object path includes at least one buffer. The method comprises: extracting buffer information of at least one buffer in the object path from a buffer description file used for the integrated circuit design; extracting path description information of the object path from a chip logic design file of the integrated circuit design based on the buffer information; and generating path information of the object path based on the path description information. The method for generating path information can automatically generate path information of the object path, greatly saving the time required to generate path information, thereby facilitating saving verification time for integrated circuit design verification and improving verification efficiency. In addition, the method for generating path information of the object path provided by the present disclosure is easy to reuse.

[0047] Figure 1A A flowchart of a method for generating path information of an object path in integrated circuit design provided by at least one embodiment of the present disclosure is shown.

[0048] like Figure 1A As shown, the generating method may include steps S10 to S30.

[0049] Step S10: extracting buffer information of at least one buffer in the object path from a buffer description file for integrated circuit design.

[0050] Step S20: extracting path description information of the object path from the chip logic design file of the integrated circuit design according to the buffer information.

[0051] Step S30: Generate path information of the object path according to the path description information.

[0052] In the embodiment of the present disclosure, the path information of the object path obtained is used to verify the object path in the integrated circuit design.

[0053] For step S10 , the object path includes at least one buffer.

[0054] In some embodiments of the present disclosure, a buffer description file may be provided by the back-end physical design process. Based on the results of chip placement and timing closure checks, the back-end physical design process provides a buffer description file containing basic buffer information. For example, the buffer description file may include the number of buffer levels required for a signal line between two circuit modules, signal information at both ends of the line, and clock information used by the buffer. For example, the buffer description file may be in the .xml file format.

[0055] Figure 1B A schematic diagram illustrating the file format of a buffer description file provided by at least one embodiment of the present disclosure is shown.

[0056] like Figure 1B As shown, the name of the buffer description file is, for example, repeater.xml. The buffer description file may include basic information such as the buffer's clock information (i.e., rep clk_wire=aaa), the buffer's instantiation name in the top-level file (i.e., rep_inst=bbb), the number of buffer stages (i.e., pd=x), the signal name of the input signal in the buffer (e.g., wire name=ccc), and circuit module information at both ends of the buffer (e.g., block_inst=xxxx port_blkport=receive; block_inst=xxxx port_blkpot=transmit). It should be understood that "bbb," "x," "ccc," etc. are only schematic representations.

[0057] It is understandable that Figure 1B Only part of the information in the buffer description file is shown, not all of the information in the buffer description file. For example, the buffer description file may also include the signal name of the output signal of the buffer.

[0058] In some embodiments of the present disclosure, the buffer information includes a name of an input signal of at least one buffer in the object path and a name of an output signal of at least one buffer.

[0059] For example, from Figure 1B In the illustrated repeater.xml file, the names of the input signals extracted from at least one buffer in the object path are "ccc," "ddd," and "eee," etc. The name of the input signal when it is output from the buffer (i.e., the name of the output signal of the buffer) can be "name of input signal_rep," such as "ccc_rep," "ddd_rep," and "eee_rep."

[0060] For step S20 , the chip logic design file may include, for example, a register transfer level (RTL) file or a register transfer level (RTL) file.

[0061] The path description information of the object path may include, for example, the starting point and the end point of the object path, the circuit module where the starting point is located and the circuit module where the end point is located, etc.

[0062] Figure 1C A schematic diagram of the file format of a chip logic design file provided by at least one embodiment of the present disclosure is shown.

[0063] like Figure 1C As shown, the name of the chip logic design file is, for example, chip.v, which includes information such as the instance name of the buffer in the top-level file (hereinafter referred to as "buffer instance name") "repeater_instance_name" and the name of the buffer input signal "repeater_signal_name".

[0064] The following combination Figure 1C and the following Figure 2 The implementation of step S20 will be described.

[0065] Figure 2 At least one embodiment of the present disclosure provides Figure 1A Flowchart of the method for step S20 in FIG.

[0066] like Figure 2 As shown, step S20 may include step S21 and step S22.

[0067] Step S21: determining a start point and an end point of an object path from a chip logic design file of an integrated circuit design according to a name of an input signal of at least one buffer and a name of an output signal of at least one buffer.

[0068] Step S22: extracting the starting point information of the starting point and the ending point information of the ending point from the chip logic design file of the integrated circuit design.

[0069] In this embodiment, the path description information includes start point information and end point information.

[0070] For step S21 , for example, a first net signal connected to an input port of an input signal of at least one buffer is determined from a chip logic design file of an integrated circuit design, and another port connected to the first net signal is used as a starting point of the object path.

[0071] For example, according to the instantiation name of the buffer extracted from the buffer description file, the corresponding buffer is found in chip.v, and then the first wire net signal connected to the input port of the input signal of the buffer is found according to the name of the input signal of the buffer. For example, the buffer description file includes rep_inst=repeater_instance_name, that is, the instantiation name of the buffer is repeater_instance_name, so according to repeater_instance_name, the corresponding buffer is found in chip.v. Next, for example, according to the name of the input signal in the buffer repeater_instance_name (for example, the name of the input signal is repeater_signal_name), the name of the first wire net signal (wire) connected to repeater_signal_name is found in chip.v. The first wire net signal represents the physical connection between hardware units. In hardware design languages ​​such as Verilog, wire is a commonly used data type, and the physical connection between hardware units is represented by the wire type. For example, in Figure 1C In the example, the name of the first line network signal is chip_level_connet_signal. Then, according to the name of the first line network signal, find the other port connected to the first line network signal in chip.v. For example, in Figure 1C In the example, the name of the signal output by the other port connected to the first net signal is a_signal_name. Therefore, the other port that outputs the a_signal_name signal is the starting point of the object path.

[0072] Similarly, for example, a second net signal connected to an output port of an output signal of at least one buffer is determined from a chip logic design file of an integrated circuit design, and another port connected to the second net signal is used as the end point of the object path.

[0073] This method can quickly and easily determine the start and end points of an object path based on the signal names connected at both ends of the wire network.

[0074] For step S22, for example, the name of the starting signal and the name of the end signal are extracted from the chip logic design file of the integrated circuit design; and the first circuit module where the starting point is located is determined according to the name of the starting signal, and the second circuit module where the end point is located is determined according to the name of the end signal.

[0075] For example, based on the starting point found in step S21, the signal name a_signal_name of the starting point connected to the first net signal is found, and the circuit module where the starting point is located is found in chip.v based on the a_signal_name signal, thereby obtaining the starting point information of the starting point connected to the input signal of the buffer. The starting point information may include, for example, complete path information such as the name of the starting point signal and the circuit module where the starting point is located.

[0076] Similarly, based on the endpoint found in step S22, the signal name of the endpoint connected to the second net signal is found, and based on the signal name of the endpoint, the circuit module where the endpoint is located is found in the chip.v file, thereby obtaining the endpoint information of the endpoint connected to the output signal of the buffer. The endpoint information may include, for example, complete path information such as the name of the endpoint signal and the circuit module where the endpoint signal is located.

[0077] For step S30, in some embodiments of the present disclosure, the generation method may also include obtaining clock path information of the clock signal of at least one buffer and the number of levels of at least one buffer from the buffer description file of the integrated circuit design, so that step S30 can be based on the path description information and further based on the clock path information and the number of levels of at least one buffer, to generate path information of the object path.

[0078] For example, extracting the instance name of at least one buffer and the name of the clock signal from the buffer description file of the integrated circuit design, and generating clock path information of the clock signal based on the instance name and the name of the clock signal. For example, the clock path information may include the signal name of the clock signal. Figure 1B In the example, the signal name of the clock signal with a complete path can be generated according to the clock information of the buffer (ie, rep clk_wire=aaa), the instantiation name of the buffer (ie, rep_inst=bbb), and the number of stages of the buffer (ie, pd=x).

[0079] For example, when there are multiple object paths, a correspondence table may be generated to record the correspondence between each object path and path information.

[0080] For example, for each object path, a correspondence is established between the name of the input signal of at least one buffer, the name of the output signal of at least one buffer, the clock path information, the number of levels of at least one buffer, and the path description information, and an object relationship table of multiple object paths is obtained, thereby generating path information of the object path based on the correspondence.

[0081] Figure 3 A flowchart of another generation method provided by at least one embodiment of the present disclosure is shown.

[0082] like Figure 3 As shown, the generation method may further include step S40 and step S50 in addition to step S10 to step S30.

[0083] Step S40: extracting an input circuit module connected to an input port of an input signal of at least one buffer and an output circuit module connected to an output port of an output signal of at least one buffer from the buffer description file of the integrated circuit design.

[0084] Step S50: determining whether the first circuit module and the second circuit module are consistent with the input circuit module and the output circuit module respectively.

[0085] In this embodiment, step S30 includes generating path information of the object path according to the path description information in response to the first circuit module and the second circuit module being consistent with the input circuit module and the output circuit module respectively.

[0086] The method can compare the circuit modules connected to both ends (i.e., input port and output port) of at least one buffer extracted from the buffer description file with the circuit modules connected to both ends of at least one buffer extracted from the chip logic design file, thereby verifying the buffer description file and the chip logic design file, which can not only improve the accuracy of the generated path information, but also timely discover problems in the buffer description file and the chip logic design file.

[0087] For step S40, for example, Figure 1B In the example of , the input circuit module and the output circuit module can be determined according to block_inst=xxxx port_blkport=receive and block_inst=xxxx port_blkpot=transmit in the buffer description file repeater.xml file.

[0088] In step S50 , it is determined whether the name of the input circuit module obtained according to block_inst=xxxx port_blkport=receive is consistent with the name of the first circuit module, and whether the name of the output circuit module obtained according to block_inst=xxxx port_blkpot=transmit is consistent with the name of the second circuit module.

[0089] In step S31 , if the name of the first circuit module is consistent with the name of the input circuit module, and the name of the second circuit module is consistent with the name of the output circuit module, path information of the object path is generated according to the path description information.

[0090] In some embodiments of the present disclosure, the path information is used to verify the object path using a verification device, and the generation method may further include generating a path information file containing the path information according to a file format recognized by the verification device.

[0091] For example, the verification device can recognize the .tcl file format, and outputs the path information into the .tcl file according to the .tcl file format.

[0092] Figure 4 A schematic diagram of the file format of a path information file provided by at least one embodiment of the present disclosure is shown.

[0093] like Figure 4 As shown, the path information file is named add_cc.tcl, for example. The add_cc.tcl file may include path start point information (for example, the name of the start point signal), end point information (for example, the name of the end point signal), the number of buffer levels, and buffer clock information.

[0094] For example, Figure 4 The add_cc.tcl file in

[15] shows the object paths a_to_b, c_to_d, and e_to_f. For example, for the object path a_to_b, the name of the starting signal is a, the circuit module where the starting signal resides is circuit module A, the name of the end signal is b, the circuit module where the end signal resides is circuit module B, and the clock signal is C.clk.

[0095] like Figure 4 As shown, the source module of the a_to_b path and the c_to_d path are both circuit module A, and the destination module is both circuit module B. The source module of the Be_to_f path is circuit module D, and the destination module is circuit module F.

[0096] like Figure 4 As shown, the path information file may also include path delay information for the target path. For example, path_delay represents the path delay information for the target path. For example, the a_to_b path and the c_to_d path are delayed by 1 clock cycle, and the e_to_f path is delayed by 2 clock cycles.

[0097] Figure 5 A flowchart of another generation method provided by at least one embodiment of the present disclosure is shown.

[0098] like Figure 5 As shown, the generating method may include steps S501 to S506.

[0099] Step S501: Obtain a buffer description file, which may be, for example, repeater.xml.

[0100] Step S502: Obtain a chip logic design file of an integrated circuit design, such as chip.v.

[0101] Step S503: Extract the signal name of the buffer (eg, the name of the input signal and the name of the output signal) and the module information at both ends of the buffer (ie, Figure 3 The input circuit module and the output circuit module in step S40).

[0102] Step S504: Using the module information and the signal name of the buffer, find the first circuit module (i.e., the circuit module where the starting signal is located), the name of the starting signal, the second circuit module (i.e., the circuit module where the end signal is located), and the name of the end signal of the object path in chip.v. Step S504 is similar to the above. Figure 2 Described method.

[0103] For example, first, the signal name of the input signal in the repeater is extracted from the repeater.xml file. The signal name of the input signal when it is output from the repeater is, for example, "input signal name_rep".

[0104] Next, the buffer instance name and the clock signal name in the repeater.xml file are extracted to form clock path information with a complete path, and a corresponding relationship is established with the name of the buffer input signal through a hash algorithm.

[0105] For example, find the corresponding buffer in chip.v according to the instantiation name of the buffer, and find the top-level net signal connected to the buffer input signal in chip.v according to the name of the input signal in the buffer (that is, Figure 2 The name of the first net signal in step S21 is obtained. Then, based on the name of the top-level net signal, another connection point (e.g., a port) of the top-level net signal is found. Based on this other connection point, the name of the signal connected to the top-level net signal (i.e., the name of the starting signal) and the circuit module where this signal name is located (i.e., the first circuit module mentioned above) are found. Thus, the name of the starting signal with complete path information and connected to the buffer's input signal can be obtained, and a corresponding relationship is established with the buffer's input signal through a hash algorithm.

[0106] Similarly, for example, the name of the destination signal with complete path information and connected to the output signal of the buffer can be found, and a corresponding relationship can be established with the output signal of the buffer through a hash algorithm.

[0107] Next, for example, the module information at both ends of the repeater extracted from the repeater.xml file can be compared with the name of the first circuit module and the name of the second circuit module where the input signal and output signal are located respectively found in the chip.v file, so as to perform a comparison and verification. This step is similar to the above Figure 3 Steps S40 and S50 are described.

[0108] Step S505: For example, extract the buffer level number and clock information in the repeater.xml file, and establish a corresponding relationship with the input signal name of the buffer through a hash algorithm.

[0109] Step S506: In response to the comparison and verification in step S504 being passed, all path information is output to the add_cc.tcl file in a format recognized by the verification device.

[0110] Figure 6A A flowchart of a verification method for verifying an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown.

[0111] like Figure 6A As shown, the verification method may include steps S610 to S630.

[0112] Step S610: Obtain path information of the object path according to the generation method.

[0113] Step S620: Obtain a black box file of the integrated circuit design, where the black box file includes module information of a plurality of circuit modules included in the integrated circuit design and circuit modules that are irrelevant to the verification of the object path.

[0114] Step S630: Based on the path information file and the black box file, verify the object path to generate a verification result.

[0115] In the above verification method, for step S610, the path information may be generated according to any of the generation methods described above, or the path information may be obtained by reading a path information file obtained according to any of the generation methods described above, for example, by reading the add_cc.tcl file described above.

[0116] In the above verification method, for step S620, the black box file may be manually written by the verifier himself, or may be automatically generated by the verification device.

[0117] In some embodiments of the present disclosure, a method for generating a black box file may include: obtaining hierarchical information of an integrated circuit design, the hierarchical information including structural information and module information of the integrated circuit design. For example, the hierarchical information of the integrated circuit design may be obtained based on the chip logic design file. Then, the hierarchical information is used to determine multiple path-related circuit modules related to the object path in the integrated circuit design; and a black box file is generated based on the module information of the path-independent circuit modules in the integrated circuit design, where the path-independent circuit modules are modules in the integrated circuit design other than the multiple path-related circuit modules. The method for generating a black box file can simplify the tedious steps of generating a black box file and improve the efficiency of generating a black box file.

[0118] Regarding step S630 , for example, the verification tool reads the path information file and the black box file, and verifies the object path according to the path information file and the black box file to generate a verification result.

[0119] Figure 6A The verification method shown can reduce the complexity of obtaining path information, shorten the verification time for buffer connectivity checks, and improve the verification efficiency of integrated circuit designs. Furthermore, this path information generation method can simultaneously obtain path information for tens of thousands of paths, enabling the verification method to simultaneously check tens of thousands of paths, with each path's inspection results presented in a report. Furthermore, this verification method facilitates the collection of flip coverage, ensuring verification completeness.

[0120] Figure 6B A flowchart of another verification method for verifying an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown.

[0121] like Figure 6B As shown, the verification method may include steps S601 to S607.

[0122] Step S601: Obtain a chip logic design file (eg, RTL file) of an integrated circuit design.

[0123] Step S602: Acquire the path information provided by any embodiment of the present disclosure, or the path information file provided by an embodiment of the present disclosure, for example, the add_cc.tcl file described above.

[0124] Step S603: Obtaining a black box file. By setting the modules in the integrated circuit design that are not related to the path to be tested as black boxes, the analysis efficiency of the verification tool can be improved.

[0125] Step S604: Obtain a verification script (e.g., a run.tcl file) to be run by the verification tool. For example, the verification tool may be a connection check tool. For example, the run.tcl file may contain basic setting commands for the connection check tool, commands for reading black box files, commands for reading design files, commands for reading path description files, and commands for starting path checking.

[0126] Step S605: Run the run.tcl file.

[0127] Step S606: Generate a verification result, which may be, for example, a result file vcf.log.

[0128] Step S607: Debug the path that failed verification through debugging commands or an interactive interface, for example, analyzing the cause of the verification failure, modifying the integrated circuit design, or modifying the path information file add_cc.tcl.

[0129] Figure 7A A schematic block diagram of an apparatus 700 for generating path information of an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown.

[0130] For example, Figure 7A As shown, the generating device 700 includes a first extracting unit 710 , a second extracting unit 720 and a generating unit 730 .

[0131] An object path in the integrated circuit design includes at least one buffer.

[0132] The first extraction unit 710 is configured to extract buffer information of at least one buffer in the object path from a buffer description file for the integrated circuit design.

[0133] The first extraction unit 710 may perform, for example, Figure 1A Step S10 is described.

[0134] The second extraction unit 720 is configured to extract the path description information of the object path from the chip logic design file of the integrated circuit design according to the buffer information.

[0135] The second extraction unit 720 may perform, for example, Figure 1A Step S20 is described.

[0136] The generating unit 730 is configured to generate path information of the object path according to the path description information.

[0137] The generating unit 730 may execute, for example, Figure 1A Step S30 is described.

[0138] For example, in the generation device provided in an embodiment of the present disclosure, the second extraction unit 720 may include a determination subunit and a first extraction subunit. The determination subunit is configured to determine the start point and end point of the object path from the chip logic design file of the integrated circuit design based on the name of the input signal of at least one buffer and the name of the output signal of at least one buffer. The first extraction subunit is configured to extract the start point information of the start point and the end point information of the end point from the chip logic design file of the integrated circuit design, where the path description information includes the start point information and the end point information.

[0139] For example, in a generation device provided in an embodiment of the present disclosure, the determination subunit includes a start point determination subunit and an end point determination subunit. The start point determination subunit is configured to determine, from a chip logic design file of the integrated circuit design, a first net signal connected to an input port of an input signal of at least one buffer, and use the other port connected to the first net signal as the start point of the object path. The end point determination subunit is configured to determine, from the chip logic design file of the integrated circuit design, a second net signal connected to an output port of an output signal of at least one buffer, and use the other port connected to the second net signal as the end point of the object path.

[0140] For example, in the generation device provided in one embodiment of the present disclosure, the first extraction subunit includes a name extraction subunit and a module extraction subunit. The name extraction subunit is configured to extract the name of the starting point and the name of the end point from the chip logic design file of the integrated circuit design. The module extraction subunit is configured to determine the first circuit module in which the starting point is located based on the name of the starting point, and to determine the second circuit module in which the end point is located based on the name of the end point.

[0141] For example, in the generation device provided in one embodiment of the present disclosure, a third extraction unit and a judgment unit are further included. The third extraction unit is configured to extract an input circuit module connected to an input port of an input signal of at least one buffer and an output circuit module connected to an output port of an output signal of at least one buffer from the buffer description file of the integrated circuit design. The judgment unit is configured to judge whether the first circuit module and the second circuit module are consistent with the input circuit module and the output circuit module, respectively. The generation unit includes a first generation sub-unit, which is configured to generate path information of the object path according to the path description information in response to the first circuit module and the second circuit module being consistent with the input circuit module and the output circuit module, respectively.

[0142] For example, a generation device provided in an embodiment of the present disclosure further includes an acquisition unit configured to acquire clock path information of a clock signal of at least one buffer and the number of stages of at least one buffer from a buffer description file of an integrated circuit design. The generation unit includes a second generation sub-unit configured to generate path information of an object path based on the path description information and further based on the clock path information and the number of stages of at least one buffer.

[0143] For example, in a generation device provided in an embodiment of the present disclosure, the acquisition unit includes a second extraction subunit and a clock information generation subunit. The second extraction subunit is configured to extract the instance name and clock signal name of at least one buffer from a buffer description file of an integrated circuit design. The clock information generation subunit is configured to generate clock path information for the clock signal based on the instance name and the clock signal name.

[0144] For example, in a generation device provided in an embodiment of the present disclosure, the second generation subunit includes an establishment subunit and a path information generation subunit. The establishment subunit is configured to establish a correspondence between the name of the input signal of at least one buffer, the name of the output signal of at least one buffer, clock path information, the number of stages of at least one buffer, and path description information. The path information generation subunit is configured to generate path information for the object path based on the correspondence.

[0145] For example, in a generation device provided in an embodiment of the present disclosure, the path information is used to verify the object path using a verification device. The generation device also includes a file generation unit configured to generate a path information file containing path information according to a file format recognized by the verification device.

[0146] For example, the first extraction unit 710, the second extraction unit 720, and the generation unit 730 can be hardware, software, firmware, or any feasible combination thereof. For example, the first extraction unit 710, the second extraction unit 720, and the generation unit 730 can be dedicated or general-purpose circuits, chips, or devices, or can be a combination of a processor and memory. The embodiments of the present disclosure do not limit the specific implementation of each of the above units.

[0147] It should be noted that, in the embodiment of the present disclosure, each unit of the generating device 700 corresponds to each step of the aforementioned verification method. For the specific functions of the generating device 700, reference can be made to the relevant description of the generating method, which will not be repeated here. Figure 7A The components and structures of the generating device 700 shown are merely exemplary and non-limiting. The generating device 700 may further include other components and structures as needed.

[0148] Figure 7BA schematic block diagram of a verification apparatus 800 for verifying an object path in an integrated circuit design provided by at least one embodiment of the present disclosure is shown.

[0149] For example, Figure 7B As shown, the verification device 800 may include a path information acquisition unit 701 , a black box file acquisition unit 702 and a verification unit 703 .

[0150] The path information acquiring unit 701 is configured to acquire path information according to the generation method provided by any embodiment of the present disclosure.

[0151] The path information acquisition unit 701 may execute, for example, Figure 6A Step S610 is described.

[0152] The black box file acquisition unit 702 is configured to acquire a black box file of the integrated circuit design, where the black box file includes module information of a plurality of circuit modules included in the integrated circuit design and irrelevant to the verification of the object path.

[0153] The black box file acquisition unit 702 may execute, for example, Figure 6A Step S620 described.

[0154] The verification unit 703 is configured to verify the object path based on the path information file and the black box file to generate a verification result.

[0155] The verification unit 703 may, for example, execute Figure 6A Step S630 described.

[0156] For example, the path information acquisition unit 701, the black box file acquisition unit 702, and the verification unit 703 can be hardware, software, firmware, or any feasible combination thereof. For example, the path information acquisition unit 701, the black box file acquisition unit 702, and the verification unit 703 can be dedicated or general-purpose circuits, chips, or devices, or can be a combination of a processor and a memory. The embodiments of the present disclosure do not limit the specific implementation of each of the above units.

[0157] It should be noted that in at least one embodiment of the present disclosure, the various units of the verification device 800 correspond to the various steps of the aforementioned verification method. For the specific functions of the verification device 800, please refer to the relevant description of the verification method, which will not be repeated here. Figure 7B The components and structures of the verification device 800 shown are merely exemplary and non-limiting. The verification device 800 may further include other components and structures as needed.

[0158] At least one embodiment of the present disclosure further provides an electronic device comprising a processor and a memory, wherein the memory comprises one or more computer program instructions. The one or more computer program instructions are stored in the memory and, when executed by the processor, implement instructions for the above-mentioned generation method or verification method. The electronic device can automatically generate path information for an object path, greatly saving the time required to generate the path information, thereby facilitating verification time for integrated circuit design verification and improving verification efficiency.

[0159] Figure 8 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 8 As shown, the electronic device 900 includes a processor 810 and a memory 820. The memory 820 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 810 is used to execute the non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by the processor 810, one or more steps in the bus device design method described above can be executed. The memory 820 and the processor 810 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0160] For example, the processor 810 may be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 810 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 900 to perform desired functions.

[0161] For example, the memory 820 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 810 may execute one or more computer program modules to implement various functions of the electronic device 900. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0162] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 900 can be referred to the above description of the design method of the bus device, which will not be repeated here.

[0163] Figure 9 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 1000 is suitable for implementing the bus device design method provided in the embodiments of the present disclosure. The electronic device 1000 can be a terminal device, etc. It should be noted that, Figure 9 The electronic device 1000 shown is merely an example and does not limit the functions and scope of use of the embodiments of the present disclosure.

[0164] like Figure 9 As shown, the electronic device 1000 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 910, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 920 or a program loaded from a storage device 980 into a random access memory (RAM) 930. Various programs and data required for the operation of the electronic device 1000 are also stored in the RAM 930. The processing device 910, the ROM 920, and the RAM 930 are connected to each other via a bus 940. An input / output (I / O) interface 950 is also connected to the bus 940.

[0165] Typically, the following devices may be connected to the I / O interface 950: an input device 960 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 970 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 980 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 990. The communication device 990 may allow the electronic device 1000 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 9 The electronic device 1000 is shown as having various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 1000 may alternatively implement or possess more or fewer devices.

[0166] For example, according to an embodiment of the present disclosure, the above-mentioned generation method and verification method can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the design method of the above-mentioned bus device. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 990, or installed from the storage device 980, or installed from the ROM 920. When the computer program is executed by the processing device 910, the functions defined in the generation method and verification method provided in the embodiment of the present disclosure can be implemented.

[0167] At least one embodiment of the present disclosure further provides a computer-readable storage medium for storing non-transitory computer-readable instructions. When executed by a computer, the non-transitory computer-readable instructions can implement the aforementioned generation and verification methods. This computer-readable storage medium can automatically generate path information for an object path, significantly reducing the time required to generate path information. This can help reduce verification time for integrated circuit designs and improve verification efficiency.

[0168] Figure 10 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Figure 10 As shown, the storage medium 1100 is used to store non-transitory computer-readable instructions 1010. For example, when the non-transitory computer-readable instructions 1010 are executed by a computer, one or more steps in the black box file generation method and verification method described above can be performed.

[0169] For example, the storage medium 1100 may be applied to the electronic device 900. Figure 8 The memory 820 in the electronic device 900 is shown. For example, the description of the storage medium 1100 can be referred to Figure 8 The corresponding description of the memory 820 in the electronic device 900 is shown and is not repeated here.

[0170] There are a few points to note:

[0171] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0172] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0173] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for generating path information of an object path in integrated circuit design, wherein: The object path includes at least one buffer, and the method includes: extracting buffer information for at least one buffer in the object path from a buffer description file for the integrated circuit design; extracting path description information of the object path from a chip logic design file of the integrated circuit design according to the buffer information; and Generate path information of the object path according to the path description information.

2. The generation method according to claim 1, wherein: The buffer information includes a name of an input signal of the at least one buffer in the object path and a name of an output signal of the at least one buffer.

3. The generation method according to claim 2, wherein: Extracting the path description information of the object path from the chip logic design file of the integrated circuit design according to the buffer information includes: determining a start point and an end point of the object path from the chip logic design file of the integrated circuit design according to a name of an input signal of the at least one buffer and a name of an output signal of the at least one buffer; and extracting the starting point information of the starting point and the ending point information of the ending point from the chip logic design file of the integrated circuit design, The path description information includes the starting point information and the end point information.

4. The generation method according to claim 3, wherein: Determining a start point and an end point of the object path from the chip logic design file of the integrated circuit design according to a name of an input signal of the at least one buffer and a name of an output signal of the at least one buffer includes: Determining a first net signal connected to an input port of an input signal of the at least one buffer from the chip logic design file of the integrated circuit design, and using another port connected to the first net signal as the starting point of the object path; and A second net signal connected to an output port of an output signal of the at least one buffer is determined from the chip logic design file of the integrated circuit design, and another port connected to the second net signal is used as the end point of the object path.

5. The generation method according to claim 3 or 4, wherein: Extracting the starting point information of the starting point and the end point information of the end point from the chip logic design file of the integrated circuit design includes: Extracting the name of the starting point and the name of the end point from the chip logic design file of the integrated circuit design; and A first circuit module where the starting point is located is determined according to the name of the starting point, and a second circuit module where the end point is located is determined according to the name of the end point.

6. The generation method according to claim 5, further comprising: Extracting, from the buffer description file of the integrated circuit design, an input circuit module connected to an input port of an input signal of the at least one buffer and an output circuit module connected to an output port of an output signal of the at least one buffer; determining whether the first circuit module and the second circuit module are consistent with the input circuit module and the output circuit module, respectively; Generating path information of the object path according to the path description information includes: In response to the first circuit module and the second circuit module being consistent with the input circuit module and the output circuit module respectively, path information of the object path is generated according to the path description information.

7. The generation method according to any one of claims 1 to 6, further comprising: Obtaining clock path information of a clock signal of the at least one buffer and the number of stages of the at least one buffer from a buffer description file of the integrated circuit design; Generating path information of the object path according to the path description information includes: Path information of the object path is generated according to the path description information and further according to the clock path information and the number of stages of the at least one buffer.

8. The generation method according to claim 7, wherein: Obtaining clock path information of a clock signal of the at least one buffer from a buffer description file of the integrated circuit design includes: extracting an instantiation name of the at least one buffer and a name of the clock signal from a buffer description file of the integrated circuit design; and Clock path information of the clock signal is generated according to the instantiation name and the name of the clock signal.

9. The generation method according to claim 8, wherein: Generating path information of the object path according to the path description information and further according to the clock path information and the number of stages of the at least one buffer, including: establishing a correspondence between a name of an input signal of the at least one buffer, a name of an output signal of the at least one buffer, the clock path information, the number of stages of the at least one buffer, and the path description information; and According to the corresponding relationship, path information of the object path is generated.

10. The generation method according to claim 1, wherein: The path information is used to verify the object path using a verification device, The method further comprises: A path information file including the path information is generated according to a file format recognized by the verification device.

11. A verification method for verifying an object path in an integrated circuit design, comprising: Acquiring path information of the object path according to the generation method according to any one of claims 1 to 10; Obtaining a black box file of the integrated circuit design, wherein the black box file includes module information of a plurality of circuit modules included in the integrated circuit design and circuit modules that are not related to the verification of the object path; Based on the path information and the black box file, the object path is verified to generate a verification result.

12. A device for generating path information of an object path in integrated circuit design, wherein: The object path includes at least one buffer, and the generating device includes: a first extraction unit configured to extract buffer information of at least one buffer in the object path from a buffer description file for the integrated circuit design; a second extraction unit configured to extract path description information of the object path from a chip logic design file of the integrated circuit design according to the buffer information; and A generating unit is configured to generate path information of the object path according to the path description information.

13. A verification device for verifying an object path in an integrated circuit design, comprising: a path information acquisition unit, configured to acquire the path information of the object path according to the generation method according to any one of claims 1 to 10; a black box file acquiring unit configured to acquire a black box file of the integrated circuit design, wherein the black box file includes module information of a plurality of circuit modules included in the integrated circuit design and irrelevant to the verification of the object path; as well as The verification unit is configured to verify the object path based on the path information and the black box file to generate a verification result.

14. An electronic device comprising: processor; a memory comprising one or more computer program instructions; The one or more computer program instructions are stored in the memory and, when executed by the processor, implement the generation method according to any one of claims 1 to 10 or the verification method according to claim 11.

15. A computer-readable storage medium non-transitorily storing computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the generation method according to any one of claims 1 to 10 or the verification method according to claim 11 is implemented.

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