A special chip packaging architecture, electronic equipment and packaging method

Abstract

The present invention discloses a dedicated chip packaging architecture, an electronic device and a packaging method. The architecture includes a first and a second packaging structure: the first packaging structure includes a substrate and a plurality of chips arranged on the substrate, each chip is connected to a corresponding interface pad group on the substrate through a respective electrical interface, and the interface pad group is connected or led out to a solder ball of the substrate through an internal wiring layer of the substrate; in the second packaging structure, a chip is used to replace one or more chips in the first packaging structure, and other components in the first packaging structure are reused. The electronic device includes a circuit board and the dedicated chip packaging architecture, and the dedicated chip packaging architecture is connected to the circuit board through a connector. The packaging method is an implementation process for realizing the dedicated chip packaging architecture. The present invention can reuse the substrate to quickly realize a dedicated chip structure customized for field applications, reduce research and development costs, shorten the development cycle, and realize the reconfiguration of the chip structure during packaging.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a dedicated chip packaging architecture, electronic equipment and a packaging method. Background Art

[0002] With the development of semiconductor technology, electronic devices are moving towards miniaturization and lightness. On the one hand, the System on Chip (SoC) based on higher technology can achieve higher integration, integrate more transistors in a single die, and realize more complex functions; on the other hand, the System in Package (SiP) can reuse dies and integrate multiple dies in one chip, greatly improving the package integration and reducing the package size. Compared with SoC technology, the advantages of SiP technology are mainly reflected in short cycle, low cost, low R&D difficulty, and heterogeneous process integration, making it the current mainstream packaging technology.

[0003] like Figure 1 As shown, the basic structure of a typical SiP packaged chip includes a substrate 10, a plurality of bare chips 201, 301, 401 arranged on the substrate, the substrate and the bare chips are electrically connected through wire bonding (Wire Bond, WB) (W1) or flip chip micro bumps (F1), the wiring layer inside the substrate is used to connect the bare chips or lead them out to the solder balls 101 of the chip, and the inside of the chip is filled with dielectric material 11.

[0004] Chips based on SiP technology can reuse mature bare chips, but substrates need to be designed and manufactured according to chip functions. The inability to reuse substrates has become a bottleneck in the design and manufacturing of SiP chips. Specialized chips for specific fields often have the same architecture but different functional components. For example, in 5G physical layer chips, they usually include functional modules such as digital front end (DFE), FFT / iFFT, forward error correction code (FECEncode / Decode), and microcontroller unit (MCU); depending on the implemented protocol, the encoding can use different modules such as LDPC or Turbo. Using general programmable devices to implement different encoding modules can reuse resources but have low performance and energy efficiency; using dedicated encoding chips to implement different encoding functions has higher performance and energy efficiency, but requires redundant resources (implementing LDPC and Turbo functions in one chip) or redesigning different packages to equip LDPC and Turbo respectively. Therefore, for specialized chips for field applications, how to reuse chips and substrates of various functional components and realize reconfiguration during packaging has become a very necessary problem to be solved at present. Summary of the invention

[0005] The purpose of the present invention is to provide a dedicated chip packaging architecture and electronic equipment, which can reuse substrates and functional component bare chips for dedicated chips for field applications, achieve reconfiguration during packaging, reduce development costs, shorten development cycles, and improve overall chip energy efficiency.

[0006] The technical solution to achieve the purpose of the present invention is: a dedicated chip packaging architecture, including a first packaging structure and a second packaging structure:

[0007] The first packaging structure includes a substrate and a plurality of chips disposed on the substrate, each chip is connected to a corresponding interface pad group on the substrate through a respective electrical interface, and the interface pad group is connected or led out to a solder ball of the substrate through an internal wiring layer of the substrate;

[0008] In the second packaging structure, one or more chips in the first packaging structure are replaced with a chip, and other components in the first packaging structure are reused.

[0009] Furthermore, in the second packaging structure, the replaced chip has the same electrical interface as the replaced chip and is electrically connected to the interface pad group on the substrate.

[0010] Furthermore, the first packaging structure includes a substrate, and a first chip, a second chip, and a third chip arranged on the substrate; a first interface pad group, a second interface pad group, and a third interface pad group are arranged on the substrate, and the first interface pad group, the second interface pad group, and the third interface pad group are connected to or led out to the solder balls of the substrate through the internal wiring layer of the substrate; the first chip is arranged with a first electrical interface, the second chip is arranged with a second electrical interface, and the third chip is arranged with a third electrical interface, the first chip is connected to the first interface pad group of the substrate through the first electrical interface, the second chip is connected to the second interface pad group of the substrate through the second electrical interface, and the third chip is connected to the third interface pad group of the substrate through the third electrical interface.

[0011] Furthermore, in the second packaging structure, a fourth chip replaces the first chip in the first packaging structure, the fourth chip and the first chip are arranged with the same first electrical interface, and the second packaging structure reuses other components in the first packaging structure except the first chip.

[0012] Furthermore, in the second packaging structure, the fourth chip replaces the first chip in the first packaging structure, and the fifth chip replaces the second chip in the first packaging structure; the fourth chip and the first chip are arranged with the same first electrical interface, and the fifth chip and the second chip are arranged with the same second electrical interface, the fourth chip and the first chip are electrically connected to the first interface pad group on the substrate, and the fifth chip and the second chip are electrically connected to the second interface pad group on the substrate.

[0013] Furthermore, the first, second and third electrical interfaces are first, second and third micro-bumps, and the first, second and third interface pad groups are micro-bumps or pads, which are correspondingly connected by solder.

[0014] Furthermore, the first, second and third electrical interfaces are the fourth, fifth and sixth interface pad groups, the first, second and third interface pad groups on the substrate are all pads, and the connection methods between the first and fourth, second and fifth, third and sixth pad groups include hybrid bonding, surface activated bonding or atomic diffusion bonding.

[0015] Furthermore, the fourth chip in the second packaging structure has the same electrical interface as the first chip in the first packaging structure, but has different external dimensions; the substrate reserves a sufficiently large space so that the replacement of the fourth chip does not affect the second and third chips arranged on the substrate.

[0016] An electronic device comprises a circuit board and the dedicated chip packaging architecture, wherein the dedicated chip packaging architecture is connected to the circuit board via a connector.

[0017] A special chip packaging method, as follows:

[0018] First, a first packaging structure and a second packaging structure are provided;

[0019] Secondly, the first packaging structure is provided with a substrate, on which a plurality of chips are arranged, each chip is connected to a corresponding interface pad group on the substrate through a respective electrical interface, and the interface pad group is connected or led out to a solder ball of the substrate through an internal wiring layer of the substrate;

[0020] Again, in the second packaging structure, a chip is used to replace one or more chips in the first packaging structure, and other components in the first packaging structure are reused; the replaced chip has the same electrical interface as the replaced chip, and is electrically connected to the interface pad group on the substrate.

[0021] Compared with the prior art, the present invention has the following significant advantages: (1) a chip packaging architecture and electronic equipment are designed, which can reuse the substrate to quickly realize a dedicated chip structure customized for field applications by determining the substrate interface pad group and the corresponding chip electrical interface; (2) the research and development cost is reduced and the development cycle is shortened, and the chip structure can be reconfigured during packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the basic structure of a typical SiP packaged chip.

[0023] Figure 2 It is a structural schematic diagram of a special chip packaging architecture and an electronic device of the present invention.

[0024] Figure 3 A schematic diagram of a dedicated chip packaging architecture provided by Embodiment 1 of the present invention.

[0025] Figure 4 A schematic diagram of a dedicated chip packaging architecture provided by Embodiment 2 of the present invention.

[0026] Figure 5 A schematic diagram of a dedicated chip packaging architecture provided by Embodiment 3 of the present invention.

[0027] Figure 6 A schematic diagram of a dedicated chip packaging architecture provided by Embodiment 4 of the present invention.

[0028] Figure 7 A schematic diagram of a dedicated chip packaging architecture provided by Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0029] In a first aspect, the present invention provides a dedicated chip packaging architecture.

[0030] The dedicated chip packaging architecture includes: a first packaging structure and a second packaging structure, the first packaging structure includes a substrate, and a first chip, a second chip and a third chip arranged on the substrate; the first chip, the second chip and the third chip are connected to the first, second and third interface pad groups of the substrate through their respective first, second and third electrical interfaces, and the first, second and third interface pad groups are connected or led out to the solder balls of the substrate through the internal wiring layer of the substrate. In the second packaging structure, the fourth chip replaces the first chip in the first packaging structure, and other components in the first packaging structure are reused. Therefore, the present invention can reuse substrates and chips, quickly realize a dedicated chip structure customized for field applications, reduce R&D costs and shorten the development cycle, and realize the reconfigurability of the chip structure during packaging.

[0031] In combination with the first aspect, in a possible implementation manner, at least two chips are arranged on a substrate in the packaging structure and are electrically connected to the substrate.

[0032] In combination with the first aspect, in a possible implementation, the first, second, and third electrical interfaces are first, second, and third micro-bumps, and the first, second, and third interface pad groups are micro-bumps or pads, which are correspondingly connected by solder.

[0033] In combination with the first aspect, in a possible implementation, the first, second, and third electrical interfaces are fourth, fifth, and sixth interface pad groups, the first, second, and third interface pad groups on the substrate are all pads, and the connection methods between the first and fourth, second and fifth, and third and sixth pad groups include hybrid bonding, surface activated bonding, or atomic diffusion bonding.

[0034] In combination with the first aspect, in a possible implementation, in the second packaging structure, the fourth chip and the fifth chip replace the first chip and the second chip in the first packaging structure. At the same time, the fourth chip and the first chip are arranged with the first electrical interface, the fifth chip and the second chip are arranged with the second electrical interface, the fourth chip and the first chip can be electrically connected to the first interface pad group on the substrate, and the fifth chip and the second chip can be electrically connected to the second interface pad group on the substrate.

[0035] In combination with the first aspect, in a possible implementation, in the second packaging structure, at least one chip is replaced, and the replaced chip has the same electrical interface as the replaced chip and can be electrically connected to the interface on the substrate.

[0036] In combination with the first aspect, in a possible implementation, the fourth chip in the second packaging structure has the same electrical interface as the first chip in the first packaging structure, but may have different external dimensions. The substrate is required to reserve a sufficiently large space so that the replaced fourth chip does not affect the second and third chips arranged on the substrate.

[0037] For example, Figure 2A dedicated chip packaging architecture provided by the present invention includes a first packaging structure 01 and a second packaging structure 02. The first packaging structure 01 includes a substrate 10, a first chip 201, a second chip 301, a third chip 401, etc. are arranged on the substrate 10, and a first interface pad group S1, a second interface pad group S2, a third interface pad group S3, etc. are arranged on the substrate 10. The first interface pad group S1, the second interface pad group S2, the third interface pad group S3, etc. are connected or led out to the wiring layer inside the substrate 10. The solder balls 101 of the substrate 10 are arranged, the first chip 201 is arranged with a first electrical interface C1, the second chip 301 is arranged with a second electrical interface C2, and the third chip 401 is arranged with a third electrical interface C3. The first chip 201 is connected to the first interface pad group S1 of the substrate 10 through the electrical interface C1, the second chip 301 is connected to the second interface pad group S2 of the substrate 10 through the electrical interface C2, and the third chip 401 is connected to the third interface pad group S3 of the substrate 10 through the electrical interface C3. In the second package structure 02, the fourth chip 202 replaces the first chip 201 in the first package structure 01. Since the fourth chip 202 and the first chip 201 are both arranged with the same first electrical interface C1, the second package structure 02 can reuse other components in the first package structure 01 except the first chip 201.

[0038] In a second aspect, the present invention further provides an electronic device.

[0039] The electronic device comprises a circuit board and the dedicated chip packaging structure described in the first aspect and any possible implementation manner of the first aspect, and the dedicated chip packaging structure is connected to the electronic device via a connector.

[0040] In a third aspect, the present invention also provides a dedicated chip packaging method.

[0041] The dedicated chip packaging method includes: a first packaging structure includes a substrate, a first chip, a second chip, a third chip, etc. arranged on the substrate, a first interface pad group, a second interface pad group, a third interface pad group, etc. are arranged on the substrate, the first interface pad group, the second interface pad group, the third interface pad group, etc. are connected or led to the solder balls of the substrate through the internal wiring layer of the substrate, the first chip is arranged with a first electrical interface, the second chip is arranged with a second electrical interface, and the third chip is arranged with a third electrical interface, the first chip is connected to the first interface pad group of the substrate through the electrical interface, the second chip is connected to the second interface pad group of the substrate through the electrical interface, and the third chip is connected to the third interface pad group of the substrate through the electrical interface. In the second packaging structure, the fourth chip replaces the first chip, and the first chip and the fourth chip are arranged with the same first electrical interface. Therefore, the second packaging structure can reuse other components in the first packaging structure except the first chip.

[0042] In combination with the third aspect, in a possible implementation manner, the first and second packaging structures include at least two chips, and are electrically connected to the substrate through a connector.

[0043] In conjunction with the third aspect, in a possible implementation, the fourth and fifth chips in the second packaging structure replace the first and second chips in the first packaging structure, the fourth chip has the same electrical interface as the first chip, and the fifth chip has the same electrical interface as the second chip. Alternatively, at least one chip in the first packaging structure is replaced in the second packaging structure, and the replaced chip has the same electrical interface as the replaced chip.

[0044] In summary, compared with the existing SiP-based packaging technology, since the present invention sets a certain electrical interface between the substrate and multiple chips adhered to the substrate, it is possible to reuse the substrate and other components to quickly realize a dedicated chip structure customized for field applications, reduce R&D costs and shorten the development cycle, and realize reconfigurable chip structure packaging.

[0045] To make the purpose, technical scheme and advantages of the present invention clearer, the following detailed description of the various embodiments of the present invention is made in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. In addition, it should be understood that, unless otherwise explicitly stated, the features of the various exemplary embodiments and / or aspects described herein can be combined with each other. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used in the present invention should be the usual meanings understood by those skilled in the art. The terms "first", "second", "third", "fourth" and similar words used in the specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Therefore, the features defined as "first", "second", "third" and "fourth" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, unless otherwise specified, the meaning of "multiple" is two or more.

[0046] Some embodiments of the present invention provide an electronic device. The electronic device may be a mobile phone, a tablet computer, a notebook, a car computer, a smart watch, a smart bracelet, and the like. The embodiments of the present invention do not impose any special restrictions on the specific form of the above-mentioned electronic device. The above-mentioned electronic device includes a dedicated chip packaging architecture, and the dedicated chip packaging architecture is connected to other related electronic devices in the electronic device through a connector. For example, the dedicated chip packaging architecture can be connected to a circuit board in the electronic device through a connector. Example

[0047] In this embodiment, Figure 3 Taking the dedicated chip packaging architecture shown in as an example, its structure is schematically described.

[0048] First, this embodiment includes a first packaging structure 01 and a second packaging structure 02. The first packaging structure 01 includes a substrate 10, a first chip 201 and a second chip 301 arranged on the substrate 10, and a first interface pad group S1 and a second interface pad group S2 are arranged on the substrate 10. The first interface pad group S1, the second interface pad group S2, the third interface pad group S3, etc. are connected to or led out to the solder ball 101 of the substrate 10 through the internal wiring layer of the substrate 10. The first chip 201 is arranged with a first electrical interface C1, and the second chip 301 is arranged with a second electrical interface C2. The first chip 201 is connected to the first interface pad group S1 of the substrate 10 through the electrical interface C1, and the second chip 301 is connected to the second interface pad group S2 of the substrate 10 through the electrical interface C2. In the second packaging structure 02, the third chip 202 replaces the first chip 201 in the first packaging structure 01. Since the third chip 202 and the first chip 201 are both arranged with the same first electrical interface C1, the second packaging structure 02 can reuse other components in the first packaging structure 01 except the first chip 201. Example

[0049] In this embodiment, Figure 4 Taking the dedicated chip packaging architecture shown in as an example, its structure is schematically described.

[0050] Different from Example 1, Example 1 Figure 3 The first electrical interface C1, the second electrical interface C2 and the first electrical interface C1 of the first chip 201, the second chip 301 and the third chip 301 are micro-bumps, and are electrically connected to the first interface pad group S1 and the second interface pad group S2 of the substrate 10; in this embodiment Figure 4 As shown, the first electrical interface C1 and the second electrical interface C2 of the first chip 201 , the second chip 301 , and the third chip 202 are pads, and are electrically connected to the first interface pad group S1 and the second interface pad group S2 of the substrate 10 through wire bonding. Example

[0051] In this embodiment, Figure 5 Taking the dedicated chip packaging architecture shown in as an example, its structure is schematically described.

[0052] This embodiment includes a first packaging structure 01 and a second packaging structure 02. The first packaging structure 01 includes a substrate 10, a first chip 201, a second chip 301 and a third chip 401 arranged on the substrate 10. A first interface pad group S1, a second interface pad group S2, a third interface pad group S3, etc. are arranged on the substrate 10. The first interface pad group S1, the second interface pad group S2 and the third interface pad group S3 are connected or led out to the solder ball 101 of the substrate 10 through the internal wiring layer of the substrate 10. The first chip 201 is arranged with a first electrical interface C1, the second chip 301 is arranged with a second electrical interface C2, and the third chip 401 is arranged with a third electrical interface C3. The first chip 201 is connected to the first interface pad group S1 of the substrate 10 through the electrical interface C1, the second chip 301 is connected to the second interface pad group S2 of the substrate 10 through the electrical interface C2, and the third chip 401 is connected to the third interface pad group S3 of the substrate 10 through the electrical interface C3. In the second packaging structure 02, the fourth chip 202 replaces the first chip 201 in the first packaging structure 01, and the fifth chip 402 replaces the third chip 401 in the first packaging structure 01. Since the fourth chip 202 and the first chip 201 are both arranged with the same first electrical interface C1, and the fifth chip 402 and the third chip 401 are both arranged with the same third electrical interface C3, the second packaging structure 02 can reuse other components in the first packaging structure 01 except the first chip 201 and the third chip 401. Example

[0053] In this embodiment, Figure 6 Taking the dedicated chip packaging architecture shown in as an example, its structure is schematically described.

[0054] This embodiment includes a first packaging structure 01, a second packaging structure 02 and a third packaging structure 03. The first packaging structure 01 includes a substrate 10, a first chip 201, a second chip 301 and a third chip 401 arranged on the substrate 10, and a first interface pad group S1, a second interface pad group S2, a third interface pad group S3 and the like are arranged on the substrate 10. The first interface pad group S1, the second interface pad group S2 and the third interface pad group S3 are connected or led out to the substrate 10 through the internal wiring layer of the substrate 10. 0, the first chip 201 is arranged with a first electrical interface C1, the second chip 301 is arranged with a second electrical interface C2, and the third chip 401 is arranged with a third electrical interface C3. The first chip 201 is connected to the first interface pad group S1 of the substrate 10 through the electrical interface C1, the second chip 301 is connected to the second interface pad group S2 of the substrate 10 through the electrical interface C2, and the third chip 401 is connected to the third interface pad group S3 of the substrate 10 through the electrical interface C3. In the second package structure 02, the fourth chip 202 replaces the first chip 201 in the first package structure 01, and the fourth chip 202 and the first chip 201 are both arranged with the same first electrical interface C1, so the second package structure 02 can reuse other components in the first package structure 01 except the first chip 201. In the third package structure 03, the fifth chip 203 replaces the first chip 201 in the first package structure 01, and the sixth chip 402 replaces the third chip 401 in the first package structure 01. The fifth chip 203 and the first chip 201 in the first packaging structure 01 are both arranged with the same first electrical interface C1, and the sixth chip 402 and the third chip 401 in the first packaging structure 01 are both arranged with the same first electrical interface C3. Therefore, the third packaging structure 03 can reuse other components in the first packaging structure 01 except the first chip 201 and the third chip 401. The third packaging structure 03 can also be expressed as that the fifth chip 203 replaces the fourth chip 202 in the second packaging structure 02, and the sixth chip 402 replaces the third chip 401 in the second packaging structure 02. The fifth chip 203 and the fourth chip 202 in the second packaging structure 02 are both arranged with the same first electrical interface C1, and the sixth chip 402 and the third chip 401 in the second packaging structure 02 are both arranged with the same first electrical interface C3. Therefore, the third packaging structure 03 can reuse other components in the second packaging structure 02 except the fourth chip 202 and the third chip 401. Example

[0055] In this embodiment, Figure 7Taking the dedicated chip packaging architecture shown in as an example, its structure is schematically described.

[0056] This embodiment includes a first packaging structure 01, a second packaging structure 02 and a third packaging structure 03. The first packaging structure 01 includes a substrate 10, a first chip 201, a second chip 301 and a third chip 401 arranged on the substrate 10, and a first interface pad group S1, a second interface pad group S2, a third interface pad group S3 and the like are arranged on the substrate 10. The first interface pad group S1, the second interface pad group S2 and the third interface pad group S3 are connected or led out to the substrate 10 through the internal wiring layer of the substrate 10. 0, the first chip 201 is arranged with a first electrical interface C1, the second chip 301 is arranged with a second electrical interface C2, and the third chip 401 is arranged with a third electrical interface C3. The first chip 201 is connected to the first interface pad group S1 of the substrate 10 through the electrical interface C1, the second chip 301 is connected to the second interface pad group S2 of the substrate 10 through the electrical interface C2, and the third chip 401 is connected to the third interface pad group S3 of the substrate 10 through the electrical interface C3. In the second package structure 02, the fourth chip 202 replaces the first chip 201 in the first package structure 01, and the fourth chip 202 and the first chip 201 are both arranged with the same first electrical interface C1, so the second package structure 02 can reuse other components in the first package structure 01 except the first chip 201. In the third package structure 03, the fifth chip 203 replaces the first chip 201 in the first package structure 01. The fifth chip 203 and the first chip 201 in the first packaging structure 01 are both arranged with the same first electrical interface C1. Therefore, the third packaging structure 03 can reuse other components in the first packaging structure 01 except the first chip 201 and the third chip 401. The third packaging structure 03 can also be expressed as that the fifth chip 203 replaces the fourth chip 202 in the second packaging structure 02. The fifth chip 203 and the fourth chip 202 in the second packaging structure 02 are both arranged with the same first electrical interface C1, and the sixth chip 402 and the third chip 401 in the second packaging structure 02 are both arranged with the same first electrical interface C3. Therefore, the third packaging structure 03 can reuse other components in the second packaging structure 02 except the fourth chip 202 and the third chip 401. The first chip 201 in the first packaging structure 01, the fourth chip 202 in the second packaging structure 02 and the fifth chip 203 in the third packaging structure 03 are all arranged with the first electrical interface C1, but their outer dimensions can be the same, such as the first chip 201 and the fourth chip 202, or different, such as the first chip 201 and the fifth chip 203, and the fourth chip 202 and the fifth chip 203.

[0057] In summary, the present invention provides a chip packaging architecture, electronic device and packaging method, which can reuse the substrate to quickly realize a dedicated chip structure customized for field applications through a determined substrate interface pad group and a corresponding chip electrical interface, thereby reducing R&D costs and shortening the development cycle, and realizing the reconfiguration of the chip structure during packaging.

Claims

1. A dedicated chip packaging architecture, characterized in that: Comprising a first packaging structure and a second packaging structure: The first packaging structure includes a substrate and a plurality of chips disposed on the substrate, each chip is connected to a corresponding interface pad group on the substrate through a respective electrical interface, and the interface pad group is connected or led out to a solder ball of the substrate through an internal wiring layer of the substrate; In the second packaging structure, one or more chips in the first packaging structure are replaced with a chip, and other components in the first packaging structure are reused; The first packaging structure includes a substrate, and a first chip, a second chip, and a third chip arranged on the substrate; a first interface pad group, a second interface pad group, and a third interface pad group are arranged on the substrate, and the first interface pad group, the second interface pad group, and the third interface pad group are connected to or led out to the solder balls of the substrate through the internal wiring layer of the substrate; the first chip is arranged with a first electrical interface, the second chip is arranged with a second electrical interface, and the third chip is arranged with a third electrical interface, the first chip is connected to the first interface pad group of the substrate through the first electrical interface, the second chip is connected to the second interface pad group of the substrate through the second electrical interface, and the third chip is connected to the third interface pad group of the substrate through the third electrical interface; In the second packaging structure, the fourth chip replaces the first chip in the first packaging structure, and the fifth chip replaces the second chip in the first packaging structure; the fourth chip and the first chip are arranged with the same first electrical interface, and the fifth chip and the second chip are arranged with the same second electrical interface, the fourth chip and the first chip are electrically connected to the first interface pad group on the substrate, and the fifth chip and the second chip are electrically connected to the second interface pad group on the substrate.

2. The dedicated chip packaging architecture according to claim 1, characterized in that: In the second packaging structure, the replaced chip has the same electrical interface as the replaced chip and is electrically connected to the interface pad group on the substrate.

3. The dedicated chip packaging architecture according to claim 1, characterized in that: In the second packaging structure, a fourth chip replaces the first chip in the first packaging structure, the fourth chip and the first chip are arranged with the same first electrical interface, and the second packaging structure reuses other components in the first packaging structure except the first chip.

4. The dedicated chip packaging architecture according to claim 1, characterized in that: The first, second and third electrical interfaces are first, second and third micro-bumps, and the first, second and third interface pad groups are micro-bumps or pads, which are connected correspondingly by solder.

5. The dedicated chip packaging architecture according to claim 1, characterized in that: The first, second and third electrical interfaces are the fourth, fifth and sixth interface pad groups. The first, second and third interface pad groups on the substrate are all pads. The connection methods between the first and fourth, second and fifth, third and sixth pad groups include hybrid bonding, surface activated bonding or atomic diffusion bonding.

6. The dedicated chip packaging architecture according to claim 1, characterized in that: The fourth chip in the second packaging structure has the same electrical interface as the first chip in the first packaging structure, but has different external dimensions; The substrate reserves a space of sufficient size so that the replaced fourth chip does not affect the second and third chips arranged on the substrate.

7. An electronic device, characterized in that: The electronic device comprises a circuit board and the dedicated chip packaging architecture according to any one of claims 1 to 6, wherein the dedicated chip packaging architecture is connected to the circuit board via a connector.

8. A packaging method for a dedicated chip packaging architecture as claimed in any one of claims 1 to 6, characterized in that: The details are as follows: First, a first packaging structure and a second packaging structure are provided; Secondly, the first packaging structure is provided with a substrate, on which a plurality of chips are arranged, each chip is connected to a corresponding interface pad group on the substrate through a respective electrical interface, and the interface pad group is connected or led out to a solder ball of the substrate through an internal wiring layer of the substrate; Again, in the second packaging structure, a chip is used to replace one or more chips in the first packaging structure, and other components in the first packaging structure are reused; the replaced chip has the same electrical interface as the replaced chip, and is electrically connected to the interface pad group on the substrate.

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