Array substrate and display device

Abstract

Embodiments of the present application provide an array substrate and a display device. The array substrate comprises a transparent hole, a display area and a non-display area. The display area surrounds the transparent hole. The non-display area comprises a first frame area and a second frame area. In a first direction, the first frame area, the display area and the second frame area are arranged in sequence. The second frame area is used to connect a touch chip or a flexible circuit board. The first frame area is provided with a load module. The display area comprises a plurality of target scan signal lines, a plurality of data signal lines and a plurality of dummy data signal lines. The target scan signal lines are electrically connected to sub-pixels in the display area and are used to provide scan signals to the sub-pixels. The display area comprises a first area and a second area. In a second direction, the first area is spaced into at least two sub-areas by the transparent hole. The target scan signal lines in the first area are electrically connected to the load module in the first frame area through the dummy data signal lines. Embodiments of the present application can improve the display effect.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to an array substrate and a display device. Background Technology

[0002] With the development of display technology, display devices are becoming increasingly sophisticated in their functionality. To accommodate electronic components such as fingerprint recognition, earpieces, light sensors, and / or cameras on the display surface of a display device, these components can be placed by setting transparent holes in the array substrate.

[0003] Figure 1 This is a schematic diagram of one type of array substrate structure. For example... Figure 1 As shown, the display area of ​​the array substrate may include a first region A1 and a second region A2. The first region A1 is divided into two sub-regions by a transparent hole k1. The inventors of this application have discovered that, when displayed on a display device, there is a difference in the display effect between the first region A1 and the second region A2, resulting in a poor overall display effect of the display device. Summary of the Invention

[0004] This application provides an array substrate and a display device that can solve the problem of large differences in display effect between the first area corresponding to the transparent hole and other display areas.

[0005] In a first aspect, embodiments of this application provide an array substrate, which includes a transparent aperture, a display area, and a non-display area. The display area surrounds the transparent aperture, and the non-display area includes a first border area and a second border area. Along a first direction, the first border area, the display area, and the second border area are arranged sequentially. The second border area is used to connect to a touch control chip or a flexible circuit board, and the first border area is provided with a load module. The display area includes: multiple target scan signal lines extending along a second direction and spaced apart along the first direction. The target scan signal lines are electrically connected to sub-pixels in the display area and are used to provide scan signals to the sub-pixels. The first direction intersects the second direction. Multiple data signal lines and multiple dummy data signal lines extending along the first direction and spaced apart along the second direction are also included. The display area includes a first region and a second region. Along the second direction, the first region is divided into at least two sub-regions by the transparent aperture. The target scan signal lines in the first region are electrically connected to the load module in the first border area through the dummy data signal lines.

[0006] Secondly, embodiments of this application provide a display device, which includes an array substrate as provided in the first aspect.

[0007] The array substrate and display device of this application embodiment, on the one hand, by adding a load module electrically connected to the target scan signal line in the first region, can achieve load compensation for the target scan signal line in the first region, so that the load size of the target scan signal line in the first region is the same as, similar to, or conforms to a certain gradual change law with the load size of the target scan signal line in the second region, thereby improving the display effect difference between the first region and the second region and enhancing the display effect; on the other hand, by multiplexing the dummy data signal line located in the display area as the connection trace between the load module and the target scan signal line in the first region, not only can the number of traces in the array substrate be reduced, but also, since the dummy data signal line is located in the display area, the connection trace between the load module and the target scan signal line in the first region does not need to be routed to the non-display area, so the number of traces in the non-display area can be reduced, thereby helping to reduce the size of the bezel and achieve a narrow bezel; furthermore, by placing the load module in the first bezel area closest to the transparent hole, the trace length of the connection trace between the load module and the target scan signal line in the first region can be reduced, saving wiring space and reducing production costs. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a structure of an array substrate;

[0010] Figure 2 This is a partial circuit diagram of an array substrate.

[0011] Figure 3 This is a schematic diagram of a pixel circuit.

[0012] Figure 4 This is a partial cross-sectional schematic diagram of the display panel where the array substrate is located, as provided in an embodiment of this application.

[0013] Figure 5 A top view schematic diagram of an array substrate provided in an embodiment of this application;

[0014] Figure 6 This is a partial top view of an array substrate provided in an embodiment of this application;

[0015] Figure 7 This is a partial cross-sectional schematic diagram of an array substrate provided in an embodiment of this application;

[0016] Figure 8Another partial cross-sectional schematic diagram of the array substrate provided in the embodiments of this application;

[0017] Figure 9 This is a partial top view of an array substrate provided in an embodiment of this application;

[0018] Figure 10 A top view schematic diagram of an array substrate provided in an embodiment of this application;

[0019] Figure 11 This is a partial circuit diagram of an array substrate provided in an embodiment of this application;

[0020] Figure 12 Another partial circuit diagram of the array substrate provided in the embodiments of this application;

[0021] Figure 13 Another partial circuit diagram of the array substrate provided in the embodiments of this application;

[0022] Figure 14 Another partial circuit diagram of the array substrate provided in the embodiments of this application;

[0023] Figure 15A A schematic diagram of a pixel circuit in an array substrate provided in an embodiment of this application;

[0024] Figure 15B for Figure 15A A timing diagram of a corresponding embodiment;

[0025] Figure 16 Another partial circuit diagram of the array substrate provided in the embodiments of this application;

[0026] Figure 17 Another partial circuit diagram of the array substrate provided in the embodiments of this application;

[0027] Figure 18 A schematic diagram of another partial structure of the array substrate provided in an embodiment of this application;

[0028] Figure 19 A schematic diagram of another partial structure of the array substrate provided in an embodiment of this application;

[0029] Figure 20 A schematic diagram of another partial structure of the array substrate provided in an embodiment of this application;

[0030] Figure 21 A schematic diagram of another partial structure of the array substrate provided in an embodiment of this application;

[0031] Figure 22Another partial cross-sectional schematic diagram of the array substrate provided in the embodiments of this application;

[0032] Figure 23 This is a partial planar schematic diagram of an array substrate provided in an embodiment of this application;

[0033] Figure 24 Another partial planar schematic diagram of the array substrate provided in the embodiments of this application;

[0034] Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0035] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0036] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0037] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0038] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors, unless otherwise specified. For N-type transistors, the on-level is high and the off-level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-level is low and the off-level is high. That is, when the gate of a P-type transistor is low, its first and second terminals are connected; when the gate of a P-type transistor is high, its first and second terminals are off. In specific implementation, the gate of each transistor is used as its control electrode. Furthermore, depending on the signal and type of the gate of each transistor, its first electrode can be used as the source and its second electrode as the drain, or its first electrode can be used as the drain and its second electrode as the source. No distinction is made here. In addition, the on-level and off-level in the embodiments of the present invention are general terms. The on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / turn off the transistor.

[0039] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components.

[0040] In the embodiments of this application, the first node is defined only for the convenience of describing the circuit structure, and the first node is not an actual circuit unit.

[0041] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0042] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0043] As mentioned above, the inventors of this application have discovered that there is a problem in the related technology where the display effect of the first area corresponding to the transparent hole differs significantly from that of other display areas.

[0044] In order to solve the above-mentioned technical problems, the inventors of this application first studied and analyzed the root causes of the above-mentioned technical problems. The specific research and analysis process is as follows:

[0045] Figure 2This is a schematic diagram of a partial circuit of an array substrate. For example... Figure 2 As shown, the inventors of this application have discovered that because pixel circuit 10' is not provided in the transparent hole k1, or in other words, sub-pixels are not provided in the transparent hole k1 ( Figure 2 (Not shown), therefore, the number of pixel circuits 10' connected to the scan signal line S in the first region A1 is less than the number of pixel circuits 10' connected to the scan signal line S in the second region A2. This results in a smaller load on the scan signal line S in the first region A1 compared to the second region A2, meaning the load on the scan signal line S in the first region A1 differs significantly from the load on the scan signal line S in the second region A2. Consequently, the display effect in the first region A1 differs from that in the second region A2, leading to a poor overall display effect.

[0046] Figure 3 This is a circuit diagram of a pixel circuit. Combined with... Figure 2 and Figure 3 As shown, for example, taking the scan signal line S as the scan signal line controlling the on / off state of the data write transistor T1', since the load of the scan signal line S in the first region A1 is less than the load of the scan signal line S in the second region A2, the delay of the scan signal output from the scan signal line S in the first region A1 will be less than the delay of the scan signal output from the scan signal line S in the second region A2. This results in the conduction time of the data write transistor T1' in the first region A1 being greater than the conduction time of the data write transistor T1' in the second region A2, meaning the write data signal time in the first region A1 is more sufficient. In some cases with higher refresh rates, because the conduction time of the data write transistor T1' is inherently shorter, the write data signal time in the second region A2 may be insufficient, causing the potential of the gate (i.e., the first node N1) of the driving transistor T0' to fail to reach the expected potential. Because the conduction time of the data writing transistor T1' in the first region A1 is longer than that of the data writing transistor T1' in the second region A2, the gate potential of the driving transistor T0' in the first region A1 can reach the expected potential more effectively, or in other words, the difference between it and the expected potential is smaller. This results in a significant difference in display brightness between the first region A1 and the second region A2, leading to a poor overall display effect.

[0047] In view of the inventors’ above-mentioned research findings, the present application provides an array substrate and a display device that can solve the technical problem in the related art of poor display effect caused by the large difference between the load of the scan signal lines in the first region and the load of the scan signal lines in the second region.

[0048] The technical concept of this application embodiment is as follows: a load module is added in the first frame area closest to the transparent hole, and the target scan signal line in the first area is electrically connected to the load module through a virtual data signal line located in the display area. On the one hand, by adding a load module and electrically connecting it to the target scan signal line in the first area, load compensation for the target scan signal line in the first area can be achieved, so that the load size of the target scan signal line in the first area is the same as, similar to, or conforms to a certain gradual change law with the load size of the target scan signal line in the second area, thereby improving the display effect difference between the first area and the second area and enhancing the display effect; on the other hand, by using a virtual data signal line in the display area, the load compensation for the target scan signal line in the first area can be achieved, so that the load size of the target scan signal line in the first area is the same as, similar to, or conforms to a certain gradual change law with the load size of the target scan signal line in the second area, thereby improving the display effect difference between the first area and the second area; The dummy data signal lines in the display area are multiplexed as connection traces between the load module and the target scan signal lines in the first area. This not only reduces the number of traces in the array substrate, but also, because the dummy data signal lines are located in the display area, the connection traces between the load module and the target scan signal lines in the first area do not need to be routed to the non-display area. This reduces the number of traces in the non-display area, which helps to reduce the size of the bezel and achieve a narrow bezel. On the other hand, placing the load module in the first bezel area, which is closest to the transparent hole, reduces the trace length of the connection traces between the load module and the target scan signal lines in the first area, saving wiring space and reducing production costs.

[0049] The array substrate provided in the embodiments of this application will be described below first.

[0050] Figure 4 This is a partial cross-sectional schematic diagram of the display panel where the array substrate is located, as provided in an embodiment of this application. Figure 4 As shown, the display panel may include the array substrate 40 and the light-emitting element D provided in this embodiment. The light-emitting element D may be disposed on the array substrate 40 and electrically connected to the pixel circuit in the array substrate 40. That is, the array substrate 40 may be part of the display panel and is used to provide the pixel circuit for driving the light-emitting element D to emit light. Exemplarily, the light-emitting element D may include a first electrode RE, a second electrode SE, and a light-emitting layer OM located between the first electrode RE and the second electrode SE. The first electrode RE of the light-emitting element D may be the anode of the light-emitting element D, and the second electrode SE of the light-emitting element D may be the cathode of the light-emitting element D.

[0051] It should be noted that, Figure 4 The film structure of the array substrate 40 is only for illustration and does not constitute a limitation on the embodiments of this application.

[0052] Figure 5 This is a top view schematic diagram of an array substrate provided in an embodiment of this application. Figure 5As shown, the array substrate 40 provided in this embodiment includes a transparent hole k1, a display area AA, and a non-display area NA. The display area AA surrounds the transparent hole k1. The non-display area NA may include a first border area NA1 and a second border area NA2. Along the first direction Y, the first border area NA1, the display area AA, and the second border area NA2 are arranged sequentially. Figure 5 For example, the first border area NA1 can be the upper border, and the second border area NA2 can be the lower border. The second border area NA2 can be used to connect a driver chip (not shown in the figure) or a flexible printed circuit (FPC). The driver chip can provide drive signals to the array substrate 40. The first border area NA1 is provided with a load module 50. The load module 50 has a certain resistance or capacitance value and can be used to compensate for the load of the target scan signal line.

[0053] See also Figure 5 The display area AA may include multiple target scan signal lines SN extending along the second direction X and spaced apart along the first direction Y. The target scan signal lines SN may be electrically connected to sub-pixels (not shown in the figure) in the display area AA, and may be used to provide scan signals to the sub-pixels. It is understood that a sub-pixel may include pixel circuitry and a light-emitting element electrically connected to the pixel circuitry. Specifically, the target scan signal lines SN may be electrically connected to the pixel circuitry in the display area AA to provide scan signals to the pixel circuitry.

[0054] The first direction Y can intersect with the second direction X. For example, the first direction Y can be perpendicular to the second direction X. Exemplarily, the first direction Y can be the column direction of the array substrate 40, and the second direction X can be the row direction of the array substrate 40.

[0055] The display area AA may also include multiple data signal lines data extending along the first direction Y and spaced apart along the second direction X, and multiple dummy data signal lines data'. In some examples, for instance, the data signal lines data located in the edge region of the array substrate 40 can be electrically connected to bonding pads (not shown in the figure) through dummy data signal lines data' located in the central region of the array substrate 40. The bonding pads are then electrically connected to the driver chip or FPC, thereby reducing the area occupied by the fan-out lines in the second bezel area NA2, which is beneficial for achieving a narrow bezel. Specific examples will be described in detail below, and will not be described in detail here.

[0056] See also Figure 5The display area AA may include a first area A1 and a second area A2. Along the second direction X, the first area A1 may be divided into at least two sub-areas a by a transparent hole k1. For example, the width w of the first area A1 along the first direction Y may be equal to the width w of the transparent hole k1 along the first direction Y. For ease of explanation, for example, the other display areas in the display area AA besides the first area A1 may be referred to as the second area A2.

[0057] The target scan signal line SN in the first region A1 can be electrically connected to the load module 50 in the first border region NA1 through the dummy data signal line data', thereby compensating for the load of the target scan signal line SN in the first region A1.

[0058] The array substrate 40 of this application embodiment, on the one hand, by adding a load module electrically connected to the target scan signal line in the first region, can achieve load compensation for the target scan signal line in the first region, so that the load size of the target scan signal line in the first region is the same as, similar to, or conforms to a certain gradient law with the load size of the target scan signal line in the second region, thereby improving the display effect difference between the first region and the second region and enhancing the display effect; on the other hand, by multiplexing the dummy data signal line located in the display area as the connection trace between the load module and the target scan signal line in the first region, not only can the number of traces in the array substrate be reduced, but also, since the dummy data signal line is located in the display area, the connection trace between the load module and the target scan signal line in the first region does not need to be routed to the non-display area, so the number of traces in the non-display area can be reduced, thereby helping to reduce the size of the bezel and achieve a narrow bezel; furthermore, by placing the load module in the first bezel area closest to the transparent hole, the trace length of the connection trace between the load module and the target scan signal line in the first region can be reduced, saving wiring space and reducing production costs.

[0059] Figure 6 This is a partial top view of an array substrate provided in an embodiment of this application. Figure 6 As shown, according to some embodiments of this application, optionally, the dummy data signal line data' may include at least two disconnected trace segments L, wherein the trace segment L closest to the first border area NA1 is the first trace segment L1. The target scan signal line SN in the first region A1 can be electrically connected to the load module 50 in the first border area NA1 through the first trace segment L1. That is, the target scan signal line SN in the first region A1 can be electrically connected to the load module 50 in the first border area NA1 through the trace segment L closest to the first border area NA1.

[0060] In this way, by dividing the dummy data signal line data' into at least two trace segments L, and using only one trace segment L of the dummy data signal line data' to connect the target scan signal line SN and the load module 50, the normal use of the other trace segments L in the dummy data signal line data' can be maintained. For example, the other trace segments L in the dummy data signal line data' besides the first trace segment L1 can be electrically connected to the data signal line data for transmitting data signals. As another example, the other trace segments L in the dummy data signal line data' besides the first trace segment L1 can also be electrically connected to the first power supply voltage signal line PVDD (not shown in the figure) and / or the second power supply voltage signal line PVEE (not shown in the figure), so that the first power supply voltage signal line PVDD and / or the second power supply voltage signal line PVEE form a mesh trace to reduce the IR-drop of the first power supply voltage signal line PVDD and / or the second power supply voltage signal line PVEE.

[0061] Further research by the inventors of this application revealed that when there is a break in the dummy data signal line data', the degree of reflected light at the break point and the non-break point on the dummy data signal line data' may differ, causing bright spots to appear in the display panel and affecting the display effect.

[0062] In view of this, this application considers setting the break point of the dummy data signal line data' directly below the anode of the light-emitting element, so as to block the break point of the dummy data signal line data' by the anode of the light-emitting element, so as to avoid bright spots appearing in the screen during display and improve the display effect.

[0063] Figure 7 This is a partial cross-sectional schematic diagram of an array substrate provided in an embodiment of this application. Figure 7 As shown, according to some embodiments of this application, optionally, a light-emitting element D is disposed on the array substrate 40, and the dummy data signal line data' may be located in a different film layer from the anode RE of the light-emitting element D. Along the direction Z perpendicular to the plane of the array substrate, the break point p1 of the dummy data signal line data' may be located within the orthographic projection of the anode RE of the light-emitting element D onto the array substrate 40, that is, the break point p1 of the dummy data signal line data' may be located directly below the anode RE of the light-emitting element D.

[0064] In this way, by blocking the breakpoint p1 of the dummy data signal line data' through the anode RE of the light-emitting element D, bright spots can be avoided in the display, thus improving the display effect.

[0065] See also Figure 7In some specific examples, the array substrate 40 may optionally include a substrate 01, a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a fifth metal layer M5 stacked together.

[0066] It is readily understood that electronic devices such as thin-film transistors and capacitors are disposed in the array substrate 40. In some specific embodiments, for example, the gates of at least some of the thin-film transistors and the first plates of at least some of the capacitors may be located in the first metal layer M1, the second plates of at least some of the capacitors may be located in the second metal layer M2, and the sources and drains of at least some of the thin-film transistors may be located in the third metal layer M3.

[0067] For example, the dummy data signal line 'data' can be located in the fifth metal layer M5.

[0068] Figure 8 This is another partial cross-sectional schematic diagram of the array substrate provided in an embodiment of this application. (See attached diagram.) Figure 8 As shown, according to some other embodiments of this application, optionally, the array substrate 40 of this application embodiment may employ low-temperature polycrystalline oxide (LTPO) technology. That is, the pixel circuit of the array substrate 40 may include both low-temperature polycrystalline silicon thin-film transistors T1' and oxide thin-film transistors T2'.

[0069] Specifically, unlike the embodiment shown in Figure 7, the array substrate 40 may further include a sixth metal layer M6, which may be located between the second metal layer M2 and the third metal layer M3 along a direction Z perpendicular to the plane of the array substrate. The oxide thin-film transistor T2' may be a dual-gate transistor, and the first gate g1 of the oxide thin-film transistor T2' may be located in the first metal layer M1 or the second metal layer M2, while the second gate g2 of the oxide thin-film transistor T2' may be located in the sixth metal layer M6.

[0070] Figure 9 This is a partial top view of an array substrate provided in an embodiment of this application. Figure 9 As shown, this application considers that the connection position p2 between some target scan signal lines SN and the first trace segment L1 may not be directly below the anode RE of the light-emitting element. If the dummy data signal line data' is broken near the connection position p2, the break point p1 of the dummy data signal line data' may no longer be directly below the anode RE of the light-emitting element. Therefore, for example, for any i-th first trace segment L1, the i-th first trace segment L1 can extend to within the orthographic projection of the anode RE of the light-emitting element onto the array substrate, and then break off from other trace segments L on the same straight line. Here, i is a positive integer.

[0071] In this way, even if the connection point p2 between the target scan signal line SN and the first trace segment L1 is not directly below the anode RE of the light-emitting element, it can still ensure that the break point p1 of the dummy data signal line data' is directly below the anode RE of the light-emitting element, thereby avoiding bright spots in the display and improving the display effect.

[0072] As mentioned earlier, the data signal line data located at the edge region of the array substrate 40 can be electrically connected to the bonding pad (not shown in the figure) through the dummy data signal line data' located in the central region of the array substrate 40. The bonding pad is then electrically connected to the driver chip or FPC, thereby reducing the area of ​​the second border region NA2 occupied by the fan-out line, which is beneficial for achieving a narrow border. For ease of understanding, the following will be combined with Figure 10 Please provide a detailed explanation.

[0073] Figure 10 This is a top view schematic diagram of an array substrate provided in an embodiment of this application. Figure 10 As shown, according to some embodiments of this application, optionally, the array substrate 40 further includes a first connection line X1 extending along the second direction X. The display area AA may include a first edge area B1, a central area Q, and a second edge area B2 arranged sequentially along the second direction X. The data signal lines data in the first edge area B1 and the second edge area B2 can be electrically connected to the dummy data signal line data' located in the central area Q through the first connection line X1. The dummy data signal line data' in the central area Q is then electrically connected to the driver chip or FPC through the bonding pads in the second border area NA2 to receive data signals.

[0074] In this way, it is no longer necessary to set fan-out lines that are electrically connected to the data signal lines in the first edge region B1 and the second edge region B2. In other words, the fan-out lines that are electrically connected to the data signal lines in the first edge region B1 and the second edge region B2 are moved to the center of the array substrate 40, thereby reducing the area of ​​the second border region NA2 occupied by the fan-out lines, which is beneficial to achieving a narrow border.

[0075] It should be noted that in some examples, the data signal line `data` and the dummy data signal line `data'` may be located in the same film layer, while the first connection line `X1` may be located in another film layer. In other examples, the dummy data signal line `data'` and the first connection line `X1` may be located in the same film layer, while the data signal line `data` may be located in another film layer. This embodiment of the present application does not limit this.

[0076] See also Figure 10According to some embodiments of this application, optionally, a trace segment L in the dummy data signal line data' that is not at least partially connected to the target scan signal line SN and the data signal line data is referred to as the target trace segment Ln. The target trace segment Ln can be electrically connected to a constant voltage signal line (not shown in the figure). Specifically, the target trace segment Ln can be electrically connected to the constant voltage signal line through a via. For example, the constant voltage signal line includes, but is not limited to, the first power supply voltage signal line PVDD and / or the second power supply voltage signal line PVEE.

[0077] In this way, on the one hand, the target trace segment Ln is electrically connected to the constant voltage signal line, which can ensure that the target trace segment Ln maintains a stable potential and ensures the stability of the circuit in the array substrate; on the other hand, it can make the constant voltage signal line form a mesh trace to reduce the IR-drop of the constant voltage signal line.

[0078] Figure 11 This is a partial circuit diagram of an array substrate provided in an embodiment of this application. Figure 11 As shown, according to some embodiments of this application, optionally, a sub-region a may include m1 target scan signal lines SN, where each of the m1 target scan signal lines SN can be electrically connected to one of the m1 dummy data signal lines data', and m1 is a positive integer. It should be noted that... Figure 11 The example shown uses m1=6, but it is understood that m1 can also be any other value besides 6, and this application does not limit this.

[0079] Target scan signal line SN1 to m1 target scan signal line SN m1 The m1 dummy data signal lines data' are arranged sequentially along the first direction Y, and sequentially along the second direction X, with the m1th dummy data signal line data' being... m1 Located on the side of the first dummy data signal line, data1, near the transparent hole k1.

[0080] Target scan signal line SN1 to m1 target scan signal line SN m1 It can be sequentially connected to the m1th dummy data signal line data m1 The first dummy data signal line, data1, is electrically connected to the first dummy data signal line, data1. That is, the first target scan signal line, SN1, is electrically connected to the m1th dummy data signal line, data1. m1 'Electrical connection, ..., m1st target scan signal line SN' m1 It can be electrically connected to the first dummy data signal line, data1'.

[0081] In this way, the first target scan signal line SN1 to the m1th target scan signal line SN in sub-region am1 The virtual data signal lines are connected sequentially to the dummy data signal lines data' in the order of their arrangement. This connection method conforms to the wiring pattern of the display area and facilitates wiring. In addition, it facilitates the location and repair of any break in the connection between the target scan signal line SN and the virtual data signal line data'.

[0082] Figure 12 This is another partial circuit diagram of the array substrate provided in an embodiment of this application. (See diagram below.) Figure 12 As shown, according to some other embodiments of this application, optionally, a sub-region a may include m1 target scan signal lines SN, where each of the m1 target scan signal lines SN can be electrically connected to one of the m1 dummy data signal lines data', and m1 is a positive integer. It should be noted that... Figure 12 The example shown uses m1=6, but it is understood that m1 can also be any other value besides 6, and this application does not limit this.

[0083] Target scan signal line SN1 to m1 target scan signal line SN m1 The m1 dummy data signal lines, data', are arranged sequentially along the first direction Y, and sequentially along the second direction X. Figure 11 The difference in the illustrated embodiment is that the first dummy data signal line data1' is located on the m1th dummy data signal line data. m1 'The side closest to the transparent hole k1.'

[0084] Target scan signal line SN1 to m1 target scan signal line SN m1 It can be sequentially connected to the m1th dummy data signal line data m1 The first dummy data signal line, data1, is electrically connected to the first dummy data signal line, data1. That is, the first target scan signal line, SN1, is electrically connected to the m1th dummy data signal line, data1. m1 'Electrical connection, ..., m1st target scan signal line SN' m1 It can be electrically connected to the first dummy data signal line, data1'.

[0085] In this way, the first target scan signal line SN1 to the m1th target scan signal line SN in sub-region a m1 The virtual data signal lines are connected sequentially to the dummy data signal lines data' in the order of their arrangement. This connection method conforms to the wiring pattern of the display area and facilitates wiring. In addition, it facilitates the location and repair of any break in the connection between the target scan signal line SN and the virtual data signal line data'.

[0086] Figure 13 This is another partial circuit diagram of the array substrate provided in an embodiment of this application. For example... Figure 13As shown, according to some embodiments of this application, optionally, a sub-region a may include m1 target scan signal lines SN, where each of the m1 target scan signal lines SN can be electrically connected to one of the m1 dummy data signal lines data', and m1 is a positive integer. It should be noted that... Figure 13 The example shown uses m1=6, but it is understood that m1 can also be any other value besides 6, and this application does not limit this.

[0087] Target scan signal line SN1 to m1 target scan signal line SN m1 The m1 dummy data signal lines data' are arranged sequentially along the first direction Y, and sequentially along the second direction X, with the m1th dummy data signal line data' being... m1 Located on the side of the first dummy data signal line, data1, near the transparent hole k1.

[0088] The first target scan signal line SN1 to the j-th target scan signal line SN j Sequentially connected to the first dummy data signal line data1' to the j-th dummy data signal line data j A one-to-one electrical connection is established, where 1 < j < m1 and j is an integer. Optionally, in some examples, j can be equal to m1 / 2. Of course, j can also be any value greater than 1 and less than m1, and this application does not limit this.

[0089] The (j+1)th target scan signal line SN j+1 Up to the m1st target scan signal line SN m1 sequentially connected to the m1th dummy data signal line data m1 'Up to the (j+1)th dummy data signal line data j+1 One-to-one electrical connection.

[0090] like Figure 13 As shown, along the second direction X, two load modules 50 can be set in a row, each load module 50 is used to compensate for the load of a target scan signal line SN. In this way, since two load modules 50 are set in a row, the width of the first border area NA1 along the first direction Y can be reduced, which is beneficial to achieving a narrow border.

[0091] Furthermore, since the edge of the transparent aperture k1 is arc-shaped, the target scanning signal line SN located at the edge of sub-region a (such as the first target scanning signal line SN1 or the m1st target scanning signal line SN) m1 The number of pixel circuits connected is relatively large, corresponding to a smaller load that needs to be compensated; while the target scan signal line SN located at the center of sub-region a (such as the m1 / 2th target scan signal line SN1 or the (m1 / 2)+1th target scan signal line SN)m1 The fewer the number of connected pixel circuits, the larger the load that needs to be compensated. The larger the resistance or capacitance value of the load module 50, the larger its size. Taking m1=6 as an example, the first target scan signal line SN1 and the sixth target scan signal line SN... m1 The load module 50 connected to the third target scan signal line SN and the fourth target scan signal line SN has the smallest size, and the load module 50 connected to the second target scan signal line SN and the fifth target scan signal line SN has a size in between.

[0092] And take Figure 13 The connection method shown allows the load module 50 connected to the first target scan signal line SN1 to be in the same row as the load module 50 connected to the fourth target scan signal line SN, the load module 50 connected to the second target scan signal line SN to be in the same row as the load module 50 connected to the fifth target scan signal line SN, and the load module 50 connected to the third target scan signal line SN to be in the same row as the load module 50 connected to the sixth target scan signal line SN. m1 The connected load modules 50 are located in the same row, ensuring that the sum of the sizes of the load modules 50 in each row is the same or similar, thus avoiding significant differences in the sum of the sizes of load modules 50 in different rows. Furthermore, [the following is taken:] Figure 13 In this connection method, any dummy data signal line 'data' can be connected to the corresponding load module 50 without overlapping with other load modules 50. This avoids cross-line design, saves wiring space, simplifies the manufacturing process, and reduces production costs. The other load modules 50 mentioned above can be understood as the load modules 50 to which other dummy data signal lines 'data' are connected.

[0093] Figure 14 This is another partial circuit diagram of the array substrate provided in an embodiment of this application. For example... Figure 14 As shown, according to some embodiments of this application, optionally, a sub-region a may include m1 target scan signal lines SN, where each of the m1 target scan signal lines SN can be electrically connected to one of the m1 dummy data signal lines data', and m1 is a positive integer. It should be noted that... Figure 14 The example shown uses m1=6, but it is understood that m1 can also be any other value besides 6, and this application does not limit this.

[0094] Target scan signal line SN1 to m1 target scan signal line SN m1 The m1 dummy data signal lines data' are arranged sequentially along the first direction Y, and sequentially along the second direction X, with the m1th dummy data signal line data' being...m1 Located on the side of the first dummy data signal line, data1, near the transparent hole k1.

[0095] The first target scan signal line SN1 to the j-th target scan signal line SN j sequentially connected to the m1th dummy data signal line data m1 'Up to the m1-j+1th dummy data signal line data m1-j+1 A one-to-one electrical connection is established, where 1 < j < m1 and j is an integer. Optionally, in some examples, j can be equal to m1 / 2. Of course, j can also be any value greater than 1 and less than m1, and this application does not limit this.

[0096] The (j+1)th target scan signal line SN j+1 Up to the m1st target scan signal line SN m1 Sequentially connected to the first dummy data signal line data1' to the (j-1)th dummy data signal line data j-1 One-to-one electrical connection.

[0097] Figure 14 The illustrated embodiment is capable of producing the same as Figure 13 The technical effects of the embodiments shown are the same or similar, as detailed above, and will not be repeated here.

[0098] As mentioned earlier, when the scan signal line S is a scan signal line for controlling data writing, if the scan signal line S in the first region A1 is not compensated, the display brightness of the first region A1 may differ significantly from that of the second region A2. Therefore, in some embodiments, the target scan signal line SN can be a scan signal line for controlling data writing, that is, compensation is performed on the scan signal line for controlling data writing in the first region A1.

[0099] Figure 15A This is a schematic diagram of a pixel circuit in an array substrate provided in an embodiment of this application. Figure 15A As shown, according to some embodiments of this application, optionally, the array substrate includes a pixel circuit 100, which may include a driving module 101 and a data writing module 102. The driving module 101 can be used to drive the light-emitting element D to emit light.

[0100] The control terminal of the data writing module 102 is electrically connected to the first scan signal line S1, the first terminal of the data writing module 102 is electrically connected to the data signal line data, and the second terminal of the data writing module 102 is electrically connected to the first terminal of the drive module 101. The data writing module 102 is used to turn on in response to the conduction level provided by the first scan signal line S1 and write the data signal of the data signal line data to the first terminal of the drive module 101.

[0101] The target scan signal line SN may include the first scan signal line S1.

[0102] In this way, by compensating for the load of the first scan signal line S1 in the first region A1, the delay of the first scan signal output by the first scan signal line S1 in the first region A1 can be made the same as or similar to the delay of the first scan signal output by the first scan signal line S1 in the second region A2. This makes the conduction time of the data writing module 102 in the first region A1 the same as or similar to the conduction time of the data writing module 102 in the second region A2, thereby reducing the difference in display brightness between the first region A1 and the second region A2 and improving the display effect.

[0103] See also Figure 15A According to some embodiments of this application, optionally, the pixel circuit 100 may further include a first reset module 102 and a threshold compensation module 103, wherein:

[0104] The control terminal of the first reset module 103 is electrically connected to the second scan signal line S2, the first terminal of the first reset module 103 is electrically connected to the first reference voltage signal line VREF1, and the second terminal of the first reset module 103 is electrically connected to the control terminal of the drive module 101. The first reset module 103 is used to turn on in response to the conduction level provided by the second scan signal line S2, and transmit the first reference voltage signal of the first reference voltage signal line VREF1 to the control terminal of the drive module 101 to reset the control terminal of the drive module 101.

[0105] The control terminal of the threshold compensation module 104 is electrically connected to the third scan signal line S3. The first terminal of the threshold compensation module 104 is electrically connected to the control terminal of the drive module 101, and the second terminal of the threshold compensation module 104 is electrically connected to the second terminal of the drive module 101. The threshold compensation module 104 is turned on in response to the conduction level provided by the third scan signal line S3, connecting the control terminal of the drive module 101 and the second terminal of the drive module 101, and cooperating with the data writing module 102 to realize the threshold voltage compensation of the drive module 101.

[0106] See also Figure 15A According to some embodiments of this application, the pixel circuit 100 may optionally include a second reset module 105, a first light emission control module 106, a second light emission control module 107, a bias voltage compensation module 108, and a storage capacitor Cst.

[0107] The control terminal of the second reset module 105 can be electrically connected to the fourth scan signal line S4. The first terminal of the second reset module 105 is electrically connected to the second reference voltage signal line VREF2, and the second terminal of the second reset module 105 is electrically connected to the first electrode of the light-emitting element D. The second reset module 105 is used to turn on in response to the conductivity level provided by the fourth scan signal line S4, and transmit the second reference voltage signal provided by the second reference voltage signal line VREF2 to the first electrode of the light-emitting element D to reset the first electrode of the light-emitting element D.

[0108] The control terminal of the first light-emitting control module 106 is electrically connected to the light-emitting control signal line EM, the first terminal of the first light-emitting control module 106 is electrically connected to the first power supply voltage signal line PVDD, and the second terminal of the first light-emitting control module 106 is electrically connected to the first terminal of the drive module 101.

[0109] The control terminal of the second light-emitting control module 107 is electrically connected to the light-emitting control signal line EM, the first terminal of the second light-emitting control module 107 is electrically connected to the second terminal of the driving module 101, and the second terminal of the second light-emitting control module 107 is electrically connected to the first electrode of the light-emitting element D.

[0110] The control terminal of the bias voltage compensation module 108 is electrically connected to the fifth scan signal line S5, the first terminal of the bias voltage compensation module 108 is electrically connected to the bias voltage signal line DVH, and the second terminal of the bias voltage compensation module 108 is electrically connected to the first terminal of the drive module 101. Before the data signal is written, the bias voltage compensation module 108 is turned on in response to the conduction level provided by the fifth scan signal line S5, transmitting the bias voltage signal provided by the bias voltage signal line DVH to the first terminal of the drive module 101. Since the drive module 101 is in the on state at this time, the bias voltage signal is also transmitted to the second terminal of the drive module 101, making the potential of the second terminal of the drive module 101 higher than the potential of the control terminal of the drive module 101, thereby adjusting the threshold voltage Vth of the drive module 101.

[0111] The storage capacitor Cst has its first plate electrically connected to the first power supply voltage signal line PVDD, and its second plate electrically connected to the first node N1, in order to maintain the potential of the first node N1.

[0112] In some embodiments, the target scan signal line SN may further include at least one of the second scan signal line S2 and the third scan signal line S3.

[0113] Since the first reset module 103 and the threshold compensation module 104 are electrically connected to the control terminal (i.e., the first node N1) of the drive module 101, the conduction duration of the first reset module 103 and the conduction duration of the threshold compensation module 104 will have a certain impact on the brightness of the light-emitting element D. Therefore, by compensating for the load of the second scan signal line S2 and / or the third scan signal line S3 in the first region A1, the difference between the display brightness of the first region A1 and the display brightness of the second region A2 can be further improved, thereby enhancing the display effect.

[0114] For example, such as Figure 15A As shown, for the 8T1C pixel circuit, each row of pixel circuits requires 5 scan signals (i.e., scan signals provided by scan signal lines S1 to S5). If each scan signal is equipped with a shift register circuit and dual-sided driving is used, 5 shift register circuits are required for a single-sided bezel, making a narrow bezel design impossible. Therefore, in this application, all scan signal lines except the first scan signal line S1 can be driven on a single side, with a one-to-two design. This can significantly reduce the width of the bezel area.

[0115] Figure 15B for Figure 15A A timing diagram corresponding to one embodiment. For example... Figure 15B As shown, Figure 15B In this diagram, S1-1 represents the first scan signal line S1 connected to the first row of pixel circuits 100 in two adjacent rows of pixel circuits 100 (hereinafter referred to as "first row first scan signal line S1"). S1-2 represents the first scan signal line S1 connected to the second row of pixel circuits 100 in two adjacent rows of pixel circuits 100 (hereinafter referred to as "second row first scan signal line S1"). Each third scan signal line S3 can be electrically connected to two rows of pixel circuits 100, thereby realizing a one-to-two design for the third scan signal line S3.

[0116] Combination Figure 15A and Figure 15BAs shown, taking the threshold compensation module 104 as an N-type transistor and the data writing module 102 as a P-type transistor as an example, when the third scan signal line S3 adopts a one-to-two design, the high-level pulse output by the third scan signal line S3 needs to cover the low-level pulses of the first scan signal line S1 of the first row and the first scan signal line S1 of the second row. When the third scan signal line S3 is on (i.e., outputs a high-level pulse), the first scan signal line S1 connected to the two rows of pixel circuits 100 is on alternately (i.e., outputs a low-level pulse). If the third scan signal line S3 is immediately off after the first scan signal line S1 of the second row is off, a brightness difference between odd and even rows will occur. This is because after the first scan signal line S1 of the first row is off, the third scan signal line S3 is still on, while after the first scan signal line S1 of the second row is off, the third scan signal line S3 is immediately off. This will cause the first row of pixel circuits 100 to have more charging time. Therefore, in order to solve the problem of brightness difference between odd and even rows, after the first scan signal line S1 of the second row is turned off, the third scan signal line S3 is kept on for a period of time, which can reduce the multiple of the difference in charging time between odd and even rows and alleviate the brightness difference between odd and even rows.

[0117] Based on the above design, since the opening time of the third scan signal line S3 affects the data signal input to the drive module 101, the brightness difference between the first region A1 and the second region A2 caused by the delay can be alleviated by load compensation for the third scan signal line S3.

[0118] In some embodiments, the fourth scan signal line S4 can be multiplexed with the first scan signal line S1.

[0119] See also Figure 15A According to some embodiments of this application, optionally, the driving module 101 may include a driving transistor T0, the data writing module 102 may include a first transistor T1, the first reset module 103 may include a second transistor T2, the threshold compensation module 104 may include a third transistor T3, the second reset module 105 may include a fourth transistor T4, the first light-emitting control module 106 may include a fifth transistor T5, the second light-emitting control module 107 may include a sixth transistor T6, and the bias voltage compensation module 108 may include a seventh transistor T7. For the connection method between the transistors, please refer to [link to relevant documentation]. Figure 15A The connection methods for each module described above will not be repeated here.

[0120] Figure 16 This is another partial circuit diagram of the array substrate provided in an embodiment of this application. For example... Figure 16As shown, according to some embodiments of this application, optionally, the array substrate 40 further includes a scan driving circuit 200, which includes a plurality of cascaded shift registers 200a. One shift register 200a can be electrically connected to an adjacent m-th target scan signal line SN and an (m+1)-th target scan signal line SN, where m is a positive integer. That is, one shift register 200a can be electrically connected to an adjacent target scan signal line SN, and the shift register 200a can be used to output a scan signal to the target scan signal line SN.

[0121] The m-th target scan signal line SN and the (m+1)-th target scan signal line SN in the first region A1 can be electrically connected to the load module 50 in the first border region NA1 through the same dummy data signal line data'. That is, for the m-th target scan signal line SN and the (m+1)-th target scan signal line SN connected to the same shift register 200a, they can be connected to adjacent m-th and (m+1)-th target scan signal lines SN through the same dummy data signal line data', and then electrically connected to a load module 50. The resistance value of the load module 50 can be the sum of the resistance values ​​to be compensated for the m-th and (m+1)-th target scan signal lines SN. Alternatively, the capacitance value of the load module 50 can be the sum of the capacitance values ​​to be compensated for the m-th and (m+1)-th target scan signal lines SN.

[0122] In this way, for the m-th target scan signal line SN and the (m+1)-th target scan signal line SN connected by the same shift register 200a, the two target scan signal lines SN can achieve load compensation through only one dummy data signal line data' and one load module 50, which greatly reduces the number of dummy data signal lines data' and load modules 50 used, saving wiring space and production costs.

[0123] Combination Figure 15A and Figure 16 As shown, in some specific embodiments, optionally, the second scan signal line S2 and the third scan signal line S3 can be adopted. Figure 16 The one-to-two connection method shown means that one shift register can be connected to two adjacent second scan signal lines S2, and / or one shift register can be connected to two adjacent third scan signal lines S3.

[0124] Figure 17 This is another partial circuit diagram of the array substrate provided in an embodiment of this application. For example... Figure 17 As shown, according to some embodiments of this application, optionally, the z1th target scan signal line SN in the first sub-region a1 z1The number of connected sub-pixels (not shown in the figure) can be related to the z2th target scan signal line SN in the first sub-region a1. z2 The number of connected sub-pixels is the same, and both z1 and z2 are positive integers. For example, such as Figure 13 As shown, for example, the number of sub-pixels connected to the first target scan signal line SN1 and the sixth target scan signal line SN m1 The number of connected sub-pixels can be the same.

[0125] Due to the z1st target scan signal line SN z1 The number of connected sub-pixels and the z2th target scan signal line SN z2 Since the number of connected sub-pixels is the same, theoretically the z1th target scan signal line SN z1 The load size to be compensated is related to the z2th target scan signal line SN. z2 The load size to be compensated. However, the inventors of this application have discovered that, in practice, if the z1th target scan signal line SN z1 With the z2th target scan signal line SN z2 Compensating for the same load may result in undercompensation or overcompensation of one or two target scan signal lines.

[0126] In view of this, this application considers the z1th target scan signal line SN z1 With the z2th target scan signal line SN z2 Difference compensation is performed. Specifically, for ease of explanation, it will be compared with the z1th target scan signal line SN. z1 The first trace segment L1 is called the first target trace segment Lm1, and it will connect with the z2th target scan signal line SN. z2 The first trace segment L1 is called the second target trace segment Lm2. The length h1 of the first target trace segment Lm1 can be greater than the length h2 of the second target trace segment, and / or the number of scan signal lines (not shown in the figure) overlapping with the first target trace segment Lm1 can be greater than the number of scan signal lines overlapping with the second target trace segment Lm2.

[0127] It's easy to understand that the longer the trace length, the greater the trace's impedance. Therefore, the impedance of the first target trace segment Lm1 is greater than that of the second target trace segment. Furthermore, the first target trace segment Lm1 and the second target trace segment Lm2, extending along the first direction Y, overlap with the scan signal lines extending along the second direction X. This overlap generates coupling capacitance, increasing the load on both the first target trace segment Lm1 and the second target trace segment Lm2. When the number of scan signal lines overlapped by the first target trace segment Lm1 is greater than the number of scan signal lines overlapped with the second target trace segment Lm2, the load on the first target trace segment Lm1 will also be greater than the load on the second target trace segment Lm2. Therefore, the first trace segment L1 can be considered as part of compensating for the load of the target scan signal line SN.

[0128] Accordingly, the z1th target scan signal line SN z1 The resistance of the corresponding connected load module 50 can be less than that of the z2th target scan signal line SN. z2 The resistance value of the corresponding connected load module 50. Or, the resistance value of the z1th target scan signal line SN. z1 The capacitance of the corresponding connected load module 50 can be less than that of the z2th target scan signal line SN. z2 The capacitance value of the corresponding connected load module 50.

[0129] In this way, differential compensation can be performed on different target scan signal lines (SN) with the same load to be compensated, which can solve the problem of undercompensation or overcompensation of the target scan signal lines and achieve accurate compensation.

[0130] For ease of understanding, the array substrate 40 of the present application will be illustrated below with some specific embodiments.

[0131] Figure 18 This is a schematic diagram of another partial structure of the array substrate provided in an embodiment of this application. For example... Figure 18 As shown, according to some embodiments of this application, optionally, along the second direction X, the first region A1 is at least spaced by the transparent hole k1 into a first sub-region a1 and a second sub-region a2.

[0132] The first sub-region a1 may include m1 target scanning signal lines SN, and the second sub-region a2 may include m2 target scanning signal lines SN. The m1 target scanning signal lines SN extend to the first side edge k1a of the transparent hole k1 and terminate there; the m2 target scanning signal lines SN extend to the second side edge k1b of the transparent hole k1 and terminate there. Both m1 and m2 are positive integers. The first side edge k1a and the second side edge k1b are opposite each other along the second direction X. Figure 18In the diagram, the first side edge k1a can be the left edge of the transparent hole k1, and the second side edge k1b can be the right edge of the transparent hole k1. For example, m1 can be equal to m2, meaning the number of target scan signal lines SN in the first sub-region a1 can be equal to the number of target scan signal lines SN in the second sub-region a2. The target scan signal lines SN in the first sub-region a1 and the target scan signal lines SN in the second sub-region a2 are not interconnected. The target scan signal lines SN in the first sub-region a1 can be electrically connected to the scan driving circuit (not shown in the figure) located on the left frame of the array substrate 40, and the target scan signal lines SN in the second sub-region a2 can be electrically connected to the scan driving circuit (not shown in the figure) located on the right frame of the array substrate 40, thereby providing scan signals for the pixel circuits in the first sub-region a1 and the second sub-region a2.

[0133] The m1 target scanning signal line SN can be electrically connected one-to-one with the m1 dummy data signal line data' located on the first side of the transparent hole k1 (such as the left side), and the m2 target scanning signal line SN can be electrically connected one-to-one with the m2 dummy data signal line data' located on the second side of the transparent hole k1.

[0134] In this way, since the target scanning signal line SN in the first sub-region a1 extends to the first side edge k1a of the transparent hole k1 and ends, and the target scanning signal line SN in the second sub-region a2 extends to the second side edge k1b of the transparent hole k1, it is not necessary to wrap the target scanning signal line SN on the first side of the transparent hole k1 to the second side of the transparent hole k1. Therefore, the number of traces around the transparent hole k1 can be reduced, effectively avoiding the signal crosstalk problem caused by too many traces around the transparent hole k1.

[0135] Figure 19 This is a schematic diagram of another partial structure of the array substrate provided in an embodiment of this application. For example... Figure 19 As shown, according to some other embodiments of this application, optionally, along the second direction X, the first region A1 is at least spaced by the transparent hole k1 into a first sub-region a1 and a second sub-region a2.

[0136] The first sub-region a1 may include m1 target scan signal lines SN. The m1 target scan signal lines SN in the first sub-region a1 can be wound along the edge of the transparent hole k1 to the second sub-region a2, and the m1 target scan signal lines can be electrically connected to the sub-pixels in the second sub-region a2. That is, the m1 target scan signal lines SN simultaneously provide scan signals to the sub-pixels in the first sub-region a1 and the second sub-region a2.

[0137] Of the m1 target scan signal lines SN, some target scan signal lines SN can be electrically connected to the load module 50 through the dummy data signal line data' located on the first side of the transparent hole k1, and other target scan signal lines SN can be electrically connected to the load module 50 through the dummy data signal line data' located on the second side of the transparent hole k1. Figure 19 In the middle, the first side of the transparent hole k1 can be the left side of the transparent hole k1, and the second side of the transparent hole k1 can be the right side of the transparent hole k1.

[0138] In this way, by connecting the target scanning signal lines SN in the first sub-region a1 and the second sub-region a2, the split-screen problem caused by inconsistent load or inconsistent load compensation effect between the first sub-region a1 and the second sub-region a2 can be avoided, thus improving the display effect.

[0139] It should be noted that in other embodiments, the m1 target scanning signal lines SN can all be electrically connected to the load module 50 through the dummy data signal line data' located on the first side of the transparent hole k1, or they can all be electrically connected to the load module 50 through the dummy data signal line data' located on the second side of the transparent hole k1. This application embodiment does not limit this.

[0140] Figure 20 This is a schematic diagram of another partial structure of the array substrate provided in an embodiment of this application. For example... Figure 20 As shown, according to some embodiments of this application, optionally, the transparent hole k1 may include a first hole k11 and a second hole k12 arranged at intervals along the second direction X. Exemplarily, both the first hole k11 and the second hole k12 may include any one of an oblong hole, a rectangular hole, an elliptical hole, and a circular hole. For example, as... Figure 20 As shown, the first hole k11 may include an oblong hole, and the second hole k12 may include a circular hole. The straight line containing the center of the oblong hole and the center of the circular hole is parallel to the second direction X. The length direction of the oblong hole may be parallel to the second direction X, the width direction of the oblong hole is parallel to the first direction Y, and the width of the oblong hole may be equal to the diameter of the circular hole.

[0141] The first region A1 is divided into a first sub-region a1, a second sub-region a2 and a third sub-region a3 by the first hole k11 and the second hole k12. The third sub-region a3 can be located between the first hole k11 and the second hole k12.

[0142] The first sub-region a1 may include m1 target scan signal lines SN, and the second sub-region a2 may include m2 target scan signal lines SN. The m1 target scan signal lines SN may extend to the edge of the first aperture k11 and terminate thereafter. The m2 target scan signal lines SN may be wound along the edge of the second aperture k12 to the third sub-region a3, and the m2 target scan signal lines SN may be electrically connected to the sub-pixels in the third sub-region a3. That is, the m2 target scan signal lines SN simultaneously provide scan signals to the sub-pixels in both the third sub-region a3 and the second sub-region a2. Optionally, the size of the second aperture k12 may be smaller than the size of the first aperture k11, that is, the target scan signal lines SN are wound along the edge of the smaller aperture to the third sub-region a3.

[0143] The m1 target scanning signal lines SN in the first sub-region a1 can be electrically connected one-to-one with the m1 dummy data signal lines data' located on the first side of the first hole k11. The first side of the first hole k11 is the side of the first hole k11 away from the second hole k12, such as the left side of the first hole k11.

[0144] The m2 target scanning signal lines SN in the second sub-region a2 can be electrically connected one-to-one with the m2 dummy data signal lines data' located on the second side of the first hole k11. The second side of the first hole k11 is the side of the first hole k11 that is closer to the second hole k12, such as the right side of the first hole k11.

[0145] In this way, since the target scan signal line SN in the first sub-region a1 extends to the first side edge of the first hole k11 and ends, and the target scan signal line SN in the second sub-region a2 extends to the second side edge of the first hole k11, it is not necessary to wrap the target scan signal line SN on the first side of the first hole k11 to the second side of the first hole k11. Therefore, the number of traces around the first hole k11 can be reduced, effectively avoiding the signal crosstalk problem caused by too many traces around the first hole k11.

[0146] See also Figure 20 According to some embodiments of this application, optionally, the m2 target scanning signal lines SN in the second sub-region a2 can be located between the first hole k11 and the second hole k12 (e.g., Figure 20 In region Q1, the m2 dummy data signal lines data' are electrically connected one-to-one. That is, the m2 target scan signal lines SN in the second sub-region a2 can be located between the first hole k11 and the second hole k12, and the dummy data signal lines data' are electrically connected to the load module 50.

[0147] In the second sub-region a2, the m2 target scanning signal lines SN extend to the region between the first hole k11 and the second hole k12 and terminate. A dummy data signal line data' is connected to the end of the target scanning signal line SN for load compensation, which has a good compensation effect.

[0148] See also Figure 20 According to other embodiments of this application, optionally, among the m2 target scanning signal lines SN in the second sub-region a2, some target scanning signal lines SN can be connected to those located between the first hole k11 and the second hole k12 (e.g., Figure 20 The dummy data signal line data' in the Q1 region is electrically connected, and another part of the target scan signal line SN can be connected to the second side of the second hole k12 (such as...). Figure 20 The dummy data signal line data' in the Q2 region is electrically connected. The second side of the second hole k12 is the side of the second hole k12 away from the first hole k11, that is, the right side of the second hole k12.

[0149] In this way, among the m2 target scan signal lines SN in the second sub-region a2, some target scan signal lines SN are electrically connected to the dummy data signal line data' in region Q1, and the other part of the target scan signal lines SN are electrically connected to the dummy data signal line data' in region Q2. This can make the wiring uniform, facilitate wiring, and reduce the size of the upper border.

[0150] Figure 21 This is a schematic diagram of another partial structure of the array substrate provided in an embodiment of this application. For example... Figure 21 As shown, according to some embodiments of this application, optionally, the transparent hole k1 may include a first hole k11 and a second hole k12 arranged at intervals along the second direction X. The first region A1 is divided into a first sub-region a1, a second sub-region a2 and a third sub-region a3 by the first hole k11 and the second hole k12, and the third sub-region a3 may be located between the first hole k11 and the second hole k12.

[0151] The first sub-region a1 may include m1 target scanning signal lines SN. The m1 target scanning signal lines SN may be sequentially wound around the edges of the first hole k11 and the second hole k12 to the third sub-region a3 and the second sub-region a2. The m1 target scanning signal lines SN are electrically connected to the sub-pixels in the third sub-region a3 and the sub-pixels in the second sub-region a2.

[0152] Of the m1 target scan signal lines SN in the first sub-region a1, some target scan signal lines SN can be electrically connected to the load module 50 through the dummy data signal line data' located on the first side of the first hole k11, and other target scan signal lines SN can be electrically connected to the load module 50 through the dummy data signal line data' located on the second side of the first hole k11. The first side of the first hole k11 is the side of the first hole k11 furthest from the second hole k12, and the second side of the first hole k11 is the side of the first hole k11 closest to the second hole k12.

[0153] In this way, by connecting the target scanning signal lines SN in the first sub-region a1, the second sub-region a2, and the third sub-region a3, the split-screen problem caused by inconsistent load or inconsistent load compensation effect in the first sub-region a1, the second sub-region a2, and the third sub-region a3 can be avoided, thus improving the display effect.

[0154] In addition, among the m1 target scan signal lines SN in the first sub-region a1, some target scan signal lines SN can be electrically connected to the load module 50 through the dummy data signal line data' located on the first side of the first hole k11, and the other part of the target scan signal lines SN can be electrically connected to the load module 50 through the dummy data signal line data' located on the second side of the first hole k11. This can make the wiring uniform, facilitate wiring, and reduce the size of the upper frame.

[0155] Of course, in other embodiments, the m1 target scanning signal lines SN of the first sub-region a1 can all be electrically connected to the load module 50 through the dummy data signal line data' located on the first side of the first hole k11, or all can be electrically connected to the load module 50 through the dummy data signal line data' located on the second side of the first hole k11. This application embodiment does not limit this.

[0156] According to some embodiments of this application, optionally, the load module 50 may include a compensation capacitor. That is, by performing capacitance compensation on the target scan signal lines in the first region, the load magnitude of the target scan signal lines in the first region is the same as, similar to, or conforms to a certain gradual change pattern with the load magnitude of the target scan signal lines in the second region, thereby improving the display effect difference between the first region and the second region and enhancing the display effect.

[0157] Of course, in other embodiments, the load module 50 may also be an electronic device with impedance, such as a resistor or an inductor.

[0158] The following example uses the load module 50 as a compensation capacitor to illustrate the film structure of the array substrate.

[0159] Figure 22This is another partial cross-sectional schematic diagram of the array substrate provided in an embodiment of this application. For example... Figure 22 As shown, according to some embodiments of this application, optionally, the array substrate 40 may include a substrate 01, a first active layer b1 and a plurality of metal layers M stacked together.

[0160] The first plate c1 of the compensation capacitor C can be located in the first active layer b1. The first plate c1 of the compensation capacitor C is electrically connected to the first power supply voltage signal line PVDD through a via. The second plate c2 of the compensation capacitor C can be electrically connected to the dummy data signal line data' through a via.

[0161] Along the direction Z perpendicular to the plane of the array substrate, the metal layer where the second plate c2 of the compensation capacitor C is located can be located between the first active layer b1 and the metal layer where the first power supply voltage signal line PVDD is located.

[0162] In this way, by forming a compensation capacitor C through the first active layer b1 and the metal layer that is close to the first active layer b1, the capacitance value of the compensation capacitor C can be made larger, thereby forming a compensation capacitor C with a large capacitance value within a limited wiring space, which meets the load compensation requirements of the target scanning signal line.

[0163] See also Figure 22 In some specific embodiments, optionally, the plurality of metal layers M may include a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and a fifth metal layer M5 stacked together. It is readily understood that the array substrate 40 may include transistors and storage capacitors, with the gate of the transistor and the first electrode of the storage capacitor located on the first metal layer M1, the second electrode of the storage capacitor located on the second metal layer M2, and the source and drain of the transistor located on the third metal layer M3.

[0164] For example, the second plate c2 of the compensation capacitor C can be located in the first metal layer M1 or the second metal layer M2, and the dummy data signal line data' can be located in the fifth metal layer M5. The dummy data signal line data' can be electrically connected to the second plate c2 of the compensation capacitor C through a via. The first power supply voltage signal line PVDD can be located in the third metal layer M3, and the first power supply voltage signal line PVDD can be electrically connected to the first plate c1 of the compensation capacitor C in the first active layer b1 through a via. It should be noted that although the material of the first plate c1 of the compensation capacitor C and the active region (including the source region, drain region, and channel region) forming the transistor in the display area are located in the same film layer, the material of the first plate c1 of the compensation capacitor C and the active region forming the transistor in the display area are disconnected from each other and are not connected.

[0165] Figure 23 This is a partial planar schematic diagram of an array substrate provided in an embodiment of this application. (In conjunction with...) Figure 22 and Figure 23 As shown, according to some embodiments of this application, optionally, the array substrate may include multiple first power supply voltage signal lines PVDD extending along a first direction Y and spaced apart along a second direction X. The beginnings of the multiple first power supply voltage signal lines PVDD may be connected to each other, and the ends of the multiple first power supply voltage signal lines PVDD may also be connected to each other, thereby reducing the IR-drop of the first power supply voltage signal lines PVDD. The first electrode c1 of the compensation capacitor C may extend along the first direction Y and be electrically connected to the first power supply voltage signal lines PVDD through a via k2. The first electrode c1 of the compensation capacitor C may be located in the first active layer b1, and the first power supply voltage signal lines PVDD may be located in the third metal layer M3. The second electrode c2 of the compensation capacitor C may be C-shaped, S-shaped, or other multi-segment winding shapes. Specifically, for example, the second electrode c2 of the compensation capacitor C may include two opposing first extensions 231 and a second extension 232 for connecting the two first extensions 231, wherein the first extensions 231 may extend along the second direction X, and the second extensions 232 may extend along the first direction Y. The two opposing first extensions 231 can be parallel. The length of the first extension 231 can be greater than the length of the second extension 232.

[0166] The dummy data signal line data' located on the fifth metal layer M5 can be electrically connected to the second plate c2 of the compensation capacitor C located on the second metal layer M2 through a multi-layer via k3. The length of the first plate c1 of different compensation capacitors C can be the same, so by adjusting the length of the second plate c2 of the compensation capacitor C, the capacitance value of different compensation capacitors C can be made different.

[0167] Figure 24 This is another partial planar schematic diagram of the array substrate provided in an embodiment of this application. (In conjunction with...) Figure 22 and Figure 24 As shown, with Figure 23Unlike the illustrated embodiment, according to other embodiments of this application, optionally, multiple first power supply voltage signal lines PVDD can extend along the second direction X and be spaced apart along the first direction Y. The first plate c1 of the compensation capacitor C can extend along the second direction X and be electrically connected to the first power supply voltage signal lines PVDD through via k2. The first plate c1 of the compensation capacitor C can be located in the first active layer b1, and the first power supply voltage signal lines PVDD can be located in the third metal layer M3. The second plate c2 of the compensation capacitor C can be C-shaped. Specifically, for example, the second plate c2 of the compensation capacitor C can include two opposing first extensions 231 and a second extension 232 for connecting the two first extensions 231. The first extensions 231 can extend along the first direction Y, and the second extensions 232 can extend along the second direction X. The two opposing first extensions 231 can be parallel. The length of the first extension 231 can be greater than the length of the second extension 232.

[0168] The dummy data signal line data' located on the fifth metal layer M5 can be electrically connected to the second plate c2 of the compensation capacitor C located on the second metal layer M2 through via k3. The length of the first plate c1 of different compensation capacitors C can be the same, so by adjusting the length of the second plate c2 of the compensation capacitor C, the capacitance value of different compensation capacitors C can be made different.

[0169] It should be noted that, in combination Figure 15A and Figure 22 As shown, in the layout design of the pixel circuit in the display area, the storage capacitor Cst may include a first plate located on the first metal layer M1 and a second plate located on the second metal layer M2.

[0170] Based on the array substrate 40 provided in the above embodiments, this application also provides a display device, including the array substrate 40 provided in this application. Please refer to... Figure 25 , Figure 25 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 25 The provided display device 1000 includes the array substrate 40 provided in any of the above embodiments of this application. Figure 25 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and vehicle-mounted display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the array substrate 40 provided in the embodiments of this application. For details, please refer to the specific descriptions of the array substrate 40 in the above embodiments. These descriptions will not be repeated here.

[0171] It should be understood that the circuit structure and cross-sectional structure of the array substrate 40 provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0172] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

[0173] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes a transparent hole, a display area and a non-display area. The display area surrounds the transparent hole. The non-display area includes a first border area and a second border area. Along a first direction, the first border area, the display area and the second border area are arranged in sequence. The second border area is used to connect to a touch chip or a flexible circuit board. The first border area is provided with a load module. The display area includes: Multiple target scanning signal lines extending along a second direction and spaced apart along a first direction are provided. The target scanning signal lines are electrically connected to sub-pixels in the display area and are used to provide scanning signals to the sub-pixels. The first direction intersects the second direction. Multiple data signal lines and multiple dummy data signal lines extending along the first direction and spaced apart along the second direction; The display area includes a first area and a second area. Along the second direction, the first area is divided into at least two sub-areas by the transparent holes. The target scanning signal line in the first area is electrically connected to the load module in the first border area through the dummy data signal line. The virtual data signal line includes at least two disconnected trace segments. The trace segment closest to the first border area is the first trace segment. The target scan signal line in the first area is electrically connected to the load module in the first border area through the first trace segment.

2. The array substrate according to claim 1, characterized in that, The array substrate is provided with a light-emitting element, and the dummy data signal line and the anode of the light-emitting element are located in different film layers; Along a direction perpendicular to the plane of the array substrate, the break point of the dummy data signal line is located within the orthographic projection of the anode of the light-emitting element onto the array substrate.

3. The array substrate according to claim 2, characterized in that, The first trace segment of the i-th line extends to the anode of the light-emitting element within the orthographic projection of the array substrate, and then disconnects from other trace segments on the same straight line, where i is a positive integer.

4. The array substrate according to claim 1, characterized in that, At least a portion of the dummy data signal lines that are not connected to the target scan signal line and the data signal line are the target traces, and the target traces are electrically connected to the constant voltage signal line.

5. The array substrate according to claim 1, characterized in that, One of the sub-regions includes m1 target scan signal lines, and the m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, where m1 is a positive integer; The target scanning signal line from the first line to the m1th line is arranged sequentially along the first direction, and the m1th line is arranged sequentially along the second direction, with the m1th line located on the side of the first line near the transparent hole. The target scanning signal line from the first line to the m1th line are sequentially electrically connected to the dummy data signal line from the m1th line to the first line.

6. The array substrate according to claim 1, characterized in that, One of the sub-regions includes m1 target scan signal lines, and the m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, where m1 is a positive integer; The target scanning signal line from the first line to the m1th line is arranged sequentially along the first direction, and the m1th line is arranged sequentially along the second direction, with the first line located on the side of the m1th line closest to the transparent hole. The target scanning signal line from the first line to the m1th line are sequentially electrically connected to the dummy data signal line from the m1th line to the first line.

7. The array substrate according to claim 1, characterized in that, One of the sub-regions includes m1 target scan signal lines, and the m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, where m1 is a positive integer; The target scanning signal line from the first line to the m1th line is arranged sequentially along the first direction, and the m1th line is arranged sequentially along the second direction, with the m1th line located on the side of the first line near the transparent hole. The target scanning signal line from the first line to the j-th line is electrically connected to the virtual data signal line from the first line to the j-th line in turn, with 1 < j < m1 and j being an integer; The target scanning signal lines from j+1 to m1 are sequentially electrically connected to the dummy data signal lines from m1 to j+1.

8. The array substrate according to claim 1, characterized in that, One of the sub-regions includes m1 target scan signal lines, and the m1 target scan signal lines are electrically connected to m1 dummy data signal lines in a one-to-one correspondence, where m1 is a positive integer; The target scanning signal line from the first line to the m1th line is arranged sequentially along the first direction, and the m1th line is arranged sequentially along the second direction, with the m1th line located on the side of the first line near the transparent hole. The target scanning signal line from the first line to the jth line are connected one-to-one with the dummy data signal line from the m1th line to the m1-j+1th line, where 1 < j < m1 and j is an integer. The target scanning signal lines from the (j+1)th to the (m1)th target scanning signal lines are sequentially electrically connected to the dummy data signal lines from the first to the (j-1)th dummy data signal lines.

9. The array substrate according to claim 1, characterized in that, The array substrate includes a pixel circuit, the pixel circuit comprising: The driving module is used to drive the light-emitting element to emit light; A data writing module, wherein the control terminal of the data writing module is electrically connected to the first scan signal line, the first terminal of the data writing module is electrically connected to the data signal line, and the second terminal of the data writing module is electrically connected to the first terminal of the driving module, and the data writing module is used to turn on in response to the conduction level provided by the first scan signal line to write the data signal of the data signal line to the first terminal of the driving module; The target scan signal line includes the first scan signal line.

10. The array substrate according to claim 9, characterized in that, The pixel circuit also includes: A first reset module is configured to be electrically connected to a second scan signal line, a first terminal of the first reset module is electrically connected to a first reference voltage signal line, and a second terminal of the first reset module is electrically connected to the control terminal of the drive module. The first reset module is configured to be turned on in response to the conduction level provided by the second scan signal line, and to transmit the first reference voltage signal of the first reference voltage signal line to the control terminal of the drive module to reset the control terminal of the drive module. A threshold compensation module is provided, wherein the control terminal of the threshold compensation module is electrically connected to the third scan signal line, the first terminal of the threshold compensation module is electrically connected to the control terminal of the drive module, and the second terminal of the threshold compensation module is electrically connected to the second terminal of the drive module. The threshold compensation module is used to conduct in response to the conduction level provided by the third scan signal line, thereby connecting the control terminal of the drive module and the second terminal of the drive module. The target scan signal line also includes at least one of the second scan signal line and the third scan signal line.

11. The array substrate according to claim 1, characterized in that, The array substrate also includes a scan driving circuit, which includes multiple cascaded shift registers; One of the shift registers is electrically connected to the adjacent m-th target scan signal line and the (m+1)-th target scan signal line, where m is a positive integer; The m-th target scan signal line and the (m+1)-th target scan signal line in the first region are electrically connected to the load module in the first border region through the same dummy data signal line.

12. The array substrate according to claim 1, characterized in that, Along the second direction, the first region is divided into at least a first sub-region and a second sub-region by the transparent aperture; The number of sub-pixels connected to the z1th target scan signal line in the first sub-region is the same as the number of sub-pixels connected to the z2th target scan signal line in the first sub-region, where z1 and z2 are both positive integers; The first trace segment connected to the target scanning signal line described in the z1th clause is the first target trace segment, and the first trace segment connected to the target scanning signal line described in the z2th clause is the second target trace segment; Wherein, the length of the first target trace segment is greater than the length of the second target trace segment, and / or, the number of scan signal lines overlapping with the first target trace segment is greater than the number of scan signal lines overlapping with the second target trace segment; The resistance of the load module connected to the target scan signal line z1 is less than the resistance of the load module connected to the target scan signal line z2.

13. The array substrate according to claim 1, characterized in that, Along the second direction, the first region is divided into at least a first sub-region and a second sub-region by the transparent aperture; The first sub-region includes m1 target scanning signal lines, and the second sub-region includes m2 target scanning signal lines. The m1 target scanning signal lines extend to the first side edge of the transparent hole and terminate, and the m2 target scanning signal lines extend to the second side edge of the transparent hole and terminate. Both m1 and m2 are positive integers. m1 target scanning signal lines are electrically connected one-to-one with m1 dummy data signal lines located on the first side of the transparent hole, and m2 target scanning signal lines are electrically connected one-to-one with m2 dummy data signal lines located on the second side of the transparent hole.

14. The array substrate according to claim 1, characterized in that, Along the second direction, the first region is divided into a first sub-region and a second sub-region by the transparent aperture; The first sub-region includes m1 target scanning signal lines, which are wound around the edge of the transparent hole to the second sub-region, and are electrically connected to the sub-pixels in the second sub-region. Of the m1 target scanning signal lines, a portion of the target scanning signal lines are electrically connected to the load module via the dummy data signal line located on the first side of the transparent hole, and the other portion is electrically connected to the load module via the dummy data signal line located on the second side of the transparent hole.

15. The array substrate according to claim 1, characterized in that, The transparent hole includes a first hole and a second hole arranged at intervals along the second direction. The first region is divided into a first sub-region, a second sub-region and a third sub-region by the first hole and the second hole. The third sub-region is located between the first hole and the second hole. The first sub-region includes m1 target scanning signal lines, the second sub-region includes m2 target scanning signal lines, the m1 target scanning signal lines extend to the edge of the first hole and terminate, the m2 target scanning signal lines are wound around the edge of the second hole to the third sub-region, and the m2 target scanning signal lines are electrically connected to the sub-pixels in the third sub-region; The m1 target scanning signal lines are electrically connected one-to-one with the m1 dummy data signal lines located on the first side of the first hole, where the first side of the first hole is the side of the first hole away from the second hole. The m2 target scanning signal lines are electrically connected one-to-one with the m2 dummy data signal lines located on the second side of the first hole, where the second side of the first hole is the side of the first hole closer to the second hole.

16. The array substrate according to claim 15, characterized in that, The m2 target scanning signal lines are electrically connected one-to-one with the m2 virtual data signal lines located between the first hole and the second hole; Alternatively, of the m2 target scanning signal lines, a portion of the target scanning signal lines are electrically connected to the dummy data signal lines located between the first hole and the second hole, and another portion of the target scanning signal lines are electrically connected to the dummy data signal lines located on the second side of the second hole, where the second side of the second hole is the side of the second hole away from the first hole.

17. The array substrate according to claim 1, characterized in that, The transparent hole includes a first hole and a second hole arranged at intervals along the second direction. The first region is divided into a first sub-region, a second sub-region and a third sub-region by the first hole and the second hole. The third sub-region is located between the first hole and the second hole. The first sub-region includes m1 target scanning signal lines, which are sequentially wound around the edges of the first hole and the second hole to the third sub-region and the second sub-region, and are electrically connected to the sub-pixels in the third sub-region and the sub-pixels in the second sub-region. Of the m1 target scanning signal lines, a portion of the target scanning signal lines are electrically connected to the load module via the dummy data signal line located on the first side of the first hole, and another portion are electrically connected to the load module via the dummy data signal line located on the second side of the first hole. The first side of the first hole is the side of the first hole away from the second hole, and the second side of the first hole is the side of the first hole closer to the second hole.

18. The array substrate according to claim 1, characterized in that, The load module includes a compensation capacitor.

19. The array substrate according to claim 18, characterized in that, The array substrate includes a substrate, a first active layer and multiple metal layers stacked together. The first plate of the compensation capacitor is located in the first active layer. The first plate of the compensation capacitor is electrically connected to the first power supply voltage signal line through a via. The second plate of the compensation capacitor is electrically connected to the dummy data signal line through a via. Along a direction perpendicular to the plane of the array substrate, the metal layer containing the second electrode of the compensation capacitor is located between the first active layer and the metal layer containing the first power supply voltage signal line.

20. The array substrate according to claim 19, characterized in that, The plurality of metal layers include a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, and a fifth metal layer stacked together; The second plate of the compensation capacitor is located on the first metal layer or the second metal layer, and the first power supply voltage signal line is located on the third metal layer. The array substrate includes transistors and storage capacitors. The gate of the transistor and the first plate of the storage capacitor are located in the first metal layer, the second plate of the storage capacitor is located in the second metal layer, and the source and drain of the transistor are located in the third metal layer.

21. A display device, characterized in that, Includes the array substrate as described in any one of claims 1 to 20.

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