An ultra-low power consumption ultra-wideband low noise amplifier

Abstract

An ultra-low power, ultra-wideband, low-noise amplifier includes an input stage amplifier and an output stage amplifier connected in sequence. The input stage amplifier consists of an input matching network, a MOS feedback common-source structure, and a cascaded matching network. The output stage amplifier consists of a resonant inductor, a MOS feedback common-source structure, and an output matching network. Through this method, the present invention can significantly reduce the power consumption of the amplifier while maintaining performance such as gain and noise through power optimization techniques. Furthermore, it optimizes noise reduction techniques to lower the noise figure and uses interleaved tuning techniques to achieve wideband flat gain.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit design technology, and specifically to an ultra-low power, ultra-wideband, low-noise amplifier. Background Technology

[0002] With the number of wireless communication standards growing at an astonishing rate, the demand for multi-band, multi-functional radio frequency transceivers in a single terminal is increasing. Ultra-wideband (UWB) technology, as a wireless communication technology with numerous advantages, is playing an increasingly important role. Especially in recent years, the development of portable devices and wireless sensor networks, such as Xiaomi's "One-Touch Connect" feature, has made power consumption a growing concern.

[0003] The low-noise amplifier (LNO) is the first active device in the receiving channel, typically connected directly to the receiving antenna, and plays a decisive role in the overall noise of the receiver. To reduce the impact of noise in subsequent stages of the receiver, the LNO needs to provide sufficiently high gain while also having a sufficiently low noise figure. Furthermore, the LNO requires input matching. Power consumption is also critical for the LNO; achieving wideband matching, low noise, high gain, and good linearity all necessitate high power consumption.

[0004] How to balance the low power consumption and flat gain of ultra-wideband low-noise amplifiers, and further, how to effectively reduce the noise figure of ultra-wideband low-noise amplifiers, are questions that urgently require more, more flexible, and better solutions. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention aims to provide an ultra-low power, ultra-wideband, low-noise amplifier that can significantly reduce the power consumption of the amplifier while ensuring performance such as gain and noise through power optimization technology. On the other hand, it optimizes noise reduction technology to reduce the noise figure and uses interleaved tuning technology to obtain wideband flat gain.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] An ultra-low power, ultra-wideband, low-noise amplifier includes an input stage amplifier (100) and an output stage amplifier (200) connected in sequence. The input stage amplifier (100) comprises an input matching network consisting of a first capacitor (101), a first inductor (102), and a second inductor (103); a MOS feedback common-source structure consisting of a first transistor (104), a second transistor (105), and a third transistor (106); and an interstage matching network consisting of a third inductor (107) and a second capacitor (108). The output stage amplifier (200) comprises a fourth inductor (201), a MOS feedback common-source structure consisting of a fourth transistor (202), a fifth transistor (203), and a sixth transistor (204); and an output matching network consisting of a fifth inductor (205) and a third capacitor (206). Both the input stage amplifier (100) and the output stage amplifier (200) are single-layer MOS transistor architectures.

[0008] In the input stage amplifier (100), the first transistor (104) adopts a common-source structure; the source of the second transistor (105) is connected to the gate of the first transistor (104), and the drain of the second transistor (105) is connected to the drain of the first transistor (104), with its gate voltage being a separate bias voltage; the source of the third transistor (106) is connected to the substrate of the first transistor (104), and the drain of the third transistor (106) is connected to the source of the first transistor (104), with its gate connected to ground; one end of the first capacitor (101) is connected to the input terminal, and the other end of the first capacitor (101) is connected to the input terminal. One end of the first inductor (102) is connected to one end of the first inductor (102); the other end of the first inductor (102) is connected to the gate of the first transistor (104); one end of the second inductor (103) is connected to the source of the first transistor (104), and the other end of the second inductor (103) is connected to ground; one end of the third inductor (107) is connected to the drain of the first transistor (104), and the other end of the third inductor (107) is connected to the power supply voltage; one end of the second capacitor (108) is connected to the drain of the first transistor (104), and the other end of the second capacitor (108) is connected to the fourth inductor (201).

[0009] In the output stage amplifier (200), the fourth transistor (202) adopts a common-source structure; the source of the fifth transistor (203) is connected to the second capacitor (108), and the drain of the fifth transistor (203) is connected to the drain of the fourth transistor (202), with its gate voltage being a separate bias voltage; the source of the sixth transistor (204) is connected to the substrate of the fourth transistor (202), and the drain of the sixth transistor (204) is connected to the source of the fourth transistor (202), with its gate voltage being a separate bias voltage; The gate is connected to ground; one end of the fourth inductor (201) is connected to the second capacitor (108), and the other end of the fourth inductor (201) is connected to the gate of the fourth transistor (202); one end of the fifth inductor (205) is connected to the drain of the fourth transistor (202), and the other end of the fifth inductor (205) is connected to the power supply voltage; one end of the third capacitor (206) is connected to the drain of the fourth transistor (202), and the other end of the third capacitor (206) is connected to the output terminal.

[0010] The first inductor (102), the third inductor (107) and the fourth inductor (201) form an interleaved tuning technique to alleviate the high-frequency gain drop caused by the second inductor (103) and obtain broadband flat gain and broadband matching.

[0011] The substrates of the second transistor (105), the third transistor (106), the fifth transistor (203), and the sixth transistor (204) are grounded.

[0012] The gates of the third transistor (106) and the sixth transistor (204) are grounded.

[0013] The beneficial results of this invention are:

[0014] First, this invention proposes a single-layer MOS architecture that effectively reduces power consumption while maintaining the RF performance of low-noise amplifiers, such as gain and noise.

[0015] Second, this invention proposes a noise reduction structure that reduces noise and further reduces power consumption by alleviating the design pressure of power optimization technology;

[0016] Third, this invention proposes a negative feedback structure, which expands the bandwidth of the common source structure;

[0017] Fourth, this invention proposes an interleaved tuning technique that uses the resonance of inductance and parasitic capacitance at different frequency points to alleviate the high-frequency gain drop caused by the second inductor, thereby obtaining broadband flat gain and broadband matching. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit structure of an ultra-low power ultra-wideband low noise amplifier according to the present invention.

[0019] Figure 2 This is the bias voltage scan result of the single common-source amplifier of the present invention;

[0020] Figure 3 This is the power supply voltage scan result of the single common-source amplifier of the present invention;

[0021] Figure 4 This is a noise reduction architecture of the present invention;

[0022] Figure 5 This is a test result of a noise reduction architecture according to the present invention;

[0023] Figure 6 This is a simulation result of the gain of an ultra-low power ultra-wideband low noise amplifier according to the present invention;

[0024] Figure 7 This is a simulation result of the noise figure of an ultra-low power, ultra-wideband, low-noise amplifier according to the present invention. Detailed Implementation

[0025] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the drawings.

[0026] The embodiments of the present invention shown in and described with reference to the accompanying drawings are merely exemplary, and the present invention is not limited to these embodiments. It should also be noted that, to avoid obscuring the present invention with unnecessary detail, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the drawings, while other details not closely related to the present invention are omitted. Furthermore, in the description of the present invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] like Figure 1 As shown, the ultra-low power ultra-wideband low noise amplifier provided by the present invention includes an input stage amplifier 100 and an output stage amplifier 200 connected in sequence.

[0028] This invention comprises a two-stage amplifier, with both the input and output stages employing a common-source architecture. The input stage amplifier 100 and the output stage amplifier 200 utilize a single-layer MOS architecture. For the single-stage common-source amplifier, power optimization techniques are used to select the bias voltage and supply voltage, such as... Figure 2, 3 As shown, due to the optimization of noise reduction technology, a lower power supply voltage can be selected, which improves power gain efficiency and reduces the power consumption of the present invention.

[0029] The input stage amplifier 100 of this invention has a common-source structure. MOS negative feedback is used to extend the bandwidth of the common-source stage and achieve lower noise than resistive feedback. A noise reduction structure is used to reduce noise. The input impedance matching consists of a first capacitor 101, a first inductor 102, and a second inductor 103, matched to a 50-ohm single-ended antenna, achieving a trade-off between gain and noise. The MOS feedback common-source structure consists of a first transistor 104, a second transistor 105, and a third transistor 106. The first transistor 104 uses a common-source structure, which has advantages such as low noise figure and high gain efficiency. The second transistor 105 is a feedback structure that extends the bandwidth of the common-source stage and provides a lower noise figure than resistive negative feedback. The third transistor 106 is a noise reduction structure used to reduce the noise figure. The inter-stage matching network consists of a third inductor 107 and a second capacitor 108, realizing cascade matching between the first-stage amplifier and the second-stage amplifier, improving gain.

[0030] The output stage amplifier 200 of this invention has a common-source structure. MOS negative feedback is used to extend the bandwidth of the common-source stage and achieve lower noise than resistive feedback. A noise reduction structure is used to reduce noise. The resonant inductor, the fourth inductor 201, is located within the feedback loop, improving the transconductance and effective transconductance bandwidth of the output stage amplifier.

[0031] The MOS feedback common-source structure consists of the fourth transistor 202, the fifth transistor 203 and the sixth transistor 204. The fourth transistor 202 adopts a common-source structure. Common-source transistors have the advantages of low noise figure and high gain efficiency.

[0032] The fifth transistor 203 is a feedback structure that extends the bandwidth of the common-source stage and provides a lower noise figure than resistive negative feedback; the sixth transistor 204 is a noise reduction structure used to reduce the noise figure. The output matching network consists of the fifth inductor 205 and the third capacitor 206 to ensure maximum output power and achieve the largest possible gain.

[0033] The interleaved tuning technique of the present invention consists of a first inductor 102, a third inductor 107 and a fourth inductor 201. The first inductor 102 resonates with the gate equivalent capacitance of the first transistor 104 at a high frequency, while the third inductor 107 and the fourth inductor 201 resonate with the drain equivalent capacitance of the first transistor 104 and the gate equivalent capacitance of the fourth transistor 202 at a low frequency, respectively, thereby mitigating the high-frequency gain drop caused by the second inductor (103) and obtaining broadband flat gain and broadband matching.

[0034] Figure 4A specific implementation of the noise reduction structure is given. A MOS transistor M2 is connected between the source and substrate of the amplifier transistor M1. The noise reduction level is optimal when the gate voltage of the MOS transistor reaches the threshold voltage, but the difference from gate grounding is small. To optimize the circuit design, the gate is grounded.

[0035] like Figure 5 As shown, the labels all refer to the connection module between the source and the substrate. Compared with the noise reduction structure of the traditional source and substrate connection resistor, the noise reduction level has been greatly improved.

[0036] This invention discloses an ultra-low power, ultra-wideband, low-noise amplifier operating in the 5-9 GHz frequency band. It should be noted that the operating frequency band of the embodiment is merely an example and not a limitation on specific operating frequencies. In actual design, this invention can be applied to different frequency bands.

[0037] The ultra-low power, ultra-wideband, low-noise amplifier of this invention relates to application areas including indoor positioning technology, multi-functional antennas, and the Internet of Things. This invention proposes a single-layer MOS architecture that effectively reduces DC power consumption while maintaining the RF performance of the low-noise amplifier, including gain and noise levels. This invention also proposes a noise reduction structure that reduces noise and further optimizes DC power consumption.

[0038] This invention proposes an interleaved tuning technique that uses the resonance of inductors and parasitic capacitances at different frequencies to mitigate the high-frequency gain drop caused by the second inductor, achieving broadband flat gain and broadband matching. This invention also proposes a negative feedback structure to extend the bandwidth of the common-source structure. Based on the above-mentioned techniques, this invention ultimately realizes an ultra-low power, low noise figure, and wide bandwidth low-noise amplifier.

[0039] The ultra-low power, ultra-wideband, low-noise amplifier has a power supply voltage of 0.2V and consumes 0.56mW of power.

[0040] Figure 6 These are simulation results of the gain of an ultra-low power, ultra-wideband, low-noise amplifier. This low-noise amplifier achieves a maximum gain of 14.6 dB at 5 GHz. A 3 dB gain is achieved across the 5-9 GHz range.

[0041] Figure 7 These are simulation results of the noise figure of an ultra-low power, ultra-wideband, low-noise amplifier. This low-noise amplifier achieves a minimum noise figure of 2.59 dB at 7.5 GHz, and a noise figure of less than 3 dB in the 5-9 GHz range.

Claims

1. An ultra-low power, ultra-wideband, low-noise amplifier, comprising an input stage amplifier (100) and an output stage amplifier (200) connected in sequence, characterized in that, The input stage amplifier (100) includes an input matching network composed of a first capacitor (101), a first inductor (102), and a second inductor (103), a MOS feedback common-source structure composed of a first transistor (104), a second transistor (105), and a third transistor (106), and an interstage matching network composed of a third inductor (107) and a second capacitor (108); the output stage amplifier (200) includes a MOS feedback common-source structure composed of a fourth inductor (201), a fourth transistor (202), a fifth transistor (203), and a sixth transistor (204), and an output matching network composed of a fifth inductor (205) and a third capacitor (206); the input stage amplifier (100) and the output stage amplifier (200) are single-layer MOS transistor architectures; In the input stage amplifier (100), the first transistor (104) adopts a common-source structure; the source of the second transistor (105) is connected to the gate of the first transistor (104), and the drain of the second transistor (105) is connected to the drain of the first transistor (104), with its gate voltage being a separate bias voltage; the source of the third transistor (106) is connected to the substrate of the first transistor (104), and the drain of the third transistor (106) is connected to the source of the first transistor (104), with its gate connected to ground; one end of the first capacitor (101) is connected to the input terminal, and the other end of the first capacitor (101) is connected to the input terminal. One end of the first inductor (102) is connected to one end of the first inductor (102); the other end of the first inductor (102) is connected to the gate of the first transistor (104); one end of the second inductor (103) is connected to the source of the first transistor (104), and the other end of the second inductor (103) is connected to ground; one end of the third inductor (107) is connected to the drain of the first transistor (104), and the other end of the third inductor (107) is connected to the power supply voltage; one end of the second capacitor (108) is connected to the drain of the first transistor (104), and the other end of the second capacitor (108) is connected to the fourth inductor (201); In the output stage amplifier (200), the fourth transistor (202) adopts a common-source structure; the source of the fifth transistor (203) is connected to the second capacitor (108), and the drain of the fifth transistor (203) is connected to the drain of the fourth transistor (202), with its gate voltage being a separate bias voltage; the source of the sixth transistor (204) is connected to the substrate of the fourth transistor (202), and the drain of the sixth transistor (204) is connected to the source of the fourth transistor (202), with its gate voltage being a separate bias voltage; The gate is connected to ground; one end of the fourth inductor (201) is connected to the second capacitor (108), and the other end of the fourth inductor (201) is connected to the gate of the fourth transistor (202); one end of the fifth inductor (205) is connected to the drain of the fourth transistor (202), and the other end of the fifth inductor (205) is connected to the power supply voltage; one end of the third capacitor (206) is connected to the drain of the fourth transistor (202), and the other end of the third capacitor (206) is connected to the output terminal.

2. The ultra-low power, ultra-wideband, low-noise amplifier according to claim 1, characterized in that, The first inductor (102), the third inductor (107) and the fourth inductor (201) form an interleaved tuning technique to alleviate the high-frequency gain drop caused by the second inductor (103) and obtain broadband flat gain and broadband matching.

3. The ultra-low power, ultra-wideband, low-noise amplifier according to claim 1, characterized in that, The substrates of the second transistor (105), the third transistor (106), the fifth transistor (203), and the sixth transistor (204) are grounded.

4. The ultra-low power, ultra-wideband, low-noise amplifier according to claim 1, characterized in that, The gates of the third transistor (106) and the sixth transistor (204) are grounded.

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