Display substrate and display device

Abstract

A display substrate and a display device, comprising: a base substrate (101), the base substrate (101) comprising: a display area (AA), and a binding area (BA) located on one side of the display area (AA); a plurality of gate lines (102), extending in the display area (AA) along a first direction (X) and arranged along a second direction (Y), wherein the first direction (X) and the second direction (Y) are arranged crosswise; a plurality of data lines (103), arranged in a different layer from the plurality of gate lines (102), and the plurality of data lines (103) extending in the display area (AA) along the second direction (Y) and arranged along the first direction (X); a plurality of lead lines 104 are arranged in different layers from the plurality of gate lines (102) and the plurality of data lines (103); the plurality of lead lines (104) extend from the display area (AA) along the second direction (Y) to the binding area (BA); each of the plurality of lead lines (104) is electrically connected to each of the plurality of data lines (103); each lead line (104) includes a first section (1041) extending along the second direction (Y); and the orthographic projection of at least part of the first section (1041) on the substrate (101) does not overlap with the orthographic projection of the data line (103).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] As the technology of the display industry becomes more and more mature, the application scenarios of display devices become more and more complex. Regular-shaped display devices can no longer meet the usage requirements. Therefore, special-shaped display devices are gradually coming into people's field of vision. Summary of the invention

[0003] The present disclosure provides a display substrate and a display device, and the specific scheme is as follows:

[0004] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0005] A base substrate, the base substrate comprising: a display area, and a binding area located on one side of the display area;

[0006] A plurality of gate lines extending along a first direction and arranged along a second direction in the display area, wherein the first direction is arranged to intersect with the second direction;

[0007] a plurality of data lines, which are arranged in different layers from the plurality of gate lines, and the plurality of data lines extend along the second direction in the display area and are arranged along the first direction;

[0008] A plurality of leads are arranged in different layers from the plurality of gate lines and the plurality of data lines, the plurality of leads extend from the display area along the second direction to the binding area, each of the plurality of leads is electrically connected to each of the plurality of data lines respectively, each of the lead lines comprises a first section extending along the second direction, and an orthographic projection of at least part of the first section on the substrate does not overlap with an orthographic projection of the data line.

[0009] Optionally, in the above-mentioned display substrate provided by an embodiment of the present disclosure, the plurality of leads are symmetrically arranged about a central axis of the display area in the second direction.

[0010] Optionally, in the above-mentioned display substrate provided by an embodiment of the present disclosure, the lead adjacent to the central axis of the display area in the second direction includes the first sub-portion;

[0011] The lead away from the central axis of the display area in the second direction includes: the first section, and a second section extending along the first direction in the middle area of ​​the display area, and at least part of the second section's orthographic projection on the substrate does not overlap with the orthographic projection of the gate line.

[0012] Optionally, the display substrate provided in the embodiment of the present disclosure further includes: a plurality of pixel units arranged in an array; and within any row gap of the pixel units, the first spacing between two adjacent second divisions is equal.

[0013] Optionally, in the above-mentioned display substrate provided by an embodiment of the present disclosure, the lengths of the second sub-portions sequentially arranged in a direction from the display area to the binding area gradually increase.

[0014] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, each of the lead lines further includes: a third section extending along the first direction in the edge area of ​​the display area, the orthographic projection of the third section on the base substrate and the orthographic projection of the gate line do not overlap with each other, and the third section is electrically connected to the corresponding data line.

[0015] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, the first section of the lead away from the central axis of the display area in the second direction includes: a first sub-section and a second sub-section; wherein,

[0016] The first end of the first sub-division is electrically connected to the third sub-division, and the second end of the first sub-division is electrically connected to the first end of the second sub-division adjacent to the boundary of the display area;

[0017] The first end of the second sub-division is electrically connected to the second end of the second sub-division away from the boundary of the display area, and the second end of the second sub-division is located in the binding area;

[0018] In the first direction, a maximum distance between all of the first subdivisions is greater than a maximum distance between all of the second subdivisions.

[0019] Optionally, in the display substrate provided by the embodiment of the present disclosure, every two adjacent data lines form a data line group, every three adjacent data line groups form a cycle, and the three data groups in one cycle are a first data group, a second data group and a third data group arranged in sequence in the first direction;

[0020] The two first sub-divisions electrically connected to the two data lines in the first data group are located on both sides of the first data group, the two first sub-divisions electrically connected to the two data lines in the second data group are located in the gap between the first data group and the second data group, and the two first sub-divisions electrically connected to the two data lines in the third data group are located on a side of the third data group away from the second data group.

[0021] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, the larger the distance between the first sub-division and the central axis of the display area in the second direction, the smaller the length of the first sub-division.

[0022] Optionally, in the above-mentioned display substrate provided by the embodiment of the present disclosure, one end of the lead wire away from the binding area is electrically connected to one end of the corresponding data line away from the binding area.

[0023] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it further includes: a plurality of pixel driving circuits located in the area defined by the plurality of gate lines and the plurality of data lines, each of the pixel driving circuits including a driving transistor and a storage capacitor; wherein,

[0024] The first electrode of the storage capacitor is reused as the gate of the driving transistor, the second electrode of the storage capacitor is located between the layer where the gate of the driving transistor is located and the layer where the data line is located, and the orthographic projection of at least part of the lead on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate.

[0025] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the ratio of the overlapping area of ​​the orthographic projection of the lead on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate to the area of ​​the gate of the driving transistor is less than 1 / 3.

[0026] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it further includes: a plurality of pixel driving circuits located in the area defined by the plurality of gate lines and the plurality of data lines, each of the pixel driving circuits including a driving transistor;

[0027] The orthographic projection of the lead on the base substrate does not overlap with the orthographic projection of the gate of the driving transistor on the base substrate.

[0028] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it further includes: an organic insulating layer located between the layer where the plurality of data lines are located and the layer where the plurality of lead lines are located;

[0029] Each of the lead lines is electrically connected to the corresponding data line through a first via hole penetrating the organic insulating layer.

[0030] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it further includes: an inorganic insulating layer located between the organic insulating layer and the layer where the plurality of leads are located;

[0031] Each of the lead lines is electrically connected to the corresponding data line through a second via hole penetrating the inorganic insulating layer, and the first via hole and the second via hole corresponding to each of the lead lines are connected.

[0032] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, it further includes: a plurality of light-emitting devices located on a side of the plurality of leads away from the base substrate;

[0033] The plurality of light emitting devices constitute a plurality of light emitting device columns extending in the second direction. The greater the distance between the light emitting device column and the central axis of the display area in the second direction, the smaller the number of light emitting devices contained in the light emitting device column.

[0034] On the other hand, an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.

[0035] Optionally, the display device provided in the embodiment of the present disclosure further includes: a source driver chip, wherein the source driver chip includes a plurality of signal channels;

[0036] The plurality of signal channels are electrically connected to the plurality of leads in the binding area in a one-to-one correspondence, and in the first direction, a total width of the plurality of leads in the binding area is equal to a total width of the plurality of signal channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural schematic diagram of a display substrate in the related art;

[0038] Figure 2 A schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0039] Figure 3 A schematic diagram of another structure of a display substrate provided in an embodiment of the present disclosure;

[0040] Figure 4 A schematic diagram of wiring of data lines and leads provided in an embodiment of the present disclosure;

[0041] Figure 5 A schematic diagram of wiring of gate lines and leads provided in an embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0043] Figure 7 for Figure 6 The layout of the pixel driving circuit shown;

[0044] Figure 8 for Figure 7 The layout of the active layer in the pixel driving circuit shown;

[0045] Fig. 9 for Figure 7The layout of the first gate metal layer in the pixel driving circuit shown;

[0046] Fig.10 for Figure 7 The layout of the second gate metal layer in the pixel driving circuit shown;

[0047] Fig.11 for Figure 7 The layout of the first source-drain metal layer in the pixel driving circuit shown;

[0048] Fig.12 for Figure 7 The layout of the second source-drain metal layer in the pixel driving circuit shown;

[0049] Fig.13 for Figure 7 The working timing diagram of the pixel driving circuit shown;

[0050] Fig.14 A diagram showing a relative position relationship between a gate electrode, a storage capacitor and a lead wire of a driving transistor in a pixel driving circuit provided by an embodiment of the present disclosure;

[0051] Fig.15 A schematic diagram of another structure of a display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0052] In order to make the purpose, technical solution and advantages of the embodiment of the present disclosure clearer, the technical solution of the embodiment of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiment of the present disclosure. It should be noted that the size and shape of the figures in the drawings do not reflect the actual proportion, and the purpose is only to illustrate the content of the present invention. And the same or similar numbers throughout represent the same or similar elements or elements with the same or similar functions. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0053] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0054] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0055] In the related art, relatively mature special-shaped display devices include round watches, "bangs" mobile phone screens, etc., which are relatively small in size or close in shape to traditional rectangular screens. Therefore, the fan-out line (Fan-out line) connecting the source driver chip (Source IC) and the data line (DL) contained in the special-shaped display area (AA) will not occupy too large a border; while for special-shaped screens with larger size, higher resolution, and more "strange" shapes such as round, elliptical, and heart-shaped, the fan-out line is designed in the traditional way, and the border area FA required is larger.

[0056] In the related art, the special-shaped display device generally uses the source-drain metal layer to make the fan-out wiring located in the frame area FA. Figure 1 As shown, the data line (DL) of the source-drain metal layer is electrically connected to the source driver chip through a fan-out wiring that is provided in the same layer and arranged in a fan-shaped manner in the frame area FA, occupying a larger frame area FA.

[0057] In view of the above technical problems existing in the related art, the present disclosure provides a display substrate, such as Figures 2 to 4 As shown, including:

[0058] A base substrate 101, the base substrate 101 comprises: a display area AA, and a binding area BA located at one side of the display area AA;

[0059] A plurality of gate lines 102 extend along a first direction X and are arranged along a second direction Y in the display area AA, wherein the first direction X and the second direction Y are intersectingly arranged;

[0060] A plurality of data lines 103 are arranged in different layers from the plurality of gate lines 102, and the plurality of data lines 103 extend along the second direction Y in the display area AA and are arranged along the first direction X;

[0061] The plurality of lead lines 104 are arranged in different layers from the plurality of gate lines (GL) 102 and the plurality of data lines 103. The plurality of lead lines 104 extend from the display area AA along the second direction Y to the binding area BA. Each of the plurality of lead lines 104 is electrically connected to each of the plurality of data lines 103. Each lead line 104 includes a first section 1041 extending along the second direction Y, and the orthographic projection of at least part of the first section 1041 on the base substrate 101 does not overlap with the orthographic projection of the data line 103. In some embodiments, the orthographic projection of all the first sections 1041 on the base substrate 101 does not overlap with the orthographic projection of the data line 103.

[0062] Combination Figures 1 to 3 It can be seen that in the display substrate provided by the embodiment of the present disclosure, a layer of leads 104 for providing grayscale signals for the data lines 103 is separately arranged, and the leads 104 are designed to extend from the display area AA along the second direction Y to the binding area BA, so that only the binding area BA on the lower side around the display area AA has the leads 104, while the fan-shaped fan-out lines in the related art are distributed in the fan-out areas FA on the left, right and lower sides around the display area AA. By comparison, it can be seen that the wiring scheme of the above-mentioned leads 104 provided by the present disclosure can eliminate the left and right borders, and the binding area BA (that is, the distance from the lower end of the display area AA to the source driver chip) is also very, very small. Therefore, the border of the display substrate is effectively reduced, and a higher screen-to-body ratio is achieved.

[0063] In addition, the data line 103 and the lead 104 are both used to transmit grayscale signals. When the grayscale signals provided by the data line 103 and the lead 104 are different, the resistance and capacitance on the two will affect the normal transmission of each other's grayscale signals, that is, it will cause the delay (RC delay) problem of the grayscale signal, and even cause the transmission distortion of the grayscale signal. By setting the orthographic projection of the first section 1041 included in the lead 104 on the base substrate 101 not to overlap with the orthographic projection of the data line 103, the parallel overlap of the data line 103 and the first section 1041 included in the lead 104 can be completely avoided, thereby avoiding the coupling capacitance between the data line 103 and the lead 104, and solving the problem of mutual interference of grayscale signals on the data line 103 and the lead 104.

[0064] It should be noted that in the present disclosure, the display area AA may be a conventional display area AA such as a right-angled rectangle or a rounded rectangle, or may be a special-shaped display area AA such as a circle, an ellipse, a sector, a heart shape, or a polygon, and no specific limitation is made here. The following description is based on the display area AA being a special-shaped display area AA, and when the shape of the special-shaped display area AA is composed of continuous arcs (such as a circle, an ellipse, a heart shape, etc.), one side of the special-shaped display area AA may specifically refer to one side of the middle area of ​​the special-shaped display area AA extending along the second direction Y; when the shape of the special-shaped display area AA is composed of multiple line segments (such as a polygon, etc.), one side of the special-shaped display area AA may specifically refer to the side of the line segments substantially perpendicular to the second direction Y contained in the special-shaped display area AA.

[0065] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, the plurality of lead lines 104 can be symmetrically arranged about the central axis MN of the special-shaped display area AA in the second direction Y. In this way, the wiring lengths of the lead lines 104 can be made equal, that is, the resistance values ​​of the lead lines 104 are almost the same, thereby ensuring that the efficiency of each lead line 104 in transmitting grayscale signals is equal, thereby improving the display effect.

[0066] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, the lead 104 adjacent to the central axis MN of the special-shaped display area AA in the second direction Y includes a first sub-portion 1041; the lead 104 away from the central axis MN of the special-shaped display area AA in the second direction Y may include: the first sub-portion 1041, and a second sub-portion 1042 extending in the middle area of ​​the special-shaped display area AA along the first direction X, and the orthographic projection of at least part of the second sub-portion 1042 on the base substrate 101 does not overlap with the orthographic projection of the gate line 102. In some embodiments, the orthographic projection of all the second sub-portions 1042 on the base substrate 101 does not overlap with the orthographic projection of the gate line 102.

[0067] By setting the lead 104 adjacent to the central axis MN of the special-shaped display area AA in the second direction Y to include only the first subsection extending in the second direction Y, the lead 104 adjacent to the central axis MN of the special-shaped display area AA in the second direction Y can be directly extended to the binding area BA on one side of the special-shaped display area AA; and by setting the lead 104 away from the central axis MN of the special-shaped display area AA in the second direction Y to be composed of the second subsection 1042 extending in the first direction X and the first subsection 1041 extending in the second direction Y, the lead 104 away from the central axis MN of the special-shaped display area AA in the second direction Y can be bent and routed in the special-shaped display area AA, and then extend to the binding area BA on one side of the special-shaped display area AA along the second direction Y. Based on this, it is effectively ensured that the frame where the binding area BA is located is relatively narrow.

[0068] In addition, by arranging the orthographic projection of the second section 1042 on the base substrate 101 to not overlap with the orthographic projection of the gate line 102 , the parasitic capacitance between the lead line 104 and the gate line 102 is effectively reduced, thereby avoiding mutual interference between the grayscale signal on the lead line 104 and the scanning signal on the gate line 102 .

[0069] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 5 As shown, it also includes: a plurality of pixel units P arranged in an array, each pixel unit P may include a pixel driving circuit and a light emitting device EL electrically connected to the pixel driving circuit, wherein the pixel driving circuit may include Figure 6 In some embodiments, two upper and lower adjacent pixel driving circuits can share a fourth switch transistor T4, so that the two upper and lower adjacent pixel driving circuits constitute a 9T2C circuit including nine transistors and two capacitors; for ease of manufacturing, in any row gap of the pixel unit P, the first spacing between two adjacent second divisions 1042 can be set to be equal.

[0070] In some embodiments, Figure 5 As shown in FIG. 1 , a plurality of second sub-sections 1042 may be arranged in the row gap between two adjacent rows of pixel units P. In this case, the first spacing between adjacent second sub-sections 1042 may divide the row gap between two adjacent rows of pixel units P into n equal parts, wherein n is the total number of second sub-sections 1042 arranged in the row gap between two adjacent rows of pixel units P. Of course, in the case of a lower resolution of the display device, the first spacing between adjacent second sub-sections 1042 may also be greater than or equal to the row gap between two adjacent rows of pixel units P, such as Figure 3 shown.

[0071] Optionally, in the display substrate provided in the embodiment of the present disclosure, in order to ensure that no cross short circuit occurs between the leads 104, as shown in FIG. Figure 2 and Figure 3 As shown, the lengths of the second sub-portions 1042 sequentially arranged in a direction from the special-shaped display area AA to the binding area BA may be gradually increased.

[0072] In other words, the closer the second sub-portion 1042 is to the binding area BA, the longer the second sub-portion 1042 is. Furthermore, considering that the lead 104 having the second sub-portion 1042 is farther from the central axis MN of the special-shaped display area AA in the second direction Y, in order to ensure that the second sub-portion 1042 is located in the special-shaped display area AA, the maximum length of the second sub-portion 1042 needs to be less than half of the maximum width of the special-shaped display area AA in the first direction X.

[0073] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, each lead 104 may further include: a third portion 1043 extending along the first direction X at the edge of the special-shaped display area AA, the orthographic projection of the third portion 1043 on the base substrate 101 does not overlap with the orthographic projection of the gate line 102, and the third portion 1043 is electrically connected to the corresponding data line 103.

[0074] By arranging the third section 1043 extending along the first direction X at the edge of the special-shaped display area AA, it is possible to ensure that the wiring of the third section 1043 is relatively short. In addition, by arranging that the orthographic projection of the third section 1043 on the base substrate 101 does not overlap with the orthographic projection of the gate line 102, the parasitic capacitance between the lead line 104 and the gate line 102 is effectively reduced, and the mutual interference between the grayscale signal on the lead line 104 and the scanning signal on the gate line 102 is avoided.

[0075] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, the first division 1041 of the lead 104 away from the central axis MN of the special-shaped display area AA in the second direction Y includes: a first sub-division 1041a and a second sub-division 1041b; wherein, the first end of the first sub-division 1041a is electrically connected to the third division 1043, and the second end of the first sub-division 1041a is electrically connected to the first end of the second division 1042 adjacent to the boundary of the special-shaped display area AA; the first end of the second sub-division 1041b is electrically connected to the second end of the second division 1042 away from the boundary of the display area, and the second end of the second sub-division 1041b is located in the binding area BA; in the first direction X, the maximum distance between all the first sub-divisions is greater than the maximum distance between all the second sub-divisions.

[0076] By setting it in the first direction X, the maximum distance between all the first sub-divisions is greater than the maximum distance between all the second sub-divisions, which is equivalent to shrinking the lead 104 near the binding area BA, so that the entire lead 104 can only occupy a smaller frame (i.e., the binding area BA) on the display substrate when connected to the external source driver chip.

[0077] Optionally, in the display substrate provided by the embodiment of the present disclosure, every two adjacent data lines 103 form a data line group, and every three adjacent data line groups form a cycle ( Figure 4 1 shows a cycle), and the three data line groups in one cycle are the first data group D1, the second data group D2 and the third data group D3 arranged in sequence in the first direction X. In order to realize the nearby wiring of the lead 104 and the corresponding data line 103, as shown in FIG. Figure 4 As shown, two first sub-divisions 1041a electrically connected to the two data lines 103 in the first data group D1 can be arranged at both sides of the first data group D1, two first sub-divisions 1041a electrically connected to the two data lines 103 in the second data group D2 can be arranged at the gap between the first data group D1 and the second data group D2, and two first sub-divisions 1041a electrically connected to the two data lines 103 in the third data group D3 can be arranged at a side of the third data group D3 away from the second data group D2.

[0078] In some embodiments, in the gap between two adjacent data groups, the spacing between the three first sub-divisions 1041a is the same, such as Figure 4 In addition, a high-level power line VDD is provided between the two data lines 103 included in the first data group D1, and a high-level power line VDD and a reference signal line V are provided at the gap between the second data group D2 and the third data group D3. ref Optionally, the high level power line VDD, the reference signal line V ref The same layer as the data line 103 is provided, and the routing line V' can also be provided on the same layer as the lead line 104 ref The incoming call is connected to the reference signal line V ref .

[0079] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, the greater the distance between the first sub-division 1041a and the central axis MN of the display area AA in the second direction Y, the smaller the length of the first sub-division 1041a. This arrangement can make the lengths of the leads 104 substantially the same, which helps to maintain the efficiency of different leads 104 in transmitting grayscale signals at a similar level, thereby improving the display effect.

[0080] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 2 and Figure 3 As shown, one end of the lead line 104 away from the binding area BA is electrically connected to one end of the corresponding data line 103 away from the binding area BA.

[0081] After coming out of the binding area BA, the lead 104 passes through the special-shaped display area AA to the top of each column of data lines 103, and is connected to the data lines 103 in the special-shaped display area AA at the top by changing layers, which can ensure that the lead 104 does not cross and the driving order remains unchanged.

[0082] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 6 As shown, it may also include: a plurality of pixel driving circuits located in the area defined by the plurality of gate lines 102 and the plurality of data lines 103, each pixel driving circuit may include: a first switch transistor T1, a second switch transistor T2, a third switch transistor T3, a light emitting control transistor T4, a driving transistor T5 and a storage capacitor Cst; wherein, as Figure 6 and Figure 7 As shown, the gate of the first switch transistor T1 is electrically connected to the first gate line G1, and the drain of the first switch transistor T1 is electrically connected to the grayscale signal V data The source of the first switch transistor T1 is electrically connected to the source of the second switch transistor T2, the gate of the driving transistor T5, and the first electrode of the storage capacitor Cst. The gate of the second switch transistor T2 is electrically connected to the second gate line G2. The drain of the second switch transistor T2 is electrically connected to the reference signal line V ref The gate of the third switch transistor T3 is electrically connected to the third gate line G3, and the drain of the third switch transistor T3 is electrically connected to the initialization signal line V int The source of the third switch transistor T3 is electrically connected to the anode of the light emitting device EL and the source of the driving transistor T5, the gate of the fourth switch transistor T4 is electrically connected to the light emitting control signal line EM, the drain of the fourth switch transistor T4 is electrically connected to the high level power line VDD, and the source of the fourth switch transistor T4 is electrically connected to the drain of the driving transistor T5. Figure 7 It can be seen that the two upper and lower adjacent pixel driving circuits share a fourth switch transistor T4 and are symmetrically arranged about the I-II line, so that the two upper and lower adjacent pixel driving circuits constitute a 9T2C circuit including nine transistors and two capacitors.

[0083] in addition, Figure 8 The film layer shown is the layer where the active layer (Poly) of each transistor is located. Fig. 9 The film layer shown is the first gate metal layer (Gate1) where the gates of each transistor and the first electrodes of the storage capacitor Cst are located. Fig.10The film layer shown is the second gate metal layer (Gate2) where the second electrode of the storage capacitor Cst is located. Fig.11 The film layer shown is the first source-drain metal layer (SD1) where the source and drain of each transistor are located. Fig.12 The film layer shown is the second source-drain metal layer (SD2) where the lead 104 is located.

[0084] In specific implementation, Fig.13 As shown, in the reset phase t1, the first gate line G1 outputs a low level, the second gate line G2 outputs a high level, the third gate line G3 outputs a high level, and the light emitting control signal line EM outputs a high level. The first switch transistor T1 is in the cut-off state under the control of the low level of the first gate line G1. The second switch transistor T2 is turned on under the control of the high level of the second gate line G2, and the reference signal line V ref The gate of the driving transistor T5 is reset by turning on the second switching transistor T2. The third switching transistor T3 is turned on under the control of the high level of the third gate line G3, and the initialization signal line V int The source of the driving transistor T5 is reset through the turned-on third switching transistor T3. The fourth switching transistor T4 is turned on under the control of the light emitting control signal line EM, and the high level power line VDD resets the drain of the driving transistor T5 through the turned-on fourth switching transistor T4.

[0085] In the compensation phase t2, if Fig.13 As shown, the second gate line G2 and the light emitting control signal line EM maintain outputting high level, the first gate line G1 maintains outputting low level, and the third gate line G3 outputs low level. The first switch transistor T1 is in the cut-off state under the low level control of the first gate line G1. The third switch transistor T3 is in the cut-off state under the low level control of the third gate line G3. The second switch transistor is turned on under the high level control of the second gate line G2, and continues to turn on the reference signal line V ref The fourth switch transistor T4 outputs the signal of the high-level power line VDD to the drain of the driving transistor T5 under the high-level control of the light-emitting control signal line EM, and the drain and source of the driving transistor T5 are turned on to perform threshold compensation on the gate of the driving transistor T5.

[0086] In the data writing phase t3, if Fig.13 As shown, the first gate line G1 outputs a high level, the second gate line G2 outputs a low level, the third gate line G3 outputs a low level, and the light emitting control signal line EM outputs a low level. The first switch transistor T1 is turned on under the control of the high level of the first gate line G1, and the grayscale signal V dataThe gate of the driving transistor T5 is written, and the source potential of the driving transistor T5 changes due to the coupling effect of the storage capacitor Cst. The second switch transistor T2, the third switch transistor T3 and the fourth switch transistor T4 are in the cut-off state under the control of the corresponding low level.

[0087] In the light-emitting stage t4, if Fig.13 As shown, the first gate line G1, the second gate line G2 and the third gate line G3 output low levels, and the light-emitting control signal line EM outputs high levels. The first switch transistor T1 is in a cut-off state under the low level control of the first gate line G1, the second switch transistor T2 is in a cut-off state under the low level control of the second gate line G2, and the third switch transistor T3 is in a cut-off state under the low level control of the third gate line G3. The fourth switch transistor T4 is turned on under the high level control of the light-emitting control signal line, and the signal of the high level power line VDD is written into the drain of the driving transistor T5 through the turned-on fourth switch transistor T4, and the drain and source of the driving transistor T5 are turned on, so that the light-emitting device EL emits light according to the source potential of the driving transistor T5 and the potential of the low level power line VSS.

[0088] Polysilicon material has high mobility, low energy consumption, and high reliability. Therefore, in some embodiments, the driving transistor T5 can be a low-temperature polysilicon thin film transistor. The band gap of the oxide semiconductor material is larger than that of the silicon material, so that electrons cannot pass through the band gap in the off state, and the off current is low. Therefore, the oxide thin film transistor is suitable for the first switch transistor T1 to the fourth switch transistor T4 that are turned on for a short time and turned off for a long time. In addition, because the off current of the first switch transistor T1 is low, the size of the storage capacitor Cst can be appropriately reduced.

[0089] It is worth noting that the present disclosure provides the above technical solution only with Figure 6 The 5T1C pixel driving circuit is taken as an example for explanation. In specific implementation, the above technical solution provided in the embodiment of the present disclosure is also applicable to pixel driving circuits of other structures known to those skilled in the art, and is not specifically limited here.

[0090] Since the lead 104 is a conductor for high-frequency grayscale signals, the grayscale signals on it continuously jump, and in order to ensure that the lead 104 does not interfere with the normal operation of the light-emitting device EL, the gate G of the driving transistor T5 in a floating state needs to avoid the lead 104 as much as possible. Figure 7 As shown, the lead 104 located on the second source-drain metal layer (SD2) may be arranged not to overlap with each transistor, and in particular, the orthographic projection of the lead 104 on the base substrate 101 and the orthographic projection of the gate G of the driving transistor T5 on the base substrate 101 do not overlap with each other. In other embodiments, such as Fig.14As shown, the orthographic projection of at least part of the lead 104 on the substrate 101 can overlap with the orthographic projection of the gate G of the driving transistor T5. At this time, the second electrode C2 located between the layer where the lead 104 is located and the layer where the gate G of the driving transistor T5 is located can be enlarged to cover most of the area of ​​the gate G of the driving transistor T5, so that the overlapping lead 104 and the gate G of the driving transistor T5 can be separated by the second electrode C2 to prevent the high-frequency grayscale signal on the lead 104 from affecting the potential of the gate G of the driving transistor T5. In addition, the second electrode C2 is reused as a shielding layer between the lead 104 and the gate G of the driving transistor T5, which avoids the need to add a shielding layer, reduces the number of film layers, facilitates a lightweight design, improves manufacturing efficiency, and reduces production costs. In addition, the first electrode C1 of the storage capacitor Cst can be reused as the gate G of the driving transistor T5, so that the first electrode C1 and the second electrode C2 covering most of the area of ​​the gate G of the driving transistor T5 overlap to form a storage capacitor Cst.

[0091] In some embodiments, to ensure display effect, the ratio of the overlapping area of ​​the orthographic projection of the lead 104 on the base substrate 101 and the orthographic projection of the gate G of the driving transistor T5 on the base substrate 101 to the area of ​​the gate G of the driving transistor T5 can be less than 1 / 3.

[0092] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Fig.15 As shown, it may also include: an organic insulating layer 105 located between the layer where the multiple data lines 103 (not shown in the figure) are located and the layer where the multiple lead lines 104 are located; each lead line 104 is electrically connected to the corresponding data line 103 through a first via hole penetrating the organic insulating layer 105.

[0093] By providing an organic insulating layer 105 between the layer where the plurality of data lines 103 (not shown) are located and the layer where the plurality of lead lines 104 are located, the parasitic capacitance between the plurality of lead lines 104 and the film layers of each film layer in the pixel driving circuit can be greatly reduced. In some embodiments, the thickness of the organic insulating layer 105 can be about 2 μm.

[0094] Optionally, in the above display substrate provided in the disclosed embodiment, if Fig.15 As shown, it may also include: an inorganic insulating layer 106 located between the organic insulating layer 105 and the layer where the multiple leads 104 are located; at this time, each lead 104 can be electrically connected to the corresponding data line 103 through a second via hole penetrating the inorganic insulating layer 106, and the first via hole and the second via hole corresponding to each lead 104 are through-set.

[0095] Since the organic insulating layer 105 may be partially peeled off and contaminate the chamber when the lead 104 is formed by the sputtering process, by adding an inorganic insulating layer 106 on the organic insulating layer 105, the organic insulating layer 105 can be protected by the inorganic insulating layer 106, thereby avoiding the organic insulating layer 105 being exposed and contaminating the chamber during the subsequent sputtering deposition of the lead 104.

[0096] Optionally, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figure 2 , Figure 3 and Fig.15 As shown, it may also include: a plurality of light emitting devices EL located on the side of the plurality of leads 104 (arranged in the same layer as the transfer electrodes 111) away from the base substrate 101; the plurality of light emitting devices EL constitute a plurality of light emitting device columns extending in the second direction Y, and the greater the distance between the light emitting device column and the central axis MN of the special-shaped display area AA in the second direction Y, the smaller the number of light emitting devices EL contained in the light emitting device column. The light emitting devices EL arranged in this way together constitute a display product having an elliptical special-shaped display area AA.

[0097] In some embodiments, Fig.15 As shown, the light-emitting device EL includes an anode AND, a light-emitting functional layer EM and a cathode CAD; wherein the light-emitting functional layer EM may include a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting material layer, a hole blocking layer, an electron transport layer and an electron injection layer; the light-emitting material layers in the regions where different anodes AND are located may be disconnected to achieve light emission of different colors (e.g., red, green and blue); of course, the light-emitting material layers in the regions where different anodes AND are located may also be integrated to achieve single-color (e.g., white) light emission. In addition, whether each of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer and electron injection layer is disconnected or not needs to be designed according to factors such as the light-emitting efficiency required for light-emitting devices EL of different colors, and is not specifically limited here.

[0098] In some embodiments, Fig.15 As shown, the display substrate provided by the present disclosure may further include: a buffer layer 107, a first gate insulating layer 108, a second gate insulating layer 109, an interlayer dielectric layer 110, a transfer electrode 111, a flat layer 112 and a pixel defining layer 113, etc.; wherein the transfer electrode 111 is provided in the same layer as the lead 104. Other essential components of the display substrate (such as a packaging layer) should be understood by those skilled in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.

[0099] It should be noted that in the present disclosure, "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for making a specific pattern, and then using the same mask plate through a single patterning process. That is, one patterning process corresponds to a mask plate (mask, also called a photomask). Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0100] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate provided by the embodiment of the present disclosure. Other essential components of the display device should be understood by ordinary technicians in the field and will not be elaborated here, nor should they be used as limitations to the present disclosure.

[0101] In some embodiments, the display device may be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0102] In addition, it should be understood that since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the display device can refer to the embodiment of the above-mentioned display substrate, and the repeated parts will not be repeated.

[0103] Optionally, the above-mentioned display substrate provided in the embodiment of the present disclosure may also include: a source driver chip, which includes multiple signal channels (Channel); wherein the multiple signal channels are electrically connected to the multiple leads 104 in the binding area BA in a one-to-one correspondence, and in the first direction X, the total width of the multiple leads 104 in the binding area BA is equal to the total width of the multiple signal channels.

[0104] This arrangement can keep the order of the signal channels of the source driver chip the same as that of the signal channels of the source driver chip in the related art, without changing the structure of the source driver chip, so as to save the R&D and design costs of the source driver chip. In addition, the multiple signal channels of the source driver chip correspond to the arrangement order of the data lines 103 from left to right in the special-shaped display area AA, that is, the first signal channel on the left of the source driver chip corresponds to the data line 103 of the first column of light-emitting devices EL on the left in the special-shaped display area AA, and the last signal channel on the right of the source driver chip corresponds to the data line 103 of the last column of light-emitting devices EL on the right in the special-shaped display area AA, so that the driving order of the source driver chip for each column of light-emitting devices EL remains unchanged.

[0105] In some embodiments, the source driver chip can be located on the display side of the display device; in other embodiments, the source driver chip can also be folded to the opposite side of the display side (i.e., the back side of the display device), so that the source driver chip does not occupy the border of the display device, further meeting the design requirements of a narrow border.

[0106] It should be noted that in the present disclosure, the total width of the multiple leads 104 in the binding area BA specifically refers to the sum of the line width of the multiple leads 104 and the gap width of the multiple leads 104 in the binding area BA. The total width of multiple signal channels refers to the sum of the width of the multiple signal channels and the gap width of the multiple signal channels.

[0107] The above-mentioned display substrate and display device provided by the present disclosure can achieve the technical effect of extremely narrow frame, including: a base substrate, the base substrate including: a display area, and a binding area located on one side of the display area; a plurality of gate lines, extending along a first direction in the display area and arranged along a second direction, wherein the first direction and the second direction are arranged crosswise; a plurality of data lines, arranged in different layers from the plurality of gate lines, and the plurality of data lines extend in the display area along the second direction and arranged along the first direction; a plurality of lead lines, arranged in different layers from the plurality of gate lines and the plurality of data lines, the plurality of lead lines extend from the display area along the second direction to the binding area, each of the plurality of lead lines is electrically connected to each of the plurality of data lines, each lead line includes a first section extending along the second direction, and the orthographic projection of at least part of the first section on the base substrate does not overlap with the orthographic projection of the data line.

[0108] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display substrate, wherein: include: A base substrate, the base substrate comprising: a display area, and a binding area located on one side of the display area; A plurality of gate lines extending along a first direction and arranged along a second direction in the display area, wherein the first direction is arranged to intersect with the second direction; a plurality of data lines, which are arranged in different layers from the plurality of gate lines, and the plurality of data lines extend along the second direction in the display area and are arranged along the first direction; A plurality of lead lines are arranged in different layers from the plurality of gate lines and the plurality of data lines, the plurality of lead lines extend from the display area along the second direction to the binding area, each of the plurality of lead lines is electrically connected to each of the plurality of data lines, each of the lead lines comprises a first subsection extending along the second direction, and an orthographic projection of at least part of the first subsection on the substrate does not overlap with an orthographic projection of the data line; Wherein, the plurality of lead lines are symmetrically arranged about the central axis of the display area in the second direction; The lead line adjacent to the central axis of the display area in the second direction includes the first sub-portion; the lead line away from the central axis of the display area in the second direction includes: the first sub-portion, and a second sub-portion extending along the first direction in the middle area of ​​the display area, and at least a part of the orthographic projection of the second sub-portion on the substrate does not overlap with the orthographic projection of the gate line; Each of the lead lines further comprises: a third section extending along the first direction at the edge of the display area, the orthographic projection of the third section on the substrate does not overlap with the orthographic projection of the gate line, and the third section is electrically connected to the corresponding data line; The first division of the lead away from the central axis of the display area in the second direction includes: a first sub-division and a second sub-division; wherein, the first end of the first sub-division is electrically connected to the third division, and the second end of the first sub-division is electrically connected to the first end of the second division adjacent to the boundary of the display area; the first end of the second sub-division is electrically connected to the second end of the second division away from the boundary of the display area, and the second end of the second sub-division is located in the binding area; the first sub-division and the second sub-division both extend in the second direction, and the first sub-division is farther away from the binding area than the second sub-division.

2. The display substrate according to claim 1, wherein: Also includes: A plurality of pixel units arranged in an array; In the gap between two adjacent rows of pixel units extending along the first direction, the first intervals between two adjacent second sub-parts are equal.

3. The display substrate according to claim 1, wherein: The lengths of the second sub-portions arranged sequentially in a direction from the display area to the binding area gradually increase.

4. The display substrate according to claim 1, wherein: In the first direction, a maximum distance between all of the first subdivisions is greater than a maximum distance between all of the second subdivisions.

5. The display substrate according to claim 4, wherein: Every two adjacent data lines form a data line group, every three adjacent data line groups form a cycle, and the three data line groups in one cycle are the first data group, the second data group and the third data group arranged in sequence in the first direction; The two first sub-divisions electrically connected to the two data lines in the first data group are located on both sides of the first data group, the two first sub-divisions electrically connected to the two data lines in the second data group are located in the gap between the first data group and the second data group, and the two first sub-divisions electrically connected to the two data lines in the third data group are located on a side of the third data group away from the second data group.

6. The display substrate according to claim 4, wherein: The larger the distance between the first sub-division and the central axis of the display area in the second direction, the smaller the length of the first sub-division.

7. The display substrate according to claim 1, wherein: One end of the lead wire away from the binding area is electrically connected to one end of the corresponding data line away from the binding area.

8. The display substrate according to claim 1, wherein: Also includes: A plurality of pixel driving circuits are located in the area defined by the plurality of gate lines and the plurality of data lines, each of the pixel driving circuits comprising a driving transistor and a storage capacitor; wherein, The first electrode of the storage capacitor is reused as the gate of the driving transistor, the second electrode of the storage capacitor is located between the layer where the gate of the driving transistor is located and the layer where the data line is located, and the orthographic projection of at least part of the lead on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate.

9. The display substrate according to claim 8, wherein: The ratio of the overlapping area of ​​the orthographic projection of the lead on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate to the area of ​​the gate of the driving transistor is less than 1 / 3.

10. The display substrate according to claim 1, wherein: Also includes: A plurality of pixel driving circuits located in an area defined by the plurality of gate lines and the plurality of data lines, each of the pixel driving circuits comprising a driving transistor; The orthographic projection of the lead on the base substrate does not overlap with the orthographic projection of the gate of the driving transistor on the base substrate.

11. The display substrate according to claim 1, wherein: Also includes: an organic insulating layer located between the layer where the plurality of data lines are located and the layer where the plurality of lead lines are located; Each of the lead lines is electrically connected to the corresponding data line through a first via hole penetrating the organic insulating layer.

12. The display substrate according to claim 11, wherein: Also includes: an inorganic insulating layer located between the organic insulating layer and the layer where the plurality of leads are located; Each of the lead lines is electrically connected to the corresponding data line through a second via hole penetrating the inorganic insulating layer, and the first via hole and the second via hole corresponding to each of the lead lines are connected.

13. The display substrate according to claim 1, wherein: Also includes: A plurality of light emitting devices located on a side of the plurality of leads away from the substrate; The plurality of light emitting devices constitute a plurality of light emitting device columns extending in the second direction. The greater the distance between the light emitting device column and the central axis of the display substrate in the second direction, the smaller the number of light emitting devices included in the light emitting device column.

14. A display device, wherein: Comprising the display substrate as described in any one of claims 1-13.

15. The display device according to claim 14, wherein: It also includes: a source driver chip, the source driver chip includes a plurality of signal channels; wherein, The plurality of signal channels are electrically connected to the plurality of leads in the binding area in a one-to-one correspondence, and in the first direction, a total width of the plurality of leads in the binding area is equal to a total width of the plurality of signal channels.

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