A pixel driving circuit, a driving method thereof, and a display panel

Abstract

The present application discloses a pixel driving circuit, a driving method thereof, and a display panel, including a driving transistor, a storage capacitor, a writing sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a first threshold control sub-circuit. The first reset sub-circuit is configured to provide the voltage of a first reset signal terminal to the first end of the driving transistor in response to the control of a first scan signal; the second reset sub-circuit is configured to provide the voltage of a second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of a third scan signal; or, configured to provide the voltage of the second reset signal terminal to the second end of the driving transistor in response to the control of the third scan signal; the first threshold control sub-circuit is configured to conduct and disconnect the connection between the second end of the driving transistor and the control terminal of the driving transistor in response to the control of a second scan signal; wherein, the voltage of the first reset signal terminal and the voltage of the second reset signal terminal have opposite polarities.

Description

Technical Field

[0001] The present application generally relates to the field of display technology, and specifically relates to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] Organic Light Emitting Diode (OLED) display panels have gradually occupied the majority of the market share in recent years. OLED display panels have attracted widespread attention due to their lightness, excellent display effect, high contrast, wide color gamut, flexibility and other advantages, and are considered to be the next generation display solution that is expected to replace LCD.

[0003] With the increasing demand for diversified screen displays, improving screen utilization has become a new development demand. Currently, the main way to reduce power consumption is to reduce the refresh rate of the screen to meet the needs of certain displays. For example, a high refresh rate drive method is used to drive the display of dynamic images (such as sports events or game scenes) to ensure the smoothness of the display; a low refresh rate drive method is used to drive the display of slow-motion images or static images to reduce power consumption.

[0004] However, while OLED display products achieve low power consumption and adaptive dynamic refresh rate driving, they also have problems such as low-frequency flicker, refresh frequency switching flicker, and first frame response flicker. Summary of the invention

[0005] In view of the above defects or deficiencies in the prior art, it is desirable to provide a pixel driving circuit and a driving method thereof, and a display panel, which can improve problems such as low-frequency flicker, refresh frequency switching flicker, and first frame response flicker.

[0006] In a first aspect, the present application provides a pixel driving circuit, including a driving transistor, a storage capacitor, a writing subcircuit, a first resetting subcircuit, a second resetting subcircuit, and a first threshold control subcircuit.

[0007] The control terminal of the driving transistor is connected to the storage capacitor, and is used to generate a driving current on a conduction path from the first terminal to the second terminal in response to control of a signal voltage at the control terminal;

[0008] The first reset subcircuit is connected to the first end of the driving transistor and is used to provide a voltage of a first reset signal end to the first end of the driving transistor in response to the control of a first scanning signal;

[0009] The second reset sub-circuit is threshold-controlledly connected to the control end of the driving transistor, and is configured to provide the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal; alternatively, the second reset sub-circuit is connected to the second end of the driving transistor, and is configured to provide the voltage of the second reset signal terminal to the second end of the driving transistor in response to the control of the third scan signal;

[0010] The writing sub-circuit is connected to the first end of the driving transistor, and is configured to provide the voltage of the data signal terminal to the first end of the driving transistor in response to the control of the fourth scan signal;

[0011] The first end of the first threshold control sub-circuit is connected to the control end of the driving transistor, and the second end of the first threshold control sub-circuit is connected to the second end of the driving transistor, and is configured to conduct and disconnect the connection between the second end of the driving transistor and the control end of the driving transistor in response to the control of the second scan signal;

[0012] Wherein, the voltages of the first reset signal terminal and the second reset signal terminal have opposite polarities.

[0013] Optionally, it further includes a light-emitting element, a first light-emitting sub-circuit, a second light-emitting sub-circuit and a third reset sub-circuit, wherein,

[0014] The first light-emitting sub-circuit is connected to the first power supply terminal and the first end of the driving transistor, and is configured to provide the voltage of the first power supply terminal to the driving transistor in response to the control of the light-emitting signal;

[0015] The second light-emitting sub-circuit is connected to the second end of the driving transistor and the first end of the light-emitting element, and is configured to provide the driving current of the driving transistor to the light-emitting element in response to the control of the light-emitting signal, and the second end of the light-emitting element is connected to the second power supply terminal;

[0016] The third reset sub-circuit is connected to the second end of the second light-emitting sub-circuit and the first end of the light-emitting element, and is configured to provide the voltage of the third reset signal terminal to the second end of the second light-emitting sub-circuit and the first end of the light-emitting element in response to the control of the first scan signal.

[0017] Optionally, the first reset sub-circuit includes a first transistor, the first end of the first transistor is connected to the first reset signal terminal, the second end of the first transistor is connected to the first end of the driving transistor, and the control end of the first transistor is connected to the first scan line that provides the first scan signal;

[0018] The second reset sub-circuit includes a fifth transistor. The first end of the fifth transistor is connected to the second reset signal terminal. The second end of the fifth transistor is connected to the control end of the driving transistor. The control end of the fifth transistor is connected to a third scan line that provides the third scan signal; alternatively, the first end of the fifth transistor is connected to the second reset signal terminal, the second end of the fifth transistor is connected to the second end of the driving transistor, and the control end of the fifth transistor is connected to a third scan line that provides the third scan signal;

[0019] The writing sub-circuit includes a fourth transistor. The first end of the fourth transistor is connected to the data signal terminal. The second end of the fourth transistor is connected to the first end of the driving transistor. The control end of the fourth transistor is connected to a fourth scan line that provides the fourth scan signal;

[0020] The first threshold control sub-circuit includes a second transistor. The first end of the second transistor is connected to the control end of the driving transistor and the storage capacitor. The second end of the second transistor is connected to the second end of the driving transistor. The control end of the second transistor is connected to a second scan line that provides the second scan signal.

[0021] Optionally, the first light-emitting sub-circuit includes a seventh transistor. The first end of the seventh transistor is connected to the first power supply terminal. The second end of the seventh transistor is connected to the first end of the driving transistor. The control end of the seventh transistor is connected to a light-emitting control line that provides a light-emitting signal;

[0022] The second light-emitting sub-circuit includes an eighth transistor. The first end of the eighth transistor is connected to the second end of the driving transistor. The second end of the eighth transistor is connected to the first end of the light-emitting element. The control end of the eighth transistor is connected to the light-emitting control line;

[0023] The third reset sub-circuit includes a sixth transistor. The first end of the sixth transistor is connected to the first end of the light-emitting element. The second end of the sixth transistor is connected to the third reset signal terminal. The control end of the sixth transistor is connected to the first scan line.

[0024] Optionally, a second threshold control sub-circuit is further included. The first end of the second threshold control sub-circuit is connected to the storage capacitor and the control end of the driving transistor. The second end of the second threshold control sub-circuit is connected to the first threshold control sub-circuit;

[0025] The second threshold control sub-circuit is configured to control the connection between the first threshold control sub-circuit and the control end of the driving transistor to be turned on and off in response to the control of a fifth scan signal.

[0026] Optionally, the second threshold control sub - circuit includes a ninth transistor. A first end of the ninth transistor is connected to a control end of the driving transistor and the storage capacitor. A second end of the ninth transistor is connected to a first end of the second transistor. A control end of the ninth transistor is connected to a fifth scan line that provides a fifth scan signal.

[0027] Optionally, the first scan signal and the third scan signal share the same scan line, and / or the second scan signal and the fourth scan signal share the same scan line.

[0028] In a second aspect, the present application provides a driving method for a pixel driving circuit, which is applied to the pixel driving circuit as described in any one of the above. The refresh driving period of the driving method includes a first reset stage, a writing stage, a first biasing stage, and a first light - emitting stage.

[0029] In the first reset stage, the first reset sub - circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal.

[0030] In the writing stage, the writing sub - circuit provides the voltage of the data signal terminal to the first end of the driving transistor in response to the control of the fourth scan signal. The first threshold control sub - circuit turns on the connection between the control end and the second end of the driving transistor in response to the second scan signal.

[0031] In the first biasing stage, the first reset sub - circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal. The first threshold control sub - circuit turns off the connection between the control end and the second end of the driving transistor in response to the second scan signal.

[0032] In the first light - emitting stage, the light - emitting element emits light in response to the driving current of the driving transistor.

[0033] Optionally, the holding driving period of the driving method includes a second reset stage, a holding stage, a second biasing stage, and a second light - emitting stage.

[0034] In the second reset stage, the first reset sub - circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal.

[0035] In the holding stage, the writing sub - circuit disconnects the connection between the writing sub - circuit and the first end of the driving transistor in response to the control of the fourth scan signal.

[0036] In the second biasing stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the connection between the control end of the driving transistor and the second end of the driving transistor in response to the second scan signal.

[0037] In the second light-emitting stage, the light-emitting element emits light in response to the driving current of the driving transistor.

[0038] Optionally, the refresh driving cycle of the driving method further includes:

[0039] In the first reset stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal, and the first threshold control sub-circuit disconnects the connection between the control end of the driving transistor and the second end of the driving transistor in response to the second scan signal.

[0040] Optionally, the first reset stage includes a first reset sub-stage, a second reset sub-stage, and a third reset sub-stage:

[0041] In the first reset sub-stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit connects the control end of the driving transistor and the second end of the driving transistor in response to the second scan signal.

[0042] In the second reset sub-stage, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit disconnects the connection between the control end of the driving transistor and the second end of the driving transistor in response to the second scan signal.

[0043] In the third reset sub-stage, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit connects the second end of the driving transistor and the control end of the driving transistor in response to the second scan signal.

[0044] Optionally, the first reset stage includes a first reset sub-stage, a second reset sub-stage, and a third reset sub-stage:

[0045] In the first reset sub-phase, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit conducts the connection between the control end of the driving transistor and the second end of the driving transistor in response to the control of the second scan signal;

[0046] In the second reset sub-phase, the second reset sub-circuit provides the voltage of the second reset signal terminal to the second end of the driving transistor in response to the control of the third scan signal; the first threshold control sub-circuit disconnects the connection between the control end of the driving transistor and the second end of the driving transistor in response to the control of the second scan signal;

[0047] In the third reset sub-phase, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit conducts the connection between the second end of the driving transistor and the control end of the driving transistor in response to the control of the second scan signal.

[0048] Optionally, in the first reset phase, it includes a first reset sub-phase and a second reset sub-phase.

[0049] In the first reset sub-phase, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the connection between the control end of the driving transistor and the second end of the driving transistor in response to the control of the second scan signal;

[0050] In the second reset sub-phase, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit disconnects the connection between the control end of the driving transistor and the second end of the driving transistor in response to the control of the second scan signal.

[0051] In a third aspect, the present application provides a display panel, including the pixel driving circuit as described in any one of the above.

[0052] The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

[0053] In the embodiment of the present application, the provided pixel driving circuit resets the first end and the control end of the driving transistor through the first reset sub-circuit and the second reset sub-circuit respectively, so that when adjusting the bias state of the driving transistor before the picture is switched, the bias state of the driving transistor can be adjusted to a negative bias state or a positive bias state, so that the driving transistor is not affected by the previous frame of picture data, and the picture can be quickly switched to the preset switching picture. Therefore, it is beneficial to improve the flicker phenomenon that occurs during the picture switching process and enhance the display effect. Before the light-emitting stage, the first reset sub-circuit makes the driving transistor enter the light-emitting stage from the conducting state with a fixed bias, so that the recovery process of the threshold voltage of the driving transistor in the holding driving cycle is consistent with the recovery process of the threshold voltage of the driving transistor in the refresh driving cycle, the brightness difference between the refresh driving cycle and the holding driving cycle is reduced, and the VRR is improved. Description of the Drawings

[0054] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, objects, and advantages of the present application will become more apparent:

[0055] Figures 1-3 A schematic structural diagram of a pixel driving circuit provided for the embodiment of the present application;

[0056] Figure 4 A schematic connection diagram of a pixel driving circuit provided for the embodiment of the present application;

[0057] Figures 5-9 A schematic state diagram of a pixel driving circuit provided for the embodiment of the present application;

[0058] Figures 10-11 A timing diagram of a pixel driving circuit driving method provided for the embodiment of the present application;

[0059] Figure 12 A schematic connection diagram of a pixel driving circuit provided for the embodiment of the present application;

[0060] Figures 13-17 A schematic state diagram of a pixel driving circuit provided for the embodiment of the present application;

[0061] Figures 18-19 A timing diagram of a pixel driving circuit driving method provided for the embodiment of the present application;

[0062] Figures 20-21 A schematic state diagram of a pixel driving circuit provided for the embodiment of the present application;

[0063] Figures 22-23 A timing diagram of a pixel driving circuit driving method provided for the embodiment of the present application;

[0064] Figure 24 A schematic diagram of the state of a pixel driving circuit provided by an embodiment of the present application;

[0065] Figures 25-26 A timing diagram of a method for driving a pixel driving circuit provided by an embodiment of the present application. Specific embodiments

[0066] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related invention, rather than limiting the invention. In addition, it should be noted that, for the sake of description, only the parts related to the invention are shown in the drawings.

[0067] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and embodiments.

[0068] The driving transistor in the pixel driving circuit can generate a driving current, and the light-emitting element emits light in response to the driving current. Among them, the driving current generated by the driving transistor is related to the potential of the gate of the driving transistor T3, and the gate of the driving transistor is connected to the storage capacitor. Due to the characteristics of the driving transistor itself, during the switching process of the display device screen, the driving transistor will be affected by the data of the previous frame, resulting in the display screen being unable to quickly switch to the preset screen, and a flickering phenomenon occurs. This phenomenon is the first-frame response flicker FFR phenomenon. For example, a gray screen between the black screen and the white screen appears before switching from the black screen to the white screen, affecting the display effect.

[0069] When the driving mode of the existing pixel circuit switches to low frequency, for example, in the conventional driving, the refresh frequency is 60HZ, which is divided into 60 frames, and there are 60 refresh driving cycles in one second. When the refresh frequency is reduced at low frequency, taking 1HZ as an example, one frame is refreshed in one second (there is only one refresh driving cycle in one frame).

[0070] Specifically, in the first refresh driving cycle, data is normally written. In the remaining 59 hold driving cycles, data writing is not performed, and the data written in the previous frame is used to continue to make the OLED emit light. In this driving mode, one frame of the picture needs to be held for a long time, and when the same picture is held for a long time, the threshold voltage will shift, affecting the characteristics of the thin-film transistor, resulting in different brightness between the refresh frame and the hold frame, forming a brightness difference that can be recognized by the human eye. This phenomenon can be called the refresh frequency switching flicker VRR phenomenon.

[0071] Please refer to Figures 1-2 , the present application provides a pixel driving circuit, including a driving transistor T3, a storage capacitor C, a writing sub-circuit 900, a first reset sub-circuit 100, a second reset sub-circuit 200, and a first threshold control sub-circuit 300.

[0072] The control terminal of the driving transistor T3 is connected to the storage capacitor C, and is configured to generate a driving current on the conduction path from the first end to the second end in response to the control of the signal voltage at the control terminal.

[0073] The first reset sub-circuit 100 is connected to the first end of the driving transistor T3, and is configured to provide the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1.

[0074] The second reset sub-circuit 200 is connected to the threshold control of the control terminal of the driving transistor T3, and is configured to provide the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3; as Figure 1 shown.

[0075] Alternatively, the second reset sub-circuit 200 is connected to the second end of the driving transistor T3, and is configured to provide the voltage of the second reset signal terminal Vinit2 to the second end of the driving transistor T3 in response to the control of the third scan signal G3, as Figure 2 shown.

[0076] The writing sub-circuit 900 is connected to the first end of the driving transistor T3, and is configured to provide the voltage of the data signal terminal Vdata to the first end of the driving transistor T3 in response to the control of the fourth scan signal G4;

[0077] The first end of the first threshold control sub-circuit 300 is connected to the control terminal of the driving transistor T3, and the second end of the first threshold control sub-circuit 300 is connected to the second end of the driving transistor T3, and is configured to conduct and disconnect the connection between the second end of the driving transistor T3 and the control terminal of the driving transistor T3 in response to the control of the second scan signal G2;

[0078] Wherein, the voltage of the first reset signal terminal Vinit1 and the voltage of the second reset signal terminal Vinit2 have opposite polarities.

[0079] In this application, the pixel driving circuit further includes a light-emitting element 800, a first light-emitting sub-circuit 500, a second light-emitting sub-circuit 600 and a third reset sub-circuit 700, as Figure 3 shown.

[0080] The first light-emitting sub-circuit 500 is connected to the first power supply terminal VDD and the first end of the driving transistor T3, and is configured to provide the voltage of the first power supply terminal VDD to the driving transistor T3 in response to the control of the light-emitting signal EM;

[0081] The second light-emitting sub-circuit 600 is connected to the second end of the driving transistor T3 and the first end of the light-emitting element 800, and is configured to provide the driving current of the driving transistor T3 to the light-emitting element 800 in response to the control of the light-emitting signal EM. The second end of the light-emitting element 800 is connected to the second power supply terminal VSS;

[0082] The third reset sub-circuit 700 is connected to the second end of the second light-emitting sub-circuit 600 and the first end of the light-emitting element 800, and is configured to provide the voltage of the third reset signal terminal Vinit3 to the second end of the second light-emitting sub-circuit 600 and the first end of the light-emitting element 800 in response to the control of the first scan signal G1.

[0083] It should be noted that in the embodiments of the present application, the light-emitting element 800 may be a current-driven light-emitting device including an LED (Light Emitting Diode) or an OLED (Organic Light Emitting Diode) in the prior art. The light-emitting element 800 may also be a micro-LED (MicroLight Emitting Diode). A micro-LED refers to a super-small inorganic light-emitting element 800 with a size of less than 100 micrometers (μm) that emits light by itself without a backlight and a color filter. In the following embodiments, the micro-LED is taken as an example for description. It should be noted that the light-emitting element 800 may be various types of LEDs, such as red, green, blue, or white light, etc. The embodiments of the present application do not limit this.

[0084] The "control terminal" specifically refers to the gate of the transistor, the "first end" specifically refers to the source of the transistor, and the "second end" specifically refers to the drain of the transistor. Of course, those skilled in the art should know that the "first end" and the "second end" can be interchanged, that is, the "first end" specifically refers to the drain of the transistor, and the "second end" specifically refers to the source of the transistor.

[0085] The first power supply terminal VDD in the embodiments of the present application may maintain an input DC high-level signal, and this DC high level is referred to as the first voltage. The second power supply terminal VSS may maintain an input DC low-level signal, and this DC low level is referred to as the second voltage, which is lower than the first voltage. The following embodiments are the same and will not be repeated.

[0086] In addition, transistors can be classified into N-type transistors and P-type transistors according to different semiconductor characteristics. Among them, when a transistor is used as a switching transistor, the N-type switching transistor is turned on when controlled by a high-level switching control signal Gate and turned off when controlled by a low-level switching control signal Gate. The P-type switching transistor is turned on when controlled by a low-level switching control signal Gate and turned off when controlled by a high-level switching control signal Gate.

[0087] It should be noted that the pixel circuit in the embodiments of the present application is applicable to pixel driving circuits of various structures (such as 8T1C, 9T1C, 12T1C, or 8T2C, etc.). The pixel driving circuits of 8T1C and 9T1C will be described below by way of example. It can be understood that different pixel circuit structures are selected in different application scenarios.

[0088] In the embodiments of the present application, the pixel driving circuit adopts an LTPO circuit, that is, an LTPO circuit is prepared by using low-temperature polysilicon (LTPS) technology and oxide (IGZO). The low-temperature polysilicon thin-film transistor (Low Temperature Poly Silicon, abbreviated as LTPS) forms an active layer by polysilicon deposition. LTPS has a high electron mobility, a fast reaction speed, and advantages such as high brightness, high resolution, and low power consumption.

[0089] The oxide thin-film transistor (oxide thin-film transistor, abbreviated as oxide TFT), for example, uses an oxide semiconductor as the active layer of the TFT, such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, abbreviated as IGZO). The oxide semiconductor has a high electron mobility and good turn-off characteristics. Compared with LTPS, the oxide semiconductor process is simple and has a high compatibility with the amorphous silicon process.

[0090] Of course, the oxide thin-film transistor can also be other metal oxide semiconductors, for example, indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO), etc. Using the oxide thin-film transistor can effectively reduce the size of the transistor and prevent leakage current, so that while the pixel circuit can be applicable to low-frequency driving, the resolution of the display substrate can also be increased.

[0091] In the embodiments of the present application, an exemplary 8T1C circuit includes eight thin-film transistors (T1-T8), where T2 is an N-type thin-film transistor NMOS using oxide TFT; the rest are P-type thin-film transistors PMOS using LTPS TFT. An exemplary 9T1C circuit includes eight thin-film transistors (T1-T9), where T9 is an N-type thin-film transistor NMOS using oxide TFT; the rest are P-type thin-film transistors PMOS using LTPS TFT.

[0092] In various embodiments of the present application, it is defined that the control terminal of the driving transistor T3 is connected to the storage capacitor C at the first node N1, the first terminal of the driving transistor T3 is connected to the second node N2, and the second terminal of the driving transistor T3 is connected to the third node N3. It should be noted that in the description of the embodiments of the present application, the first node N1, the second node N2, and the third node N3 do not represent actually existing components, but represent the convergence points of relevant circuit connections in the circuit diagram.

[0093] It should be noted that in the embodiments of the present application, the valid signal (level) refers to the signal (level) used to turn on the corresponding switching element, and the invalid signal (level) refers to the signal (level) used to turn off the corresponding switching element. Similarly, in other embodiments of the present application, the same explanation is made. The valid level and the invalid level only represent that the level of the signal has two state quantities, and do not represent that the valid level or the invalid level in the full text has a specific value.

[0094] The pixel driving circuit provided in the embodiments of the present application resets the first terminal and the control terminal of the driving transistor T3 through the first reset sub-circuit 100 and the second reset sub-circuit 200 respectively, so that when adjusting the bias state of the driving transistor T3 before the picture is switched, the bias state of the driving transistor T3 can be adjusted to a negative bias state or a positive bias state, so that the driving transistor T3 is not affected by the previous frame of picture data, and the picture can be quickly switched to the preset switching picture. Therefore, it is beneficial to improve the flicker phenomenon that occurs during the picture switching process and improve the display effect. Before the light-emitting stage, the first reset sub-circuit 100 causes the driving transistor T3 to enter the light-emitting stage from the on state with a fixed bias, so that the recovery process of the threshold voltage of the driving transistor T3 in the holding driving period t200 tends to be consistent with the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving period t100, and the brightness difference between the refresh driving period t100 and the holding driving period t200 is reduced, and the VRR is improved.

[0095] In the embodiments of the present application, two exemplary descriptions for adjusting the bias state of the transistor are respectively shown.

[0096] Embodiment 1

[0097] In the embodiment of the present application, the pixel driving circuit adopts 8T1C, as Figure 4 shown, the first reset sub-circuit 100 includes a first transistor T1. The first end of the first transistor T1 is connected to the first reset signal terminal Vinit1. The second end of the first transistor T1 is electrically connected to the first end of the driving transistor T3 at the second node N2. The control end of the first transistor T1 is connected to the first scan line providing the first scan signal G1.

[0098] The second reset sub-circuit 200 includes a fifth transistor T5. The first end of the fifth transistor T5 is connected to the second reset signal terminal Vinit2. The second end of the fifth transistor T5 is electrically connected to the second end of the driving transistor T3 at the third node N3. The control end of the fifth transistor T5 is connected to the third scan line providing the third scan signal G3.

[0099] The writing sub-circuit 900 includes a fourth transistor T4. The first end of the fourth transistor T4 is connected to the data signal terminal Vdata. The second end of the fourth transistor T4 is electrically connected to the first end of the driving transistor T3 at the first node N1. The control end of the fourth transistor T4 is connected to the fourth scan line providing the fourth scan signal G4.

[0100] The first threshold control sub-circuit 300 includes a second transistor T2. The first end of the second transistor T2 is electrically connected to the control end of the driving transistor T3 at the first node N1 and is connected to the storage capacitor C. The second end of the second transistor T2 is electrically connected to the second end of the driving transistor T3 at the third node N3. The control end of the second transistor T2 is connected to the second scan line providing the second scan signal G2.

[0101] The first light-emitting sub-circuit 500 includes a seventh transistor T7. The first end of the seventh transistor T7 is connected to the first power supply terminal VDD. The second end of the seventh transistor T7 is electrically connected to the first end of the driving transistor T3 at the second node N2. The control end of the seventh transistor T7 is connected to the light-emitting control line providing the light-emitting signal EM.

[0102] The second light-emitting sub-circuit 600 includes an eighth transistor T8. The first end of the eighth transistor T8 is electrically connected to the second end of the driving transistor T3 at the third node N3. The second end of the eighth transistor T8 is connected to the first end of the light-emitting element 800. The control end of the eighth transistor T8 is connected to the light-emitting control line.

[0103] The third reset sub-circuit 700 includes a sixth transistor T6. The first end of the sixth transistor T6 is connected to the first end of the light-emitting element 800. The second end of the sixth transistor T6 is connected to the third reset signal terminal Vinit3. The control end of the sixth transistor T6 is connected to the first scan line.

[0104] In this embodiment, it is exemplarily described that T2 is an N-type thin-film transistor NMOS, and the rest are P-type thin-film transistors PMOS. Among them, the voltage of the first reset signal terminal Vinit1 is a positive voltage, the voltage of the second reset signal terminal Vinit2 is a negative voltage, the voltage of the third reset signal terminal Vinit3 is a negative voltage, and the voltage value of the first reset signal terminal Vinit1 is greater than the voltage value of the second signal terminal, that is, |Vinit1| > |Vinit2|. Through this setting, a large forward bias can be formed between the first node N1 and the third node N3 during the reset process of the driving transistor T3, which will accelerate the release of carriers on the gate of the driving transistor T3 and eliminate the influence of the previous frame display image.

[0105] The voltages of Vinit2 and Vinit3 can be the same or different. Vinit2 is responsible for resetting the control end of the driving transistor T3, and Vinit3 is responsible for resetting the anode of the light-emitting element 800. The advantage is that the two processes do not interfere with each other. Vinit3 for resetting the anode of the light-emitting element 800 can perform a lower-voltage reset to eliminate positive charges, which is more beneficial for improving the lifespan.

[0106] The present application provides a driving method for a pixel driving circuit, which is applied to the pixel driving circuit as described in any one of the above, as Figures 5-10 shown, the refresh driving cycle t100 of the driving method includes a first reset stage t110, a writing stage t120, a first biasing stage t130, and a first light-emitting stage t140.

[0107] In the first reset stage t110, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1, as Figure 5 and 10 shown.

[0108] Specifically, in this embodiment, the first reset stage t110 includes a first reset sub-stage t101, a second reset sub-stage t102, and a third reset sub-stage t103:

[0109] In the first reset sub-phase t101, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub-circuit 300 turns on the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the control of the second scan signal G2.

[0110] In the first reset sub-phase t101, the first scan signal G1 is at a low level, the first transistor T1 is turned on, the second scan signal G2 is at a high level, and the second transistor T2 is turned on; the third scan signal G3, the fourth scan signal G4, and the light-emitting signal EM are at high levels, and the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off; the control end of the sixth transistor T6 multiplexes the first scan signal G1, and the first scan signal G1 is at a low level, so the sixth transistor T6 is turned on. In this stage, the driving transistor T3 is turned on, and the voltage of the first reset signal terminal Vinit1 is applied to the control end of the driving transistor T3 through the first transistor T1 and the second transistor T2 to reset the control end of the driving transistor T3 until the driving transistor T3 is turned off. In this stage, the voltage at the first node N1 is Vinit1 + Vth, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the driving transistor T3.

[0111] In the second reset sub-phase t102, the second reset sub-circuit 200 provides the voltage of the second reset signal terminal Vinit2 to the second end of the driving transistor T3 in response to the control of the third scan signal G3. The first threshold control sub-circuit 300 disconnects the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 6 and 10 shown.

[0112] In the second reset sub-phase t102, the third scan signal G3 is at a low level, and the fifth transistor T5 is turned on; the second scan signal G2 is at a low level, and the second transistor T2 is turned off; the first scan signal G1, the fourth scan signal G4, and the light-emitting signal EM are at high levels, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. The voltage of the second reset signal terminal Vinit2 is applied to the second end of the driving transistor T3 through the fifth transistor T5; in this stage, the driving transistor T3 is turned off, the control end of the driving transistor T3 is connected to the storage capacitor C, the voltage at the first node N1 is Vinit1 + Vth, the voltage at the second node N2 is Vinit2, and the voltage at the third node N3 is Vinit2.

[0113] In the second reset sub-phase t102, a large forward bias is formed between the N1-N3 nodes of the driving transistor T3, which will accelerate the release of carriers captured by the gate, enabling the driving transistor T3 to be unaffected by the previous frame of picture data and still generate a driving current corresponding to the preset switching picture, so that the picture can be quickly switched to the preset switching picture. Therefore, it is beneficial to improve the FFR flicker phenomenon that occurs during the picture switching process and enhance the display effect. The large forward bias causes the driving transistor T3 not to conduct, and the threshold voltage shift is relatively small, which will not cause excessive in-frame brightness changes and will not have a great impact on the VRR effect.

[0114] In the third reset sub-phase t103, the second reset sub-circuit 200 responds to the control of the third scan signal G3 to provide the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C. The first threshold control sub-circuit 300 responds to the second scan signal G2 to conduct the connection between the second end of the driving transistor T3 and the control terminal of the driving transistor T3, as Figure 7 and 10 shown.

[0115] In the third reset sub-phase t103, the third scan signal G3 is at a low level and the fifth transistor T5 conducts; the second scan signal G2 is at a high level and the second transistor T2 conducts; the first scan signal G1, the fourth scan signal G4, and the emission signal EM are at high levels, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. At this stage, the voltage of the second reset signal terminal Vinit2 is applied to the control terminal of the driving transistor T3 through the fifth transistor T5 and the second transistor T2 to reset the gate of the driving transistor T3. The driving transistor T3 conducts under the control of the voltage of the second reset signal terminal Vinit2, and the voltage of the first reset signal terminal Vinit1 is applied to the first end and the second end of the driving transistor T3 through the fifth transistor T5. At this stage, the voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit2-Vth, and the voltage at the third node N3 is Vinit2, where Vth is the threshold voltage of the driving transistor T3.

[0116] In the writing phase t120, the writing sub-circuit 900 responds to the control of the fourth scan signal G4 to provide the voltage of the data signal terminal Vdata to the first end of the driving transistor T3. The first threshold control sub-circuit 300 responds to the second scan signal G2 to conduct the connection between the control terminal of the driving transistor T3 and the second end of the driving transistor T3, as Figure 8 and 10 shown.

[0117] In the writing stage t120, the fourth scan signal G4 is at a low level, the fourth transistor T4 is turned on, the second scan signal G2 is at a high level, and the second transistor T2 is turned on; the first scan signal G1, the third scan signal G3, and the emission signal EM are at high levels, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. In this stage, the driving transistor T3 is turned on, and the voltage of the data signal terminal Vdata is applied to the control terminal of the driving transistor T3 through the fourth transistor T4 and the second transistor T2, realizing the writing of the data signal and the voltage compensation for the control terminal of the driving transistor T3. In this stage, the voltage at the first node N1 is Vdata + Vth, the voltage at the second node N2 is Vdata, and the voltage at the third node N3 is Vdata, where Vth is the threshold voltage of the driving transistor T3.

[0118] In the first bias stage t130, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1, and the first threshold control sub - circuit 300 disconnects the connection between the control terminal and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 8 and 10 shown.

[0119] In the first bias stage t130, the first scan signal G1 is at a low level, the first transistor T1 and the sixth transistor T6 are turned on, the second scan signal G2 is at a low level, and the second transistor T2 is turned off; the third scan signal G3, the fourth scan signal G4, and the emission signal EM are at high levels, and the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off. In this stage, the driving transistor T3 is turned on, and the voltage of the first reset signal terminal Vinit1 is applied to the second end and the third end of the driving transistor T3 through the first transistor T1. In this stage, the voltage at the first node N1 is Vdata + Vth, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the driving transistor T3, as Figure 9 and 10 shown.

[0120] In this stage, the second node N2 and the third node N3 are reset to a high voltage through the first transistor T1, which is equivalent to applying a negative bias voltage to the gate - source of the driving transistor T3 again, so as to change the recovery process of the threshold voltage of the driving transistor T3 again during the emission stage.

[0121] In the first light-emitting stage t140, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3. The light-emitting signal EM is at a low level. The seventh transistor T7 and the eighth transistor T8 are turned on at a low level, and the driving transistor T3 is turned on; other transistors are all in an off state under the control of corresponding switching control signals.

[0122] The driving transistor T3DN operates in a saturation state. According to the current characteristics of the saturation state, the saturation current I flowing through the driving transistor T3DN and used to drive the light-emitting element 80030 satisfies the formula:

[0123] I = 1 / 2 * μ * Cox * W / L * (Vgs - Vth)^2

[0124] = K(Vdata + Vth - VDD - Vth)^2

[0125] = K(Vdata - VDD)^2

[0126] Where K is a structural parameter, and this value is relatively stable in the same structure and can be regarded as a constant.

[0127] Where K is a structural parameter, and this value is relatively stable in the same structure and can be regarded as a constant. Thus, it can be seen that the operating current of the light-emitting element 800 is no longer affected by the threshold voltage Vth of the driving transistor T3DN, completely solving the problem of the threshold voltage Vth drift of the driving transistor T3DN caused by the process and long-term operation, effectively improving problems such as low-frequency flicker (Flicker), and thus improving the non-uniformity of the panel display.

[0128] Optionally, as Figure 11 shown, the holding driving period t200 of the driving method includes a second reset stage t210, a holding stage t220, a second biasing stage t230, and a second light-emitting stage t240.

[0129] In the first reset stage t110, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1.

[0130] In the holding stage t220, the writing sub-circuit 900 disconnects the connection between the writing sub-circuit 900 and the first end of the driving transistor T3 in response to the control of the fourth scan signal G4. This holding stage t220 corresponds to the writing stage t120 in the refresh driving period t100, and no data signal voltage is written in this stage.

[0131] It can be understood that during the light-emitting stage of the refresh driving period t100, a voltage signal is written to the control terminal of the driving transistor T3; during the hold driving period t200, since no data signal is written, the voltage written to the control terminal of the driving transistor T3 during the write stage t120 of the refresh driving period t100 is present both before and during the light-emitting stage, so as to control the driving current during the light-emitting stage of the hold driving stage.

[0132] During the second bias stage t230, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first terminal of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub-circuit 300 disconnects the connection between the control terminal of the driving transistor T3 and the second terminal of the driving transistor T3 in response to the second scan signal G2.

[0133] During the second light-emitting stage t240, the light-emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0134] In this embodiment, the driving timings of the first scan signal G1 and the third scan signal G3 in the hold driving period t200 are the same as those of the first scan signal G1 and the third scan signal G3 in the refresh driving period t100, while the driving timings of the remaining scan signals in the hold driving period t200 are such that the corresponding transistors can remain off in each stage of the hold driving period t200.

[0135] During the second reset stage t210 of the hold driving period t200, since the second transistor T2 remains off during the second reset stage t210, when the first reset sub-stage t101 corresponding to the refresh driving period t100 applies a high level to the second node N2 and the third node N3 of the driving transistor T3, and when the corresponding second reset sub-stage t102 and third reset sub-stage t103 apply a low level to the second node N2 and the third node N3 of the driving transistor T3, the drift of the threshold voltage of the driving transistor T3 within the hold driving period t200 is eliminated, so that the threshold voltage of the driving transistor T3 is restored to the initial value; in addition, through the first bias stage t130 and the second bias stage t230, the driving circuit is in a fixed-bias conduction state, which can ensure that regardless of whether the data signal of the previous frame is a black-state or white-state signal, the driving transistor T3 starts to enter the light-emitting stage from the fixed-bias conduction state, making the threshold voltage recovery process of the driving transistor T3 in the hold driving period t200 tend to be consistent with the threshold voltage recovery process of the driving transistor T3 in the refresh driving period t100, reducing the brightness difference between the refresh driving period t100 and the hold driving period t200 and improving the VRR.

[0136] In the embodiment of the present application, during the reset phase, the anode potential of the light-emitting element 800EL is reset multiple times by the third reset sub-circuit 700 to control the light-emitting element 800EL not to emit light, thereby avoiding the influence of the charge remaining at the anode of the light-emitting element 800 on the emission brightness.

[0137] Embodiment 2

[0138] In the embodiment of the present application, as Figure 12 shown, the pixel driving circuit adopts 9T1C. The first reset sub-circuit 100 includes a first transistor T1. The first end of the first transistor T1 is connected to the first reset signal terminal Vinit1. The second end of the first transistor T1 is electrically connected to the first end of the driving transistor T3 at the second node N2. The control end of the first transistor T1 is connected to the first scan line that provides the first scan signal G1.

[0139] The second reset sub-circuit 200 includes a fifth transistor T5. The first end of the fifth transistor T5 is connected to the second reset signal terminal Vinit2. The second end of the fifth transistor T5 is electrically connected to the control end of the driving transistor T3 at the first node N1. The control end of the fifth transistor T5 is connected to the third scan line that provides the third scan signal G3.

[0140] The writing sub-circuit 900 includes a fourth transistor T4. The first end of the fourth transistor T4 is connected to the data signal terminal Vdata. The second end of the fourth transistor T4 is electrically connected to the first end of the driving transistor T3 at the second node N2. The control end of the fourth transistor T4 is connected to the fourth scan line that provides the fourth scan signal G4.

[0141] The first threshold control sub-circuit 300 includes a second transistor T2. The first end of the second transistor T2 is electrically connected to the control end of the driving transistor T3 at the first node N1 and is connected to the storage capacitor C. The second end of the second transistor T2 is electrically connected to the second end of the driving transistor T3 at the third node N3. The control end of the second transistor T2 is connected to the second scan line that provides the second scan signal G2.

[0142] The first light-emitting sub-circuit 500 includes a seventh transistor T7. The first end of the seventh transistor T7 is connected to the first power supply terminal VDD. The second end of the seventh transistor T7 is electrically connected to the first end of the driving transistor T3 at the second node N2. The control end of the seventh transistor T7 is connected to the light-emitting control line that provides the light-emitting signal EM.

[0143] The second light-emitting sub-circuit 600 includes an eighth transistor T8. A first end of the eighth transistor T8 is electrically connected to a second end of the driving transistor T3 at a third node N3. A second end of the eighth transistor T8 is connected to a first end of the light-emitting element 800. A control end of the eighth transistor T8 is connected to the light-emitting control line.

[0144] The third reset sub-circuit 700 includes a sixth transistor T6. A first end of the sixth transistor T6 is connected to the first end of the light-emitting element 800. A second end of the sixth transistor T6 is connected to a third reset signal terminal Vinit3. A control end of the sixth transistor T6 is connected to the first scan line.

[0145] The pixel driving circuit in this embodiment further includes a second threshold control sub-circuit 400. A first end of the second threshold control sub-circuit 400 is connected to the storage capacitor C and a control end of the driving transistor T3. A second end of the second threshold control sub-circuit 400 is connected to the first threshold control sub-circuit 300. The second threshold control sub-circuit 400 is configured to connect and disconnect the connection between the first threshold control sub-circuit 300 and the control end of the driving transistor T3 in response to the control of a fifth scan signal G5.

[0146] Specifically, the second threshold control sub-circuit 400 includes a ninth transistor T9. A first end of the ninth transistor T9 is electrically connected to the control end of the driving transistor T3 at a first node N1 and the storage capacitor C. A second end of the ninth transistor T9 is connected to a first end of the second transistor T2. A control end of the ninth transistor T9 is connected to a fifth scan line that provides the fifth scan signal G5.

[0147] In the embodiment of the present application, the driving transistor T3 is a P-type transistor. Since the leakage current of the P-type transistor is relatively large, using low-frequency driving will cause phenomena such as flicker, thus limiting the use of this pixel circuit. In this embodiment, by adding a ninth transistor T9 in the pixel circuit, the leakage of the first node N1 can be further reduced.

[0148] In this embodiment, it is exemplarily described that T9 is an N-type thin-film transistor NMOS, and the rest are P-type thin-film transistors PMOS. The present application provides a driving method for a pixel driving circuit, which is applied to the pixel driving circuit as described in any one of the above, as Figures 13-19 shown, the refresh driving period t100 of the driving method includes a first reset stage t110, a writing stage t120, a first biasing stage t130, and a first light-emitting stage t140.

[0149] In the first reset stage t110, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1.

[0150] Specifically, in this embodiment, the first reset stage t110 includes a first reset sub - stage t101, a second reset sub - stage t102, and a third reset sub - stage t103:

[0151] In the first reset sub - stage t101, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub - circuit 300 turns on the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 13 and 18 .

[0152] In the first reset sub - stage t101, the first scan signal G1 and the second scan signal G2 are at low levels, the first transistor T1 and the second transistor T2 are turned on, the fifth scan signal G5 is at a high level, and the fifth transistor T5 is turned on; the third scan signal G3, the fourth scan signal G4, and the emission signal EM are at high levels, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are turned off; the control end of the sixth transistor T6 multiplexes the first scan signal G1, and since the first scan signal G1 is at a low level, the sixth transistor T6 is turned on. At this stage, the driving transistor T3 is turned on, and the voltage of the first reset signal terminal Vinit1 is applied to the control end of the driving transistor T3 through the first transistor T1 and the second transistor T2 to reset the control end of the driving transistor T3 until the driving transistor T3 is turned off. At this stage, the voltage at the first node N1 is Vinit1 + Vth, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the driving transistor T3.

[0153] In the second reset sub - stage t102, the second reset sub - circuit 200 provides the voltage of the second reset signal terminal Vinit2 to the control end of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3. The first threshold control sub - circuit 300 disconnects the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 14 and 18 .

[0154] In the second reset sub-phase t102, the third scan signal G3 is at a low level, and the fifth transistor T5 is turned on; the fifth scan signal G5 is at a high level, and the ninth transistor T9 is turned on; the first scan signal G1, the second scan signal G2, the fourth scan signal G4, and the emission signal EM are at high levels, and the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. The voltage of the second reset signal terminal Vinit2 is applied to the second terminal of the driving transistor T3 through the fifth transistor T5; in this stage, the driving transistor T3 is turned off, the control terminal of the driving transistor T3 is connected to the storage capacitor C, the voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1.

[0155] In the second reset sub-phase t102, the control terminal of the driving transistor T3 is charged by the second reset signal. Since the voltage at point N1 is a relatively small negative voltage, and the voltages at nodes N2 and N3 maintain the Vinit1 of the previous stage, which is a relatively large positive voltage, the driving transistor T3 changes from the off state in the first reset sub-phase t101 to the on state. At this time, a relatively large negative bias voltage is applied to the gate-source of the driving transistor T3, causing the driving transistor T3 to be deeply negatively biased, improving the gate saturation carrier capture, helping to eliminate the influence of the previous frame, and significantly improving the FFR; in the second reset sub-phase t102, the driving transistor T3 is turned on, and the deep negative bias voltage on the driving transistor T3 will cause the saturation carriers to be released within the frame, resulting in threshold drift and brightness change of the driving transistor T3, and the improvement of the VRR is not obvious.

[0156] In the third reset sub-phase t103, the second reset sub-circuit 200 provides the voltage of the second reset signal terminal Vinit2 to the control terminal of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3. The first threshold control sub-circuit 300 turns on the connection between the second terminal of the driving transistor T3 and the control terminal of the driving transistor T3 in response to the second scan signal G2, as Figure 15 and 18 .

[0157] In the third reset sub-phase t103, the third scan signal G3 and the second scan signal G2 are at low level, and the fifth transistor T5 and the second transistor T2 are turned on; the fifth scan signal G5 is at high level, and the eighth transistor T8 is turned on; the first scan signal G1, the fourth scan signal G4, and the emission signal EM are at high level, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. In this stage, the voltage of the second reset signal terminal Vinit2 is applied to the control terminal of the driving transistor T3 through the fifth transistor T5 and the second transistor T2 to reset the gate of the driving transistor T3. The driving transistor T3 is turned on under the control of the voltage of the second reset signal terminal Vinit2, and the voltage of the first reset signal terminal Vinit1 is applied to the first terminal of the driving transistor T3 through the fifth transistor T5. In this stage, the voltage at the first node N1 is Vinit2, the voltage at the second node N2 is Vinit2 - Vth, and the voltage at the third node N3 is Vinit2, where Vth is the threshold voltage of the driving transistor T3.

[0158] In this stage, due to the large negative bias between the gate and source of the driving transistor T3 in the second reset sub-phase t102, the threshold voltage of the driving transistor T3 drifts to a certain extent. In this embodiment, N1 / N2 / N3 in the first reset sub-phase t101 are all at positive voltage, and N1 / N2 / N3 in the third reset sub-phase t103 all become negative voltage. By performing charge and discharge actions on the driving transistor T3 multiple times in the first reset stage t110, at least one voltage flip is achieved for the three nodes of the driving transistor T3, and the emission control line is not opened for emission during this process. After the driving transistor T3 is stabilized, emission is performed to improve the drift and hysteresis characteristics of the driving transistor T3 and improve the short-term afterimage problem.

[0159] In the writing stage t120, the writing sub-circuit 900 provides the voltage of the data signal terminal Vdata to the first terminal of the driving transistor T3 in response to the control of the fourth scan signal G4, and the first threshold control sub-circuit 300 turns on the connection between the control terminal and the second terminal of the driving transistor T3 in response to the second scan signal G2, as Figure 16 and 18 .

[0160] In the writing stage t120, the fourth scan signal G4 and the second scan signal G2 are at low level, the fourth transistor T4 and the second transistor T2 are turned on, the fifth scan signal G5 is at high level, and the eighth transistor T8 is turned on; the first scan signal G1, the third scan signal G3, and the emission signal EM are at high level, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. In this stage, the driving transistor T3 is turned on, and the voltage of the data signal terminal Vdata is applied to the control terminal of the driving transistor T3 through the fourth transistor T4 and the second transistor T2, realizing the writing of the data signal and the voltage compensation for the control terminal of the driving transistor T3. In this stage, the voltage at the first node N1 is Vdata + Vth, the voltage at the second node N2 is Vdata, and the voltage at the third node N3 is Vdata, where Vth is the threshold voltage of the driving transistor T3.

[0161] In the first bias stage t130, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1, and the first threshold control sub - circuit 300 disconnects the connection between the control terminal and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 17 and 18 .

[0162] In the first bias stage t130, the first scan signal G1 is at low level, the first transistor T1 and the fifth transistor T5 are turned on, the fifth scan signal G5 is at low level, and the eighth transistor T8 is turned off; the second scan signal G2, the third scan signal G3, the fourth scan signal G4, and the emission signal EM are at high level, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are turned off. In this stage, the driving transistor T3 is turned on, and the voltage of the first reset signal terminal Vinit1 is applied to the second end and the third end of the driving transistor T3 through the first transistor T1. In this stage, the voltage at the first node N1 is Vdata + Vth, the voltage at the second node N2 is Vinit1, and the voltage at the third node N3 is Vinit1, where Vth is the threshold voltage of the driving transistor T3.

[0163] In this stage, the second node N2 and the third node N3 are reset to a high voltage through the first transistor T1, which is equivalent to applying a negative bias voltage to the gate - source of the driving transistor T3 again, so as to change the recovery process of the threshold voltage of the driving transistor T3 again during the emission stage.

[0164] In the first light-emitting stage t140, the light-emitting element 800 emits light in response to the drive current of the drive transistor T3. The light-emitting signal EM is at a low level. The seventh transistor T7 and the eighth transistor T8 are turned on at a low level, and the drive transistor T3 is turned on. Other transistors are all in an off state under the control of corresponding switching control signals.

[0165] The drive transistor T3DN operates in a saturation state. According to the current characteristics of the saturation state, the saturation current I flowing through the drive transistor T3DN and used to drive the light-emitting element 80030 satisfies the formula:

[0166] I = 1 / 2 * μ * Cox * W / L * (Vgs - Vth)^2

[0167] = K(Vdata + Vth - VDD - Vth)^2

[0168] = K(Vdata - VDD)^2

[0169] Where K is a structural parameter. In the same structure, this value is relatively stable and can be regarded as a constant.

[0170] Where K is a structural parameter. In the same structure, this value is relatively stable and can be regarded as a constant. Thus, it can be seen that the operating current of the light-emitting element 800 is no longer affected by the threshold voltage Vth of the drive transistor T3DN, completely solving the problem of the threshold voltage Vth drift of the drive transistor T3DN caused by the process manufacturing and long-term operation, thereby improving the non-uniformity of the panel display.

[0171] Optionally, as Figure 19 shown, the holding drive period t200 of the drive method includes a second reset stage t210, a holding stage t220, a second bias stage t230, and a second light-emitting stage t240.

[0172] In the second reset stage t210, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the drive transistor T3 in response to the control of the first scan signal G1.

[0173] In the holding stage t220, the writing sub-circuit 900 disconnects the connection between the writing sub-circuit 900 and the first end of the drive transistor T3 in response to the control of the fourth scan signal G4.

[0174] In the second biasing stage t230, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub - circuit 300 disconnects the connection between the control end and the second end of the driving transistor T3 in response to the second scan signal G2.

[0175] In the second light - emitting stage t240, the light - emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0176] In this embodiment, the driving timing of the first scan signal G1 in the holding driving period t200 is the same as that of the first scan signal G1 in the refresh driving period t100, while the driving timing of the remaining scan signals in the holding driving period t200 is such that the corresponding transistors can remain off in each stage of the holding driving period t200.

[0177] In the second reset stage t210 of the holding driving period t200, only high levels are applied to the second node N2 and the third node N3 of the driving transistor T3. There is no reset process at the N1 point during the holding driving period t200, only the process of Vinit1 voltage biasing. By biasing the voltages of the N2 and N3 nodes, the drift states of the threshold voltages of the driving transistor T3 in the holding driving period t200 and the refresh driving period t100 are made substantially the same; additionally, through the biasing stage, the recovery process of the threshold voltage of the driving transistor T3 in the holding driving period t200 tends to be the same as the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving period t100, reducing the brightness difference between the refresh driving period t100 and the holding driving period t200 and improving VRR.

[0178] Embodiment Three

[0179] In the embodiment of the present application, the pixel driving circuit adopts 9T1C. On the basis of Embodiment Two, the setting method of the scan signal lines is optimized. Based on using 6 groups of GOA (Gate Driver on Array) to drive each gate control signal in Embodiment Two, the number of GOA is reduced. In this embodiment, the second scan signal G2 and the fourth scan signal G4 share the same scan line, that is, the driving timings of the second scan signal G2 and the fourth scan signal G4 are the same, and 5 groups of GOA are used to control the pixel driving circuit in this embodiment. Through the technical solution in the embodiment of the present application, GOA space and pixel space can be saved, the power consumption of GOA can be reduced, which is suitable for products with narrow borders and high pixel densities.

[0180] In this embodiment, as Figures 20-22As shown, the refresh driving period t100 of the driving method includes a first reset stage t110, a writing stage t120, a first bias stage t130, and a first light-emitting stage t140, where:

[0181] In the first reset stage t110, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1.

[0182] Among them, the first reset stage t110 includes a first reset sub-stage t111 and a second reset sub-stage t112. Specifically,

[0183] In the first reset sub-stage t111, the first reset sub-circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1; the first threshold control sub-circuit 300 disconnects the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 20 and 22 shown.

[0184] In the first reset sub-stage t111, the second transistor T2 is turned off, and the second node N2 and the third node N3 of the driving transistor T3 are reset through the first reset sub-circuit 100, so that the voltages of the second node N2 and the third node N3 are reset to Vinit1.

[0185] In the second reset sub-stage t112, the second reset sub-circuit 200 provides the voltage of the second reset signal terminal Vinit2 to the control end of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3; the first threshold control sub-circuit 300 disconnects the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 21 and 22 shown.

[0186] In the second reset sub-stage t112, the second transistor T2 is turned off, and the first node N1 of the driving transistor T3 is reset through the second reset sub-circuit 200, so that the voltage of the first node N1 is reset to Vinit2. By forming a negative bias voltage between the gate and source of the driving transistor T3 in the first reset stage t110, the FFR can be effectively improved. It can be understood that in this embodiment, since a relatively large negative bias voltage of the gate-source of the driving transistor T3 in Embodiment 2 is not formed, therefore, the improvement effect on the FFR in this embodiment is weaker than that of Embodiment 2, but compared with the prior art solutions, the FFR can be greatly improved and the display effect can be improved.

[0187] In the writing stage t120, the writing sub - circuit 900 provides the voltage of the data signal terminal Vdata to the first end of the driving transistor T3 in response to the control of the fourth scan signal G4, and the first threshold control sub - circuit 300 turns on the connection between the control end and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 16 and 22 shown.

[0188] In the first biasing stage t130, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1, and the first threshold control sub - circuit 300 turns off the connection between the control end and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 17 and 22 shown.

[0189] In the first light - emitting stage t140, the light - emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0190] As Figure 23 shown, the holding driving period t200 of the driving method includes a second reset stage t210, a holding stage t220, a second biasing stage t230, and a second light - emitting stage t240, where

[0191] in the second reset stage t210, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1.

[0192] In the holding stage t220, the writing sub - circuit 900 disconnects the connection between the writing sub - circuit 900 and the first end of the driving transistor T3 in response to the control of the fourth scan signal G4.

[0193] In the second biasing stage t230, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1; the first threshold control sub - circuit 300 turns off the connection between the control end and the second end of the driving transistor T3 in response to the second scan signal G2.

[0194] In the second light - emitting stage t240, the light - emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0195] In this embodiment, the timing of the first scan signal G1 during the hold driving period t200 is the same as that of the first scan signal G1 during the refresh driving period t100. During the hold driving period t200, the driving timings of the remaining scan signals are such that the corresponding transistors can be kept off at each stage of the hold driving period t200. Through the second bias stage t230, the threshold voltage recovery process of the driving transistor T3 during the hold driving period t200 tends to be consistent with that of the driving transistor T3 during the refresh driving period t100, reducing the brightness difference between the refresh driving period t100 and the hold driving period t200 and improving the VRR.

[0196] It can be understood that in this embodiment, since a large negative bias voltage is not formed between the gate and source of the driving transistor T3 during the refresh driving period t100, the threshold voltage shift during the refresh driving period t100 is mainly determined by the positive bias voltages on N2 and N3 of the driving transistor T3. Therefore, during both the hold driving period t200 and the refresh driving period t100, the N2 and N3 of the driving transistor T3 are positively biased through the first reset sub-circuit 100, making the threshold voltage drift of the driving transistor T3 during the hold driving period t200 and the refresh driving period t100 basically the same. Additionally, the threshold voltage recovery process of the driving transistor T3 also tends to be the same, resulting in a smaller brightness difference between the refresh driving period t100 and the hold driving period t200 and a significant improvement in VRR.

[0197] Embodiment 4

[0198] In the embodiment of the present application, the pixel driving circuit adopts 9T1C. Based on Embodiment 2, the setting method of the scan signal lines is optimized. On the basis of using 6 groups of GOA to drive each gate control signal in Embodiment 2, the number of GOA is reduced. In this embodiment, the second scan signal G2 and the fourth scan signal G4 share the same scan line, and the first scan signal G1 and the third scan signal G3 share the same scan line, that is, the driving timings of the second scan signal G2 and the fourth scan signal G4 are the same, and the driving timings of the first scan signal G1 and the third scan signal G3 are the same. 4 groups of GOA are used to control the pixel driving circuit in this embodiment. Through the technical solution in the embodiment of the present application, the GOA space and pixel space can be saved, the power consumption of the GOA can be reduced, and it is suitable for products with narrow borders and high pixel densities.

[0199] The present application provides a driving method for a pixel driving circuit, as Figures 24-25 shown, applied to the pixel driving circuit as described in any of the above. The refresh driving period t100 of the driving method includes a first reset stage t110, a writing stage t120, a first bias stage t130, and a first light-emitting stage t140.

[0200] In the first reset stage t110, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1; the second reset sub - circuit 200 provides the voltage of the second reset signal terminal Vinit2 to the control end of the driving transistor T3 and the storage capacitor C in response to the control of the third scan signal G3, and the first threshold control sub - circuit 300 disconnects the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2.

[0201] In this embodiment, the first reset sub - circuit 100 performs a positive - voltage reset on the second node N2 and the third node N3 of the driving transistor T3, and the second reset sub - circuit 200 performs a negative - voltage reset on the first node N1 of the driving transistor T3, forming a large negative bias voltage between the gate and source of the driving transistor T3, so that the FFR of the refresh driving period t100 can be significantly improved.

[0202] In the writing stage t120, the writing sub - circuit 900 provides the voltage of the data signal terminal Vdata to the first end of the driving transistor T3 in response to the control of the fourth scan signal G4, and the first threshold control sub - circuit 300 conducts the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 16 and 25 shown.

[0203] In the first bias stage t130, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1, and the first threshold control sub - circuit 300 disconnects the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2, as Figure 17 and 25 shown.

[0204] In the first light - emitting stage t140, the light - emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0205] In this embodiment, as Figure 26 shown, the holding driving period t200 of the driving method includes a second reset stage t210, a holding stage t220, a second bias stage t230, and a second light - emitting stage t240.

[0206] In the second reset stage t210, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1.

[0207] In the holding stage t220, the writing sub - circuit 900 disconnects the connection between the writing sub - circuit 900 and the first end of the driving transistor T3 in response to the control of the fourth scan signal G4.

[0208] In the second biasing stage t230, the first reset sub - circuit 100 provides the voltage of the first reset signal terminal Vinit1 to the first end of the driving transistor T3 in response to the control of the first scan signal G1. The first threshold control sub - circuit 300 disconnects the connection between the control end of the driving transistor T3 and the second end of the driving transistor T3 in response to the second scan signal G2.

[0209] In the second light - emitting stage t240, the light - emitting element 800 emits light in response to the driving current of the driving transistor T3.

[0210] In this embodiment, the driving timing of the first scan signal G1 in the holding driving period t200 is the same as that of the first scan signal G1 in the refresh driving period t100, while the driving timing of the remaining scan signals in the holding driving period t200 is such that the corresponding transistors can remain off in each stage of the holding driving period t200. In the second reset stage t210 of the holding driving period t200, the ninth transistor T9 remains off, and only the first reset sub - circuit 100 resets the N2 and N3 nodes, and the second reset sub - circuit 200 cannot reset the N1 node.

[0211] Through the first biasing stage t130 and the second biasing stage t230, the first reset sub - circuit 100 performs positive - voltage reset on the second node N2 and the third node N3 of the driving transistor T3, so that the recovery process of the threshold voltage of the driving transistor T3 in the refresh driving period t100 and the holding driving period t200 tends to be consistent, the brightness difference between the refresh driving period t100 and the holding driving period t200 can be reduced, and VRR improvement can be achieved.

[0212] It can be understood that, in this embodiment, a relatively large negative bias voltage is formed between the gate and source of the driving transistor T3 within the refresh driving period t100, effectively improving the FFR, but causing a certain drift in the threshold voltage of the driving transistor T3. While within the holding driving period t200, a high level is only applied to the second node N2 and the third node N3 of the driving transistor T3. There is no reset process at the N1 point within the holding driving period t200, only the process of Vinit1 voltage biasing. Therefore, compared with the solution of Embodiment 2, only through the first biasing stage t130 and the second biasing stage t230, the improvement effect on the VRR is relatively weak. However, compared with the prior art, it has a stronger improvement effect on the FRR and also achieves the improvement effect on the VRR.

[0213] Based on the same inventive concept, the present application provides a display panel including the pixel driving circuit as described in any one of the above. This display panel can be applied to: OLED display devices, AMOLED display devices, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, and any other products or components with a display function.

[0214] It should be understood that the orientation or positional relationship indicated by terms such as "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present invention.

[0215] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0216] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present invention. The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. Terms such as "arranged" as used herein can mean that one component is directly attached to another component or that one component is attached to another component through an intermediate component. The features described in one embodiment herein can be applied to another embodiment alone or in combination with other features, unless the feature is not applicable or otherwise stated in that other embodiment.

[0217] The present invention has been described by the above embodiments. However, it should be understood that the above embodiments are for illustrative and explanatory purposes only, and are not intended to limit the present invention to the scope of the described embodiments. Those skilled in the art can understand that more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope claimed by the present invention.

Claims

1. A driving method for a pixel driving circuit, characterized in that, The refresh driving cycle of the driving method includes a first reset stage, a writing stage, a first biasing stage, and a first light-emitting stage. In the first reset stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal. In the writing stage, the writing sub-circuit provides the voltage of the data signal terminal to the first end of the driving transistor in response to the control of the fourth scan signal, and the first threshold control sub-circuit turns on the connection between the control end and the second end of the driving transistor in response to the second scan signal. In the first biasing stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal, and the first threshold control sub-circuit turns off the connection between the control end and the second end of the driving transistor in response to the second scan signal. In the first light-emitting stage, the light-emitting element emits light in response to the driving current of the driving transistor. The first reset stage includes a first reset sub-stage, a second reset sub-stage, and a third reset sub-stage: In the first reset sub-stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit turns on the connection between the control end and the second end of the driving transistor in response to the second scan signal. In the second reset sub-stage, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit turns off the connection between the control end and the second end of the driving transistor in response to the second scan signal. In the third reset sub-stage, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control end of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit turns on the connection between the second end and the control end of the driving transistor in response to the second scan signal.

2. The driving method for a pixel driving circuit according to claim 1, characterized in that, The holding driving cycle of the driving method includes a second reset stage, a holding stage, a second biasing stage, and a second light-emitting stage. In the second reset stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal. In the holding stage, the writing sub-circuit disconnects the connection between the writing sub-circuit and the first end of the driving transistor in response to the control of the fourth scan signal. In the second biasing stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit turns off the connection between the control end and the second end of the driving transistor in response to the second scan signal. In the second light-emitting stage, the light-emitting element emits light in response to the driving current of the driving transistor.

3. The driving method for a pixel driving circuit according to claim 1, characterized in that, The refresh driving cycle of the driving method further includes: In the first reset stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal, and the first threshold control sub-circuit disconnects the connection between the control terminal of the driving transistor and the second end of the driving transistor in response to the second scan signal.

4. The driving method for a pixel driving circuit according to claim 1, characterized in that, The first reset stage includes a first reset sub-stage and a second reset sub-stage. In the first reset sub-stage, the first reset sub-circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub-circuit disconnects the connection between the control terminal of the driving transistor and the second end of the driving transistor in response to the second scan signal; In the second reset sub-stage, the second reset sub-circuit provides the voltage of the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal; the first threshold control sub-circuit disconnects the connection between the control terminal of the driving transistor and the second end of the driving transistor in response to the second scan signal.

5. The driving method for a pixel driving circuit according to claim 1, characterized in that, The pixel driving circuit includes a driving transistor, a storage capacitor, a writing sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a first threshold control sub-circuit. The control terminal of the driving transistor is connected to the storage capacitor and is used to generate a driving current on the conduction path from the first end to the second end in response to the control of the control terminal signal voltage. The first reset sub-circuit is connected to the first end of the driving transistor and is used to provide the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal. The second reset sub-circuit is connected to the control terminal threshold control of the driving transistor and is used to provide the voltage of the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal. The writing sub-circuit is connected to the first end of the driving transistor and is used to provide the voltage of the data signal terminal to the first end of the driving transistor in response to the control of the fourth scan signal. The first end of the first threshold control sub-circuit is connected to the control terminal of the driving transistor, and the second end of the first threshold control sub-circuit is connected to the second end of the driving transistor and is used to conduct and disconnect the connection between the second end of the driving transistor and the control terminal of the driving transistor in response to the control of the second scan signal. Wherein, the voltages of the first reset signal terminal and the second reset signal terminal have opposite polarities.

6. The driving method for a pixel driving circuit according to claim 5, characterized in that, It further includes a light-emitting element, a first light-emitting sub-circuit, a second light-emitting sub-circuit, and a third reset sub-circuit, wherein, The first light-emitting sub-circuit is connected to the first power supply terminal and the first end of the driving transistor and is used to provide the voltage of the first power supply terminal to the driving transistor in response to the control of the light-emitting signal. The second light-emitting sub-circuit is connected to the second end of the driving transistor and the first end of the light-emitting element, and is configured to provide a driving current of the driving transistor to the light-emitting element in response to the control of the light-emitting signal. The second end of the light-emitting element is connected to a second power supply terminal; The third reset sub-circuit is connected to the second end of the second light-emitting sub-circuit and the first end of the light-emitting element, and is configured to provide a voltage of a third reset signal terminal to the second end of the second light-emitting sub-circuit and the first end of the light-emitting element in response to the control of the first scan signal.

7. The driving method for a pixel driving circuit according to claim 6, characterized in that, The first reset sub-circuit includes a first transistor. The first end of the first transistor is connected to the first reset signal terminal. The second end of the first transistor is connected to the first end of the driving transistor. The control end of the first transistor is connected to a first scan line that provides the first scan signal; The second reset sub-circuit includes a fifth transistor. The first end of the fifth transistor is connected to the second reset signal terminal. The second end of the fifth transistor is connected to the control end of the driving transistor. The control end of the fifth transistor is connected to a third scan line that provides the third scan signal; alternatively, the first end of the fifth transistor is connected to the second reset signal terminal, the second end of the fifth transistor is connected to the second end of the driving transistor, and the control end of the fifth transistor is connected to the third scan line that provides the third scan signal; The writing sub-circuit includes a fourth transistor. The first end of the fourth transistor is connected to the data signal terminal. The second end of the fourth transistor is connected to the first end of the driving transistor. The control end of the fourth transistor is connected to a fourth scan line that provides the fourth scan signal; The first threshold control sub-circuit includes a second transistor. The first end of the second transistor is connected to the control end of the driving transistor and the storage capacitor. The second end of the second transistor is connected to the second end of the driving transistor. The control end of the second transistor is connected to a second scan line that provides the second scan signal.

8. The driving method of the pixel driving circuit according to claim 7, wherein, The first light-emitting sub-circuit includes a seventh transistor. The first end of the seventh transistor is connected to the first power supply terminal. The second end of the seventh transistor is connected to the first end of the driving transistor. The control end of the seventh transistor is connected to a light-emitting control line that provides a light-emitting signal; The second light-emitting sub-circuit includes an eighth transistor. The first end of the eighth transistor is connected to the second end of the driving transistor. The second end of the eighth transistor is connected to the first end of the light-emitting element. The control end of the eighth transistor is connected to the light-emitting control line; The third reset sub-circuit includes a sixth transistor. The first end of the sixth transistor is connected to the first end of the light-emitting element. The second end of the sixth transistor is connected to the third reset signal terminal. The control end of the sixth transistor is connected to the first scan line.

9. The driving method of the pixel driving circuit according to claim 7, wherein, It further includes a second threshold control sub-circuit. The first end of the second threshold control sub-circuit is connected to the storage capacitor and the control end of the driving transistor. The second end of the second threshold control sub-circuit is connected to the first threshold control sub-circuit; The second threshold control sub - circuit is used to respond to the control of the fifth scan signal to conduct and disconnect the connection between the first threshold control sub - circuit and the control terminal of the driving transistor.

10. The driving method of the pixel driving circuit according to claim 9, wherein, The second threshold control sub - circuit includes a ninth transistor. The first end of the ninth transistor is connected to the control terminal of the driving transistor and the storage capacitor. The second end of the ninth transistor is connected to the first end of the second transistor. The control terminal of the ninth transistor is connected to the fifth scan line that provides the fifth scan signal.

11. The driving method of the pixel driving circuit according to claim 5, wherein, The first scan signal and the third scan signal share the same scan line, and / or the second scan signal and the fourth scan signal share the same scan line.

12. A driving method of a pixel driving circuit, wherein, The refresh driving cycle of the driving method includes a first reset stage, a writing stage, a first biasing stage, and a first light - emitting stage. In the first reset stage, the first reset sub - circuit responds to the control of the first scan signal to provide the voltage of the first reset signal terminal to the first end of the driving transistor. In the writing stage, the writing sub - circuit responds to the control of the fourth scan signal to provide the voltage of the data signal terminal to the first end of the driving transistor. The first threshold control sub - circuit responds to the second scan signal to conduct the connection between the control terminal of the driving transistor and the second end of the driving transistor. In the first biasing stage, the first reset sub - circuit responds to the control of the first scan signal to provide the voltage of the first reset signal terminal to the first end of the driving transistor. The first threshold control sub - circuit responds to the second scan signal to disconnect the connection between the control terminal of the driving transistor and the second end of the driving transistor. In the first light - emitting stage, the light - emitting element emits light in response to the driving current of the driving transistor. The first reset stage includes a first reset sub - stage, a second reset sub - stage, and a third reset sub - stage. In the first reset sub - stage, the first reset sub - circuit responds to the control of the first scan signal to provide the voltage of the first reset signal terminal to the first end of the driving transistor. The first threshold control sub - circuit responds to the control of the second scan signal to conduct the connection between the control terminal of the driving transistor and the second end of the driving transistor. In the second reset sub - stage, the second reset sub - circuit responds to the control of the third scan signal to provide the voltage of the second reset signal terminal to the second end of the driving transistor. The first threshold control sub - circuit responds to the second scan signal to disconnect the connection between the control terminal of the driving transistor and the second end of the driving transistor. In the third reset sub - stage, the second reset sub - circuit responds to the control of the third scan signal to provide the voltage of the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor. The first threshold control sub - circuit responds to the second scan signal to conduct the connection between the second end of the driving transistor and the control terminal of the driving transistor.

13. The driving method of the pixel driving circuit according to claim 12, wherein, The holding driving cycle of the driving method includes a second reset stage, a holding stage, a second biasing stage, and a second light - emitting stage. In the second reset stage, the first reset sub - circuit responds to the control of the first scan signal to provide the voltage of the first reset signal terminal to the first end of the driving transistor. During the holding stage, the writing sub - circuit disconnects the connection between the writing sub - circuit and the first end of the driving transistor in response to the control of the fourth scan signal; During the second biasing stage, the first reset sub - circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal; the first threshold control sub - circuit disconnects the connection between the control terminal of the driving transistor and the second end of the driving transistor in response to the second scan signal; During the second light - emitting stage, the light - emitting element emits light in response to the driving current of the driving transistor.

14. The driving method of the pixel driving circuit according to claim 12, wherein, The refresh driving period of the driving method further includes: During the first reset stage, the first reset sub - circuit provides the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal, the second reset sub - circuit provides the voltage of the second reset signal terminal to the control terminal of the driving transistor and the storage capacitor in response to the control of the third scan signal, and the first threshold control sub - circuit disconnects the connection between the control terminal of the driving transistor and the second end of the driving transistor in response to the second scan signal.

15. The driving method of the pixel driving circuit according to claim 12, wherein, The pixel driving circuit includes a driving transistor, a storage capacitor, a writing sub - circuit, a first reset sub - circuit, a second reset sub - circuit, and a first threshold control sub - circuit. The control terminal of the driving transistor is connected to the storage capacitor and is used to generate a driving current on the conduction path from the first end to the second end in response to the control of the signal voltage at the control terminal. The first reset sub - circuit is connected to the first end of the driving transistor and is used to provide the voltage of the first reset signal terminal to the first end of the driving transistor in response to the control of the first scan signal. The second reset sub - circuit is connected to the second end of the driving transistor and is used to provide the voltage of the second reset signal terminal to the second end of the driving transistor in response to the control of the third scan signal. The writing sub - circuit is connected to the first end of the driving transistor and is used to provide the voltage of the data signal terminal to the first end of the driving transistor in response to the control of the fourth scan signal. The first end of the first threshold control sub - circuit is connected to the control terminal of the driving transistor, and the second end of the first threshold control sub - circuit is connected to the second end of the driving transistor. It is used to conduct and disconnect the connection between the second end of the driving transistor and the control terminal of the driving transistor in response to the control of the second scan signal. Wherein, the voltages of the first reset signal terminal and the second reset signal terminal have opposite polarities.

16. The driving method of the pixel driving circuit according to claim 15, wherein, It further includes a light - emitting element, a first light - emitting sub - circuit, a second light - emitting sub - circuit, and a third reset sub - circuit. Among them, The first light - emitting sub - circuit is connected to the first power supply terminal and the first end of the driving transistor and is used to provide the voltage of the first power supply terminal to the driving transistor in response to the control of the light - emitting signal. The second light - emitting sub - circuit is connected to the second end of the driving transistor and the first end of the light - emitting element and is used to provide the driving current of the driving transistor to the light - emitting element in response to the control of the light - emitting signal. The second end of the light - emitting element is connected to the second power supply terminal. The third reset sub-circuit is connected to the second end of the second light-emitting sub-circuit and the first end of the light-emitting element, and is configured to provide the voltage of the third reset signal terminal to the second end of the second light-emitting sub-circuit and the first end of the light-emitting element in response to the control of the first scan signal.

17. The driving method of the pixel driving circuit according to claim 16, wherein, The first reset sub-circuit includes a first transistor. The first end of the first transistor is connected to the first reset signal terminal. The second end of the first transistor is connected to the first end of the driving transistor. The control end of the first transistor is connected to the first scan line that provides the first scan signal. The second reset sub-circuit includes a fifth transistor. The first end of the fifth transistor is connected to the second reset signal terminal. The second end of the fifth transistor is connected to the control end of the driving transistor. The control end of the fifth transistor is connected to the third scan line that provides the third scan signal; alternatively, the first end of the fifth transistor is connected to the second reset signal terminal, the second end of the fifth transistor is connected to the second end of the driving transistor, and the control end of the fifth transistor is connected to the third scan line that provides the third scan signal. The writing sub-circuit includes a fourth transistor. The first end of the fourth transistor is connected to the data signal terminal. The second end of the fourth transistor is connected to the first end of the driving transistor. The control end of the fourth transistor is connected to the fourth scan line that provides the fourth scan signal. The first threshold control sub-circuit includes a second transistor. The first end of the second transistor is connected to the control end of the driving transistor and the storage capacitor. The second end of the second transistor is connected to the second end of the driving transistor. The control end of the second transistor is connected to the second scan line that provides the second scan signal.

18. The driving method of the pixel driving circuit according to claim 17, wherein, The first light-emitting sub-circuit includes a seventh transistor. The first end of the seventh transistor is connected to the first power supply terminal. The second end of the seventh transistor is connected to the first end of the driving transistor. The control end of the seventh transistor is connected to the light-emitting control line that provides the light-emitting signal. The second light-emitting sub-circuit includes an eighth transistor. The first end of the eighth transistor is connected to the second end of the driving transistor. The second end of the eighth transistor is connected to the first end of the light-emitting element. The control end of the eighth transistor is connected to the light-emitting control line. The third reset sub-circuit includes a sixth transistor. The first end of the sixth transistor is connected to the first end of the light-emitting element. The second end of the sixth transistor is connected to the third reset signal terminal. The control end of the sixth transistor is connected to the first scan line.

19. The driving method of the pixel driving circuit according to claim 17, wherein, It further includes a second threshold control sub-circuit. The first end of the second threshold control sub-circuit is connected to the storage capacitor and the control end of the driving transistor. The second end of the second threshold control sub-circuit is connected to the first threshold control sub-circuit. The second threshold control sub-circuit is configured to conduct and disconnect the connection between the first threshold control sub-circuit and the control end of the driving transistor in response to the control of the fifth scan signal.

20. The driving method of the pixel driving circuit according to claim 19, wherein, The second threshold control sub-circuit includes a ninth transistor. A first end of the ninth transistor is connected to a control end of the driving transistor and the storage capacitor. A second end of the ninth transistor is connected to a first end of the second transistor. A control end of the ninth transistor is connected to a fifth scan line that provides a fifth scan signal.

21. A display panel, wherein, Display is performed by using the driving method of the pixel driving circuit according to any one of claims 1-20.

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