A method and system for improving NAND Flash read and write operation verification efficiency

Abstract

The present invention provides a method and system for improving the efficiency of NAND Flash read and write operation verification. The method includes: selecting a random number of times or selecting to traverse the entire NAND Flash address; selecting to enter SLC mode or TLC mode through a command; if SLC mode is selected, directly returning the word line address through the SLC address model in the system and marking the used addresses; if TLC mode is selected, first returning the number of pages contained in the word line and the available read and write modes through the TLC address model in the system, and the user selects the corresponding SLC, MLC, or TLC read and write operation based on the number of pages; outputting the word line address and marking the used addresses; and continuing to randomize unmarked addresses based on the marked addresses until the entire NAND address is traversed or a specified random number of times is reached. The present invention realizes the function of randomizing addresses, independently defining the random number of times, and quickly covering all addresses when performing NAND Flash read and write operations, thereby improving verification efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a method and system for improving the verification efficiency of NAND Flash read and write operations. Background Art

[0002] NAND FLASH is widely used as a storage medium in SSDs. The capacity structure of NAND Flash, from largest to smallest, is Device, Chip, LUN, Plane, Block, Wordline, Page, and Cell. A Wordline corresponds to one or more Pages, depending on the SLC, MLC, or TLC configuration. For SLC, one Wordline corresponds to one Page; for MLC, two Pages; and for TLC, three Pages. A Block is the smallest unit capable of performing an erase operation, typically consisting of multiple Pages. A Page is the smallest unit capable of performing program and read operations, typically ranging in size from 4KB, 8KB, 16KB, or 32KB. MLC stands for Multi-Level Cell, meaning multi-layer storage, with each cell storing two bits of data.

[0003] A NAND Flash consists of many blocks, each block contains many word lines, and each word line contains several pages. Device refers to a single NAND Flash. A single NAND Flash usually contains one or more chips, and each chip has an independent chip select unit, including one or more LUNs. Some structures are as follows: Figure 1 shown.

[0004] For some NAND Flash, the SLC mode directly reads and writes a word line. SLC: Single Level Cell, that is, single-layer storage, the principle is to store 1 bit of data in 1 storage unit (cell); in TLC mode, a word line (Word Line) may contain 2 pages (pages): LSB and CSB, 3 pages (pages): LSB, CSB, MSB, where LSB: Least Significant Bit, least significant bit; CSB: middle significant bit; MSB: Most Significant Bit, most significant bit; during the write operation, the word line (Word Line) address is input, and during the read operation, the corresponding page (page) address is input. TLC: Triple-Level Cell, that is, 3 bits per cell architecture, 1 storage unit stores 3 bits of data.

[0005] When performing read and write operations on NAND Flash, word line and page addresses are required. Manually entering word line and page addresses each time during large-scale verification of read and write operations wastes significant time and may reuse previously used addresses. This invention provides TLC and SLC address models to achieve random address selection and overwrite of NAND Flash addresses. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a method and system for improving the efficiency of NAND Flash read and write operation verification. Based on the random word line address, the method and system can determine the number of pages contained in the word line, determine whether the write mode (SLC, TLC, or MLC) can be performed, and output the address of each page. The present invention realizes the function of random address, self-defining the random number of times, and quickly covering all addresses during NAND Flash read and write operations, thereby improving verification efficiency.

[0007] Based on the above objectives, on one hand, the present invention provides a method for improving the efficiency of NAND Flash read and write operation verification, the method comprising the following steps:

[0008] Select a random number of times or choose to traverse the entire NADN Flash address;

[0009] Select to enter SLC mode or TLC mode through command;

[0010] If the SLC mode is selected, the word line address is directly returned through the SLC address model in the system, and the used address is marked;

[0011] If TLC mode is selected, the number of pages contained in this word line and the available read and write modes are first returned through the TLC address model in the system. The user can then select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

[0012] Output word line address and mark the address that has been used;

[0013] Based on the marked addresses, the unmarked addresses are randomized until the entire NAND address is traversed or the specified number of random times is reached.

[0014] As a further solution of the present invention, when the random number is defined, if the random number is greater than the number of all word lines of the NAND Flash, an error is returned.

[0015] As a further solution of the present invention, when performing read and write verification on NAND Flash, the address is random.

[0016] As a further solution of the present invention, when performing read and write verification on NAND Flash, a custom address random number is set.

[0017] As a further solution of the present invention, a customized random number is used to traverse all addresses in the NAND and automatically output all addresses.

[0018] As a further solution of the present invention, the random word line address is used to determine the number of pages contained in the word line, determine the writing method and output the address of each page.

[0019] As a further solution of the present invention, the writing mode includes SLC, TLC, and MLC writing modes.

[0020] Another aspect of the present invention further provides a system for improving the efficiency of NAND Flash read and write operation verification, which includes a random number selection module, a mode selection module, an SLC mode module, and a TLC mode module;

[0021] The random number selection module is used to select a random number of times or to traverse the entire NADN Flash address;

[0022] The mode selection module is used to select to enter the SLC mode or the TLC mode through a command;

[0023] The SLC mode module is used to directly return the word line address through the SLC address model in the system and mark the address that has been used;

[0024] The TLC mode module is used to first return the number of pages contained in this word line and the available read and write modes through the TLC address model in the system. The user can select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

[0025] As a further solution of the present invention, it also includes a random number judgment module, which is used to judge whether the random number exceeds the maximum value after selecting the random number. If it exceeds the maximum value, an error is displayed and the current operation is terminated. If it does not exceed the maximum value, the selection mode is performed.

[0026] As a further solution of the present invention, it also includes an address marking module, which is used to mark the used addresses after the TLC mode module outputs the word line address, and continue to randomize the unmarked addresses according to the marked addresses until the entire NAND address is traversed or a specified number of random times is reached.

[0027] In another aspect of the present invention, a computer-readable storage medium is provided, storing computer program instructions, which, when executed, implement any of the above methods for improving the efficiency of NAND Flash read and write operation verification according to the present invention.

[0028] In another aspect of the present invention, a computer device is provided, including a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, any one of the above methods for improving the efficiency of NAND Flash read and write operation verification according to the present invention is performed.

[0029] Another aspect of the present invention further provides a chip for performing process control according to any of the above methods for improving the efficiency of NAND Flash read and write operation verification according to the present invention, wherein the chip architecture comprises a CPU reset vector register, a CPU release control pin, a CPU release control register, and a debug interface, wherein

[0030] The CPU reset vector register is used to control the address of the instruction read and executed after the CPU is released;

[0031] The CPU release control register is used to control the CPU release when the chip is powered on;

[0032] The CPU release control pin is used to control the validity of the CPU release control register;

[0033] The debug interface is used to read and write on-chip RAM and registers to perform chip process control.

[0034] The present invention has at least the following beneficial technical effects:

[0035] The present invention proposes a method and system for improving the efficiency of NAND Flash read and write operation verification. By using this method, randomness is improved when performing read and write operations on Nand Flash, and the address of the NAND can be quickly covered. The time for querying the page address contained in a specified word line can be reduced, and intermediate verification links are reduced. The flexibility of Nand Flash verification is increased, the verification efficiency is improved, the verification cost is reduced, the operation is convenient, and the threshold for verifying NAND Flash is lowered.

[0036] These and other aspects of the present application will be more clearly understood in the following description of the embodiments. It should be understood that the above general description and the following detailed description are merely exemplary and explanatory and cannot limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0038] In the figure:

[0039] Figure 1 A schematic diagram of a partial structure of a conventional single NAND Flash is shown;

[0040] Figure 2 A schematic diagram of a chip showing a method for improving NAND Flash read and write operation verification efficiency according to the present invention;

[0041] Figure 3 A schematic block diagram of an embodiment of a system for improving NAND Flash read and write operation verification efficiency according to the present invention is shown;

[0042] Figure 4 A schematic diagram illustrating an embodiment of a computer-readable storage medium for implementing a method for improving NAND Flash read and write operation verification efficiency according to the present invention;

[0043] Figure 5 A schematic diagram of the hardware structure of an embodiment of a computer device for implementing a method for improving the efficiency of NAND Flash read and write operation verification according to the present invention is shown;

[0044] Figure 6 A schematic diagram showing a framework of an embodiment of a chip according to the present invention. DETAILED DESCRIPTION

[0045] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0046] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. Therefore, "first" and "second" are used for convenience of expression only and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product, or device that includes a series of steps or units.

[0047] To make the purpose, technical solutions and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application.

[0048] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0049] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0050] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0051] For some NAND Flash memories, the SLC mode directly reads and writes a word line. During a write operation, the word line address is input, and during a read operation, the corresponding page address is input. TLC (Triple-Level Cell), a 3-bit per cell architecture, stores 3 bits of data in one storage cell. When performing read and write operations on NAND Flash, both the word line and page addresses need to be provided. When performing large-scale verification of read and write operations, manually inputting the word line and page addresses each time wastes a significant amount of time and may reuse previously used addresses. The present invention provides TLC and SLC address models to achieve the functions of randomly selecting addresses and overwriting NAND Flash addresses.

[0052] In view of this, embodiments of the present invention provide a method and system for improving the efficiency of NAND Flash read and write operation verification. Based on the address of a random word line, the method and system determine how many pages the word line contains, determine which write mode (SLC, TLC, or MLC) can be performed, and output the address of each page. Among them, MLC: Multi Level Cell, that is, multi-layer storage, one storage cell stores 2 bits of data.

[0053] The present invention realizes the function of randomizing addresses, independently defining random times, and quickly covering all addresses when performing read and write operations on NAND Flash, thereby improving verification efficiency.

[0054] In some embodiments of the present invention, a method for improving the efficiency of NAND Flash read and write operation verification is provided, comprising the following steps:

[0055] Select a random number of times or choose to traverse the entire NADN Flash address;

[0056] Select to enter SLC mode or TLC mode through command;

[0057] If the SLC mode is selected, the word line address is directly returned through the SLC address model in the system, and the used address is marked;

[0058] If TLC mode is selected, the number of pages contained in this word line and the available read and write modes are first returned through the TLC address model in the system. The user can then select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

[0059] Output word line address and mark the address that has been used;

[0060] Based on the marked addresses, the unmarked addresses are randomized until the entire NAND address is traversed or the specified number of random times is reached.

[0061] Among them, if the random number is greater than the number of all word lines of NAND Flash when the random number is defined, an error is returned.

[0062] In some embodiments, when performing read and write verification on the NAND Flash, the address is random.

[0063] In some embodiments, when performing read and write verification on NAND Flash, a custom address random number is used.

[0064] In some embodiments, a custom random number is used to traverse all addresses in the NAND and automatically output all addresses.

[0065] In some embodiments, the random word line address is used to determine the number of pages contained in the word line, determine the writing method, and output the address of each page.

[0066] In some embodiments, the writing mode includes SLC, TLC, and MLC writing modes.

[0067] In summary, to address the above-mentioned problems existing in the prior art, the present invention proposes a method for improving the efficiency of NAND Flash read and write operation verification. This method improves randomness during read and write operations on Nand Flash, enables rapid coverage of NAND addresses, reduces the time required to query the page address contained in a specified word line, reduces intermediate verification steps, increases the flexibility of Nand Flash verification, improves verification efficiency, reduces verification costs, facilitates operation, and lowers the threshold for NAND Flash verification.

[0068] See also Figure 2 As shown, a method for improving the efficiency of NAND Flash read and write operation verification according to an embodiment of the present invention is specifically implemented in the following steps:

[0069] Step 1. Select the number of random operations or select to traverse the entire NAND Flash address. If the number of random operations is greater than the number of all word lines in the NAND Flash, an error is returned.

[0070] Step 2. Use the command to select whether to enter SLC mode or TLC mode;

[0071] Step 3: If SLC mode is selected, the word line address is directly returned through the SLC address model in the system, and the used address is marked;

[0072] Step 4: If TLC mode is selected, the number of pages contained in this word line and the available read and write modes are returned through the TLC address model in the system. The user can select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

[0073] Step 5: Output the word line address and mark the used address.

[0074] Step 6: The system continues to randomize the unmarked addresses according to the marked addresses until the entire NAND address is traversed or the specified random number of times is reached.

[0075] It should be understood that, although the above is described in a certain order, these steps are not necessarily performed in sequence according to the above order. Unless there is clear explanation in this article, the execution of these steps does not have strict order restriction, and these steps can be performed in other orders. Moreover, a part of the steps of the present embodiment may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.

[0076] A second aspect of the present invention further provides a system for improving the efficiency of NAND Flash read and write operation verification. Figure 3 FIG. 1 is a schematic block diagram of an embodiment of a system for improving NAND Flash read and write operation verification efficiency according to the present invention. Figure 3 As shown, the system includes a random number selection module 210, a mode selection module 220, an SLC mode module 230 and a TLC mode module 240;

[0077] The random number selection module 210 is used to select a random number of times or to traverse the entire NADN Flash address;

[0078] The mode selection module 220 is used to select to enter the SLC mode or the TLC mode through a command;

[0079] The SLC mode module 230 is used to directly return the word line address through the SLC address model in the system and mark the address that has been used;

[0080] The TLC mode module 240 is used to first return the number of pages contained in this word line and the available read and write modes through the TLC address model in the system. The user selects the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

[0081] In some embodiments, the system for improving the efficiency of NAND Flash read and write operation verification further includes a random number judgment module 211, which is used to judge whether the random number exceeds a maximum value after selecting a random number. If it exceeds the maximum value, an error is displayed and the current operation is terminated. If it does not exceed the maximum value, the selection mode is selected.

[0082] In some embodiments, the system for improving the efficiency of NAND Flash read and write operation verification further includes an address marking module 250, which is used to mark the used addresses after the TLC mode module 240 outputs the word line address, and continue to randomize the unmarked addresses based on the marked addresses until the entire NAND address is traversed or a specified number of random times is reached.

[0083] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to an embodiment of the present invention, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0084] A third aspect of the embodiments of the present invention further provides a computer-readable storage medium. Figure 4 A schematic diagram of a computer-readable storage medium for improving the efficiency of NAND Flash read and write operation verification according to an embodiment of the present invention is shown. Figure 4 As shown, the computer-readable storage medium 300 stores computer program instructions 310, which can be executed by a processor. When the computer program instructions 310 are executed, the method of any one of the above embodiments is implemented.

[0085] It should be understood that, to the extent that they do not conflict with each other, all the embodiments, features, and advantages described above for the method for improving the efficiency of NAND Flash read and write operation verification according to the present invention are also applicable to the system and storage medium for improving the efficiency of NAND Flash read and write operation verification according to the present invention.

[0086] A fourth aspect of the embodiments of the present invention further provides a computer device 400, including a memory 420 and a processor 410. The memory stores a computer program, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented, including the following steps:

[0087] Step 1. Select the number of random operations or select to traverse the entire NAND Flash address. If the number of random operations is greater than the number of all word lines in the NAND Flash, an error is returned.

[0088] Step 2. Use the command to select whether to enter SLC mode or TLC mode;

[0089] Step 3: If SLC mode is selected, the word line address is directly returned through the SLC address model in the system, and the used address is marked;

[0090] Step 4: If TLC mode is selected, the number of pages contained in this word line and the available read and write modes are returned through the TLC address model in the system. The user can select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

[0091] Step 5: Output the word line address and mark the used address.

[0092] Step 6: The system continues to randomize the unmarked addresses according to the marked addresses until it traverses the entire NAND address or reaches the specified random number of times.

[0093] like Figure 5 FIG. 1 is a schematic diagram of the hardware structure of a computer device for executing a method for improving the efficiency of NAND Flash read and write operation verification provided by the present invention. Figure 5 Taking the computer device 400 shown as an example, the computer device includes a processor 410 and a memory 420, and may also include: an input device 430 and an output device 440. The processor 410, the memory 420, the input device 430 and the output device 440 can be connected via a bus or other means. Figure 5 The bus connection is used as an example. The input device 430 can receive input digital or character information and generate signal input related to improving the efficiency of NAND Flash read and write operation verification. The output device 440 can include a display device such as a display screen.

[0094] The memory 420, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs, and modules, such as the program instructions / modules corresponding to the method for improving the efficiency of NAND Flash read and write operation verification in the embodiments of the present application. The memory 420 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created by using the method for improving the efficiency of NAND Flash read and write operation verification, etc. In addition, the memory 420 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 420 may optionally include a memory remotely located relative to the processor 410, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0095] The processor 410 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 420, that is, the method for improving the efficiency of NAND Flash read and write operation verification of the above method embodiment is implemented. The steps are as follows:

[0096] Step 1. Select the number of random operations or select to traverse the entire NAND Flash address. If the number of random operations is greater than the number of all word lines in the NAND Flash, an error is returned.

[0097] Step 2. Use the command to select whether to enter SLC mode or TLC mode;

[0098] Step 3: If SLC mode is selected, the word line address is directly returned through the SLC address model in the system, and the used address is marked;

[0099] Step 4: If TLC mode is selected, the number of pages contained in this word line and the available read and write modes are returned through the TLC address model in the system. The user can select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

[0100] Step 5: Output the word line address and mark the used address.

[0101] Step 6: The system continues to randomize the unmarked addresses according to the marked addresses until it traverses the entire NAND address or reaches the specified random number of times.

[0102] According to a fifth aspect of the embodiments of the present invention, there is provided a chip 500 for performing process control according to any one of the above methods for improving verification efficiency of NAND Flash read and write operations according to the present invention. Figure 6 FIG. 5 shows a schematic diagram of a frame of a chip 500 according to the present invention. Figure 6 As shown, in this embodiment, the architecture of the chip 500 includes a CPU reset vector register 510, a CPU release control pin 520, a CPU release control register 530, and a debug interface 540, wherein

[0103] The CPU reset vector register 510 is used to control the address of the instruction read and executed after the CPU is released;

[0104] The CPU release control register 530 is used to control the CPU release when the chip 500 is powered on;

[0105] The CPU release control pin 520 is used to control the validity of the CPU release control register 530;

[0106] The debug interface 540 is used to read and write on-chip RAM and registers to perform chip process control.

[0107] It will also be appreciated by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithmic steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0108] Finally, it should be noted that the computer-readable storage medium (e.g., memory) herein may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which may act as external cache memory. By way of example and not limitation, RAM may be available in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The memory devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

[0109] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components, designed to perform the functions herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0110] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless expressly limited to the singular.

[0111] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0112] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to limit the scope of the disclosure of the present invention (including the claims) to these examples. Within the spirit of the present invention, the technical features of the above embodiments or different embodiments may be combined, and many other variations exist in different aspects of the above embodiments, which are not provided in detail for the sake of clarity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for improving the efficiency of NAND Flash read and write operation verification, characterized in that: The method comprises the following steps: Select a random number of times or choose to traverse the entire NADN Flash address; Select to enter SLC mode or TLC mode through command; If the SLC mode is selected, the word line address is directly returned through the SLC address model in the system, and the used address is marked; If TLC mode is selected, the system uses the TLC address model to first return the number of pages contained in this word line and the available read and write modes. The user can then select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages, output the word line address, and mark the used addresses. Based on the marked addresses, the unmarked addresses are randomized until the entire NAND address is traversed or the specified number of random times is reached.

2. The method for improving NAND Flash read and write operation verification efficiency according to claim 1, characterized in that: If the number of random times is greater than the number of all word lines of NAND Flash, an error is returned.

3. The method for improving NAND Flash read and write operation verification efficiency according to claim 1, wherein: Customize the number of random addresses when performing read and write verification on NAND Flash.

4. The method for improving NAND Flash read and write operation verification efficiency according to claim 3, wherein: The customized random number is used to traverse all addresses in NAND and automatically output all addresses.

5. The method for improving NAND Flash read and write operation verification efficiency according to claim 4, characterized in that: According to the random word line address, it is also used to determine the number of pages contained in the word line, determine the writing method and output the address of each page.

6. A system for improving the efficiency of NAND Flash read and write operation verification, characterized in that: Including random number selection module, mode selection module, SLC mode module and TLC mode module; The random number selection module is used to select a random number of times or to traverse the entire NADN Flash address; The mode selection module is used to select to enter the SLC mode or the TLC mode through a command; The SLC mode module is used to directly return the word line address through the SLC address model in the system and mark the address that has been used; The TLC mode module is used to first return the number of pages contained in this word line and the available read and write modes through the TLC address model in the system. The user can select the corresponding SLC, MLC, or TLC read and write operations based on the number of pages.

7. The system for improving NAND Flash read and write operation verification efficiency according to claim 6, characterized in that: The system for improving the efficiency of NAND Flash read and write operation verification also includes a random number judgment module, which is used to judge whether the random number exceeds a maximum value after selecting a random number. If it exceeds the maximum value, an error is displayed and the current operation is terminated. If it does not exceed the maximum value, the mode is selected.

8. The system for improving NAND Flash read and write operation verification efficiency according to claim 7, characterized in that: The system for improving the efficiency of NAND Flash read and write operation verification further includes an address marking module for marking used addresses after the TLC mode module outputs the word line address, and continuing to randomly select unmarked addresses based on the marked addresses until the entire NAND address is traversed or a specified number of random times is reached.

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