Gate driving circuit, driving method thereof, and display panel

Abstract

A gate driving circuit (100), a driving method thereof, and a display panel are provided. The gate driving circuit (100) includes a plurality of driving units (DU1, DU2) connected in cascade. Each driving unit (DU1, DU2) includes: N shift register units (120_1... 120_8); and mode control circuits (110_1, 110_2) connected to the N shift register units (120_1... 120_8). The mode control circuits (110_1, 110_2) are configured to receive control signals (SW1, SW2) for the driving unit (DU1, DU2), and connect the N shift register units (120_1... 120_8) in one of a plurality of resolution modes under the control of the control signals (SW1, SW2).

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a gate driving circuit, a driving method of the gate driving circuit, and a display panel. Background Art

[0002] In display technologies, a gate driving circuit is generally used to drive a plurality of sub-pixels for display. For example, the gate driving circuit generates a gate driving signal, and the gate driving signal is provided to a plurality of sub-pixels to turn on the sub-pixels. A data signal is applied to the turned-on sub-pixels to cause the sub-pixels to emit light. The gate driving circuit generally includes a plurality of cascaded shift registers to generate a plurality of sequentially shifted output signals as the gate driving signal. However, the conventional technology cannot flexibly control the display resolution of different regions on the display panel. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a gate driving circuit including a plurality of cascaded driving units, each driving unit including:

[0004] N shift register units; and

[0005] a mode control circuit connected to the N shift register units, the mode control circuit being configured to receive a control signal for the driving unit and connect the N shift register units in one of a plurality of resolution modes under the control of the control signal.

[0006] For example, the plurality of resolution modes include a first resolution mode, a second resolution mode, and a third resolution mode, and the mode control circuit is configured to:

[0007] in the first resolution mode, cascade-connect the N shift register units;

[0008] in the second resolution mode, divide the N shift register units into M groups, cascade-connect the M groups, and connect the shift register units in each group in parallel;

[0009] in the third resolution mode, connect the N shift register units in parallel.

[0010] For example, N = 4, M = 2, the N shift register units include a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit, and each shift register unit has a cascaded input terminal and a first cascaded output terminal, and the mode control circuit is configured to:

[0011] In the first resolution mode, connect the first cascaded output terminal of the n-th shift register unit to the cascaded input terminal of the (n + 1)-th shift register unit, and disconnect the cascaded input terminal of the n-th shift register unit from the cascaded input terminal of the (n + 1)-th shift register unit, where 1 ≤ n ≤ N - 1;

[0012] In the second resolution mode, disconnect the first cascaded output terminal of the first shift register unit from the cascaded input terminal of the second shift register unit, connect the first cascaded output terminal of the second shift register unit to the cascaded input terminal of the third shift register unit, disconnect the first cascaded output terminal of the third shift register unit from the cascaded input terminal of the fourth shift register unit, connect the cascaded input terminal of the first shift register unit to the cascaded input terminal of the second shift register unit, and connect the cascaded input terminal of the third shift register unit to the cascaded input terminal of the fourth shift register unit; and

[0013] In the third resolution mode, disconnect the first cascaded output terminal of the n-th shift register unit from the cascaded input terminal of the (n + 1)-th shift register unit, and connect the cascaded input terminal of the n-th shift register unit to the cascaded input terminal of the (n + 1)-th shift register unit.

[0014] For example, each of the first shift register unit, the second shift register unit, the third shift register unit, and the fourth shift register unit further has a reset terminal and a second cascaded output terminal, and the mode control circuit is further configured to:

[0015] In the first resolution mode, connect the reset terminal of the n-th shift register unit to the second cascaded output terminal of the (n + 1)-th shift register unit, and disconnect the reset terminal of the n-th shift register unit from the reset terminal of the (n + 1)-th shift register unit,

[0016] In the second resolution mode, disconnect the reset terminal of the first shift register unit from the second cascaded output terminal of the second shift register unit, connect the reset terminal of the second shift register unit to the second cascaded output terminal of the third shift register unit, disconnect the reset terminal of the third shift register unit from the second cascaded output terminal of the fourth shift register unit, connect the reset terminal of the first shift register unit to the reset terminal of the second shift register unit, disconnect the reset terminal of the second shift register unit from the reset terminal of the third shift register unit, and connect the reset terminal of the third shift register unit to the reset terminal of the fourth shift register unit; and

[0017] In the third resolution mode, disconnect the reset terminal of the nth shift register unit from the second cascaded output terminal of the (n + 1)th shift register unit, and connect the reset terminal of the nth shift register unit to the reset terminal of the (n + 1)th shift register unit.

[0018] For example, the control signals include a first control signal, a second control signal, a third control signal, and a fourth control signal, and the mode control circuit includes:

[0019] A first transistor, the gate of the first transistor is connected to receive the first control signal, the first pole of the first transistor is connected to the first cascaded output terminal of the first shift register unit, and the second pole of the first transistor is connected to the cascaded input terminal of the second shift register unit;

[0020] A second transistor, the gate of the second transistor is connected to receive the second control signal, the first pole of the second transistor is connected to the cascaded input terminal of the first shift register unit, and the second pole of the second transistor is connected to the cascaded input terminal of the second shift register unit;

[0021] A third transistor, the gate of the third transistor is connected to receive the third control signal, the first pole of the third transistor is connected to the first cascaded output terminal of the second shift register unit, and the second pole of the third transistor is connected to the cascaded input terminal of the third shift register unit;

[0022] A fourth transistor, the gate of the fourth transistor is connected to receive the fourth control signal, the first pole of the fourth transistor is connected to the cascaded input terminal of the first shift register unit, and the second pole of the fourth transistor is connected to the cascaded input terminal of the third shift register unit;

[0023] A fifth transistor, the gate of the fifth transistor is connected to the first control signal, the first pole of the fifth transistor is connected to the first cascaded output terminal of the third shift register unit, and the second pole of the fifth transistor is connected to the cascaded input terminal of the fourth shift register unit; and

[0024] A sixth transistor, the gate of the sixth transistor is connected to receive the second control signal, the first pole of the sixth transistor is connected to the cascaded input terminal of the third shift register unit, and the second pole of the sixth transistor is connected to the cascaded input terminal of the fourth transistor.

[0025] For example, the control signals further include a fifth control signal, and the mode control circuit further includes:

[0026] A seventh transistor, the gate of the seventh transistor is connected to receive the first control signal, the first pole of the seventh transistor is connected to the reset terminal of the first shift register unit, and the second pole of the seventh transistor is connected to the second cascaded output terminal of the second shift register unit;

[0027] The eighth transistor, the gate of the eighth transistor is connected to receive the fifth control signal, the first pole of the eighth transistor is connected to the reset terminal of the first shift register unit, and the second pole of the eighth transistor is connected to the reset terminal of the second shift register unit;

[0028] The ninth transistor, the gate of the ninth transistor is connected to receive the third control signal, the first pole of the ninth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the ninth transistor is connected to the second cascade output terminal of the third shift register unit;

[0029] The tenth transistor, the gate of the tenth transistor is connected to receive the fourth control signal, the first pole of the tenth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the tenth transistor is connected to the reset terminal of the third shift register unit;

[0030] The eleventh transistor, the gate of the eleventh transistor is connected to receive the first control signal, the first pole of the eleventh transistor is connected to the reset terminal of the third shift register unit, and the second pole of the eleventh transistor is connected to the second cascade output terminal of the fourth shift register unit; and

[0031] The twelfth transistor, the gate of the twelfth transistor is connected to receive the second control signal, the first pole of the twelfth transistor is connected to the reset terminal of the third shift register unit, and the second pole of the twelfth transistor is connected to the reset terminal of the fourth shift register unit.

[0032] For example, the first cascade output terminal of the Nth shift register unit in the ith - stage driving unit is connected to the cascade input terminal of the first shift register unit in the (i + 1)th - stage driving unit.

[0033] For example, the reset terminal of the Nth shift register unit in the ith - stage driving unit is connected to the second cascade output terminal of the first shift register unit in the (i + 1)th - stage driving unit.

[0034] For example, the multiple driving units are divided into multiple groups, and each group of driving units is connected to a group of control signal lines to receive the control signal for this group of driving units.

[0035] For example, each shift register unit includes a first shift register, a second shift register, and a third shift register, where

[0036] The input terminal of the first shift register serves as the cascade input terminal of the shift register unit, and the output terminal of the first shift register serves as the second cascade output terminal of the shift register unit;

[0037] The input terminal of the second shift register is connected to the output terminal of the first shift register; and

[0038] The input end of the third shift register is connected to the output end of the second shift register, and the output end of the third shift register serves as the first cascaded output end of the shift register unit.

[0039] For example, each of the first shift register, the second shift register, and the third shift register includes:

[0040] An input sub - circuit, connecting the input end of the shift register and the pull - up node, and configured to provide the signal at the input end to the pull - up node;

[0041] An output sub - circuit, connecting the pull - up node, the clock signal end of the shift register, and the output end, and configured to provide the signal at the clock signal end to the output end under the control of the potential of the pull - up node;

[0042] A control sub - circuit, connecting the pull - up node, the output end, and the pull - down node of the shift register, and configured to control the potential of the pull - down node based on the potential of the pull - up node, and pull down the potential of the output end under the control of the potential of the pull - down node.

[0043] For example, each of the first shift register, the second shift register, and the third shift register further includes:

[0044] A reset sub - circuit, connecting the pull - up node and the reset end of the shift register, and configured to reset the pull - up node according to the reset signal at the reset end, wherein the reset end of the third shift register in the shift register unit serves as the reset end of the shift register unit.

[0045] According to a second aspect of the present disclosure, there is provided a driving method for the gate driving circuit according to the first aspect of the present disclosure, including:

[0046] The mode control circuit of each driving unit among the plurality of driving units receives a control signal for this driving unit, and connects the N shift register units in one of a plurality of resolution modes under the control of the control signal,

[0047] The N connected shift register units in each driving unit generate an output signal.

[0048] For example, the plurality of resolution modes include a first resolution mode, a second resolution mode, and a third resolution mode, wherein,

[0049] In the first resolution mode, the mode control circuit cascades and connects the N shift register units, and the N shift register units generate sequentially shifted output signals;

[0050] In the second resolution mode, the mode control circuit divides the N shift register units into M groups, cascades the M groups, and connects the shift register units in each group in parallel. The shift register units in each group generate output signals in parallel, and a set of output signals generated by the (m + 1)-th group of shift register units is shifted relative to a set of output signals generated by the m-th group of shift register units, where m is an integer and 1 ≤ m ≤ M - 1;

[0051] In the third resolution mode, the mode control circuit connects the N shift register units in parallel, and the N shift register units generate output signals in parallel.

[0052] For example, N = 4 and M = 2. The N shift register units include a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit, where

[0053] In the first resolution mode, the mode control circuit connects the first cascaded output end of the n-th shift register unit to the cascaded input end of the (n + 1)-th shift register unit, and disconnects the cascaded input end of the n-th shift register unit from the cascaded input end of the (n + 1)-th shift register unit, where 1 ≤ n ≤ N - 1;

[0054] In the second resolution mode, the mode control circuit disconnects the first cascaded output end of the first shift register unit from the cascaded input end of the second shift register unit, and connects the cascaded input end of the second shift register unit to the cascaded input end of the first shift register unit; connects the first cascaded output end of the second shift register unit to the cascaded input end of the third shift register unit, and disconnects the cascaded input end of the third shift register unit from the cascaded input end of the second shift register unit; and disconnects the first cascaded output end of the third shift register unit from the cascaded input end of the fourth shift register unit, and connects the cascaded input end of the third shift register unit to the cascaded input end of the fourth shift register unit; and

[0055] In the third resolution mode, the mode control circuit disconnects the first cascaded output end of the n-th shift register unit from the cascaded input end of the (n + 1)-th shift register unit, and connects the cascaded input end of the n-th shift register unit to the cascaded input end of the (n + 1)-th shift register unit.

[0056] For example, the method further includes:

[0057] In the first resolution mode, the mode control circuit connects the reset terminal of the n-th shift register unit to the second cascaded output terminal of the (n + 1)-th shift register, and disconnects the reset terminal of the n-th shift register unit from the reset terminal of the (n + 1)-th shift register unit.

[0058] In the second resolution mode, the mode control circuit disconnects the reset terminal of the first shift register unit from the second cascaded output terminal of the second shift register unit, connects the reset terminal of the second shift register unit to the second cascaded output terminal of the third shift register unit, disconnects the reset terminal of the third shift register unit from the second cascaded output terminal of the fourth shift register unit, connects the reset terminal of the first shift register unit to the reset terminal of the second shift register unit, and connects the reset terminal of the third shift register unit to the reset terminal of the fourth shift register unit; and

[0059] In the third resolution mode, the mode control circuit disconnects the reset terminal of the n-th shift register unit from the second cascaded output terminal of the (n + 1)-th shift register unit, and connects the reset terminal of the n-th shift register unit to the reset terminal of the (n + 1)-th shift register unit.

[0060] For example, the mode control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, where

[0061] In the first resolution mode, the first control signal and the third control signal are at the first level, the second control signal and the fourth control signal are at the second level, the first transistor, the third transistor, and the fifth transistor are turned on, and the second transistor, the fourth transistor, and the sixth transistor are turned off;

[0062] In the second resolution mode, the second control signal and the third control signal are at the first level, the first control signal and the fourth control signal are at the second level, the second transistor, the third transistor, and the sixth transistor are turned on, and the first transistor, the fourth transistor, and the fifth transistor are turned off; and

[0063] In the third resolution mode, the second control signal and the fourth control signal are at the first level, the first control signal and the third control signal are at the second level, the second transistor, the fourth transistor, and the sixth transistor are turned on, and the first transistor, the third transistor, and the fifth transistor are turned off.

[0064] For example, the mode control circuit further includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, where

[0065] In the first resolution mode, the fifth control signal is at the second level, the seventh transistor, the ninth transistor, and the eleventh transistor are turned on, and the eighth transistor, the tenth transistor, and the twelfth transistor are turned off;

[0066] In the second resolution mode, the fifth control signal is at the first level, the eighth transistor, the ninth transistor, and the twelfth transistor are turned on, and the seventh transistor, the tenth transistor, and the eleventh transistor are turned off; and

[0067] In the third resolution mode, the fifth control signal is at the first level, the eighth transistor, the tenth transistor, and the twelfth transistor are turned on, and the seventh transistor, the ninth transistor, and the eleventh transistor are turned off.

[0068] According to a third aspect of the present disclosure, a gate driving circuit is provided, including:

[0069] A plurality of driving units, each driving unit including a plurality of cascaded shift registers;

[0070] A plurality of start signal lines, connected to the plurality of driving units in one-to-one correspondence, wherein each start signal line is connected to the first-stage shift register in the corresponding driving unit;

[0071] K clock signal lines, connected to the plurality of shift registers in each driving unit, where K is an integer greater than 1; and

[0072] A mode control circuit, connected to the K clock signal lines, the mode control circuit being configured to receive K initial clock signals and a control signal, and generate K clock signals based on the K initial clock signals in one of a first resolution mode, a second resolution mode, and a third resolution mode under the control of the control signal, and provide the generated K clock signals to the K clock signal lines respectively.

[0073] For example, the mode control circuit is configured to:

[0074] In the first resolution mode, generate K first clock signals that are sequentially shifted based on the K initial clock signals;

[0075] In the second resolution mode, generate K second clock signals that are divided into 2M groups based on the K initial clock signals, the plurality of second clock signals in each group being synchronized, and the (m + 1)-th group of second clock signals being shifted relative to the m-th group of second clock signals;

[0076] In the third resolution mode, K third clock signals divided into M groups are generated based on the K initial clock signals, multiple third clock signals in each group are synchronized, and the third clock signals of the (m'+1)-th group are shifted relative to the third clock signals of the m'-th group, where M is an integer greater than 1, both m and m' are integers, 1 ≤ m ≤ 2M - 1, and 1 ≤ m' ≤ M - 1.

[0077] For example, K = 8, M = 2, the control signals include a first control signal, a second control signal, a third control signal, and a fourth control signal, and the mode control circuit includes:

[0078] A first clock input terminal to an eighth clock input terminal are respectively connected to receive 8 initial clock signals;

[0079] A first clock output terminal to an eighth clock output terminal are connected in one-to-one correspondence with 8 clock signal lines;

[0080] A first mode control sub-circuit, configured to connect the second clock input terminal to the second clock output terminal, connect the fourth clock input terminal to the fourth clock output terminal, connect the sixth clock input terminal to the sixth clock output terminal, and connect the eighth clock input terminal to the eighth clock output terminal under the control of the first control signal;

[0081] A second mode control sub-circuit, configured to connect the third clock input terminal to the third clock output terminal and connect the seventh clock input terminal to the seventh clock output terminal under the control of the second control signal;

[0082] A third mode control sub-circuit, configured to connect the first clock output terminal to the second clock output terminal, connect the third clock output terminal to the fourth clock output terminal, connect the fifth clock output terminal to the sixth clock output terminal, and connect the seventh clock output terminal to the eighth clock output terminal under the control of the third control signal;

[0083] A fourth mode control sub-circuit, configured to connect the second clock output terminal to the third clock output terminal and connect the sixth clock output terminal to the seventh clock output terminal under the control of the fourth control signal.

[0084] For example, the first mode control sub-circuit includes:

[0085] A first transistor, the gate of the first transistor is connected to receive the first control signal, the first pole of the first transistor is connected to the second clock input terminal, and the second pole of the first transistor is connected to the second clock output terminal;

[0086] A second transistor, the gate of the second transistor is connected to receive the first control signal, the first pole of the second transistor is connected to the fourth clock input terminal, and the second pole of the second transistor is connected to the fourth clock output terminal;

[0087] A third transistor, the gate of the third transistor is connected to receive a first control signal, a first pole of the third transistor is connected to a sixth clock input terminal, and a second pole of the third transistor is connected to a sixth clock output terminal; and

[0088] A fourth transistor, the gate of the fourth transistor is connected to receive a first control signal, a first pole of the fourth transistor is connected to an eighth clock input terminal, and a second pole of the fourth transistor is connected to an eighth clock output terminal.

[0089] For example, the second mode control sub - circuit includes:

[0090] A fifth transistor, the gate of the fifth transistor is connected to receive a second control signal, a first pole of the fifth transistor is connected to a third clock input terminal, and a second pole of the fifth transistor is connected to a third clock output terminal; and

[0091] A sixth transistor, the gate of the sixth transistor is connected to receive a second control signal, a first pole of the sixth transistor is connected to a seventh clock input terminal, and a second pole of the sixth transistor is connected to a seventh clock output terminal.

[0092] For example, the third mode control sub - circuit includes:

[0093] A seventh transistor, the gate of the seventh transistor is connected to receive a third control signal, a first pole of the seventh transistor is connected to a first clock output terminal, and a second pole of the seventh transistor is connected to a second clock output terminal;

[0094] An eighth transistor, the gate of the eighth transistor is connected to receive a third control signal, a first pole of the eighth transistor is connected to a third clock output terminal, and a second pole of the eighth transistor is connected to a fourth clock output terminal;

[0095] A ninth transistor, the gate of the ninth transistor is connected to receive a third control signal, a first pole of the ninth transistor is connected to a fifth clock output terminal, and a second pole of the ninth transistor is connected to a sixth clock output terminal; and

[0096] A tenth transistor, the gate of the tenth transistor is connected to receive a third control signal, a first pole of the tenth transistor is connected to a seventh clock output terminal, and a second pole of the tenth transistor is connected to an eighth clock output terminal.

[0097] For example, the fourth mode control sub - circuit includes:

[0098] An eleventh transistor, the gate of the eleventh transistor is connected to receive a fourth control signal, a first pole of the eleventh transistor is connected to a second clock output terminal, and a second pole of the eleventh transistor is connected to a third clock output terminal; and

[0099] A twelfth transistor, the gate of the twelfth transistor is connected to receive a fourth control signal, a first pole of the twelfth transistor is connected to a sixth clock output terminal, and a second pole of the twelfth transistor is connected to a seventh clock output terminal.

[0100] For example, in each driving unit, the output terminal of the n-th stage shift register is connected to the input terminal of the (n + 1)-th stage shift register, and the output terminal of the (n + 1)-th stage shift register is connected to the reset terminal of the n-th stage shift register, where n is an integer greater than or equal to 1; and

[0101] The multiple shift registers in each driving unit are divided into at least one group, each group includes K cascaded shift registers, and the clock signal terminals of the K shift registers are connected to the K clock signal lines in a one-to-one correspondence.

[0102] According to a fourth aspect of the present disclosure, there is provided a driving method for a gate driving circuit according to the third aspect of the present disclosure, including:

[0103] The mode control circuit generates K clock signals based on the K initial clock signals in one of multiple resolution modes under the control of a control signal, and provides the generated K clock signals to the K clock signal lines respectively; and

[0104] A start signal is applied to at least one start signal line among multiple start signal lines to start the driving unit connected to the at least one start signal line, and the multiple shift registers in the started driving unit generate output signals according to the clock signals on the K clock signal lines.

[0105] For example, the multiple resolution modes include a first resolution mode, a second resolution mode, and a third resolution mode, where

[0106] In the first resolution mode, the mode control circuit generates K first clock signals that are sequentially shifted based on the K initial clock signals and provides them to the K clock signal lines respectively;

[0107] In the second resolution mode, the mode control circuit generates K second clock signals based on the K initial clock signals and provides them to the K clock signal lines respectively. The K second clock signals are divided into 2M groups, and the multiple second clock signals in each group are synchronized. The (m + 1)-th group of second clock signals is shifted relative to the m-th group of second clock signals;

[0108] In the third resolution mode, the mode control circuit generates K third clock signals based on the K initial clock signals and provides them to the K clock signal lines respectively. The K third clock signals are divided into M groups, and the multiple third clock signals in each group are synchronized. The (m'+1)-th group of third clock signals is shifted relative to the m'-th group of third clock signals, where M is an integer greater than 1, m and m' are both integers, 1 ≤ m ≤ 2M - 1, and 1 ≤ m' ≤ M - 1.

[0109] For example, K = 8, M = 2, where

[0110] In the first resolution mode, the first mode control sub-circuit connects the second clock input terminal to the second clock output terminal, the fourth clock input terminal to the fourth clock output terminal, the sixth clock input terminal to the sixth clock output terminal, and the eighth clock input terminal to the eighth clock output terminal; the second mode control sub-circuit connects the third clock input terminal to the third clock output terminal and the seventh clock input terminal to the seventh clock output terminal;

[0111] In the second resolution mode, the second mode control sub-circuit connects the third clock input terminal to the third clock output terminal and the seventh clock input terminal to the seventh clock output terminal; the third mode control sub-circuit connects the first clock output terminal to the second clock output terminal, the third clock output terminal to the fourth clock output terminal, the fifth clock output terminal to the sixth clock output terminal, and the seventh clock output terminal to the eighth clock output terminal;

[0112] In the third resolution mode, the third mode control sub-circuit connects the first clock output terminal to the second clock output terminal, the third clock output terminal to the fourth clock output terminal, the fifth clock output terminal to the sixth clock output terminal, and the seventh clock output terminal to the eighth clock output terminal; the fourth mode control sub-circuit connects the second clock output terminal to the third clock output terminal and the sixth clock output terminal to the seventh clock output terminal.

[0113] For example, in the first resolution mode, the first control signal and the second control signal are at the first level, the third control signal and the fourth control signal are at the second level, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are turned on, and the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are turned off;

[0114] In the second resolution mode, the first control signal and the fourth control signal are at the second level, the second control signal and the third control signal are at the first level, the first transistor, the second transistor, the third transistor, the fourth transistor, the eleventh transistor, and the twelfth transistor are turned off, and the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are turned on;

[0115] In the third resolution mode, the first control signal and the second control signal are at the second level, the third control signal and the fourth control signal are at the first level, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are turned off, and the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are turned on.

[0116] For example, the K initial clock signals are periodic signals with a duty cycle of 50%, where the (k + 1)-th initial clock signal is shifted by a unit scan time relative to the k-th initial clock signal, and the duration of the active level of each initial clock signal is 4 times the unit scan time.

[0117] For example, the K initial clock signals are periodic signals with a duty cycle of 12.5%, where the (k + 1)-th initial clock signal is shifted by a unit scan time relative to the k-th initial clock signal, and the duration of the active level of each initial clock signal is the unit scan time.

[0118] According to a fifth aspect of the present disclosure, a gate driving circuit is provided, including:

[0119] A plurality of driving units, each driving unit including a plurality of shift register units connected in cascade. Among the plurality of shift register units, the cascade output end of the n-th stage shift register unit is connected to the cascade input end of the (n + d)-th stage shift register unit;

[0120] A plurality of start signal lines, connected to the plurality of driving units in one-to-one correspondence, where each start signal line is connected to the cascade input ends of the first d stage shift register units in the corresponding driving unit, where both n and d are integers greater than or equal to 1;

[0121] K clock signal lines, connected to the clock signal terminals of the plurality of shift register units in each driving unit, where K = 2d.

[0122] For example, each shift register unit includes a first shift register, a second shift register, and a third shift register, where

[0123] The input end of the first shift register serves as the cascade input end of the shift register unit, the output end of the first shift register is connected to the input end of the second shift register, the output end of the second shift register is connected to the input end of the third shift register, and the output end of the third shift register serves as the cascade output end of the shift register unit; and

[0124] The clock signal terminals of the first shift register, the second shift register, and the third shift register serve as the clock signal terminals of the shift register unit.

[0125] For example, the plurality of shift register units in each driving unit are divided into at least one group, each group including K shift register units connected in cascade. Among the K shift register units:

[0126] The clock signal terminals of the first shift register and the third shift register of the k-th shift register unit are connected to the k-th clock signal line, where k is an integer and 1 ≤ k ≤ K;

[0127] The clock signal terminal of the second shift register of the k-th shift register unit is connected to the (k + d)-th clock signal line when k ≤ 2 / K, and is connected to the (k - d)-th clock signal line when 2 / K < k ≤ K.

[0128] For example, each of the first shift register, the second shift register, and the third shift register includes:

[0129] An input sub-circuit, connecting the input terminal of the shift register and the pull-up node, and configured to provide the signal at the input terminal to the pull-up node;

[0130] An output sub-circuit, connecting the pull-up node, the clock signal terminal of the shift register, and the output terminal, and configured to provide the signal at the clock signal terminal to the output terminal under the control of the potential of the pull-up node;

[0131] A control sub-circuit, connecting the pull-up node, the output terminal, and the pull-down node of the shift register, and configured to control the potential of the pull-down node based on the potential of the pull-up node, and pull down the potential of the output terminal under the control of the potential of the pull-down node.

[0132] For example, K = 8 and d = 4.

[0133] According to a sixth aspect of the present disclosure, there is provided a driving method for a gate driving circuit according to the fifth aspect of the present disclosure, including:

[0134] Applying K clock signals to K clock signal lines respectively and applying a start signal to at least one start signal line among the multiple start signal lines in one of multiple resolution modes,

[0135] The applied start signal causes the driving unit connected to the at least one start signal line to start, and multiple shift registers in the started driving unit generate output signals according to the clock signals on the K clock signal lines.

[0136] For example, in the first resolution mode, applying K first clock signals that are sequentially shifted to the K clock signal lines respectively, and applying a first start signal to at least one start signal line among the multiple start signal lines;

[0137] In the second resolution mode, applying K second clock signals to the K clock signal lines respectively, and applying a second start signal to at least one start signal line among the multiple start signal lines, where the K second clock signals are divided into 2M groups, multiple second clock signals in each group are synchronized, and the (m + 1)-th group of second clock signals is shifted relative to the m-th group of second clock signals;

[0138] In the third resolution mode, K third clock signals are respectively applied to the K clock signal lines, and a third start signal is applied to at least one start signal line among the multiple start signal lines, where the K third clock signals are divided into M groups, multiple third clock signals in each group are synchronized, and the (m'+1)-th group of third clock signals is shifted relative to the m'-th group of third clock signals, where M is an integer greater than 1, both m and m' are integers, 1 ≤ m ≤ 2M - 1, and 1 ≤ m' ≤ M - 1.

[0139] For example, the first clock signal, the second clock signal, and the third clock signal are all periodic signals with a duty cycle of 50%, where,

[0140] the duration of the effective level within the signal period of the first clock signal is 4H, where the (k + 1)-th first clock signal is shifted by H relative to the k-th first clock signal, where H represents the unit scanning time;

[0141] the duration of the effective level within the signal period of the second clock signal is 2H, where the (m + 1)-th group of second clock signals is shifted by H relative to the m-th group of second clock signals;

[0142] the duration of the effective level within the signal period of the third clock signal is H, where the (m'+1)-th group of third clock signals is shifted by H relative to the m'-th group of third clock signals.

[0143] For example, the duration of the effective level of the first start signal is 4H, the duration of the effective level of the second start signal is 2H, and the duration of the effective level of the third start signal is H.

[0144] For example, the multiple driving units include a first driving unit, a second driving unit, and a third driving unit, and the multiple start signal lines include a first start signal line, a second start signal line, and a third start signal line respectively connected to the first driving unit, the second driving unit, and the third driving unit, where,

[0145] in the first time period, K clock signals are applied to the K clock signal lines in the first resolution mode and the first start signal is applied to the second start signal line, and the second driving unit generates an output signal according to the applied K clock signals in response to the applied first start signal;

[0146] in the second time period, K clock signals are applied to the K clock signal lines in the second resolution mode or the third resolution mode and the second start signal or the third start signal is applied to the first start signal line, and the first driving unit generates an output signal according to the applied K clock signals in response to the applied second start signal or third start signal;

[0147] In a third time period, K clock signals are applied to K clock signal lines in a first resolution mode and a first start signal is applied to a second start signal line, and a second driving unit generates an output signal in response to the applied first start signal according to the applied K clock signals;

[0148] In a fourth time period, K clock signals are applied to K clock signal lines in a second resolution mode or a third resolution mode and a third start signal is applied to a third start signal line, and a third driving unit generates an output signal in response to the applied third start signal according to the applied K clock signals.

[0149] For example, K = 8 and M = 2.

[0150] According to a seventh aspect of the present disclosure, a display panel is provided, including the above-mentioned gate driving circuit. Description of the Drawings

[0151] Figure 1 A schematic diagram of a display panel according to an embodiment of the present disclosure is shown.

[0152] Figure 2A A circuit diagram of a shift register according to an embodiment of the present disclosure is shown.

[0153] Figure 2B A circuit diagram of a shift register according to another embodiment of the present disclosure is shown.

[0154] Figure 3 A block diagram of a gate driving circuit according to an embodiment of the present disclosure is shown.

[0155] Figure 4 Shows Figure 3 An example structural diagram of the gate driving circuit.

[0156] Figure 5A Shows Figure 4 An equivalent schematic diagram of the gate driving circuit in a first resolution mode.

[0157] Figure 5B Shows Figure 4 A signal timing diagram of the gate driving circuit in a first resolution mode.

[0158] Figure 6A Shows Figure 4 An equivalent schematic diagram of the gate driving circuit in a second resolution mode.

[0159] Figure 6B Shows Figure 4 A signal timing diagram of the gate driving circuit in a second resolution mode.

[0160] Figure 7A ShowsFigure 4 Equivalent schematic diagram of the gate driving circuit in the third resolution mode.

[0161] Figure 7B Shows Figure 4 Signal timing diagram of the gate driving circuit in the third resolution mode.

[0162] Figure 8A Shows Figure 4 Equivalent schematic diagram of the gate driving circuit in the second and third resolution modes.

[0163] Figure 8B Shows Figure 4 Signal timing diagram of the gate driving circuit in the second and third resolution modes.

[0164] Figure 9 Shows Figure 3 Another example structural diagram of the gate driving circuit.

[0165] Figure 10 Shows the structural diagram of the gate driving circuit according to another embodiment of the present disclosure.

[0166] Figure 11 Shows Figure 10 Example circuit diagram of the mode control circuit in the gate driving circuit.

[0167] Figure 12 Shows Figure 10 Timing diagram of the initial clock signal received by the gate driving circuit.

[0168] Figure 13 Shows Figure 10 Signal timing diagram of the gate driving circuit in the first resolution mode.

[0169] Figure 14 Shows Figure 10 Signal timing diagram of the gate driving circuit in the second resolution mode.

[0170] Figure 15 Shows Figure 10 Signal timing diagram of the gate driving circuit in the third resolution mode.

[0171] Figure 16 Shows Figure 10 An example of the signal timing diagram of the gate driving circuit in the first, second, and third resolution modes.

[0172] Figure 17 Shows Figure 10 Another example of the signal timing diagram of the gate driving circuit in the first, second, and third resolution modes.

[0173] Figure 18 A block diagram of a gate driving circuit according to another embodiment of the present disclosure is shown.

[0174] Figure 19 Shows Figure 18 An example structural diagram of the gate driving circuit of

[0175] Figure 20 Shows Figure 19 The signal timing diagram of the gate driving circuit of

[0176] Figure 21 Shows Figure 19 The signal timing diagram of the gate driving circuit of

[0177] Figure 22 Shows Figure 19 The signal timing diagram of the gate driving circuit of

[0178] Figure 23 Shows Figure 19 The timing diagram of the start signal of the gate driving circuit of Detailed implementation manners

[0179] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as any limitation to the present disclosure, but merely examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure.

[0180] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second" and similar terms used in the embodiments of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components.

[0181] In addition, in the description of the embodiments of the present disclosure, the terms "connected" or "connected to" may mean that two components are directly connected, or may mean that two components are connected via one or more other components. In addition, these two components may be connected or coupled by wired or wireless means.

[0182] In addition, in the description of the embodiments of the present disclosure, the terms "first level" and "second level" are only used to distinguish the different amplitudes of two levels. For example, in the following, the case where the "first level" is a high level and the "second level" is a low level is taken as an example for description. Those skilled in the art can understand that the present disclosure is not limited thereto.

[0183] The transistors adopted in the embodiments of the present disclosure can all be thin-film transistors or field-effect transistors or other devices with the same characteristics. Preferably, the thin-film transistors used in the embodiments of the present disclosure can be oxide semiconductor transistors or low-temperature poly-silicon (LTPS, Low Temperature Poly-silicon) thin-film transistors. Since the source and drain of the thin-film transistors adopted here are symmetric, their source and drain can be interchanged. In the embodiments of the present disclosure, one of the source and drain is called the first pole, and the other of the source and drain is called the second pole. In the following examples, N-type thin-film transistors are taken as an example for description. Those skilled in the art can understand that the embodiments of the present disclosure can obviously be applied to the case of P-type thin-film transistors.

[0184] Figure 1 A schematic diagram of a display panel according to an embodiment of the present disclosure is shown. As Figure 1 shown, the display panel includes pixel units PXL arranged in an array, and each pixel unit PXL includes a plurality of sub-pixels, which are a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B in this embodiment. In Figure 1 , each row of pixel units PXL includes three rows of sub-pixels, where the red sub-pixels R are arranged in the first row, the green sub-pixels G are arranged in the second row, and the blue sub-pixels are arranged in the third row. The display panel further includes a gate driving circuit 100, and the gate driving circuit 100 is connected to multiple rows of pixel units through a plurality of gate lines G1, G2,... GX. For example, it is connected to the red sub-pixel R of the first row of pixel units PXL through the gate line G1, connected to the green sub-pixel G of the first row of pixel units PXL through the gate line G2, connected to the blue sub-pixel B of the first row of pixel units PXL through the gate line G3, and so on.

[0185] The gate driving circuit 100 of the embodiments of the present disclosure may include a plurality of shift registers, and the shift registers of the embodiments of the present disclosure will be exemplified below with reference to Figure 2A and Figure 2B for illustration.

[0186] Figure 2Ashows a circuit diagram of a shift register according to an embodiment of the present disclosure. As Figure 2A shown, the shift register may include an input sub-circuit 10, an output sub-circuit 20, and a control sub-circuit 30.

[0187] The input sub-circuit 10 is connected to the input terminal IN of the shift register and the pull-up node PU, and can provide the signal of the input terminal IN to the pull-up node PU. In Figure 2A this case, the input sub-circuit 10 may include a transistor M1. The gate and the first pole of the transistor M1 are connected to the input terminal IN, and the second pole is connected to the pull-up node PU.

[0188] The output sub-circuit 20 is connected to the pull-up node PU, the clock signal terminal CK of the shift register, and the output terminal OUT of the shift register, and can provide the signal of the clock signal terminal CK to the output terminal OUT under the control of the potential of the pull-up node PU. In Figure 2A this case, the output sub-circuit 20 may include a transistor M7 and a capacitor C1. The gate of the transistor M7 is connected to the pull-up node PU, the first pole is connected to the clock signal terminal CK, and the second pole is connected to the output terminal OUT. One end of the capacitor C1 is connected to the pull-up node PU, and the other end is connected to the output terminal OUT.

[0189] The control sub-circuit 30 is connected to the pull-up node PU, the output terminal OUT, and the pull-down node PD of the shift register, and can control the potential of the pull-down node PD based on the potential of the pull-up node, and pull down the potential of the output terminal OUT under the control of the potential of the pull-down node PD. In Figure 2A this case, the control sub-circuit 30 may include transistors M2, M4, and M6, and a capacitor C2. The gate and the first pole of the transistor M2 are connected to the control terminal CKB, and the second pole is connected to the pull-down node PD. The gate of the transistor M4 is connected to the pull-up node PU, the first pole is connected to the reference signal terminal VGL, and the second pole is connected to the pull-down node PD. The gate of the transistor M6 is connected to the pull-down node PD, the first pole is connected to the reference signal terminal VGL, and the second pole is connected to the output terminal OUT. One end of the capacitor C2 is connected to the gate of the transistor M6, and the other end is connected to the first pole of the transistor M6. In some embodiments, the control sub-circuit 30 may further include a transistor M3. The gate of the transistor M3 is connected to the pull-down node PD, the first pole is connected to the reference signal terminal VGL, and the second pole is connected to the pull-up node PU. In some embodiments, the control sub-circuit 30 may further include a transistor M5. The gate of the transistor M5 is connected to the output terminal OUT, the first pole is connected to the reference signal terminal VGL, and the second pole is connected to the pull-down node PD.

[0190] When the input signal at the input terminal IN is at a high level, the transistor M1 conducts, thereby providing the high level of the input terminal IN to the pull-up node PU, and the transistor M7 conducts; when the input signal at the input terminal IN becomes low, the capacitor C1 causes the pull-up node PU to remain at a high level. During the period when the pull-up node PU is at a high level, the high level of the clock signal at the clock signal terminal CK arrives, and the conducting transistor M7 provides the high level of the clock signal terminal CK to the output terminal OUT, thereby generating a high-level output signal. The high level at the output terminal OUT causes the transistor M5 to conduct, pulling the pull-down node PD to a low level. Thereafter, the clock signal at the clock signal terminal CK is at a low level, the control terminal CKB is at a high level, and the conducting transistor M7 provides the low level of the clock signal terminal CK to the output terminal OUT, thereby generating a low-level output signal, further causing the transistor M5 to turn off; and the high level at the control terminal CKB causes the transistor M2 to conduct, thereby causing the pull-down node PD to become high. The high level at the pull-down node PD causes the transistor M3 to conduct, thereby pulling the pull-up node PU to a low level.

[0191] Figure 2B The circuit diagram of a shift register according to another embodiment of the present disclosure is shown. Figure 2B The shift register of Figure 2A is similar in structure to the shift register of Figure 2B The shift register of

[0192] As Figure 2B shown, the shift register includes an input sub-circuit 10, an output sub-circuit 20', a control sub-circuit 30', and a reset sub-circuit 40.

[0193] The input sub-circuit 10 may have the same structure as the above-mentioned input sub-circuit 10, which will not be elaborated here.

[0194] The reset sub-circuit 40 is connected to the pull-up node PU and the reset terminal RST, and can reset the pull-up node PU according to the reset signal at the reset terminal RST. In Figure 2B , the reset sub-circuit 40 includes a transistor M8, the gate of the transistor M8 is connected to the reset terminal RST, the first pole is connected to the first reference signal terminal LVGL. The reset sub-circuit 40 may further include a transistor M9, the gate of the transistor M9 is connected to the total reset terminal TRST, the first pole is connected to the first reference signal terminal LVGL, and the second pole is connected to the pull-up node PU.

[0195] The output sub - circuit 20' includes a first output sub - circuit, a second output sub - circuit, and a third output sub - circuit. The first output sub - circuit may include a transistor M10. The gate of the transistor M10 is connected to the pull - up node, the first pole is connected to the first clock signal terminal CK1, and the second pole is connected to the first output terminal OUT1. The second output sub - circuit may have the same structure as the above - mentioned output sub - circuit 20 and includes a transistor M7 and a capacitor C1. The first pole of the transistor M7 is connected to the second clock signal terminal CK2, and the second pole is connected to the second output terminal OUT2. The third output sub - circuit may include a transistor M11 and a capacitor C3. The gate of the transistor M11 is connected to the pull - up node PU, the first pole is connected to the third clock signal terminal CK3, and the second pole is connected to the third output terminal OUT; one end of the capacitor C3 is connected to the gate of the transistor M11, and the other end is connected to the second pole of the transistor M11. At least one of the second output terminal OUT2 and the third output terminal OUT3 may be used to connect to a sub - pixel to apply a gate driving signal thereto. The first output terminal OUT1 may be used to connect to other shift registers to achieve the cascading of the shift registers.

[0196] The control sub - circuit 30' may include a first control sub - circuit and a second control sub - circuit. The first control sub - circuit may have the same structure as the above - mentioned control sub - circuit 30, and includes transistors M2, M3, M4, M5, and M6. The gate and the first pole of transistor M2 are connected to the first control terminal CKA, and the second pole is connected to the first pull - down node PD_A. The gate of transistor M3 is connected to the first pull - down node PD_A, the first pole is connected to the pull - up node PU, and the second pole is connected to the first reference signal terminal LVGL. The gate of transistor M4 is connected to the pull - up node PU, the first pole is connected to the first reference signal terminal LVGL, and the second pole is connected to the first pull - down node PD_A. The gate of transistor M5 is connected to the second output terminal OUT, the first pole is connected to the first reference signal terminal LVGL, and the second pole is connected to the first pull - down node PD_A. The gate of transistor M6 is connected to the first pull - down node PD_A, the first pole is connected to the second reference signal terminal VGL, and the second pole is connected to the second output terminal OUT2. The second control sub - circuit may include transistors M12, M13, M14, M15, M16, and M17. The gate and the first pole of transistor M12 are connected to the second control terminal CKB, and the second pole is connected to the second pull - down node PD_B. The gate of transistor M13 is connected to the pull - up node PU, the first pole is connected to the first reference signal terminal VGL, and the second pole is connected to the second pull - down node PD_B. The gate of transistor M14 is connected to the second pull - down node PD_B, the first pole is connected to the first reference signal terminal LVGL, and the second pole is connected to the first output terminal OUT1. The gate of transistor M15 is connected to the second pull - down node PD_B, the first pole is connected to the first reference signal terminal VGL, and the second pole is connected to the third output terminal OUT3. The gate of transistor M16 is connected to the second pull - down node PD_B, the first pole is connected to the first reference signal terminal LVGL, and the second pole is connected to the pull - up node PU. The gate of transistor M17 is connected to the third output terminal OUT3, the first pole is connected to the first reference signal terminal LVGL, and the second pole is connected to the second pull - down node PD_B. The control sub - circuit 30' may further include transistors M18 and M19, where the gates of transistors M18 and M19 are both connected to the input terminal IN, the first poles of transistors M18 and M19 are both connected to the first reference signal terminal LVGL, the second pole of transistor M18 is connected to the first pull - down node PD_A, and the second pole of transistor M19 is connected to the second pull - down node PD_B. The control sub - circuit 30' may further include a transistor M20, the gate of transistor M20 is connected to the first pull - down node PD_A, the first pole is connected to the first reference signal terminal LVGL, and the second pole is connected to the first output terminal OUT1.

[0197] Although the shift register is illustrated above with a specific structure, embodiments of the present disclosure are not limited thereto, and any suitable shift register may be employed as needed.

[0198] Figure 3 A block diagram of a gate driving circuit according to an embodiment of the present disclosure is shown.

[0199] As Figure 3 shown, the gate driving circuit 100 includes a plurality of driving units connected in cascade, such as driving units DU1 and DU2. Each driving unit includes N shift register units and a mode control circuit, where N is an integer greater than 1. For example, when N = 4, the driving unit DU1 includes shift register units 120_1, 120_2, 120_3, and 120_4 and a mode control circuit 110_1, and the driving unit DU2 includes shift register units 120_5, 120_6, 120_7, and 120_8 and 110_2. Each shift register unit may include a plurality of shift registers, which will be described in detail below.

[0200] In the driving unit DU1, the mode control circuit 110_1 is connected to the shift register units 120_1, 120_2, 120_3, and 120_4. The mode control circuit 110_1 can receive a control signal SW_1 for the driving unit DU1 and connect the shift register units 120_1, 120_2, 120_3, and 120_4 in one of a plurality of resolution modes under the control of the control signal SW_1.

[0201] In the driving unit DU2, the mode control circuit 110_2 is connected to the shift register units 120_5, 120_6, 120_7, and 120_8. The mode control circuit 110_2 can receive a control signal SW_2 for the driving unit DU2 and connect the shift register units 120_5, 120_6, 120_7, and 120_8 in one of a plurality of resolution modes under the control of the control signal SW_2.

[0202] For example, the plurality of resolution modes may include a first resolution mode, a second resolution mode, and a third resolution mode. The operations in the three resolution modes will be described below taking the driving unit DU1 as an example.

[0203] In the first resolution mode, the mode control circuit 110_1 can connect the shift register units 120_1, 120_2, 120_3, and 120_4 in cascade.

[0204] In the second resolution mode, the mode control circuit 110_1 can divide the shift register units 120_1, 120_2, 120_3, and 120_4 into M groups, cascade-connect the M groups, and connect the shift register units in each group in parallel. For example, the shift register units 120_1 and 120_2 are divided into the first group, the shift register units 120_3 and 120_4 are divided into the second group, the first group and the second group are cascade-connected, the shift register units 120_1 and 120_2 in the first group are connected in parallel, and the shift register units 120_3 and 120_4 in the second group are connected in parallel.

[0205] In the third resolution mode, the mode control circuit 110_1 can connect the shift register units 120_1, 120_2, 120_3, and 120_4 in parallel.

[0206] The operation of the driving unit DU2 at the three resolutions is similar to that of the driving unit DU1, and will not be elaborated here.

[0207] Figure 4 Shows Figure 3 An example structural diagram of the gate driving circuit.

[0208] As Figure 4 shown, the gate driving circuit 100A includes driving units DU1 and DU2. In each of the driving units DU1 and DU2, each shift register unit includes a first shift register, a second shift register, and a third shift register. Each of the first shift register, the second shift register, and the third shift register can adopt the shift register structure of any of the above embodiments. For example, they can all be implemented as Figure 2AThe shift register shown. In the driving unit DU1, the shift register unit 120_1 (first shift register unit) includes shift registers GOA1, GOA2, and GOA3 as the first shift register, second shift register, and third shift register respectively. The shift register unit 120_2 (second shift register unit) includes shift registers GOA4, GOA5, and GOA6 as the first shift register, second shift register, and third shift register respectively. The shift register unit 120_3 (third shift register unit) includes shift registers GOA7, GOA8, and GOA9 as the first shift register, second shift register, and third shift register respectively. The shift register unit 120_4 (fourth shift register unit) includes shift registers GOA10, GOA11, and GOA12 as the first shift register, second shift register, and third shift register respectively. Similarly, in the driving unit DU2, the shift register unit 120_5 (first shift register unit) includes shift registers GOA13, GOA14, and GOA15. The shift register unit 120_6 (second shift register unit) includes shift registers GOA16, GOA17, and GOA18. The shift register unit 120_7 (third shift register unit) includes shift registers GOA19, GOA20, and GOA21. The shift register unit 120_8 (fourth shift register unit) includes shift registers GOA22, GOA23, and GOA24.

[0209] Each shift register unit has a cascaded input terminal and a first cascaded output terminal.

[0210] For example, in the shift register unit 120_1 of the driving unit DU1, the input terminal IN of the shift register GOA1 serves as the cascaded input terminal of the shift register unit 120_1 to receive the start signal STV. The input terminal IN of the shift register GOA2 is connected to the output terminal OUT of the shift register GOA1. The input terminal IN of the shift register GOA3 is connected to the output terminal OUT of the shift register GOA2, and the output terminal OUT of the shift register GOA3 serves as the first cascaded output terminal of the shift register unit 120_1. The connection manners of the respective shift registers in the shift register units 120_2, 120_3, and 120_4 of the driving unit DU1 are similar to those of the shift register unit 120_1 and will not be elaborated here.

[0211] Similarly, in the shift register unit 120_5 of the driving unit DU2, the input terminal IN of the shift register GOA13 serves as the cascaded input terminal of the shift register unit 120_5 to receive the cascaded output signal from the driving unit DU1; the input terminal IN of the shift register GOA14 is connected to the output terminal OUT of the shift register GOA13; the input terminal IN of the shift register GOA15 is connected to the output terminal OUT of the shift register GOA14, and the output terminal OUT of the shift register GOA15 serves as the first cascaded output terminal of the shift register unit 120_5. The connection manners of the respective shift registers in the shift register units 120_6, 120_7, and 120_8 of the driving unit DU2 are similar to those of the shift register unit 120_5, and will not be elaborated here.

[0212] As Figure 4 shown, the first cascaded output terminal (i.e., the output terminal OUT of the shift register GOA12) of the shift register unit 120_4 in the driving unit DU1 is connected to the cascaded input terminal (i.e., the input terminal IN of the shift register GOA13) of the shift register unit 120_5 in the driving unit DU2, thereby realizing the cascaded connection between the driving units DU1 and DU2.

[0213] In each driving unit, the mode control circuit may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, and the control signals for each driving unit may include a first control signal, a second control signal, a third control signal, and a fourth control signal.

[0214] For example, in the driving unit DU1, the mode control circuit 110_1 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; the control signal SW_1 for the driving unit DU1 may include a first control signal SW1, a second control signal SW2, a third control signal SW3, and a fourth control signal SW4.

[0215] The gate of the first transistor T1 is connected to receive the first control signal SW1, the first pole of the first transistor T1 is connected to the first cascaded output terminal (i.e., the output terminal OUT of the shift register GOA3) of the first shift register unit 120_1, and the second pole of the first transistor T1 is connected to the cascaded input terminal (i.e., the input terminal IN of the shift register GOA4) of the second shift register unit 120_2.

[0216] The gate of the second transistor T2 is connected to receive a second control signal SW2. The first pole of the second transistor T2 is connected to the cascade input terminal of the first shift register unit 120_1 (i.e., the input terminal IN of the shift register GOA1). The second pole of the second transistor T2 is connected to the cascade input terminal of the second shift register unit 120_2 (i.e., the input terminal IN of the shift register GOA4).

[0217] The gate of the third transistor T3 is connected to receive a third control signal SW3. The first pole of the third transistor T3 is connected to the first cascade output terminal of the second shift register unit 120_2 (i.e., the output terminal OUT of the shift register GOA6). The second pole of the third transistor T3 is connected to the cascade input terminal of the third shift register unit 120_3 (i.e., the input terminal IN of the shift register GOA7).

[0218] The gate of the fourth transistor T4 is connected to receive a fourth control signal SW4. The first pole of the fourth transistor T4 is connected to the cascade input terminal of the first shift register unit 120_2 (i.e., the input terminal IN of the shift register GOA1). The second pole of the fourth transistor T4 is connected to the cascade input terminal of the third shift register unit 120_3 (i.e., the input terminal IN of the shift register GOA7).

[0219] The gate of the fifth transistor T5 is connected to the first control signal SW1. The first pole of the fifth transistor T5 is connected to the first cascade output terminal of the third shift register unit 120_3 (i.e., the output terminal OUT of the shift register GOA9). The second pole of the fifth transistor T5 is connected to the cascade input terminal of the fourth shift register unit 120_4 (i.e., the input terminal IN of the shift register GOA10).

[0220] The gate of the sixth transistor T6 is connected to receive a second control signal SW2. The first pole of the sixth transistor T6 is connected to the cascade input terminal of the third shift register unit 120_3 (i.e., the input terminal IN of the shift register GOA7). The second pole of the sixth transistor T6 is connected to the cascade input terminal of the fourth transistor T4 (i.e., the input terminal IN of the shift register GOA10).

[0221] Similarly, in the driving unit DU2, the mode control circuit 110_2 may include a first transistor T1', a second transistor T2', a third transistor T3', a fourth transistor T4', a fifth transistor T5', and a sixth transistor T6'; the control signal SW_2 for the driving unit DU2 may include a first control signal SW1', a second control signal SW2', a third control signal SW3', and a fourth control signal SW4'. The connection manners of the first transistor T1', the second transistor T2', the third transistor T3', the fourth transistor T4', the fifth transistor T5', and the sixth transistor T6' are similar to those of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in the mode control circuit 110_1, and will not be described herein again.

[0222] In some embodiments, multiple driving units in the gate driving circuit 100A may be divided into multiple groups, and each group of driving units is connected to a group of control signal lines to receive the control signal for the group of driving units, so as to perform display driving in different resolution modes between groups.

[0223] In Figure 4 the gate driving circuit 100A, the driving units DU1 and DU2 are divided into different groups. For example, the driving unit DU1 is divided into a first group for performing display driving in a first resolution mode, and the driving unit DU2 is divided into a second group for performing display driving in the first resolution mode. The boundary between the first group and the second group is as Figure 4 shown by the center dash line. In this case, the driving unit DU1 in the first group may be connected to the first to fourth control signal lines to receive the control signals SW1 to SW4 for the first group of driving units respectively; the driving unit DU2 in the second group may be connected to the fifth to eighth control signal lines to receive the control signals SW1' to SW4' for the second group of driving units respectively.

[0224] In some embodiments, if the driving units DU1 and DU2 are grouped into the same group, the gates of the first transistors T1 of the driving unit DU1 and the gates of the first transistors T1' of the driving unit DU2 may be both connected to the first control signal line to receive the same first control signal. In this case, the first control signal SW1 for the driving unit DU1 and the first control signal for the driving unit DU2 are the same signal. Similarly, the gates of the second transistors T2 of the driving unit DU1 and the gates of the first transistors T2' of the driving unit DU2 may be connected to the second control signal line to receive the same second control signal, the gates of the third transistors T3 of the driving unit DU1 and the gates of the third transistors T3' of the driving unit DU2 may be connected to the third control signal line to receive the same third control signal, and the gates of the fourth transistors T4 of the driving unit DU1 and the gates of the fourth transistors T4' of the driving unit DU2 may be connected to the fourth control signal line to receive the same fourth control signal.

[0225] The operation of the Figure 4 gate driving circuit 100A in different resolution modes will be described below with reference to Table 1. For the sake of simplicity, the description will be made by taking one driving unit DU1 as an example.

[0226] Table 1

[0227] First resolution mode Second resolution mode Third resolution mode SW1 1 0 0 SW2 0 1 1 SW3 1 1 0 SW4 0 0 1

[0228] In Table 1, 0 represents a low level and 1 represents a high level. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, 0 may represent a high level and 1 may represent a low level.

[0229] In the first resolution mode, as shown in Table 1, the first control signal SW1 and the third control signal SW3 are high levels, and the second control signal SW2 and the fourth control signal SW4 are low levels, such that Figure 4 in the mode control circuit 110_1 of the Figure 5A , the transistors T1, T3, and T5 are turned on, and the transistors T2, T4, and T6 are turned off, thereby obtaining the equivalent circuit structure as shown in

[0230] As shown in Figure 5AAs shown, when the transistor T1 is turned on, the first cascaded output terminal of the first shift register unit 120_1 is connected to the cascaded input terminal of the second shift register unit 120_2. When the transistor T2 is turned off, the cascaded input terminal of the first shift register unit 120_1 is disconnected from the cascaded input terminal of the second shift register unit 120_2. Similarly, when the transistor T3 is turned on, the first cascaded output terminal of the second shift register unit 120_2 is connected to the cascaded input terminal of the third shift register unit 120_3. When the transistors T2 and T4 are turned off, the cascaded input terminal of the second shift register unit 120_2 is disconnected from the cascaded input terminal of the third shift register unit 120_3. When the transistor T5 is turned on, the first cascaded output terminal of the third shift register unit 120_3 is connected to the cascaded input terminal of the fourth shift register unit 120_4. When the transistor T6 is turned off, the cascaded input terminal of the third shift register unit 120_3 is disconnected from the cascaded input terminal of the fourth shift register unit 120_4. In this way, the cascaded connection of the shift register units 120_1 to 120_4 is achieved.

[0231] As Figure 5B shown, in Figure 5A the equivalent circuit structure shown, the shift register GOA1 can generate an output signal G1 in response to the input of the start signal STV. This output signal G1 is provided as an input signal to the shift register GOA2, causing the shift register GOA2 to generate an output signal G2 that is shifted relative to the output signal G1, and so on, to obtain sequentially shifted output signals G1 to G12. Combining Figure 1 , the gate driving circuit can achieve the sequential scanning of the sub-pixels in the display area row by row by generating an output signal as Figure 5B shown, so as to perform display driving at the highest first resolution.

[0232] In the second resolution mode, as shown in Table 1, the first control signal SW1 and the second control signal SW4 are at low level, and the second control signal SW2 and the third control signal SW3 are at high level, such that Figure 4 in the mode control circuit 110_1, the transistors T1, T4, and T5 are turned off, and the transistors T2, T3, and T6 are turned on, thereby obtaining the equivalent circuit structure as Figure 6A shown.

[0233] As Figure 6AAs shown, when transistor T1 is turned off, the first cascaded output terminal of the first shift register unit 120_1 is disconnected from the cascaded input terminal of the second shift register unit 120_2. When transistor T2 is turned on, the cascaded input terminal of the second shift register unit 120_2 is connected to the cascaded input terminal of the first shift register unit 120_1. When transistor T3 is turned on, the first cascaded output terminal of the second shift register unit 120_2 is connected to the cascaded input terminal of the third shift register unit 120_3. When the fourth transistor T4 is turned off, the cascaded input terminal of the third shift register unit 120_3 is disconnected from the cascaded input terminal of the second shift register unit 120_2. When transistor T5 is turned off, the first cascaded output terminal of the third shift register unit 120_3 is disconnected from the cascaded input terminal of the fourth shift register unit 120_4. When transistor T6 is turned on, the cascaded input terminal of the third shift register unit is connected to the cascaded input terminal of the fourth shift register unit. In this way, the shift register units 120_1 to 120_4 are divided into two groups. The first group includes the shift register units 120_1 and 120_2 connected in parallel, and the second group includes the shift register units 120_3 and 120_4 connected in parallel. The first group and the second group are cascaded.

[0234] As Figure 6B shown, in Figure 6A the equivalent circuit structure shown, in the first group of shift register units 120_1 and 120_2, the shift registers GOA1 and GOA4 can generate output signals G1 and G4 in parallel in response to the input of the start signal STV. The output signals G1 and G4 are respectively provided as input signals to the shift registers GOA2 and GOA5, so that the shift register GOA2 generates an output signal G2 shifted relative to the output signal G1, and the shift register GOA5 generates an output signal G5 shifted relative to the output signal G4. The output signals G2 and G5 are respectively provided as input signals to the shift registers GOA3 and GOA6, so that the shift register GOA3 generates an output signal G3 shifted relative to the output signal G2, and the shift register GOA6 generates an output signal G5 shifted relative to the output signal G5. In this way, the first group of shift register units 120_1 and 120_2 generate output signals in parallel, that is, the output signals G1 to G3 generated by the shift register unit 120_1 are synchronized with the output signals G4 to G6 generated by the shift register unit 120_2 respectively.

[0235] The output signal G6 is provided as an input signal to the shift register GOA7 in the shift register unit 120_3 and GOA10 in the shift register unit 120_4, such that the shift register units 120_3 and 120_4 generate two sets of output signals in parallel in a manner similar to that described above, and the output signals G7 to G12 are shifted relative to the output signals G1 to G6 respectively. In this way, a set of output signals generated by the second set of shift register units 120_3 and 120_4 is shifted relative to a set of output signals generated by the first set of shift register units 120_1 and 120_2.

[0236] Combined Figure 1 , the gate driving circuit can achieve grouped scanning of the sub-pixels in the display area by generating output signals as shown in Figure 6B . For example, every two rows of pixel units are taken as a group. First, the red sub-pixels in the first and second row pixel units are scanned simultaneously, then the green sub-pixels in these two rows of pixel units are scanned simultaneously, and finally the blue sub-pixels in these two rows of pixel units are scanned simultaneously. After scanning the first and second row pixel units, the third and fourth row pixel units are scanned in the same way. Thus, display driving with a second resolution lower than the first resolution can be achieved. For example, the second resolution can be one-half of the first resolution.

[0237] In the third resolution mode, as shown in Table 1, the first control signal SW1 and the third control signal SW3 are at low level, and the second control signal SW2 and the fourth control signal SW4 are at high level, such that Figure 4 in the mode control circuit 110_1, the transistors T1, T3, and T5 are turned off, and the transistors T2, T4, and T6 are turned on, thereby obtaining the equivalent circuit structure as shown in Figure 7A .

[0238] As shown in Figure 7AAs shown, when transistor T1 is turned off, the first cascaded output terminal of the first shift register unit 120_1 is disconnected from the cascaded input terminal of the second shift register unit 120_2. When transistor T2 is turned on, the cascaded input terminal of the first shift register unit 120_1 is connected to the cascaded input terminal of the second shift register unit 120_2. Similarly, when transistor T3 is turned off, the first cascaded output terminal of the second shift register unit 120_2 is disconnected from the cascaded input terminal of the third shift register unit 120_3. When transistors T2 and T4 are turned on, the cascaded input terminal of the second shift register unit 120_2 is connected to the cascaded input terminal of the third shift register unit 120_3. When transistor T5 is turned off, the first cascaded output terminal of the third shift register unit 120_3 is disconnected from the cascaded input terminal of the fourth shift register unit 120_4. When transistor T6 is turned on, the cascaded input terminal of the third shift register unit 120_3 is connected to the cascaded input terminal of the fourth shift register unit 120_4. In this way, the parallel connection of the shift register units 120_1 to 120_4 is achieved.

[0239] As Figure 7B shown, in Figure 7A the equivalent circuit structure shown, the shift registers GOA1, GOA4, GOA7, and GOA10 can generate output signals G1, G4, G7, and G10 in parallel in response to the input of the start signal STV. The output signals G1, G4, G7, and G10 are respectively provided as input signals to the shift registers GOA2, GOA5, GOA8, and GOA11, such that the shift registers GOA2, GOA5, GOA8, and GOA11 generate shifted output signals G2, G5, G8, and G11 in parallel. The output signals G2, G5, G8, and G11 are respectively provided as input signals to the shift registers GOA3, GOA6, GOA9, and GOA12, such that the shift registers GOA3, GOA6, GOA9, and GOA12 generate shifted output signals G3, G6, G9, and G12 in parallel. In this way, the shift register units 120_1 to 120_4 generate output signals in parallel.

[0240] Combined with Figure 1 , the gate driving circuit generates as Figure 7BThe output signal shown can achieve grouped scanning of the sub-pixels in the display area. For example, every four rows of pixel units are taken as a group. First, the red sub-pixels in the first to fourth row pixel units are scanned simultaneously, then the green sub-pixels in these 4 row pixel units are scanned simultaneously, and finally the blue sub-pixels in these 4 row pixel units are scanned simultaneously. After scanning the first to fourth row pixel units, the fifth to eighth row pixel units are scanned in the same way. Thus, display driving with a third resolution lower than the second resolution can be achieved. For example, the third resolution can be one-half of the second resolution.

[0241] Figure 8A shows Figure 4 The equivalent schematic diagrams of the gate driving circuit 100A in the second resolution and third resolution modes are shown. In some embodiments, the sub-pixels in the display area can be divided into multiple groups. For example, multiple rows of sub-pixels located in the central area of the display area are divided into the first group, and multiple rows of sub-pixels located in the areas on both sides of the central area along the column direction are respectively divided into the second group and the third group. The multiple driving units in the gate driving circuit of the embodiments of the present disclosure are also correspondingly divided into multiple groups, and each group of driving units is connected to a group of sub-pixels, so that the sub-pixels in each group can be independently driven to be displayed at different resolutions. For example, the sub-pixels in the central area are driven to be displayed at a higher resolution, while the sub-pixels in the areas on both sides are driven to be displayed at a lower resolution.

[0242] As Figure 8A shown, the driving unit DU1 and the driving unit DU2 are respectively divided into two groups for display driving in different resolution modes. In this case, for example, the mode control circuit 110_1 in the driving unit DU1 can connect the shift register units 120_1 to 120_4 in the second resolution mode under the control of the control signals SW1 to SW4, obtaining the equivalent circuit structure as Figure 6A shown. The mode control circuit 110_2 in the driving unit DU2 can connect the shift register units 120_5 to 120_8 in the third resolution mode under the control of the control signals SW1’ to SW4’, obtaining the equivalent circuit structure as Figure 7A shown. The driving unit DU1 and the driving unit DU2 are cascaded, so that the output signal G12 of the shift register GOA12 is provided as an input signal to the shift registers GOA13, GOA16, GOA19, and GOA22 of the driving unit DU2.

[0243] During the working process, as Figure 8B shown, the shift register units 120_1 to 120_4 connected in the second resolution mode generate as Figure 6BThe output signals G1 to G12 shown. The output signal G12 of the shift register GOA12 is provided as an input signal to the shift registers GOA13, GOA16, GOA19, and GOA22 of the driving unit DU2, such that the shift register units 120_5 to 120_8 connected in the third resolution mode generate output signals G13 to G24 similar to Figure 7B shown. In this way, the driving unit DU1 can drive multiple rows of sub-pixels connected thereto to display at the second resolution, and the driving unit DU2 can drive multiple rows of sub-pixels connected thereto to display at the third resolution, thereby realizing multi-resolution display in regions. As can be seen from Figure 8B compared with the first resolution mode, the second resolution mode shortens the scanning time (the time required for the gate driving circuit to scan all sub-pixels). In this embodiment, the scanning time is shortened by half; and the third resolution mode further shortens the scanning time compared with the second resolution. With the frame time length unchanged, the shortening of the scanning time makes the blanking period increase accordingly.

[0244] Figure 9 shows Figure 3 Another example structural diagram of the gate driving circuit.

[0245] Figure 9 The gate driving circuit 100B of Figure 4 is similar to the gate driving circuit 100A of

[0246] except that at least each shift register unit further has a reset terminal and the mode control circuit is also connected to the reset terminals of each shift register unit. For the sake of simplicity, the different parts will be mainly described in detail below. Figure 9 As shown in Figure 4 similar to

[0247] the driving unit DU1 includes four shift register units, where the first shift register unit includes shift registers GOA1 to GOA3, the second shift register unit includes shift registers GOA4 to GOA6, the third shift register unit includes shift registers GOA7 to GOA9, and the fourth shift register unit includes shift registers GOA10 to GOA12. Figure 4 Different from Figure 9 each shift register in the shift register unit of Figure 2BIt is implemented by the described shift register. In this case, in each shift register unit, the output terminal of the first shift register can be used as the second cascaded output terminal of the shift register unit, and the output terminal and the reset terminal of the third shift register can be used as the first cascaded output terminal and the reset terminal of the shift register unit respectively. For example, in the shift register unit 120_1, the output terminal of the shift register GOA1 is used as the second cascaded output terminal of the shift register unit 120_1, the output terminal of the shift register GOA3 is used as the first cascaded output terminal of the shift register unit 120_1, and the reset terminal RST of the shift register GOA3 is used as the reset terminal of the shift register unit 120_1; in the shift register unit 120_2, the output terminal of the shift register GOA4 is used as the second cascaded output terminal of the shift register unit 120_2, the output terminal of the shift register GOA6 is used as the first cascaded output terminal of the shift register unit 120_2, and the reset terminal RST of the shift register GOA4 is used as the reset terminal of the shift register unit 120_2, and so on. The reset terminal of the fourth shift register unit of the driving unit DU1 (i.e., the reset terminal RST of the shift register GOA12) is connected to the second cascaded output terminal of the first shift register unit in the driving unit DU2 (i.e., the output terminal OUT of the shift register GOA13), so as to realize the cascading of the driving unit DU1 and the driving unit DU2.

[0248] The mode control circuit includes a first mode control sub - circuit 1101 and a second mode control sub - circuit 1102. The first mode control sub - circuit 1101 has the same structure as the above - mentioned mode control circuit 110_1, including a first transistor T1 to a sixth transistor T6, which will not be elaborated here. The second mode control sub - circuit 1102 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12. The gate of the seventh transistor T7 is connected to receive a first control signal SW1, the first pole is connected to the reset terminal of the first shift register unit (i.e., the reset terminal RST of the shift register GOA3), and the second pole is connected to the second cascaded output terminal of the second shift register unit (i.e., the output terminal of the shift register GOA4). The gate of the eighth transistor T8 is connected to receive a fifth control signal SW5, the first pole is connected to the reset terminal of the first shift register unit (i.e., the reset terminal RST of the shift register GOA3), and the second pole is connected to the reset terminal of the second shift register unit (i.e., the reset terminal RST of the shift register GOA6). The gate of the ninth transistor T9 is connected to receive a third control signal SW3, the first pole is connected to the reset terminal of the second shift register unit (i.e., the reset terminal RST of the shift register GOA6), and the second pole is connected to the second cascaded output terminal of the third shift register unit (i.e., the output terminal OUT of the shift register GOA7). The gate of the tenth transistor T10 is connected to receive a fourth control signal SW4, the first pole is connected to the reset terminal of the second shift register unit (i.e., the reset terminal RST of the shift register GOA6), and the second pole is connected to the reset terminal of the third shift register unit (i.e., the reset terminal of the shift register GOA9). The gate of the eleventh transistor T11 is connected to receive a first control signal SW1, the first pole is connected to the reset terminal of the third shift register unit (i.e., the reset terminal RST of the shift register GOA9), and the second pole is connected to the second cascaded output terminal of the fourth shift register unit (i.e., the output terminal of the shift register GOA10). The gate of the twelfth transistor T12 is connected to receive a second control signal SW2, the first pole is connected to the reset terminal of the third shift register unit (i.e., the reset terminal RST of the shift register GOA9), and the second pole is connected to the reset terminal of the fourth shift register unit (i.e., the reset terminal RST of the shift register GOA12).

[0249] The driving method of the gate driving circuit will be described below with reference to Table 2 Figure 9 will be described as follows.

[0250] Table 2

[0251] First resolution mode Second resolution mode Third resolution mode SW1 1 0 0 SW2 0 1 1 SW3 1 1 0 SW4 0 0 1 SW5 0 1 1

[0252] In Table 2, 0 represents a low level and 1 represents a high level. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, 0 may represent a high level and 1 may represent a low level.

[0253] In the first resolution mode, as shown in Table 2, the first control signal SW1 and the third control signal SW3 are at high level, and the second control signal SW2, the fourth control signal SW4, and the fifth control signal SW5 are at low level. The first mode control sub-circuit 1101 cascades the respective shift registers in the manner described above for reference Figure 5A The second mode control sub-circuit 1102 connects the reset terminal of the n-th shift register unit to the second cascaded output terminal of the (n + 1)-th shift register unit, and disconnects the reset terminal of the n-th shift register unit from the reset terminal of the (n + 1)-th shift register unit, where 1 ≤ n ≤ 3. As Figure 9 shown, the high levels of the first control signal SW1 and the third control signal SW3 turn on the transistors T7, T9, and T11, and the low levels of the second control signal SW2, the fourth control signal SW4, and the fifth control signal SW5 turn off the transistors T8, T10, and T12, thereby connecting the reset terminal RST of the shift register GOA3 to the output terminal OUT of the shift register GOA4 and disconnecting the reset terminal RST of the shift register GOA3 from the reset terminal of the shift register GOA6; connecting the reset terminal RST of the shift register GOA6 to the output terminal OUT of the shift register GOA7 and disconnecting the reset terminal RST of the shift register GOA6 from the reset terminal RST of the shift register GOA9; connecting the reset terminal RST of the shift register GOA9 to the output terminal OUT of the shift register GOA10 and disconnecting the reset terminal RST of the shift register GOA9 from the reset terminal RST of the shift register GOA12.

[0254] In the second resolution mode, as shown in Table 2, the second control signal SW2, the third control signal SW3, and the fifth control signal SW5 are at high level, and the first control signal SW1 and the fourth control signal SW4 are at low level. The first mode control sub-circuit 1101 operates in accordance with the above reference Figure 6AThe respective shift register units are grouped and connected in the described manner. The second mode control sub-circuit 1102 disconnects the reset terminal of the first shift register unit (i.e., the reset terminal RST of the shift register GOA3) from the second cascaded output terminal of the second shift register unit (i.e., the output terminal OUT of the shift register GOA4), connects the reset terminal of the second shift register unit (i.e., the reset terminal RST of the shift register GOA6) to the second cascaded output terminal of the third shift register unit (i.e., the output terminal OUT of the shift register GOA7), disconnects the reset terminal of the third shift register unit (i.e., the reset terminal RST of the shift register GOA9) from the second cascaded output terminal of the fourth shift register unit (i.e., the output terminal OUT of the shift register GOA10), connects the reset terminal of the first shift register unit (i.e., the reset terminal RST of the shift register GOA3) to the reset terminal of the second shift register unit (i.e., the reset terminal RST of the shift register GOA6), disconnects the reset terminal of the second shift register unit (i.e., the reset terminal RST of the shift register GOA6) from the reset terminal of the third shift register unit (i.e., the reset terminal RST of the shift register GOA9), and connects the reset terminal of the third shift register unit (i.e., the reset terminal RST of the shift register GOA9) to the reset terminal of the fourth shift register unit (i.e., the reset terminal RST of the shift register GOA12).

[0255] In the third resolution mode, as shown in Table 2, the second control signal SW2, the fourth control signal SW4, and the fifth control signal SW are at high level, and the first control signal SW1 and the third control signal SW3 are at low level. The first mode control sub-circuit 1101 connects the respective shift registers in parallel in the manner described above with reference to Figure 7A The respective shift register units are connected in parallel in the described manner. The second mode control sub-circuit 1102 disconnects the reset terminal of the n-th shift register unit from the second cascaded output terminal of the (n + 1)-th shift register unit, and connects the reset terminal of the n-th shift register unit to the reset terminal of the (n + 1)-th shift register unit, where 1 ≤ n ≤ 3. As Figure 9As shown, when the second control signal SW2, the fourth control signal SW4, and the fifth control signal SW are at high level, transistors T8, T10, and T12 are turned on, and when the first control signal SW1 and the third control signal SW3 are at low level, transistors T7, T9, and T11 are turned off, thereby disconnecting the reset terminal RST of the shift register GOA3 from the output terminal OUT of the shift register GOA4, disconnecting the reset terminal RST of the shift register GOA6 from the output terminal OUT of the shift register GOA7, disconnecting the reset terminal RST of the shift register GOA9 from the output terminal OUT of the shift register GOA10, connecting the reset terminal RST of the shift register GOA3 to the reset terminal RST of the shift register GOA6, connecting the reset terminal RST of the shift register GOA6 to the reset terminal RST of the shift register GOA9, and connecting the reset terminal RST of the shift register GOA9 to the reset terminal RST of the shift register GOA12.

[0256] Figure 10 FIG. shows a structural diagram of a gate driving circuit according to another embodiment of the present disclosure.

[0257] The gate driving circuit 200 includes a plurality of driving units, and each driving unit includes a plurality of cascaded shift registers. For Figure 10 sake of simplicity, two driving units DU1 and DU2 are taken as examples for illustration. As Figure 10 shown, the driving unit DU1 includes a plurality of cascaded shift registers GOA1, GOA2,... GOA8, and the driving unit DU2 includes a plurality of cascaded shift registers GOA9, GOA10,.... For the sake of description, it is illustrated that the driving unit DU1 includes 8 shift registers, however, the embodiments of the present disclosure are not limited thereto, and each driving unit may include other numbers of shift registers according to needs. Each of the shift registers GOA1, GOA2,... may adopt the shift register structure according to any embodiment of the present disclosure, for example, implemented by the shift register described above with reference to Figure 2B description.

[0258] The gate driving circuit 200 further includes a plurality of start signal lines connected to the plurality of driving units in one-to-one correspondence, such as the start signal line STV1 connected to the driving unit DU1 and the start signal line STV2 connected to the driving unit DU2. The start signal line STV1 is connected to the first-stage shift register GOA1 in the driving unit DU1, and the start signal line STV2 is connected to the first-stage shift register GOA9 in the driving unit DU2.

[0259] The gate driving circuit 200 further includes K clock signal lines, where K is an integer greater than 1. For example, in Figure 10In the case where K = 8, eight clock signal lines CLK1 to CLK8 are connected to respective shift registers in each of the driving units DU1 and DU2.

[0260] The gate driving circuit 200 further includes a mode control circuit 210. The mode control circuit 210 is connected to the K clock signal lines CLK1 to CLK8. The mode control circuit 210 can receive K initial clock signals clk1 to clk8 and a control signal SW, and generate K clock signals based on the K initial clock signals clk1 to clk8 in one of a first resolution mode, a second resolution mode, and a third resolution mode under the control of the control signal SW, and supply the generated K clock signals to the K clock signal lines CLK1 to CLK8 respectively. For example, in the first resolution mode, the mode control circuit 210 can generate K first clock signals that are sequentially shifted based on the K initial clock signals. In the second resolution mode, the mode control circuit 210 can generate K second clock signals that are divided into 2M groups based on the K initial clock signals, multiple second clock signals in each group are synchronized, and the (m + 1)-th group of second clock signals is shifted relative to the m-th group of second clock signals. In the third resolution mode, the mode control circuit 210 can generate K third clock signals that are divided into M groups based on the K initial clock signals, multiple third clock signals in each group are synchronized, and the (m'+ 1)-th group of third clock signals is shifted relative to the m'-th group of third clock signals, where M is an integer greater than 1, both m and m' are integers, 1 ≤ m ≤ 2M - 1, and 1 ≤ m' ≤ M - 1.

[0261] In some embodiments, in each driving unit, the output end of the n-th stage shift register is connected to the input end of the (n + 1)-th stage shift register, and the output end of the (n + 1)-th stage shift register is connected to the reset end of the n-th stage shift register, where n is an integer greater than or equal to 1. The multiple shift registers in each driving unit are divided into at least one group, and each group includes K cascaded shift registers, and the clock signal ends of the K shift registers are connected to the K clock signal lines in a one-to-one correspondence.

[0262] For example, in Figure 10 the shown driving unit DU1, the output end OUT of the first stage shift register GOA1 is connected to the input end IN of the second stage shift register GOA2, and the output end OUT of the second stage shift register GOA2 is connected to the reset end RST of the first stage shift register GOA1; the output end OUT of the second stage shift register GOA2 is connected to the input end IN of the third shift register GOA3, and the output end OUT of the third stage shift register GOA3 is connected to the reset end RST of the second stage shift register GOA2, and so on. In Figure 10In the driving unit DU1, the first-stage shift register GOA1 to the eighth-stage shift register GOA8 are grouped together, and the clock signal terminals CK of the first-stage shift register GOA1 to the eighth-stage shift register GOA8 are respectively connected to the clock signal lines CLK1 to CLK8 in a one-to-one correspondence. If the driving unit DU1 includes more shift registers, for example, 16 shift registers, the first-stage to eighth-stage shift registers can be divided into the first group and connected to the clock signal lines CLK1 to CLK8 in a one-to-one correspondence in the above manner, and the ninth-stage to sixteenth-stage shift registers can be divided into the second group and connected to the clock signal lines CLK1 to CLK8 in a one-to-one correspondence in the above manner. In Figure 10 In the driving unit DU2 shown, the first-stage shift register GOA9, the second-stage shift register GOA10... are connected in a manner similar to the shift registers GOA1 to GOA8 in the driving unit 1, which will not be elaborated here.

[0263] Figure 11 shows Figure 10 an example circuit diagram of the mode control circuit in the gate driving circuit.

[0264] As Figure 11 shown, the mode control circuit 210 includes a first clock input terminal to an eighth clock input terminal, which are respectively connected to receive 8 initial clock signals clk1 to clk8. The mode control circuit 210 further includes a first clock output terminal to an eighth clock output terminal, which are respectively connected to the 8 clock signal lines CLK1 to CLK8 in a one-to-one correspondence. In some embodiments, the first clock input terminal and the first clock output terminal of the mode control circuit 210 can be connected. For example, the first clock signal line CLK1 can be implemented to receive the first initial clock signal clk1. For the convenience of description, hereinafter, clk1 to clk8 will be used to represent the first clock input terminal to the eighth clock input terminal respectively, and CLK1 to CLK8 will be used to represent the first clock output terminal to the eighth clock output terminal respectively.

[0265] The mode control circuit 210 further includes a first mode control sub-circuit 2101, a second mode control sub-circuit 2102, a third mode control sub-circuit 2103, and a second mode control sub-circuit 2104.

[0266] The first mode control sub-circuit 2101 can, under the control of the first control signal SW1, connect the second clock input terminal clk2 to the second clock output terminal CLK8, connect the fourth clock input terminal clk4 to the fourth clock output terminal CLK4, connect the sixth clock input terminal clk6 to the sixth clock input terminal CLK6, and connect the eighth clock input terminal clk8 to the eighth clock output terminal CLK8. For example, in Figure 11In it, the first mode control sub-circuit 2101 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4. The gates of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all connected to receive a first control signal SW1. A first pole of the first transistor T1 is connected to a second clock input terminal clk2, and a second pole is connected to a second clock output terminal CLK2. A first pole of the second transistor T2 is connected to a fourth clock input terminal clk4, and a second pole is connected to a fourth clock output terminal CLK4. A first pole of the third transistor T3 is connected to a sixth clock input terminal clk6, and a second pole is connected to a sixth clock input terminal CLK6. A first pole of the fourth transistor T4 is connected to an eighth clock input terminal clk8, and a second pole is connected to an eighth clock output terminal CLK8.

[0267] The second mode control sub-circuit 2102 can, under the control of a second control signal SW2, connect a third clock input terminal clk3 to a third clock output terminal CLK3, and connect a seventh clock output terminal clk7 to a seventh clock output terminal CLK7. For example, in Figure 11 it, the second mode control sub-circuit 2102 includes a fifth transistor T5 and a sixth transistor T6. The gates of the fifth transistor T5 and the sixth transistor T6 are all connected to receive the second control signal SW2. A first pole of the fifth transistor T5 is connected to the third clock input terminal clk3, and a second pole is connected to the third clock output terminal CLK3. A first pole of the sixth transistor T6 is connected to the seventh clock output terminal clk7, and a second pole is connected to the seventh clock output terminal CLK7.

[0268] The third mode control sub-circuit 2103 can, under the control of a third control signal SW3, connect a first clock output terminal CLK1 to a second clock output terminal CLK2, connect a third clock output terminal CLK3 to a fourth clock output terminal CLK4, connect a fifth clock output terminal CLK5 to a sixth clock output terminal CLK6, and connect a seventh clock output terminal CLK7 to an eighth clock output terminal CLK8. For example, in Figure 11 it, the third mode control sub-circuit 2103 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The gates of the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all connected to receive the third control signal SW3. A first pole of the seventh transistor T7 is connected to the first clock output terminal CLK1, and a second pole is connected to the second clock output terminal CLK2. A first pole of the eighth transistor T8 is connected to the third clock output terminal CLK3, and a second pole is connected to the fourth clock output terminal CLK4. A first pole of the ninth transistor T9 is connected to the fifth clock output terminal CLK5, and a second pole is connected to the sixth clock output terminal CLK6. A first pole of the tenth transistor T10 is connected to the seventh clock output terminal CLK7, and a second pole is connected to the eighth clock output terminal CLK8.

[0269] The fourth mode control sub-circuit 2104 can connect the second clock output terminal CLK2 to the third clock output terminal CLK3 and connect the sixth clock output terminal CLK6 to the seventh clock output terminal CLK7 under the control of the fourth control signal SW4. For example, in Figure 11 , the fourth mode control sub-circuit 2104 includes an eleventh transistor T11 and a twelfth transistor T12. The gates of the eleventh transistor T11 and the twelfth transistor T12 are both connected to receive the fourth control signal SW4. The first pole of the eleventh transistor T11 is connected to the second clock output terminal CLK2, and the second pole is connected to the third clock output terminal CLK3. The first pole of the twelfth transistor T12 is connected to the sixth clock output terminal CLK6, and the second pole is connected to the seventh clock output terminal CLK7.

[0270] During operation, the mode control circuit 210 generates K clock signals based on the K initial clock signals clk1 to clk8 in one of multiple resolution modes under the control of a control signal, and supplies the generated K clock signals to the K clock signal lines CLK1 to CLK8 respectively. A start signal is applied to at least one start signal line (e.g., STV1) among the multiple start signal lines STV1 and STV2 to start the driving unit connected to the at least one start signal line. For example, when the start signal on the start signal line STV1 starts the driving unit DU1, the multiple shift registers GOA1 to GOA8 in the started driving unit DU1 generate output signals G1 to G8 respectively according to the clock signals on the clock signal lines CLK1 to CLK8. When the start signal on the start signal line STV2 starts the driving unit DU2, the multiple shift registers GOA9, GOA10,... in the started driving unit DU2 generate output signals G9, G10,... respectively according to the clock signals on the clock signal lines CLK1 to CLK8.

[0271] Next, in combination with Figure 10 and Figure 11 , with reference to Table 3 and Figures 12 to 17 , the driving method of the above-mentioned gate driving circuit 200 will be described in detail. For the sake of simplicity, one driving unit DU1 in Figure 10 will be taken as an example for illustration. The working principle of the driving unit DU2 is similar to that of the driving unit DU1 and will not be elaborated here.

[0272] Table 3

[0273] First resolution mode Second resolution mode Third resolution mode SW1 1 0 0 SW2 1 1 0 SW3 0 1 1 SW4 0 0 1

[0274] In Table 3, 0 represents a low level and 1 represents a high level. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, 0 may represent a high level and 1 may represent a low level.

[0275] Figure 12 shows Figure 10 the timing diagram of the initial clock signal received by the gate driving circuit of. As Figure 12 shown, the initial clock signals clk1 to clk8 are sequentially shifted clock signals, where the (k + 1)-th initial clock signal is shifted by a unit scan time H with respect to the k-th initial clock signal, and the active level duration of each of the initial clock signals clk1 to clk8 is 4H. Here, the unit scan time can be the time required to scan one row of sub-pixels.

[0276] In the first resolution mode, as shown in Table 3, the first control signal SW1 and the second control signal SW2 are at a high level, and the third control signal SW3 and the fourth control signal SW4 are at a low level. Figure 11 In, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on, and the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned off. The first mode control sub-circuit 2101 connects the second clock input terminal clk2 to the second clock output terminal CLK2, connects the fourth clock input terminal clk4 to the fourth clock output terminal CLK4, connects the sixth clock input terminal clk6 to the sixth clock output terminal CLK6, and connects the eighth clock input terminal clk8 to the eighth clock output terminal CLK8. The second mode control sub-circuit 2102 connects the third clock input terminal clk3 to the third clock output terminal CLK3, and connects the seventh clock input terminal clk7 to the seventh clock output terminal CLK7.

[0277] In this way, as Figure 13 shown, the mode control circuit generates 8 sequentially shifted first clock signals based on the initial clock signals clk1 to clk8 and supplies them to the clock signal lines CLK1 to CLK8 respectively. Figure 10 In, the shift registers GOA1 to GOA8 generate sequentially shifted output signals G1 to G8 based on the clock signals on the clock signal lines CLK1 to CLK8, as Figure 13 shown.

[0278] In the second resolution mode, as shown in Table 3, the first control signal SW1 and the fourth control signal SW4 are at a low level, and the second control signal SW2 and the third control signal SW3 are at a high level. Figure 11The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the eleventh transistor T11, and the twelfth transistor T12 in [circuit] are turned off, and the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned on. The second mode control sub-circuit 2102 connects the third clock input terminal clk3 to the third clock output terminal CLK3, and connects the seventh clock input terminal clk7 to the seventh clock output terminal CLK7. The third mode control sub-circuit 2103 connects the first clock output terminal CLK1 to the second clock output terminal CLK2, connects the third clock output terminal CLK3 to the fourth clock output terminal CLK4, connects the fifth clock output terminal CLK5 to the sixth clock output terminal CLK6, and connects the seventh clock output terminal CLK7 to the eighth clock output terminal CLK8.

[0279] In this way, the mode control circuit generates eight second clock signals based on the initial clock signals clk1 to clk8 and supplies them to the clock signal lines CLK1 to CLK8 respectively. As Figure 14 shown, the second clock signals on the clock signal lines CLK1 to CLK8 are divided into 2M groups. For example, when M = 2, they are divided into 4 groups. The first group includes the clock signal lines CLK1 and CLK2, the second group includes the clock signal lines CLK3 and CLK4, the third group includes the clock signal lines CLK5 and CLK6, and the fourth group includes the clock signal lines CLK7 and CLK8. The second clock signal on the clock signal line CLK1 is synchronized with the second clock signal on CLK2, the second clock signal on the clock signal line CLK3 is synchronized with the second clock signal on CLK4, and so on. The second clock signals on the second group of clock signal lines CLK3 and CLK4 are shifted relative to the second clock signals on the first group of clock signal lines CLK1 and CLK2, the second clock signals on the third group of clock signal lines CLK5 and CLK6 are shifted relative to the second clock signals on the second group of clock signal lines CLK3 and CLK4, and the second clock signals on the fourth group of clock signal lines CLK7 and CLK8 are shifted relative to the second clock signals on the third group of clock signal lines CLK5 and CLK6. Figure 10 The shift registers GOA1 to GOA8 in [circuit] generate output signals G1 to G8 accordingly based on the clock signals on the clock signal lines CLK1 to CLK8. As Figure 14 shown, the output signals G1 and G2 are synchronized, the output signals G3 and G4 are synchronized, and any one of the output signals G3 and G4 is shifted relative to any one of the output signals G1 and G2, and so on.

[0280] In the third resolution mode, as shown in Table 3, the first control signal SW1 and the second control signal SW2 are at low level, and the third control signal SW3 and the fourth control signal SW4 are at high level. Figure 11 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in Figure 11 are turned off, and the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned on. The third mode control sub - circuit 2103 connects the first clock output terminal CLK1 to the second clock output terminal CLK2, connects the third clock output terminal CLK3 to the fourth clock output terminal CLK4, connects the fifth clock output terminal CLK5 to the sixth clock output terminal CLK6, and connects the seventh clock output terminal CLK7 to the eighth clock output terminal CLK8. The fourth mode control sub - circuit 2104 connects the second clock output terminal CLK2 to the third clock output terminal CLK3 and connects the sixth clock output terminal CLK6 to the seventh clock output terminal CLK7.

[0281] In this way, the mode control circuit generates 8 third clock signals based on the initial clock signals clk1 to clk8 and provides them to the clock signal lines CLK1 to CLK8. These 8 third clock signals are divided into M groups, and multiple third clock signals in each group are synchronized. For example, as Figure 15 shown, when M = 2, the first group includes the clock signal lines CLK1 to CLK4, and the second group includes the clock signal lines CLK5 to CLK8. The third clock signals on the first group of clock signal lines CLK1 to CLK4 are synchronized with each other, and the third clock signals on the second group of clock signal lines CLK5 to CLK8 are synchronized with each other. The third clock signals on the second group of clock signal lines CLK5 to CLK8 are shifted relative to the third clock signals on the first group of clock signal lines CLK1 to CLK4. Figure 10 The shift registers GOA1 to GOA8 in Figure 10 generate output signals G1 to G8 accordingly based on the clock signals on the clock signal lines CLK1 to CLK8. As Figure 15 shown, the output signals G1 to G4 are synchronized with each other, the output signals G5 to G8 are synchronized, and any one of the output signals G1 to G4 is shifted relative to any one of the output signals G5 to G8, and so on.

[0282] Figure 16 shows Figure 10An example of the signal timing diagram of the gate driving circuit in the first resolution mode, the second resolution mode, and the third resolution mode. In this embodiment, the first resolution mode is a display mode of 8K resolution, the second resolution mode is a display mode of 4K resolution, and the third resolution mode is a display mode of 2K resolution as an example for illustration. However, the embodiments of the present disclosure are not limited thereto, and the first resolution mode, the second resolution mode, and the third resolution mode can be set to display modes of other resolutions as needed.

[0283] As Figure 16 shown, in the first period P1, the mode control circuit generates 8 clock signals that are sequentially shifted as shown in Figure 13 and supplies them to the clock signal lines CLK1 to CLK8 respectively, and the shift registers GOA1, GOA2,... generate output signals that are sequentially shifted in the same order. In the second period P2, the mode control circuit generates 8 clock signals that are sequentially shifted in 4 groups as shown in Figure 14 and supplies them to the clock signal lines CLK1 to CLK8 respectively, and the shift registers GOA1, GOA2,... generate output signals G1 that are sequentially shifted in 4 groups in the same order. In the third period P3, the mode control circuit generates 8 clock signals that are sequentially shifted in 2 groups as shown in Figure 15 and supplies them to the clock signal lines CLK1 to CLK8 respectively, and the shift registers GOA1, GOA2,... generate output signals that are sequentially shifted in 2 groups in the same order.

[0284] Figure 17 Shows Figure 10 Another example of the signal timing diagram of the gate driving circuit in the first resolution, the second resolution, and the third resolution modes. Figure 17 The embodiment of Figure 16 is similar to

[0285] In the above reference Figures 12 to 16In the described driving method, the duration of the effective level of the output signal generated by each stage of the shift register is 4H, and the shift between each other is H. This enables the sub-pixels connected thereto to be pre-charged for a period of time first, and then the data signal is written to the sub-pixels in this row. In contrast, Figure 17 both the duration of the effective level of the output signal generated by the method of

[0286] Figure 18 FIG. 6 shows a block diagram of a gate driving circuit according to still another embodiment of the present disclosure. Figure 19 FIG. 7 shows Figure 18 an exemplary structural diagram of the gate driving circuit of

[0287] As Figure 18 and 19 shown, the gate driving circuit 300 may include a plurality of driving units, such as driving units DU1, DU2, and DU3. The driving unit DU2 may be connected to the first group of sub-pixels described above, the driving unit DU1 may be connected to the second group of sub-pixels described above, and the driving unit DU3 may be connected to the third group of sub-pixels described above.

[0288] Each of the driving units DU1, DU2, and DU3 includes a plurality of cascaded shift register units. For example, the driving unit DU1 includes cascaded shift register units 320_1, 320_2, … 320_Y. Each shift register unit may include a first shift register, a second shift register, and a third shift register. For example, the shift register unit 320_1 includes shift registers GOA1, GOA2, and GOA3 as the first shift register, the second shift register, and the third shift register respectively, and the shift register unit 320_2 includes shift registers GOA4, GOA5, and GOA6 as the first shift register, the second shift register, and the third shift register respectively, and so on. The above shift registers may adopt the shift register structure of any embodiment of the present disclosure, such as those referred to above with reference to Figure 2A or Figure 2BIt is implemented by the described shift register. In the shift register unit 320_1, the input terminal IN of the first shift register GOA1 serves as the cascaded input terminal of the shift register unit 320_1. The output terminal OUT of the first shift register GOA1 is connected to the input terminal IN of the second shift register GOA2. The output terminal OUT of the second shift register GOA2 is connected to the input terminal IN of the third shift register GOA3. The output terminal OUT of the third shift register GOA3 serves as the cascaded output terminal of the shift register unit 320_1. The clock signal terminals CK of the first shift register GOA1, the second shift register GOA2, and the third shift register GOA3 serve as the clock signal terminals of the shift register unit 320_1. The other shift register units 320_2, 320_3, … have similar structures and will not be elaborated here.

[0289] In the shift register units 320_1, 320_2, … 320_Y, the cascaded output terminal of the nth-stage shift register unit is connected to the cascaded input terminal of the (n + d)th-stage shift register unit, where K = 2d. For example, when K = 8, d = 4. The cascaded output terminal of the first-stage shift register unit 320_1 (i.e., the output terminal OUT of the shift register GOA3) is connected to the cascaded input terminal of the fifth-stage shift register unit 320_5 (i.e., the input terminal IN of the shift register GOA13). The cascaded output terminal of the second-stage shift register unit 320_2 (i.e., the output terminal OUT of the shift register GOA6) is connected to the cascaded input terminal of the sixth-stage shift register unit 320_6 (i.e., the input terminal IN of the shift register GOA16), and so on.

[0290] The gate driving circuit 300 further includes multiple start signal lines STV1, STV2, and STV3. The start signal lines STV1, STV2, and STV3 are connected to the driving units DU1, DU2, and DU3 in one-to-one correspondence. Each start signal line is connected to the cascaded input terminals of the first d-stage shift register units in the corresponding driving unit. For example, the start signal line STV1 is connected to the cascaded input terminals of the first 4-stage shift register units 320_1, 320_2, 320_3, and 320_4 in the driving unit DU1 (i.e., the input terminals IN of GOA1, GOA4, GOA7, and GOA10).

[0291] The gate driving circuit 300 further includes K clock signal lines, such as clock signal lines CLK1 to CLK8. The clock signal lines CLK1 to CLK8 are connected to the clock signal terminals of a plurality of shift register units in each of the driving units DU1, DU2, and DU3. For example, the shift register units in each driving unit can be divided into at least one group, each group including K cascaded shift register units, and the clock signal terminals of the first shift register and the third shift register of the k-th shift register unit are connected to the k-th clock signal line, where k is an integer and 1 ≤ k ≤ K.

[0292] For example, in Figure 19 , every 8 shift register units are divided into one group, where the first group includes cascaded shift register units 320_1 to 320_8. The clock signal terminals CK of the first shift register GOA1 and the third shift register GOA3 in the first shift register unit 320_1 are connected to the first clock signal line CLK1, the clock signal terminals CK of the first shift register GOA4 and the third shift register GOA6 in the second shift register unit 320_2 are connected to the second clock signal line CLK2, the clock signal terminals CK of the first shift register GOA7 and the third shift register GOA9 in the third shift register unit 320_3 are connected to the third clock signal line CLK3, and so on.

[0293] The clock signal terminal of the second shift register of the k-th shift register unit is connected to the (k + d)-th clock signal line when k ≤ 2 / K, and is connected to the (k - d)-th clock signal line when 2 / K < k ≤ K. For example, the clock signal terminal CK of the second shift register GOA2 in the first shift register unit 320_1 is connected to the fifth clock signal line CLK5, the clock signal terminal CK of the second shift register GOA5 in the second shift register unit 320_2 is connected to the sixth clock signal line CLK6, the clock signal terminal CK of the second shift register GOA8 in the third shift register unit 320_3 is connected to the seventh clock signal line CLK7, the clock signal terminal CK of the second shift register GOA11 in the fourth shift register unit 320_4 is connected to the eighth clock signal line CLK8, the clock signal terminal CK of the second shift register GOA14 in the fifth shift register unit 320_5 is connected to the first clock signal line CLK1, and so on.

[0294] During operation, K clock signals can be respectively applied to the K clock signal lines in one of multiple resolution modes, and a start signal is applied to at least one start signal line among the multiple start signal lines. The applied start signal causes the driving unit connected to the at least one start signal line to start, and multiple shift registers in the started driving unit generate output signals according to the clock signals on the K clock signal lines.

[0295] The following will refer to Figures 20 to 23 to describe the driving method of the above-mentioned gate driving circuit 300. For the sake of simplicity, the driving unit DU1 connected to the start signal line STV1 will be taken as an example for illustration below.

[0296] Figure 20 shows Figure 19 the signal timing diagram of the gate driving circuit in the first resolution mode.

[0297] As Figure 20 shown, in the first resolution mode, eight first clock signals that are sequentially shifted are respectively applied to the clock signal lines CLK1 to CLK8, and a first start signal is applied to the start signal line STV1. The first clock signals on the clock signal lines CLK1 to CLK8 can be periodic signals with a duty cycle of 50%, and the duration of the effective level in each signal cycle is 4H, where the (k + 1)-th first clock signal is shifted by H relative to the k-th first clock signal, and H represents the unit scan time. For example, the first clock signal on the second clock signal line CLK2 is shifted by H relative to the first clock signal on the first clock signal line CLK1, the first clock signal on the third clock signal line CLK3 is shifted by H relative to the first clock signal on the second clock signal line CLK2, and so on. The duration of the effective level of the first start signal can be 4H.

[0298] Combined with Figure 19 , the shift registers GOA1, GOA2, and GOA3 in the first shift register unit 320_1 respectively generate output signals G1, G2, and G3 based on the first clock signals on the first clock signal line CLK1, the fifth clock signal line CLK5, and the first clock signal line CLK1, where the output signal G2 is shifted by 4H relative to the output signal G1, and the output signal G3 is shifted by 4H relative to the output signal G2. The shift registers GOA4, GOA5, and GOA6 in the second shift register unit 320_2 respectively generate output signals G4, G5, and G6 based on the first clock signals on the second clock signal line CLK2, the sixth clock signal line CLK6, and the second clock signal line CLK2, where the output signal G4 is shifted by H relative to the output signal G1, the output signal G5 is shifted by 4H relative to the output signal G4, and the output signal G6 is shifted by 4H relative to the output signal G5. The shift registers GOA7, GOA8, and GOA9 in the third shift register unit 320_3 respectively generate output signals G7, G8, and G9 based on the first clock signals on the third clock signal line CLK3, the seventh clock signal line CLK7, and the third clock signal line CLK3, where the output signal G7 is shifted by H relative to the output signal G4, the output signal G8 is shifted by 4H relative to the output signal G7, and the output signal G9 is shifted by 4H relative to the output signal G8, and so on.

[0299] Figure 21 shows Figure 19 the signal timing diagram of the gate driving circuit in the second resolution mode.

[0300] As Figure 21 shown, in the second resolution mode, eight second clock signals are respectively applied to the clock signal lines CLK1 to CLK8, and a second start signal is applied to the start signal line STV1. The second clock signals on the clock signal lines CLK1 to CLK8 can also be periodic signals with a duty cycle of 50%. Different from the first clock signal, the duration of the effective level within each signal cycle is 2H. The duration of the effective level of the second start signal can be 2H.

[0301] The second clock signals on the clock signal lines CLK1 to CLK8 can be divided into 2M groups. For example, when M = 2, they are divided into 4 groups. The first group includes the second clock signals on the clock signal lines CLK1 and CLK2, the second group includes the second clock signals on the clock signal lines CLK3 and CLK4, the third group includes the second clock signals on the clock signal lines CLK5 and CLK6, and the fourth group includes the second clock signals on the clock signal lines CLK7 and CLK8. The second clock signals on the clock signal lines CLK1 and CLK2 are synchronized, the second clock signals on the clock signal lines CLK3 and CLK4 are synchronized, the second clock signals on the clock signal lines CLK5 and CLK6 are synchronized, and the second clock signals on the clock signal lines CLK7 and CLK8 are synchronized. The second clock signals on the clock signal lines CLK3 and CLK4 are shifted by H relative to the second clock signals on the clock signal lines CLK1 and CLK2. The second clock signals on the clock signal lines CLK5 and CLK6 are shifted by H relative to the second clock signals on the clock signal lines CLK3 and CLK4. The second clock signals on the clock signal lines CLK7 and CLK8 are shifted by H relative to the second clock signals on the clock signal lines CLK5 and CLK6, and so on.

[0302] Combined with Figure 19, in the first shift register unit 320_1, the shift registers GOA1, GOA2, and GOA3 in the shift register generate output signals G1, G2, and G3 based on the first clock signal on the first clock signal line CLK1, the fifth clock signal line CLK5, and the first clock signal line CLK1 respectively, where the output signal G2 is shifted by 2H relative to the output signal G1, and the output signal G3 is shifted by 2H relative to the output signal G2. In the second shift register unit 320_2, the shift registers GOA4, GOA5, and GOA6 in the shift register generate output signals G4, G5, and G6 based on the second clock signal on the second clock signal line CLK2, the sixth clock signal line CLK6, and the second clock signal line CLK2 respectively, where the output signal G4 is synchronized with the output signal G1, the output signal G5 is shifted by 2H relative to the output signal G4, and the output signal G6 is shifted by 2H relative to the output signal G5. In the third shift register unit 320_3, the shift registers GOA7, GOA8, and GOA9 in the shift register generate output signals G7, G8, and G9 based on the third clock signal on the third clock signal line CLK3, the seventh clock signal line CLK7, and the third clock signal line CLK3 respectively, where the output signal G7 is shifted by H relative to the output signal G4, the output signal G8 is shifted by 2H relative to the output signal G7, and the output signal G9 is shifted by 2H relative to the output signal G8, and so on.

[0303] Figure 22 shows Figure 19 the signal timing diagram of the gate driving circuit in the third resolution mode.

[0304] As Figure 22 shown, in the third resolution mode, eight third clock signals are applied to the clock signal lines CLK1 to CLK8 respectively, and a third start signal is applied to the start signal line STV1. The third clock signal is also a periodic signal with a duty cycle of 50%. Different from the first clock signal, the duration of the effective level within the signal period of the third clock signal is H. The third clock signals on the clock signal lines CLK1 to CLK8 can be divided into M groups, for example, 2 groups, where the first group includes the third clock signals on the clock signal lines CLK1 to CLK4, and the second group includes the third clock signals on the clock signal lines CLK5 to CLK8. The third clock signals on the clock signal lines CLK1 to CLK4 are synchronized with each other, the third clock signals on the clock signal lines CLK5 to CLK8 are synchronized with each other, and the third clock signals on the clock signal lines CLK5 to CLK8 are shifted by H relative to the third clock signals on the clock signal lines CLK1 to CLK4. The duration of the effective level of the third start signal can be H.

[0305] Combined with Figure 19, in the first shift register unit 320_1, the shift registers GOA1, GOA2, and GOA3 in the shift register unit 320_1 generate output signals G1, G2, and G3 based on the first clock signal on the first clock signal line CLK1, the fifth clock signal line CLK5, and the first clock signal line CLK1, respectively, where the output signal G2 is shifted by H relative to the output signal G1, and the output signal G3 is shifted by H relative to the output signal G2. In the second shift register unit 320_2, the shift registers GOA4, GOA5, and GOA6 generate output signals G4, G5, and G6 based on the second clock signal on the second clock signal line CLK2, the sixth clock signal line CLK6, and the second clock signal line CLK2, respectively, where the output signal G4 is synchronized with the output signal G1, the output signal G5 is shifted by H relative to the output signal G4, and the output signal G6 is shifted by H relative to the output signal G5. In the third shift register unit 320_3, the shift registers GOA7, GOA8, and GOA9 generate output signals G7, G8, and G9 based on the third clock signal on the third clock signal line CLK3, the seventh clock signal line CLK7, and the third clock signal line CLK3, respectively, where the output signal G7 is synchronized with the output signal G4, the output signal G8 is shifted by H relative to the output signal G7, and the output signal G9 is shifted by H relative to the output signal G8. In the fourth shift register unit 320_4, the shift registers GOA10, GOA11, and GOA12 generate output signals G10, G11, and G12 based on the fourth clock signal on the fourth clock signal line CLK4, the eighth clock signal line CLK8, and the fourth clock signal line CLK4, respectively, where the output signal G10 is synchronized with the output signal G7, the output signal G11 is shifted by H relative to the output signal G10, and the output signal G12 is shifted by H relative to the output signal G11.

[0306] Figure 23 shows Figure 19 the timing diagram of the start signal of the gate driving circuit. Taking Figure 10 the gate driving circuit as an example, the first driving unit DU1 is connected to the first start signal line STV1, the second driving unit DU2 is connected to the second start signal line STV2, and the third driving unit DU3 is connected to the third start signal line STV3.

[0307] In the first period P1, control the second driving unit DU2 to operate in the first resolution mode. For example, as Figure 20 shown, apply clock signals to the clock signal lines CLK1 to CLK8 and apply a first start signal to the second start signal line STV2. The second driving unit DU2 generates output signals G(X + 1), G(X + 2), … G2X as Figure 20 shown in response to the start signal on the second start signal line STV2 according to the clock signals on the clock signal lines CLK1 to CLK8.

[0308] In the second time period P2, control the first driving unit DU1 to operate in the second resolution mode or the third resolution mode. For example, clock signals can be applied to the clock signal lines CLK1 to CLK8 as shown in Figure 21 and a second start signal can be applied to the first start signal line STV1. The first driving unit DU1 generates output signals G1, G2, G3, … in response to the second start signal on the first start signal line STV1 according to the clock signals on the clock signal lines CLK1 to CLK8 as shown in Figure 21 In some embodiments, clock signals can be applied to the clock signal lines CLK1 to CLK8 as shown in Figure 22 and a third start signal can be applied to the first start signal line STV1. The first driving unit DU1 generates output signals G1, G2, G3, … GX in response to the third start signal on the first start signal line STV1 according to the clock signals on the clock signal lines CLK1 to CLK8 as shown in Figure 22 In the third time period P3, control the second driving unit DU2 to operate in the first resolution mode again. For example, clock signals can be applied to the clock signal lines CLK1 to CLK8 as shown in

[0309] and a first start signal can be applied to the second start signal line STV2. The second driving unit DU2 generates output signals G(X + 1), G(X + 2), … G2X in response to the first start signal on the second start signal line STV2 according to the K clock signals on the clock signal lines CLK1 to CLK8 as shown in Figure 20 In the fourth time period, control the third driving unit DU3 to operate in the second resolution mode or the third resolution mode. For example, clock signals can be applied to the clock signal lines CLK1 to CLK8 as shown in Figure 20 and a second start signal can be applied to the third start signal line STV3. The third driving unit DU3 generates output signals G(2X + 1), G(2X + 2), … G3X in response to the second start signal on the third start signal line STV3 according to the clock signals on the clock signal lines CLK1 to CLK8 as shown in

[0310] In some embodiments, clock signals can be applied to the clock signal lines CLK1 to CLK8 as shown in Figure 21 and a third start signal can be applied to the third start signal line STV3. The third driving unit DU3 generates output signals G(2X + 1), G(2X + 2), … G3X in response to the third start signal on the third start signal line STV3 according to the clock signals on the clock signal lines CLK1 to CLK8 as shown in Figure 21 In some embodiments, clock signals can be applied to the clock signal lines CLK1 to CLK8 as shown in Figure 22 and a third start signal can be applied to the third start signal line STV3. The third driving unit DU3 generates output signals G(2X + 1), G(2X + 2), … G3X in response to the third start signal on the third start signal line STV3 according to the clock signals on the clock signal lines CLK1 to CLK8 as shown in Figure 22 In some embodiments, clock signals can be applied to the clock signal lines CLK1 to CLK8 as shown in

[0311] It can be seen that in the above process, the driving unit DU2 drives the sub-pixels in the central region twice at a relatively high first resolution, while the driving units DU1 and DU3 respectively perform a display drive on the sub-pixels in the two side regions at a relatively low second or third resolution. Thus, it is possible to achieve a higher resolution display in the central region of the display panel and a lower resolution display in the two side regions.

[0312] Those skilled in the art can understand that the embodiments described above are all exemplary, and those skilled in the art can make improvements thereto. The structures described in various embodiments can be freely combined without conflict in terms of structure or principle.

[0313] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art can clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and the present disclosure is not limited to the implementation manners of the exemplary embodiments described in the specification.

Claims

1. A gate driving circuit includes a plurality of driving units connected in cascade, and each driving unit includes: N shift register units; and a mode control circuit connected to the N shift register units. The mode control circuit is configured to receive a control signal for the driving unit and connect the N shift register units in one of a first resolution mode, a second resolution mode, and a third resolution mode under the control of the control signal; wherein, in the first resolution mode, the N shift register units are connected in cascade; in the second resolution mode, the N shift register units are divided into M groups, the M groups are connected in cascade, and the shift register units in each group are connected in parallel; in the third resolution mode, the N shift register units are connected in parallel; The control signal includes a first control signal, a second control signal, a third control signal, and a fourth control signal, N = 4, M = 2, the N shift register units include a first shift register unit, a second shift register unit, a third shift register unit, and a fourth shift register unit, and each shift register unit has a cascade input terminal and a first cascade output terminal; The mode control circuit includes: a first transistor, the gate of the first transistor is connected to receive the first control signal, the first pole of the first transistor is connected to the first cascade output terminal of the first shift register unit, and the second pole of the first transistor is connected to the cascade input terminal of the second shift register unit; a second transistor, the gate of the second transistor is connected to receive the second control signal, the first pole of the second transistor is connected to the cascade input terminal of the first shift register unit, and the second pole of the second transistor is connected to the cascade input terminal of the second shift register unit; a third transistor, the gate of the third transistor is connected to receive the third control signal, the first pole of the third transistor is connected to the first cascade output terminal of the second shift register unit, and the second pole of the third transistor is connected to the cascade input terminal of the third shift register unit; a fourth transistor, the gate of the fourth transistor is connected to receive the fourth control signal, the first pole of the fourth transistor is connected to the cascade input terminal of the first shift register unit, and the second pole of the fourth transistor is connected to the cascade input terminal of the third shift register unit; a fifth transistor, the gate of the fifth transistor is the first control signal, the first pole of the fifth transistor is connected to the first cascade output terminal of the third shift register unit, and the second pole of the fifth transistor is connected to the cascade input terminal of the fourth shift register unit; and a sixth transistor, the gate of the sixth transistor is connected to receive the second control signal, the first pole of the sixth transistor is connected to the cascade input terminal of the third shift register unit, and the second pole of the sixth transistor is connected to the cascade input terminal of the fourth shift register unit.

2. The gate driving circuit according to claim 1, wherein, the mode control circuit is configured to: In the first resolution mode, the first cascaded output terminal of the nth shift register unit is connected to the cascaded input terminal of the (n + 1)th shift register unit, and the cascaded input terminal of the nth shift register unit is disconnected from the cascaded input terminal of the (n + 1)th shift register unit, where 1 ≤ n ≤ N - 1; In the second resolution mode, the first cascaded output terminal of the first shift register unit is disconnected from the cascaded input terminal of the second shift register unit, the first cascaded output terminal of the second shift register unit is connected to the cascaded input terminal of the third shift register unit, the first cascaded output terminal of the third shift register unit is disconnected from the cascaded input terminal of the fourth shift register unit, the cascaded input terminal of the first shift register unit is connected to the cascaded input terminal of the second shift register unit, and the cascaded input terminal of the third shift register unit is connected to the cascaded input terminal of the fourth shift register unit; And In the third resolution mode, the first cascaded output terminal of the nth shift register unit is disconnected from the cascaded input terminal of the (n + 1)th shift register unit, and the cascaded input terminal of the nth shift register unit is connected to the cascaded input terminal of the (n + 1)th shift register unit.

3. The gate driving circuit according to claim 2, Wherein, The first shift register unit, the second shift register unit, the third shift register unit, and the fourth shift register unit each further have a reset terminal and a second cascaded output terminal, and the mode control circuit is further configured to: In the first resolution mode, the reset terminal of the nth shift register unit is connected to the second cascaded output terminal of the (n + 1)th shift register unit, and the reset terminal of the nth shift register unit is disconnected from the reset terminal of the (n + 1)th shift register unit, In the second resolution mode, the reset terminal of the first shift register unit is disconnected from the second cascaded output terminal of the second shift register unit, the reset terminal of the second shift register unit is connected to the second cascaded output terminal of the third shift register unit, the reset terminal of the third shift register unit is disconnected from the second cascaded output terminal of the fourth shift register unit, the reset terminal of the first shift register unit is connected to the reset terminal of the second shift register unit, the reset terminal of the second shift register unit is disconnected from the reset terminal of the third shift register unit, and the reset terminal of the third shift register unit is connected to the reset terminal of the fourth shift register unit; And In the third resolution mode, the reset terminal of the nth shift register unit is disconnected from the second cascaded output terminal of the (n + 1)th shift register unit, and the reset terminal of the nth shift register unit is connected to the reset terminal of the (n + 1)th shift register unit.

4. The gate driving circuit according to claim 1, Wherein, The control signal further includes a fifth control signal, and the mode control circuit further includes: The seventh transistor, the gate of the seventh transistor is connected to receive the first control signal, the first pole of the seventh transistor is connected to the reset terminal of the first shift register unit, and the second pole of the seventh transistor is connected to the second cascade output terminal of the second shift register unit; The eighth transistor, the gate of the eighth transistor is connected to receive the fifth control signal, the first pole of the eighth transistor is connected to the reset terminal of the first shift register unit, and the second pole of the eighth transistor is connected to the reset terminal of the second shift register unit; The ninth transistor, the gate of the ninth transistor is connected to receive the third control signal, the first pole of the ninth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the ninth transistor is connected to the second cascade output terminal of the third shift register unit; The tenth transistor, the gate of the tenth transistor is connected to receive the fourth control signal, the first pole of the tenth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the tenth transistor is connected to the reset terminal of the third shift register unit; The eleventh transistor, the gate of the eleventh transistor is connected to receive the first control signal, the first pole of the eleventh transistor is connected to the reset terminal of the third shift register unit, and the second pole of the eleventh transistor is connected to the second cascade output terminal of the fourth shift register unit; and The twelfth transistor, the gate of the twelfth transistor is connected to receive the second control signal, the first pole of the twelfth transistor is connected to the reset terminal of the third shift register unit, and the second pole of the twelfth transistor is connected to the reset terminal of the fourth shift register unit.

5. The gate driving circuit according to claim 2 or 3, wherein, The first cascade output terminal of the Nth shift register unit in the ith driving unit is connected to the cascade input terminal of the first shift register unit in the (i + 1)th driving unit.

6. The gate driving circuit according to claim 5, wherein, The reset terminal of the Nth shift register unit in the ith driving unit is connected to the second cascade output terminal of the first shift register unit in the (i + 1)th driving unit.

7. The gate driving circuit according to claim 1, wherein, The multiple driving units are divided into multiple groups, and each group of driving units is connected to a group of control signal lines to receive control signals for the group of driving units.

8. The gate driving circuit according to claim 2 or 3, wherein, Each shift register unit includes a first shift register, a second shift register, and a third shift register, wherein, The input terminal of the first shift register serves as the cascade input terminal of the shift register unit, and the output terminal of the first shift register serves as the second cascade output terminal of the shift register unit; The input terminal of the second shift register is connected to the output terminal of the first shift register; and The input terminal of the third shift register is connected to the output terminal of the second shift register, and the output terminal of the third shift register serves as the first cascade output terminal of the shift register unit.

9. The gate driving circuit according to claim 8, wherein, Each of the first shift register, the second shift register, and the third shift register includes: An input sub - circuit, connected to the input terminal of the shift register and the pull - up node, and configured to provide the signal at the input terminal to the pull - up node; An output sub - circuit, connected to the pull - up node, the clock signal terminal and the output terminal of the shift register, and configured to provide the signal at the clock signal terminal to the output terminal under the control of the potential of the pull - up node; A control sub - circuit, connected to the pull - up node, the output terminal and the pull - down node of the shift register, and configured to control the potential of the pull - down node based on the potential of the pull - up node, and pull down the potential of the output terminal under the control of the potential of the pull - down node.

10. The gate driving circuit according to claim 9, wherein, each of the first shift register, the second shift register and the third shift register further includes: A reset sub - circuit, connected to the pull - up node and the reset terminal of the shift register, and configured to reset the pull - up node according to the reset signal at the reset terminal, wherein the reset terminal of the third shift register in the shift register unit serves as the reset terminal of the shift register unit.

11. A driving method for the gate driving circuit according to any one of claims 1 to 10, comprising: The mode control circuit of each driving unit among the plurality of driving units receives a control signal for the driving unit, and connects the N shift register units in one of a plurality of resolution modes under the control of the control signal; The connected N shift register units in each driving unit generate output signals.

12. The method according to claim 11, wherein, the plurality of resolution modes include a first resolution mode, a second resolution mode and a third resolution mode, wherein, in the first resolution mode, the mode control circuit cascades the N shift register units, and the N shift register units generate sequentially - shifted output signals; in the second resolution mode, the mode control circuit divides the N shift register units into M groups, cascades the M groups, and connects the shift register units in each group in parallel. The shift register units in each group generate output signals in parallel, and a group of output signals generated by the (m + 1) - th group of shift register units is shifted relative to a group of output signals generated by the m - th group of shift register units, where m is an integer and 1 ≤ m ≤ M - 1; in the third resolution mode, the mode control circuit connects the N shift register units in parallel, and the N shift register units generate output signals in parallel.

13. The method according to claim 12, wherein, N = 4, M = 2, and the N shift register units include a first shift register unit, a second shift register unit, a third shift register unit and a fourth shift register unit, wherein, In the first resolution mode, the mode control circuit connects the first cascaded output terminal of the n-th shift register unit to the cascaded input terminal of the (n + 1)-th shift register unit, and disconnects the cascaded input terminal of the n-th shift register unit from the cascaded input terminal of the (n + 1)-th shift register unit, where 1 ≤ n ≤ N - 1; In the second resolution mode, the mode control circuit disconnects the first cascaded output terminal of the first shift register unit from the cascaded input terminal of the second shift register unit, and connects the cascaded input terminal of the second shift register unit to the cascaded input terminal of the first shift register unit; connects the first cascaded output terminal of the second shift register unit to the cascaded input terminal of the third shift register unit, and disconnects the cascaded input terminal of the third shift register unit from the cascaded input terminal of the second shift register unit; and disconnects the first cascaded output terminal of the third shift register unit from the cascaded input terminal of the fourth shift register unit, and connects the cascaded input terminal of the third shift register unit to the cascaded input terminal of the fourth shift register unit; and In the third resolution mode, the mode control circuit disconnects the first cascaded output terminal of the n-th shift register unit from the cascaded input terminal of the (n + 1)-th shift register unit, and connects the cascaded input terminal of the n-th shift register unit to the cascaded input terminal of the (n + 1)-th shift register unit.

14. The method according to claim 13, further comprising: In the first resolution mode, the mode control circuit connects the reset terminal of the n-th shift register unit to the second cascaded output terminal of the (n + 1)-th shift register, and disconnects the reset terminal of the n-th shift register unit from the reset terminal of the (n + 1)-th shift register unit, In the second resolution mode, the mode control circuit disconnects the reset terminal of the first shift register unit from the second cascaded output terminal of the second shift register unit, connects the reset terminal of the second shift register unit to the second cascaded output terminal of the third shift register unit, the mode control circuit disconnects the reset terminal of the third shift register unit from the second cascaded output terminal of the fourth shift register unit, connects the reset terminal of the first shift register unit to the reset terminal of the second shift register unit, and connects the reset terminal of the third shift register unit to the reset terminal of the fourth shift register unit; and In the third resolution mode, the mode control circuit disconnects the reset terminal of the n-th shift register unit from the second cascaded output terminal of the (n + 1)-th shift register unit, and connects the reset terminal of the n-th shift register unit to the reset terminal of the (n + 1)-th shift register unit.

15. The method according to claim 13, wherein, the mode control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein, In the first resolution mode, the first control signal and the third control signal are at the first level, the second control signal and the fourth control signal are at the second level, the first transistor, the third transistor, and the fifth transistor are turned on, and the second transistor, the fourth transistor, and the sixth transistor are turned off; In the second resolution mode, the second control signal and the third control signal are at the first level, the first control signal and the fourth control signal are at the second level, the second transistor, the third transistor, and the sixth transistor are turned on, and the first transistor, the fourth transistor, and the fifth transistor are turned off; and In the third resolution mode, the second control signal and the fourth control signal are at the first level, the first control signal and the third control signal are at the second level, the second transistor, the fourth transistor, and the sixth transistor are turned on, and the first transistor, the third transistor, and the fifth transistor are turned off.

16. The method according to claim 15, wherein, the control signal further includes a fifth control signal, and the mode control circuit further includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, wherein, for the seventh transistor, the gate of the seventh transistor is connected to receive the first control signal, the first pole of the seventh transistor is connected to the reset terminal of the first shift register unit, and the second pole of the seventh transistor is connected to the second cascade output terminal of the second shift register unit; for the eighth transistor, the gate of the eighth transistor is connected to receive the fifth control signal, the first pole of the eighth transistor is connected to the reset terminal of the first shift register unit, and the second pole of the eighth transistor is connected to the reset terminal of the second shift register unit; for the ninth transistor, the gate of the ninth transistor is connected to receive the third control signal, the first pole of the ninth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the ninth transistor is connected to the second cascade output terminal of the third shift register unit; for the tenth transistor, the gate of the tenth transistor is connected to receive the fourth control signal, the first pole of the tenth transistor is connected to the reset terminal of the second shift register unit, and the second pole of the tenth transistor is connected to the reset terminal of the third shift register unit; for the eleventh transistor, the gate of the eleventh transistor is connected to receive the first control signal, the first pole of the eleventh transistor is connected to the reset terminal of the third shift register unit, and the second pole of the eleventh transistor is connected to the second cascade output terminal of the fourth shift register unit; and for the twelfth transistor, the gate of the twelfth transistor is connected to receive the second control signal, the first pole of the twelfth transistor is connected to the reset terminal of the third shift register unit, and the second pole of the twelfth transistor is connected to the reset terminal of the fourth shift register unit; wherein, in the first resolution mode, the fifth control signal is at the second level, the seventh transistor, the ninth transistor, and the eleventh transistor are turned on, and the eighth transistor, the tenth transistor, and the twelfth transistor are turned off; in the second resolution mode, the fifth control signal is at the first level, the eighth transistor, the ninth transistor, and the twelfth transistor are turned on, and the seventh transistor, the tenth transistor, and the eleventh transistor are turned off; and In the third resolution mode, the fifth control signal is at the first level, the eighth transistor, the tenth transistor, and the twelfth transistor are turned on, and the seventh transistor, the ninth transistor, and the eleventh transistor are turned off.

17. A display panel, comprising the gate driving circuit according to any one of claims 1-10.

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