Display panel and display device

Abstract

A display panel (100) comprises a substrate (1), a plurality of sub-pixels (2) and a gate drive circuit (3). The sub-pixels (2) comprise a pixel drive circuit (21). The gate drive circuit (3) comprises a multi-stage cascaded shift register (31), wherein a stage of the shift register (31) is electrically connected to a plurality of pixel drive circuits (21) in a row of sub-pixels (2). The gate drive circuit (3) further comprises: a plurality of cascade input signal lines (34) and a plurality of cascade display reset signal lines (35). The cascade input signal line (34) is configured to connect a shift signal terminal (CR) of a stage of the shift register (31). <n>) and the input signal terminal (Iput) of another stage of the shift register; the cascade display reset signal line (35) is configured to connect the shift signal terminal (CR <n>) and a display reset signal end (STD) of another stage of shift register (31). The display panel (100) comprises a plurality of sub-pixel regions (S) for arranging a plurality of sub-pixels (2), and a first gap region (D) located between two adjacent columns of sub-pixel regions (S); the cascade display reset signal line (35) and the cascade input signal line (34) are both arranged in the first gap region (D), and the two are arranged in different first gap regions (D).< / n> < / n>

Description

[0001] This application claims priority to PCT international application No. PCT / CN2020 / 138717, filed on December 23, 2020, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] The gate drive circuit (also called the scan drive circuit) is an important component of the display device. The gate drive circuit may include a multi-stage cascaded shift register, and each stage of the shift register is electrically connected to a row of gate lines in the display device. The gate drive circuit can input scan signals (also called gate signals) to the multiple gate lines in the display device row by row, and drive each row of sub-pixels in the display device to perform display scanning, thereby enabling the display device to display a picture.

[0004] Providing a gate driving circuit on a display panel of a display device can effectively reduce costs and improve yield. Summary of the invention

[0005] In one aspect, a display panel is provided. The display panel includes: a substrate; a plurality of sub-pixels arranged on one side of the substrate; and a gate drive circuit, which is located on the same side of the substrate as the plurality of sub-pixels. The plurality of sub-pixels are arranged in a plurality of rows along a first direction and in a plurality of columns along a second direction. The sub-pixels include a pixel drive circuit and a light-emitting device electrically connected to the pixel drive circuit. The gate drive circuit includes a multi-stage cascaded shift register, wherein a first-stage shift register is electrically connected to a plurality of pixel drive circuits in a row of sub-pixels. The shift register includes a plurality of device groups, wherein one device group is located in a region between two adjacent sub-pixels in a corresponding row of sub-pixels. The device group includes at least one transistor and / or at least one capacitor. The gate drive circuit further includes: a plurality of cascade input signal lines and a plurality of cascade display reset signal lines; the cascade input signal lines are configured to connect a shift signal end of a first-stage shift register and an input signal end of another-stage shift register; and the cascade display reset signal lines are configured to connect a shift signal end of a first-stage shift register and a display reset signal end of another-stage shift register. The display panel has multiple sub-pixel areas for setting the multiple sub-pixels, and a first gap area located between two adjacent columns of sub-pixel areas; the cascade display reset signal line and the cascade input signal line are both set in the first gap area, and the two are set in different first gap areas.

[0006] In some embodiments, the plurality of cascade input signal lines are divided into a plurality of groups, each group of cascade input signal lines includes at least one cascade input signal line, and at least one group of cascade input signal lines is disposed in one of the first gap regions. The plurality of cascade display reset signal lines are divided into a plurality of groups, each group of cascade display reset signal lines includes at least one cascade display reset signal line, and at least one group of cascade display reset signal lines is disposed in one of the first gap regions.

[0007] In some embodiments, at least one column of sub-pixels is disposed between two adjacent groups of cascade input signal lines located in different first gap regions. At least one column of sub-pixels is disposed between two adjacent groups of cascade display reset signal lines located in different first gap regions.

[0008] In some embodiments, a plurality of groups of cascade input signal lines are arranged in one of the first gap regions, and at least one row of sub-pixels is arranged between two adjacent groups of cascade input signal lines in the same first gap region. A plurality of groups of cascade display reset signal lines are arranged in one of the first gap regions, and at least one row of sub-pixels is arranged between two adjacent groups of cascade display reset signal lines in the same first gap region.

[0009] In some embodiments, the display panel further comprises: a plurality of data lines extending along the second direction. One data line is electrically connected to a plurality of pixel driving circuits in a column of sub-pixels. The plurality of cascade input signal lines, the plurality of cascade display reset signal lines and the plurality of data lines are made of the same material and are arranged in the same layer.

[0010] In some embodiments, the plurality of sub-pixels are divided into a plurality of pixel units; a pixel unit includes at least three sub-pixels arranged in sequence along the first direction; the plurality of pixel units are arranged into a plurality of rows along the first direction and into a plurality of columns along the second direction. The area between any two adjacent columns of pixel units is the first gap area.

[0011] In some embodiments, each sub-pixel region includes: a sub-pixel circuit region arranged along the second direction and used to set a corresponding pixel driving circuit and a sub-pixel light-emitting region used to set a corresponding light-emitting device. Along the second direction, any three adjacent rows of sub-pixel regions are respectively a first row of sub-pixel regions, a second row of sub-pixel regions, and a third row of sub-pixel regions. The region between the first row of sub-pixel regions and the second row of sub-pixel regions is a second gap region, and the region between the second row of sub-pixel regions and the third row of sub-pixel regions is a third gap region. Among them, in the first row of sub-pixel regions and the second row of sub-pixel regions, the sub-pixel light-emitting region is closer to the second gap region relative to the sub-pixel circuit region. In the second row of sub-pixel regions and the third row of sub-pixel regions, the sub-pixel circuit region is closer to the third gap region relative to the sub-pixel light-emitting region.

[0012] In some embodiments, the display panel further comprises: a plurality of power supply voltage lines and a plurality of auxiliary power supply voltage lines, the power supply voltage lines extending along the second direction, the auxiliary power supply voltage lines extending along the first direction, and each power supply voltage line being electrically connected to the plurality of auxiliary power supply voltage lines. Each row of pixel regions corresponds to at least one auxiliary power supply voltage line, and pixel driving circuits of a plurality of sub-pixels in a pixel region corresponding to each auxiliary power supply voltage line are electrically connected to the auxiliary power supply voltage line.

[0013] In some embodiments, the display panel further includes: a passivation layer, a color filter layer, and a planar layer, which are sequentially arranged on the substrate and located between the pixel driving circuit of the sub-pixel and the light-emitting device. A first via hole penetrating the passivation layer and the planar layer is provided, and the pixel driving circuit is electrically connected to the light-emitting device through the first via hole. The color filter layer includes a plurality of filter parts, each of which is arranged in a sub-pixel light-emitting area of ​​a sub-pixel region. In the same sub-pixel region, along the second direction, the filter part and the first via hole located in the sub-pixel region are separated by at least a portion of the pixel driving circuit located in the sub-pixel region and / or the auxiliary power supply voltage line.

[0014] In some embodiments, the display panel further includes: a gate line for transmitting a gate signal, a data line for transmitting a data signal, and a first sensing signal line for transmitting a sensing signal.

[0015] The pixel driving circuit includes: a switching transistor, a storage capacitor, a driving transistor and a sensing transistor, wherein the control electrode of the switching transistor is electrically connected to the gate line, and the first electrode of the switching transistor is electrically connected to the data line. The first plate of the storage capacitor is electrically connected to the second electrode of the switching transistor, and the second plate of the storage capacitor is electrically connected to the light-emitting device. The control electrode of the driving transistor is electrically connected to the second electrode of the switching transistor and the first plate of the storage capacitor, the first electrode of the driving transistor is electrically connected to the auxiliary power supply voltage line, and the second electrode of the driving transistor is electrically connected to the light-emitting device and the second plate of the storage capacitor. The control electrode of the sensing transistor is electrically connected to the gate line, the first electrode of the sensing transistor is electrically connected to the first sensing signal line, and the second electrode of the sensing transistor is electrically connected to the light-emitting device, the second plate of the storage capacitor and the second electrode of the driving transistor. Wherein, the switching transistor and the sensing transistor are farther away from the sub-pixel light-emitting area of ​​the sub-pixel area where the pixel driving circuit is located than the driving transistor.

[0016] In some embodiments, the display panel further includes: an active layer, a gate insulating layer, a gate conductive layer, an interlayer dielectric layer, and a source-drain conductive layer sequentially arranged on the substrate. The active layer includes the first electrode, the channel portion, and the second electrode of the switch transistor, the drive transistor, and the sensing transistor. The gate conductive layer includes the control electrode of the switch transistor, the drive transistor, and the sensing transistor. The source-drain conductive layer includes a first connection pattern and a second connection pattern. A second via hole penetrating the interlayer dielectric layer and the gate insulating layer is provided, and a third via hole is provided in the interlayer dielectric layer. The first connection pattern is electrically connected to the second electrode of the switch transistor through the second via hole, and is electrically connected to the control electrode of the drive transistor through the third via hole. A fourth via hole is provided in the interlayer dielectric layer, and the second connection pattern is electrically connected to the second electrode of the drive transistor through the fourth via hole. In the same sub-pixel region, along the second direction, the filter portion and the first via hole located in the sub-pixel region are separated by the control electrode, the channel portion, the first electrode, and the auxiliary power supply voltage line of the drive transistor.

[0017] In some embodiments, the display panel further includes: a first electrode layer and a buffer layer sequentially arranged on the substrate, the first electrode layer and the buffer layer being located on a side of the active layer close to the substrate. The first electrode layer includes the second electrode plate of the storage capacitor, and the active layer also includes the first electrode plate of the storage capacitor. A fifth via is provided in the interlayer dielectric layer, and the first connection pattern is also electrically connected to the first electrode plate of the storage capacitor through the fifth via. A sixth via is provided in the interlayer dielectric layer and the buffer layer, penetrating the two, and the second connection pattern is also electrically connected to the second electrode plate of the storage capacitor through the sixth via. The fifth via and the sixth via are both located on a side of the storage capacitor close to the third gap region.

[0018] In some embodiments, each row of pixel regions corresponds to a plurality of auxiliary power supply voltage lines. Along the first direction, two adjacent auxiliary power supply voltage lines are separated by the first gap region.

[0019] In some embodiments, each column of pixel regions corresponds to a power supply voltage line, and the power supply voltage line is located on one side of two opposite sides of the pixel region along the first direction. Each pixel region corresponds to an auxiliary power supply voltage line, and each of the auxiliary power supply voltage lines is electrically connected to a pixel driving circuit of a plurality of sub-pixels in the corresponding pixel region.

[0020] In some embodiments, the display panel further includes: an active layer, a gate insulating layer, a gate conductive layer, an interlayer dielectric layer, and a source-drain conductive layer sequentially arranged on the substrate. The pixel driving circuit includes a driving transistor, and the active layer includes a first electrode, a channel portion, and a second electrode of the driving transistor. The source-drain conductive layer includes a plurality of third connection patterns. The auxiliary power supply voltage line is located in the gate conductive layer. A seventh via is provided in the interlayer dielectric layer, and an eighth via is provided in the interlayer dielectric layer and the gate insulating layer. The third connection pattern is electrically connected to the auxiliary power supply voltage line through the seventh via, and is electrically connected to the first electrode of the driving transistor through the eighth via. The power supply voltage line is located in the source-drain conductive layer. In the same pixel area, the third connection pattern closest to the power supply voltage line corresponding to the pixel area among the plurality of third connection patterns is electrically connected to the power supply voltage line.

[0021] In some embodiments, the display panel further comprises a plurality of gate lines, each gate line is in a zigzag shape and extends substantially along the first direction. A gate line is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels.

[0022] The gate line includes a plurality of first extension segments, a plurality of second extension segments and a plurality of connecting segments, each first extension segment and each second extension segment extends approximately along the first direction, the plurality of first extension segments and the plurality of second extension segments are alternately arranged, adjacent first extension segments and second extension segments are connected by connecting segments, and along the second direction, there is a spacing between the extension lines of adjacent first extension segments and second extension segments.

[0023] The first extension segment and two connecting segments connected to the first extension segment form a first recess, and the opening of the first recess faces a direction away from the third gap region. The second extension segment and two connecting segments connected to the second extension segment form a second recess, and the opening of the second recess faces a direction close to the third gap region. At least part of the pixel driving circuit is located in the first recess and the second recess.

[0024] In some embodiments, the pixel driving circuit includes: a first sensing signal line located in the third gap region and extending along the first direction. When the plurality of sub-pixels are divided into a plurality of pixel units, and one pixel unit includes at least three sub-pixels arranged in sequence along the first direction, two pixel units opposite to each other along the second direction in the sub-pixels located in the second row of sub-pixel regions and the third row of sub-pixel regions share the first sensing signal line.

[0025] In some embodiments, the sub-pixel further comprises: a light shielding layer disposed on a side of the pixel driving circuit close to the substrate. The first sensing signal line and the light shielding layer are made of the same material and are disposed in the same layer.

[0026] In some embodiments, the pixel driving circuit further includes: a second sensing signal line extending along the second direction. The second sensing signal line is located in a region between two adjacent columns of sub-pixels in two pixel units opposite to each other along the second direction. The first sensing signal line is electrically connected to the second sensing signal line through a via.

[0027] In some embodiments, when the display panel further includes a plurality of data lines, the second sensing signal line is made of the same material and disposed in the same layer as the plurality of data lines.

[0028] In some embodiments, the gate drive circuit further includes: a plurality of transmission signal lines located in the second gap region and extending along the first direction. A two-stage shift register electrically connected to the sub-pixels located in the first row of sub-pixel regions and the sub-pixels located in the second row of sub-pixel regions shares at least one transmission signal line among the plurality of transmission signal lines.

[0029] In some embodiments, the gate drive circuit further comprises: a first voltage signal line electrically connected to the first voltage signal terminal of the two-stage shift register; a second voltage signal line electrically connected to the second voltage signal terminal of the two-stage shift register; and a third voltage signal line electrically connected to the third voltage signal terminal of the two-stage shift register. The transmission signal line is the first voltage signal line, the second voltage signal line or the third voltage signal line.

[0030] In some embodiments, at least one cascade input signal line includes a first sub-input signal line and a second sub-input signal line located in different first gap regions; the gate drive circuit further includes: an input signal connection line located in the second gap region and electrically connected to the first sub-input signal line and the second sub-input signal line; the transmission signal line is the input signal connection line. And / or, at least one cascade display reset signal line includes a first sub-display reset signal line and a second sub-display reset signal line located in different first gap regions; the gate drive circuit further includes: a display reset connection line located in the second gap region and electrically connected to the first sub-display reset signal line and the second sub-display reset signal line; the transmission signal line is the display reset connection line.

[0031] In some embodiments, the gate drive circuit further comprises: a plurality of node voltage transmission lines located in the second gap region. In the same level shift register, at least two device groups are electrically connected to the same node through a node voltage transmission line. In the two-level shift register, at least two device groups are electrically connected to the same node through a node voltage transmission line. The transmission signal line is the node voltage transmission line.

[0032] In some embodiments, the shift register includes: a first input circuit electrically connected to an input signal terminal, a pull-up node, and an anti-leakage node; the first input circuit is configured to transmit the input signal to the pull-up node in response to an input signal received at the input signal terminal during a display period of a frame display stage; an output circuit electrically connected to the pull-up node, a first clock signal terminal, and a first output signal terminal; the output circuit is configured to transmit the first clock signal received at the first clock signal terminal to the first output signal terminal under the control of the voltage of the pull-up node during a display period of a frame display stage; and an anti-leakage circuit electrically connected to the pull-up node, a first voltage signal terminal, and the anti-leakage node; the anti-leakage circuit is configured to transmit the first voltage signal received at the first voltage signal terminal to the anti-leakage node under the control of the voltage of the pull-up node to prevent leakage of the pull-up node. The first input circuit, the output circuit, and the anti-leakage circuit each include at least one device group. The device group in the first input circuit used to be electrically connected to the pull-up node, and the device group in the output circuit used to be electrically connected to the pull-up node, are electrically connected to the pull-up node through a node voltage transmission line. The device group in the first input circuit used to be electrically connected to the anti-leakage node, and the device group in the anti-leakage circuit used to be electrically connected to the anti-leakage node, are electrically connected to the anti-leakage node through a node voltage transmission line.

[0033] In some embodiments, the gate drive circuit also includes: multiple blanking input circuits; one blanking input circuit is electrically connected to at least two adjacent shift registers; the blanking input circuit is configured to control the corresponding shift register to input a blanking control signal to the pixel drive circuit of the corresponding row during a blanking period of a frame display stage, so that the pixel drive circuit obtains a sensing signal. The blanking input circuit includes: a selection control circuit electrically connected to a selection control signal terminal, a shift signal terminal, a second voltage signal terminal and a first blanking node; the selection control circuit is configured to transmit the shift signal received at the shift signal terminal to the first blanking node under the control of the selection control signal transmitted by the selection control signal terminal; a second input circuit electrically connected to the first blanking node, the second blanking node and a second clock signal terminal or a first voltage signal terminal; the second input circuit is configured to transmit the second clock signal received at the second clock signal terminal or the first voltage signal received at the first voltage signal terminal to the second blanking node under the control of the voltage of the first blanking node; and at least two transmission circuits, one transmission circuit electrically connected to the pull-up node of a first-stage shift register; the transmission circuit is also electrically connected to the second blanking node and the second clock signal terminal; the transmission circuit is configured to transmit the second clock signal or the first voltage signal received at the second blanking node to the pull-up node under the control of the second clock signal transmitted by the second clock signal terminal. The second input circuit and the transmission circuit each include at least one device group; each device group included in the second input circuit and the transmission circuit is respectively located in a region between two adjacent sub-pixels in a row of sub-pixels where the corresponding shift register is located. The device group in the second input circuit for being electrically connected to the second blanking node and the device group in the at least two transmission circuits for being electrically connected to the second blanking node are electrically connected to the second blanking node via a node voltage transmission line.

[0034] In some embodiments, the display panel further comprises: a plurality of gate lines extending along the first direction; one gate line is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels. The plurality of transmission signal lines and the plurality of gate lines are made of the same material and are disposed in the same layer.

[0035] In some embodiments, the gate drive circuit further comprises: a plurality of control signal lines extending along the second direction; a first-stage shift register is electrically connected to at least a portion of the plurality of control signal lines; and the shift register is configured to provide output signals to a plurality of pixel drive circuits of a corresponding row under the control of at least a portion of the control signal lines electrically connected to the shift register.

[0036] In some embodiments, at least one control signal line among the plurality of control signal lines is located in the first gap region.

[0037] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, etc.

[0039] Figure 1 is a structural diagram of a display panel according to the related art;

[0040] Figure 2 is a structural diagram of a display device according to some embodiments of the present disclosure;

[0041] Figure 3 is a structural diagram of a display panel according to some embodiments of the present disclosure;

[0042] Figure 4 is a circuit diagram of a sub-pixel according to some embodiments of the present disclosure;

[0043] Figure 5 is a circuit diagram of a shift register according to some embodiments of the present disclosure;

[0044] Figure 6 is a circuit diagram of a two-stage adjacent shift register according to some embodiments of the present disclosure;

[0045] Figure 7 is a structural diagram of a gate driving circuit according to some embodiments of the present disclosure;

[0046] Figure 8 is a circuit diagram of another adjacent two-stage shift register according to some embodiments of the present disclosure;

[0047] Figure 9a to Figure 9h is a structural diagram of a sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0048] Fig.10 is a structural diagram of another sub-pixel and gate driving circuit according to some embodiments of the present disclosure;

[0049] Fig.11is a partial enlarged diagram of a sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0050] Fig.12 is a partial enlarged diagram of another sub-pixel and a gate driving circuit according to some embodiments of the present disclosure;

[0051] Fig.13a is a partial enlarged view of a sub-pixel according to some embodiments of the present disclosure;

[0052] Fig.13b and Fig.13c Both Fig.13a A partial enlarged view of the middle A;

[0053] Figure 14a to Figure 14e for Fig.13b Top view of each film layer at B in the middle;

[0054] Fig.15 for Fig.14e A cross-sectional view of the structure shown along section line MM';

[0055] Fig.16 for Fig.14e The structure shown is a cross-sectional view along section line NN'. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0057] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0058] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0059] When describing some embodiments, the term "electrically connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "electrically connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0060] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0061] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0062] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0063] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0064] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0065] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0066] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0067] The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors (such as oxide thin film transistors) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples.

[0068] In some embodiments, the control electrode of each transistor used in the shift register is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source, and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain, and the second electrode is the source.

[0069] In the circuit provided by the embodiments of the present disclosure, nodes such as the first pull-up node, the second pull-up node, the first pull-down node, and the second pull-down node do not represent actually existing components, but represent the meeting points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent meeting points of related electrical connections in the circuit diagram.

[0070] In the embodiments of the present disclosure, the term "pull-up" means charging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (e.g., turn-on). The term "pull-down" means discharging a node or an electrode of a transistor so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the operation of the corresponding transistor (e.g., turn-off).

[0071] In the following, in the circuits provided in the embodiments of the present disclosure, N-type transistors are used as examples for description.

[0072] Some embodiments of the present disclosure provide a display panel 100 and a display device 1000 . The display panel 100 and the display device 1000 are respectively introduced below.

[0073] Some embodiments of the present disclosure provide a display device 1000, such as Figure 2As shown. The display device 1000 can be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether text or. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0074] In some examples, the display device 1000 includes a frame, a display panel 100 disposed in the frame, a circuit board, a display driver IC (Integrated Circuit), and other electronic components.

[0075] In some examples, the display panel 100 may be in a non-rectangular shape. For example, when the display panel 100 is applied to a building, the shape of the display panel 100 may be set according to the shape of the building and the requirements of the application site environment.

[0076] Exemplarily, the shape of the display panel 100 may be circular, elliptical, arc-shaped, diamond-shaped, or the like.

[0077] The above-mentioned display panel 100 can be, for example: an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (Micro LED) display panel, etc., and the present disclosure does not make any specific limitations on this.

[0078] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as an OLED display panel as an example.

[0079] In some embodiments, Figure 3 As shown, the display panel 100 may include: a substrate 1 , a plurality of sub-pixels 2 and a gate driving circuit 3 .

[0080] There are many types of the substrate 1, which can be selected according to actual needs.

[0081] Exemplarily, the substrate 1 may be a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0082] Exemplarily, the substrate 1 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethyleneterephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate. In this case, the display panel 100 may be a flexible display panel.

[0083] In some examples, such as Figure 3 As shown, the above-mentioned multiple sub-pixels 2 are arranged on one side of the substrate 1. The multiple sub-pixels 2 can be arranged into multiple rows along the first direction X, and arranged into multiple columns along the second direction Y. Each row of sub-pixels 2 can include multiple sub-pixels 2, and each column of sub-pixels 2 can include multiple sub-pixels 2.

[0084] Here, the first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 89° or 90°, etc.

[0085] Exemplarily, the shape of the substrate 1 may be the same as that of the display panel 100, that is, the shape of the substrate 1 may be a non-rectangular shape. Based on this, the number of sub-pixels 2 included in the sub-pixel columns (that is, a certain column of sub-pixels 2 arranged along the second direction Y) located at different positions of the substrate 1 may be different, and the number of sub-pixels 2 included in the sub-pixel rows (that is, a certain row of sub-pixels 2 arranged along the first direction X) located at different positions of the substrate 1 may be different.

[0086] In some examples, such as Figure 3 As shown, the display panel 100 may include: a plurality of gate lines GL disposed on one side of the substrate 1 and extending along a first direction X, a plurality of data lines DL disposed on one side of the substrate 1 and extending along a second direction Y, a first sensing signal line ( Figure 3), and a power supply voltage line arranged on one side of the substrate 1, wherein the gate line GL is used to transmit a gate signal, the data line DL is used to transmit a data signal, and the first sensing signal line is used to transmit a sensing signal. Exemplarily, the plurality of data lines DL are located on a side of the plurality of gate lines GL away from the substrate 1, and the plurality of data lines DL and the plurality of gate lines GL are insulated from each other.

[0087] In some examples, such as Figure 4 As shown, among the above-mentioned multiple sub-pixels 2, each sub-pixel 2 may include a pixel driving circuit 21 and a light-emitting device 22 electrically connected to the pixel driving circuit 21.

[0088] For example, Figure 3 and Figure 4 As shown, one gate line GL can be electrically connected to multiple pixel driving circuits 21 in the same row of sub-pixels 2, and one data line DL can be electrically connected to multiple pixel driving circuits 21 in the same column of sub-pixels 2. The number of gate lines GL electrically connected to multiple pixel driving circuits 21 in the same row of sub-pixels 2 can be set according to the structure of the pixel driving circuit 21.

[0089] The structure of the above-mentioned pixel driving circuit 21 includes multiple types, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit 21 may include a structure such as "2T1C", "6T1C", "7T1C", "6T2C" or "7T2C". Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors, and "C" represents a storage capacitor, and the number in front of "C" represents the number of storage capacitors. Among them, the pixel driving circuit 21 may include a switching transistor and a driving transistor.

[0090] Here, during the use of the display panel 100, the stability of the thin film transistor and the light emitting device 22 in the pixel driving circuit 21 may decrease (for example, the threshold voltage of the driving transistor drifts), affecting the display effect of the display panel 100, so that the sub-pixel 2 needs to be compensated.

[0091] There are many ways to compensate the sub-pixel 2, which can be selected according to actual needs. For example, a pixel compensation circuit can be set in the sub-pixel 2 to use the pixel compensation circuit to perform internal compensation on the sub-pixel 2. For another example, the driving transistor or the light-emitting device 22 can be sensed by the thin film transistor inside the sub-pixel 2, and the sensed data can be transmitted to the external sensing circuit, so that the driving voltage value to be compensated can be calculated by the external sensing circuit and fed back, thereby realizing external compensation for the sub-pixel 2.

[0092] The present disclosure takes the external compensation method (sensing the driving transistor) and the pixel driving circuit 21 adopting the 3T1C structure as an example to schematically illustrate the structure and working process of the sub-pixel 2.

[0093] For example, Figure 4 As shown, the pixel driving circuit 21 may include: a switching transistor T1, a driving transistor T2, a sensing transistor T3 and a storage capacitor Cst.

[0094] For example, Figure 4 As shown, the control electrode of the switch transistor T1 is electrically connected to the first gate signal terminal G (gate line GL) 1, the first electrode of the switch transistor T1 is electrically connected to the data signal terminal Data (data line DL), and the second electrode of the switch transistor T1 is electrically connected to the first node G. The switch transistor T1 is configured to transmit the data signal received at the data signal terminal Data to the first node G in response to the first gate signal received at the first gate signal terminal G1.

[0095] Here, the data signal includes, for example, a detection data signal and a display data signal.

[0096] For example, Figure 4 As shown, the control electrode of the driving transistor T2 is electrically connected to the first node G, the first electrode of the driving transistor T2 is electrically connected to the fourth voltage signal terminal Vdd (power supply voltage line), and the second electrode of the driving transistor T2 is electrically connected to the second node S. The driving transistor T2 is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal Vdd to the second node S under the control of the voltage of the node G.

[0097] For example, Figure 4 As shown, the first plate of the storage capacitor Cst is electrically connected to the first node G, and the second plate of the storage capacitor Cst is electrically connected to the second node S. In the process of charging the first node G, the switch transistor T1 simultaneously charges the storage capacitor Cst.

[0098] For example, Figure 4 As shown, the anode of the light emitting device 22 is electrically connected to the second node S, and the cathode of the light emitting device 22 is electrically connected to the fifth voltage signal terminal ELVSS. The light emitting device 22 is configured to emit light under the cooperation of the fourth voltage signal from the second node S and the fifth voltage signal transmitted by the fifth voltage signal terminal ELVSS.

[0099] Here, the level of the first voltage signal may range from, for example, -5 V to 5 V. The second voltage signal may be, for example, a fixed voltage signal, and the level of the fixed voltage signal may be less than or equal to 0V.

[0100] For example, Figure 4 As shown, the control electrode of the sensing transistor T3 is electrically connected to the second gate signal terminal G2 (gate line GL), the first electrode of the sensing transistor T3 is electrically connected to the second node S, and the second electrode of the sensing transistor T3 is electrically connected to the sensing signal terminal Sense (first sensing signal line). Among them, the sensing transistor T3 is configured to detect the electrical characteristics of the driving transistor T2 in response to the second gate signal received at the second gate signal terminal G2 to achieve external compensation. The electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the driving transistor T2.

[0101] Here, the sensing signal terminal Sense may provide a reset signal or obtain a sensing signal, wherein the reset signal is used to reset the second node S, and the sensing signal is used to obtain a threshold voltage of the driving transistor T2.

[0102] Based on the structure of the pixel driving circuit 21, in some examples, a plurality of pixel driving circuits 21 in the same row of sub-pixels 2 can be electrically connected to two gate lines GL (i.e., the first gate line and the second gate line). For example, each first gate signal terminal G1 can be electrically connected to the first gate line and receive the first gate signal transmitted by the first gate line; each second gate signal terminal G2 can be electrically connected to the second gate line and receive the second gate signal transmitted by the second gate line. In other examples, a plurality of pixel driving circuits 21 in the same row of sub-pixels 2 can also be electrically connected to the same gate line GL, and the arrangement space of the display panel 100 can be saved by reducing the number of settings of the gate line GL, which is conducive to increasing the pixel density (Pixels Per Inch, PPI) of the display panel 100. For example, the control electrode of the switching transistor T1 and the control electrode of the sensing transistor T3 are both electrically connected to the same gate line GL and receive the gate signal transmitted by the gate line GL.

[0103] In this example, the display phase of one frame may include, for example, a display period and a blanking period performed sequentially.

[0104] During the display period in a frame display stage, the working process of the sub-pixel 2 may include, for example: a reset stage, a data writing stage and a light emitting stage.

[0105] In the reset stage, the level of the second gate signal provided by the second gate signal terminal G2 is high, and the sensing signal terminal Sense provides a reset signal (the level of the reset signal is, for example, low). The sensing transistor T3 is turned on under the control of the second gate signal, receives the reset signal, and transmits the reset signal to the second node S to reset the second node S.

[0106] In the data writing stage, the level of the first gate signal provided by the first gate signal terminal G1 is high, and the level of the display data signal provided by the data signal terminal Data is high. The switching transistor T1 is turned on under the control of the first gate signal, receives the display data signal, and transmits the display data signal to the first node G, while charging the storage capacitor Cst.

[0107] In the light-emitting stage, the level of the first gate signal provided by the first gate signal terminal G1 is low, the level of the second gate signal provided by the second gate signal terminal G2 is low, and the level of the fourth voltage signal provided by the fourth voltage signal terminal Vdd is high. The switching transistor T1 is turned off under the control of the first gate signal, and the sensing transistor T3 is turned off under the control of the second gate signal. The storage capacitor Cst begins to discharge, so that the voltage of the first node G remains at a high level. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal, and transmits the fourth voltage signal to the second node S, so that the light-emitting device 22 emits light under the mutual cooperation of the fourth voltage signal and the fifth voltage signal transmitted by the fifth voltage signal terminal ELVSS.

[0108] During the blanking period in a frame display stage, the working process of the sub-pixel 2 may include, for example, a first stage and a second stage.

[0109] In the first stage, the level of the first gate signal provided by the first gate signal terminal G1 and the level of the second gate signal provided by the second gate signal terminal G2 are both high levels, and the level of the detection data signal provided by the data signal terminal Data is high. The switching transistor T1 is turned on under the control of the first gate signal, receives the detection data signal, and transmits the detection data signal to the first node G to charge the first node G. The sensing transistor T3 is turned on under the control of the second gate signal, receives the reset signal provided by the sensing signal terminal Sense, and transmits the reset signal to the second node S.

[0110] In the second stage, the sensing signal terminal Sense is in a suspended state. The driving transistor T2 is turned on under the control of the voltage of the first node G, receives the fourth voltage signal provided by the fourth voltage signal terminal Vdd, and transmits the fourth voltage signal to the second node S, charging the second node S, so that the voltage of the second node S increases until the driving transistor T2 is turned off. At this time, the voltage difference Vgs between the first node G and the second node S is equal to the threshold voltage Vth of the driving transistor T2.

[0111] Since the sensing transistor T3 is in the on state and the sensing signal terminal Sense is in the suspended state, the sensing signal terminal Sense is also charged while the driving transistor T2 is charging the second node S. By sampling the voltage of the sensing signal terminal Sense (i.e., obtaining the sensing signal), the threshold voltage Vth of the driving transistor T2 can be calculated based on the relationship between the voltage of the sensing signal terminal Sense and the level of the detection data signal.

[0112] After the threshold voltage Vth of the driving transistor T2 is calculated, the threshold voltage Vth can be compensated into the display data signal of the display period in the next frame display stage, thereby completing the external compensation of the sub-pixel 2.

[0113] In some examples, the gate driving circuit 3 and the plurality of sub-pixels 2 are located on the same side of the substrate 1. The gate driving circuit 3 may include a multi-stage cascaded shift register 31, and a stage of the shift register 31 may be electrically connected to a plurality of pixel driving circuits 21 in at least one row of sub-pixels 2.

[0114] It should be noted that, in the display stage of one frame, the first gate signal transmitted by the first gate signal terminal G1 and the second gate signal transmitted by the second gate signal terminal G2 are both provided by the gate driving circuit 3. That is, each stage of the shift register 31 in the gate driving circuit 3 can be electrically connected to the first gate signal terminal G1 through the first gate line, transmit the first gate signal to the first gate signal terminal G1 through the first gate line, and be electrically connected to the second gate signal terminal G2 through the second gate line, and transmit the second gate signal to the second gate signal terminal G2 through the second gate line.

[0115] The shift register 31 has a variety of structures, which can be selected and set according to actual needs. The following schematically illustrates the structures of the shift register 31 with two structures, but the shift register 31 in the present disclosure is not limited to these two structures.

[0116] In some examples, such as Figure 5 and Figure 6 As shown, the shift register 31 may include: a first input circuit 3101, an anti-leakage circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108 and a fifth reset circuit 3109.

[0117] For example, Figure 5 and Figure 6 As shown, the first input circuit 3101 is connected to the input signal terminal Input (abbreviated as Iput in the drawings and below), the pull-up node Q <n>And leakage protection node OFF <n>The first input circuit 3101 is configured to transmit the input signal to the pull-up node Q in response to the input signal received at the input signal terminal Iput during the display period of a frame display stage. <n>. Wherein, N is a positive integer, which represents the number of rows of sub-pixels.

[0118] For example, during a display period in a frame display stage, when the level of the input signal is high, the first input circuit 3101 can be turned on under the action of the input signal and transmit the input signal to the pull-up node Q <n>, pull up node Q <n>Charging is performed so that the pull-up node Q <n>The voltage increases.

[0119] Optional, such as Figure 5 and Figure 6 As shown, the first input circuit 3101 may include: a first transistor M1 and a second transistor M2.

[0120] For example, Figure 5 and Figure 6 As shown, the control electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, the first electrode of the first transistor M1 is electrically connected to the input signal terminal Iput, and the second electrode of the first transistor M1 is electrically connected to the first electrode of the second transistor M2 and the first anti-leakage node OFF1. The control electrode of the second transistor M2 is electrically connected to the input signal terminal Iput, and the second electrode of the second transistor M2 is electrically connected to the first pull-up node Q1.

[0121] Here, during a display period in a frame display stage, when the level of the input signal transmitted by the input signal terminal Iput is high, the first transistor M1 and the second transistor M2 can be turned on at the same time under the action of the input signal. The first transistor M1 can receive the input signal transmitted by the input signal terminal Iput, and transmit the received input signal to the first electrode and the anti-leakage node OFF of the second transistor M2. <n>The second transistor M2 can transmit the received input signal to the pull-up node Q <n>, pull up node Q <n>Charging is performed so that the pull-up node Q <n>The voltage increases.

[0122] For example, Figure 5 and Figure 6 As shown, the leakage protection circuit 3102 and the pull-up node Q <n>, the first voltage signal terminal VDD and the leakage prevention node OFF <n>The leakage protection circuit 3102 is configured to pull up the node Q <n>Under the control of the voltage of the first voltage signal terminal VDD, the first voltage signal transmitted is transmitted to the leakage protection node OFF <n>to prevent the pull-up node Q <n>The first voltage signal is, for example, a constant high voltage signal.

[0123] For example, at the pull-up node Q <n>When the voltage of is high, the leakage protection circuit 3102 can pull up the node Q <n>The first voltage signal is received and transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage increases.

[0124] Optional, such as Figure 5 and Figure 6 As shown, the leakage protection circuit 3102 may include: a third transistor M3.

[0125] For example, Figure 5 and Figure 6 As shown, the control electrode of the third transistor M3 is connected to the pull-up node Q <n>The first electrode of the third transistor M3 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the third transistor M3 is electrically connected to the anti-leakage node OFF <n>Electrical connection.

[0126] Here, at the pull-up node Q <n>When the voltage of is high, the third transistor M3 can pull up the node Q <n>The first voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the second transistor M2 is increased, and the voltage difference between the control electrode and the first electrode of the second transistor M2 is less than zero, ensuring that the second transistor M2 is completely or relatively completely turned off. This can avoid pulling up the node Q <n>Leakage occurs through the first input circuit 3101, causing the node Q to be pulled up. <n>Able to maintain a higher and more stable voltage.

[0127] For example, Figure 5 and Figure 6 As shown, the output circuit 3103 and the pull-up node Q <n>, a first clock signal terminal CLKE_1 and a first output signal terminal Output1 <n>(The attached figure and the following text are abbreviated as Oput1 <n>) is electrically connected. The output circuit 3103 is configured to pull up the node Q during the display period of a frame display stage. <n>Under the control of the voltage of <n>.

[0128] Of course, if Figure 6 As shown, the output circuit 3103 can also be connected to the third clock signal terminal CLKD_1 and the shift signal terminal CR <n>The output circuit 3103 is also configured to, during a display period in a frame display phase, pull up the node Q <n>Under the control of the voltage of , the third clock signal received at the third clock signal terminal CLKD_1 is transmitted to the shift signal terminal CR <n>.

[0129] Of course, if Figure 6 As shown, the output circuit 3103 can also be connected to the fourth clock signal terminal CLKF_1 and the second output signal terminal Output2 <n>(The attached figure and the following text are abbreviated as Oput2 <n>) is electrically connected. The output circuit 3103 is also configured to pull up the node Q during the blanking period in a frame display stage. <n>Under the control of the voltage of , the fourth clock signal received at the fourth clock signal terminal CLKF_1 is transmitted to the second output signal terminal Oput2 <n>.

[0130] For example, during the display period of a frame display stage, at the pull-up node Q <n>When the voltage of the output circuit 3103 increases, the output circuit 3103 can pull up the node Q <n>The third clock signal received at the third clock signal terminal CLKD_1 is turned on under the control of the voltage of the third clock signal terminal CLKD_1, and the third clock signal received at the third clock signal terminal CLKD_1 is used as the shift signal, and the third clock signal received at the third clock signal terminal CLKD_1 is turned on under the control of the voltage of the third clock signal terminal CLKD_1, and the third clock signal received at the third clock signal terminal CLKD_1 is used as the shift <n>Output; the first clock signal received at the first clock signal terminal CLKE_1 is used as the first output signal, from the first output signal terminal Oput1 <n>Output. During the blanking period in a frame display phase, the pull-up node Q <n>When the voltage of the output circuit 3103 increases, the output circuit 3103 can pull up the node Q <n>The fourth clock signal received at the fourth clock signal terminal CLKF_1 is turned on under the control of the voltage of the fourth clock signal terminal CLKF_1, and the fourth clock signal received at the fourth clock signal terminal CLKF_1 is used as the second output signal, and the fourth clock signal is output from the second output signal terminal Oput2 <n>Output.

[0131] In this example, the first output signal terminal Oput1 <n>Can be electrically connected to the first gate line, the first output signal terminal Oput1 <n>The first output signal can be used as a first gate signal and transmitted to the pixel driving circuit 21 via the first gate line and the first gate signal terminal G1 in sequence. <n>Can be electrically connected to the second gate line, the second output signal terminal Oput2 <n>The output second output signal can be used as a second gate signal and transmitted to the pixel driving circuit 21 via the second gate line and the second gate signal terminal G2 in sequence.

[0132] Optional, such as Figure 6 As shown, the output circuit 3103 may include: a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1 and a second capacitor C2.

[0133] For example, Figure 6 As shown, the control electrode of the fourth transistor M4 is connected to the pull-up node Q <n>The first electrode of the fourth transistor M4 is electrically connected to the third clock signal terminal CLKD_1, and the second electrode of the fourth transistor M4 is electrically connected to the shift signal terminal CR <n>Electrical connection.

[0134] During the display period of a frame display stage, the first input circuit 3101 is turned on, so that the pull-up node Q <n>When the voltage of the node Q increases, the fourth transistor M4 can pull up the node Q <n>The third clock signal is transmitted to the shift signal terminal CR under the control of the high voltage <n>and uses the third clock signal as a shift signal from the shift signal terminal CR <n>Output.

[0135] For example, Figure 6 As shown, the control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>The first electrode of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE_1, and the second electrode of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1 <n>The first end of the first capacitor C1 is electrically connected to the pull-up node Q <n>The second end of the first capacitor C1 is electrically connected to the first output signal end Oput1 <n>Electrical connection.

[0136] During the display period of a frame display stage, when the first input circuit 3101 is turned on, the pull-up node Q <n>When the voltage of the first input circuit 3101 is turned off, the first capacitor C1 can be discharged, so that the pull-up node Q <n>The first clock signal is kept at a high level, so that the fifth transistor M5 can remain in a conducting state, and the first clock signal is transmitted to the first output signal terminal Oput1. <n>and output the first clock signal as the first output signal from the first output signal terminal Oput1 <n>Output.

[0137] For example, Figure 6 As shown, the control electrode of the sixth transistor M6 is connected to the pull-up node Q <n>The first electrode of the sixth transistor M6 is electrically connected to the fourth clock signal terminal CLKF_1, and the second electrode of the sixth transistor M6 is electrically connected to the second output signal terminal Oput2 <n>The first end of the second capacitor C2 is electrically connected to the pull-up node Q <n>The second end of the second capacitor C2 is electrically connected to the second output signal end Oput2 <n>Electrical connection.

[0138] During the blanking period of a frame display stage, the pull-up node Q <n>When the voltage of the pull-up node Q increases, the second capacitor C2 will be charged. In the corresponding stage, the second capacitor C2 can be discharged, so that the pull-up node Q <n>The fourth clock signal is maintained at a high level, so that the sixth transistor M6 can remain in a conductive state, and the fourth clock signal is transmitted to the second output signal terminal Oput2 <n>and outputs the fourth clock signal as the second output signal from the second output signal terminal Oput2 <n>Output.

[0139] Here, after the multiple shift registers 31 are cascaded to form the gate drive circuit 3, the shift signal terminal CR in the Nth shift register 31 is <n>For example, it can be electrically connected to the input signal terminal Iput in the N+1th stage shift register 31, thereby connecting the shift signal terminal CR of the Nth stage shift register 31 to the input signal terminal Iput of the N+1th stage shift register 31. <n>The output shift signal is used as an input signal in the (N+1)th stage shift register 31. Of course, the cascade connection of the multiple stages of shift registers 31 is not limited to this.

[0140] In addition, the input signal terminal Iput of the partial shift register 31 can be electrically connected to the start signal terminal STU, so as to receive the start signal transmitted by the start signal terminal STU as the input signal. Wherein, the partial shift register 31 can be, for example, the first-stage shift register 31 in the gate drive circuit 3, or can be, for example, the first-stage shift register 31 and the second-stage shift register 31, etc.

[0141] Here, the number of the shift registers 31 electrically connected to the start signal terminal STU is not limited and can be selected and set according to actual needs.

[0142] For example, Figure 5 and Figure 6 As shown, the control circuit 3104 and the pull-up node Q <n>, the sixth voltage signal terminal VDD_A, the pull-down node QB_A and the second voltage signal terminal VGL1 are electrically connected. The control circuit 3104 is configured to pull up the node Q <n>The voltage of the pull-down node QB_A is controlled under the control of the voltage of the pull-down node QB_A and the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A. The level of the sixth voltage signal may be unchanged during the display phase of a frame, for example. The second voltage signal terminal VGL1 may be configured to transmit a DC low-level signal (for example, lower than or equal to the low-level portion of the clock signal). The second voltage signal terminal VGL1 may be grounded, for example.

[0143] For example, at the pull-up node Q <n>When the voltage of the pull-up node Q increases, the control circuit 3104 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, and pull the voltage of the pull-down node QB_A down to a low voltage. <n>When the voltage of is a low voltage, the control circuit 3104 may transmit the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A to the pull-down node QB_A, and pull the voltage of the pull-down node QB_A to a high level.

[0144] Optional, such as Figure 5 and Figure 6 As shown, the control circuit 3104 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10.

[0145] For example, Figure 5 and Figure 6 As shown, the control electrode of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD_A, the first electrode of the seventh transistor M7 is electrically connected to the sixth voltage signal terminal VDD_A, the second electrode of the seventh transistor M7 is electrically connected to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The first electrode of the eighth transistor M8 is electrically connected to the sixth voltage signal terminal VDD_A, the second electrode of the eighth transistor M8 is electrically connected to the pull-down node QB_A and the first electrode of the tenth transistor M10. The control electrode of the ninth transistor M9 is electrically connected to the pull-up node Q <n>The control electrode of the tenth transistor M10 is electrically connected to the pull-up node Q. <n>The second electrode of the tenth transistor M10 is electrically connected to the second voltage signal terminal VGL1.

[0146] When the level of the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A is high, the seventh transistor M7 can be turned on under the action of the sixth voltage signal, and receive and transmit the sixth voltage signal to the control electrode of the eighth transistor M8 and the first electrode of the ninth transistor M9. The eighth transistor M8 can be turned on under the action of the sixth voltage signal, and receive and transmit the sixth voltage signal to the pull-down node QB_A and the first electrode of the tenth transistor M10.

[0147] At the pull-up node Q <n>When the voltage of Q is high, the ninth transistor M9 and the tenth transistor M10 can pull up the node Q <n>The ninth transistor M9 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the control electrode of the eighth transistor M8, so that the eighth transistor M8 is turned off, and the tenth transistor M10 can transmit the second voltage signal to the pull-down node QB_A, pulling the voltage of the pull-down node QB_A down to a low level.

[0148] At the pull-up node Q <n>When the voltage of Q is low, the ninth transistor M9 and the tenth transistor M10 can pull up the node Q <n>The eighth transistor M8 is turned off under the control of the voltage, and the eighth transistor M8 can transmit the received sixth voltage signal to the pull-down node QB_A, pulling the voltage of the pull-down node QB_A to a high level.

[0149] For example, Figure 5 and Figure 6 As shown, the first reset circuit 3105 is connected to the pull-down node QB_A and the pull-up node Q <n>, the second voltage signal terminal VGL1 and the leakage prevention node OFF <n>The first reset circuit 3105 is configured to, under the control of the voltage of the pull-down node QB_A, reset the pull-up node Q <n>Perform a reset.

[0150] For example, when the voltage of the pull-down node QB_A is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q <n>, pull up node Q <n>Pull-down reset.

[0151] Optional, such as Figure 5 and Figure 6 As shown, the first reset circuit 3105 may include: an eleventh transistor M11 and a twelfth transistor M12.

[0152] For example, Figure 5 and Figure 6 As shown, the control electrode of the eleventh transistor M11 is electrically connected to the pull-down node QB_A, and the first electrode of the eleventh transistor M11 is electrically connected to the pull-up node Q <n>The second electrode of the eleventh transistor M11 is electrically connected to the first electrode of the twelfth transistor M12 and the leakage prevention node OFF. <n>The control electrode of the twelfth transistor M12 is electrically connected to the pull-down node QB_A, and the second electrode of the twelfth transistor M12 is electrically connected to the second voltage signal terminal VGL1.

[0153] When the voltage of the pull-down node QB_A is at a high level, the eleventh transistor M11 and the twelfth transistor M12 can be turned on at the same time under the action of the voltage of the pull-down node QB_A, and the twelfth transistor M12 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF. <n>, the eleventh transistor M11 can turn off the leakage protection node <n>The second voltage signal is transmitted to the pull-up node Q <n>, pull up node Q <n>Perform a reset.

[0154] Here, at the pull-up node Q <n>When the potential of the first reset circuit 3105 is high and the first reset circuit 3105 is not in operation, the third transistor M3 can pull up the node Q <n>The first voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the eleventh transistor M11 is increased, so that the voltage difference between the control electrode and the second electrode of the eleventh transistor M11 is less than zero, ensuring that the eleventh transistor M11 is completely or relatively completely turned off. <n>Leakage occurs through the first reset circuit 3105, causing the node Q to be pulled up. <n>Able to maintain a higher and more stable voltage.

[0155] For example, Figure 5 and Figure 6 As shown, the second reset circuit 3106 is connected to the display reset signal terminal STD and the pull-up node Q <n>, the second voltage signal terminal VGL1 and the leakage prevention node OFF <n>The second reset circuit 3106 is configured to, under the control of the display reset signal transmitted by the display reset signal terminal STD, pull up the node Q <n>Perform a reset.

[0156] For example, when the level of the display reset signal is high, the second reset circuit 3106 can be turned on under the action of the display reset signal to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q <n>, pull up node Q <n>Pull-down reset.

[0157] Optional, such as Figure 5 and Figure 6 As shown, the second reset circuit 3106 may include: a thirteenth transistor M13 and a fourteenth transistor M14.

[0158] For example, Figure 5 and Figure 6 As shown, the control electrode of the thirteenth transistor M13 is electrically connected to the display reset signal terminal STD, and the first electrode of the thirteenth transistor M13 is electrically connected to the pull-up node Q <n>The second electrode of the thirteenth transistor M13 is electrically connected to the first electrode of the fourteenth transistor M14 and the anti-leakage node OFF <n>The control electrode of the fourteenth transistor M14 is electrically connected to the display reset signal terminal STD, and the second electrode of the fourteenth transistor M14 is electrically connected to the second voltage signal terminal VGL1.

[0159] When the voltage of the display reset signal is at a high level, the thirteenth transistor M13 and the fourteenth transistor M14 can be turned on at the same time under the action of the display reset signal, and the fourteenth transistor M14 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF <n>, the thirteenth transistor M13 can turn off the leakage protection node <n>The second voltage signal is transmitted to the pull-up node Q <n>, pull up node Q <n>Perform a reset.

[0160] Here, at the pull-up node Q <n>When the potential of the node Q is high and the second reset circuit 3106 is not in operation, the third transistor M3 can pull up the node Q <n>The first voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the thirteenth transistor M13 is increased, so that the voltage difference between the control electrode and the second electrode of the thirteenth transistor M13 is less than zero, ensuring that the thirteenth transistor M13 is completely or relatively completely turned off. <n>The second reset circuit 3106 causes leakage, which pulls up the node Q <n>Able to maintain a higher and more stable voltage.

[0161] Here, after the multiple shift registers 31 are cascaded to form the gate driving circuit 3, the display reset signal terminal STD of the Nth stage shift register 31 can be connected to the shift signal terminal CR of the N+4th stage shift register 31. <n>The shift signal terminal CR of the N+4th stage shift register 31 is electrically connected to <n>The output shift signal serves as a display reset signal of the N-th stage shift register 31. Of course, the cascade connection of the multiple stages of shift registers 31 is not limited to this.

[0162] For example, Figure 5 and Figure 6 As shown, the third reset circuit 3107 is connected to the global reset signal terminal TRST and the pull-up node Q <n>, the second voltage signal terminal VGL1 and the leakage prevention node OFF <n>The third reset circuit 3107 is configured to, under the control of the global reset signal transmitted by the global reset signal terminal TRST, pull up the node Q <n>Perform a reset.

[0163] For example, when the level of the global reset signal is high, the third reset circuit 3107 can be turned on under the action of the global reset signal to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-up node Q <n>, pull up node Q <n>Pull-down reset.

[0164] Optional, such as Figure 5 and Figure 6 As shown, the third reset circuit 3107 may include: a fifteenth transistor M15 and a sixteenth transistor M16.

[0165] For example, Figure 5 and Figure 6 As shown, the control electrode of the fifteenth transistor M15 is electrically connected to the global reset signal terminal TRST, and the first electrode of the fifteenth transistor M15 is electrically connected to the pull-up node Q <n>The second electrode of the fifteenth transistor M15 is electrically connected to the first electrode of the sixteenth transistor M16 and the anti-leakage node OFF. <n>The control electrode of the sixteenth transistor M16 is electrically connected to the global reset signal terminal TRST, and the second electrode of the sixteenth transistor M16 is electrically connected to the second voltage signal terminal VGL1.

[0166] When the voltage of the global reset signal is at a high level, the fifteenth transistor M15 and the sixteenth transistor M16 can be turned on at the same time under the action of the global reset signal, and the sixteenth transistor M16 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the anti-leakage node OFF. <n>, the fifteenth transistor M15 can turn off the leakage protection node <n>The fifth voltage signal is transmitted to the pull-up node Q <n>, pull up node Q <n>Perform a reset.

[0167] Here, at the pull-up node Q <n>When the potential of the node Q is high and the third reset circuit 3107 is not in operation, the third transistor M3 can pull up the node Q <n>The first voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the node Q is increased, thereby making the voltage difference between the control electrode and the second electrode of the fifteenth transistor M15 less than zero, ensuring that the fifteenth transistor M15 is completely or relatively completely turned off. <n>Leakage occurs through the third reset circuit 3107, causing the node Q to be pulled up. <n>Able to maintain a higher and more stable voltage.

[0168] For example, Figure 6 As shown, the fourth reset circuit 3108 is connected to the pull-down node QB_A and the shift signal terminal CR <n>, the first output signal terminal Oput1 <n>, the second output signal terminal Oput2 <n>, the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 are electrically connected. The fourth reset circuit 3108 is configured to, under the control of the voltage of the pull-down node QB_A, reset the shift signal terminal CR <n>, the first output signal terminal Oput1 <n>And the second output signal terminal Oput2 <n>The third voltage signal terminal VGL2 is configured to transmit a DC low-level signal (for example, lower than or equal to the low-level portion of the clock signal). The third voltage signal terminal VGL2 can be grounded, for example. The low-level signals transmitted by the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 can be equal or unequal.

[0169] For example, when the voltage of the pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Pull-down reset is performed to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second output signal terminal Oput2 <n>, for the second output signal terminal Oput2 <n>Pull-down reset.

[0170] Optional, such as Figure 6 As shown, the fourth reset circuit 3108 may include: a seventeenth transistor M17, an eighteenth transistor M18 and a nineteenth transistor M19.

[0171] For example, Figure 6 As shown, the control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A, and the first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR <n>The second electrode of the seventeenth transistor M17 is electrically connected to the second voltage signal terminal VGL1.

[0172] When the voltage of the pull-down node QB_A is at a high level, the seventeenth transistor M17 can be turned on by the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset.

[0173] For example, Figure 6 As shown, the control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A, and the first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 <n>The second electrode of the eighteenth transistor M18 is electrically connected to the third voltage signal terminal VGL2.

[0174] When the voltage of the pull-down node QB_A is at a high level, the eighteenth transistor M18 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1. <n>, for the first output signal terminal Oput1 <n>Pull-down reset.

[0175] For example, Figure 6 As shown, the control electrode of the nineteenth transistor M19 is electrically connected to the pull-down node QB_A, and the first electrode of the nineteenth transistor M19 is electrically connected to the second output signal terminal Oput2 <n>The second electrode of the nineteenth transistor M19 is electrically connected to the third voltage signal terminal VGL2.

[0176] When the voltage of the pull-down node QB_A is at a high level, the nineteenth transistor M19 can be turned on under the action of the voltage of the pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second output signal terminal Oput2. <n>, for the second output signal terminal Oput2 <n>Pull-down reset.

[0177] For example, Figure 5 and Figure 6 As shown, the fifth reset circuit 3109 is electrically connected to the input signal terminal Iput, the pull-down node QB_A and the second voltage signal terminal VGL1. The fifth reset circuit 3109 is configured to reset the pull-down node QB_A under the control of the input signal transmitted by the input signal terminal Iput.

[0178] For example, when the level of the input signal is high, the fifth reset circuit 3109 may be turned on by the input signal to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, thereby pulling down and resetting the pull-down node QB_A.

[0179] Optional, such as Figure 5 and Figure 6 As shown, the fifth reset circuit 3109 may include: a twentieth transistor M20.

[0180] For example, Figure 5 and Figure 6 As shown, the control electrode of the twentieth transistor M20 is electrically connected to the input signal terminal Iput, the first electrode of the twentieth transistor M20 is electrically connected to the pull-down node QB_A, and the second electrode of the twentieth transistor M20 is electrically connected to the second voltage signal terminal VGL1.

[0181] When the level of the input signal is high, the twentieth transistor M20 may be turned on by the input signal to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the pull-down node QB_A, and pull down and reset the pull-down node QB_A.

[0182] It should be noted that if Figure 6 As shown, the gate driving circuit 3 may further include: a plurality of blanking input circuits 32. Among them, one blanking input circuit 32 may be electrically connected to at least two adjacent shift registers 31. That is, at least two shift registers 31 share one blanking input circuit 32. Among them, the blanking input circuit 32 is configured to control the corresponding shift register 31 to input a blanking control signal to the pixel driving circuit 21 of the corresponding row during the blanking period of a frame display stage, so that the pixel driving circuit 21 obtains the sensing signal.

[0183] Here, if Figure 6 As shown, the blanking input circuit 32 may include, for example: a selection control circuit 3201 , a second input circuit 3202 and at least two transmission circuits 3203 .

[0184] For example, Figure 6 As shown, the selection control circuit 3201 is connected to the selection control signal terminal OE and the shift signal terminal CR <n>, the second voltage signal terminal VGL1 and the first blanking node H. The selection control circuit 3201 is configured to, under the control of the selection control signal transmitted by the selection control signal terminal OE, shift the signal terminal CR to the shift signal terminal CR. <n>The shift signal received at is transmitted to the first blanking node H.

[0185] For example, when the level of the selection control signal is high, the selection control circuit 3201 can be turned on under the control of the selection control signal, and transmit the received shift signal to the first blanking node H, charge the first blanking node H, so that the voltage of the first blanking node H increases.

[0186] During the blanking period of a frame display stage, when it is necessary to obtain a sensing signal, the waveform timing of the selection control signal can be made the same as the waveform timing of the input signal, thereby turning on the selection control circuit 3201.

[0187] Optional, such as Figure 6 As shown, the selection control circuit 3201 may include: a twenty-first transistor M21, a twenty-second transistor M22 and a third capacitor C3.

[0188] For example, Figure 6 As shown, the control electrode of the twenty-first transistor M21 is electrically connected to the selection control signal terminal OE, and the first electrode of the twenty-first transistor M21 is electrically connected to the shift signal terminal CR <n>The second electrode of the 21st transistor M21 is electrically connected to the first electrode of the 22nd transistor M22. The control electrode of the 22nd transistor M22 is electrically connected to the selection control signal terminal OE, and the second electrode of the 22nd transistor M22 is electrically connected to the first blanking node H.

[0189] When the level of the selection control signal transmitted by the selection control signal terminal OE is high, the twenty-first transistor M21 and the twenty-second transistor M22 can be turned on at the same time under the action of the selection control signal, and the twenty-first transistor M21 can shift the shift signal terminal CR <n>The transmitted shift signal is transmitted to the first electrode of the twenty-second transistor M22 . The twenty-second transistor M22 can receive and transmit the shift signal to the first blanking node H to charge the first blanking node H.

[0190] For example, Figure 6 As shown, a first end of the third capacitor C3 is electrically connected to the first blanking node H, and a second end of the third capacitor C3 is electrically connected to the second voltage signal terminal VGL1.

[0191] The third capacitor C3 is also charged when the selection control circuit 3201 charges the first blanking node H. In this way, when the selection control circuit 3201 is turned off, the third capacitor C3 is used to discharge, so that the first blanking node H maintains a high level.

[0192] In addition, if Figure 6 As shown, the selection control circuit 3201 may further include, for example: a twenty-third transistor M23. The control electrode of the twenty-third transistor M23 is electrically connected to the first blanking node H, the first electrode of the twenty-third transistor M23 is electrically connected to the first voltage signal terminal VDD, and the second electrode of the twenty-third transistor M23 is electrically connected to the first electrode of the twenty-second transistor M22.

[0193] When the voltage of the first blanking node H is at a high level and the 21st transistor M21 and the 22nd transistor M22 are not working, the 23rd transistor M23 can be turned on under the control of the voltage of the first blanking node H, and the first voltage signal transmitted by the first voltage signal terminal VDD is transmitted to the first electrode of the 22nd transistor M22, so that the voltage of the first electrode of the 22nd transistor M22 is increased, and then the voltage difference between the control electrode and the first electrode of the 22nd transistor M22 is less than zero, ensuring that the 22nd transistor M22 is completely or relatively completely turned off. In this way, the first blanking node H can be prevented from leaking through the 22nd transistor M22, so that the first blanking node H can maintain a higher and more stable voltage.

[0194] For example, Figure 6 As shown, the second input circuit 3202 is electrically connected to the first blanking node H, the second blanking node N and the second clock signal terminal CLKA or the first voltage signal terminal VDD. The second input circuit 3202 is configured to transmit the second clock signal received at the second clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD to the second blanking node N under the control of the voltage of the first blanking node H.

[0195] For example, when the selection control circuit 3201 is turned on and the voltage of the first blanking node H increases, the second input circuit 3202 can be turned on under the control of the voltage of the first blanking node H, receive the second clock signal transmitted by the second clock signal terminal CLKA, and transmit the second clock signal to the second blanking node N.

[0196] Optional, such as Figure 6 As shown, the second input circuit 3202 may include: a twenty-fourth transistor M24.

[0197] For example, Figure 6 As shown, the control electrode of the twenty-fourth transistor M24 is electrically connected to the first blanking node H, the first electrode of the twenty-fourth transistor M24 is electrically connected to the second clock signal terminal CLKA or the first voltage signal terminal VDD, and the second electrode of the twenty-fourth transistor M24 is electrically connected to the second blanking node N.

[0198] When the voltage of the first blanking node H is at a high level, the twenty-fourth transistor M24 can be turned on under the control of the voltage of the first blanking node H, and transmit the fourth clock signal received at the fourth clock signal terminal CLKA or the first voltage signal received at the first voltage signal terminal VDD to the second blanking node N.

[0199] For example, Figure 6 As shown, the at least two transmission circuits 3203 can be electrically connected to at least two shift registers 31 in a one-to-one correspondence. One transmission circuit 3203 is connected to the second blanking node N, the second clock signal terminal CLKA and the pull-up node Q of the first shift register 31. <n>The transmission circuit 3202 is configured to transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q under the control of the second clock signal transmitted by the second clock signal terminal CLKA. <n>.

[0200] For example, when the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the transmission circuit 3202 can be turned on under the control of the second clock signal, and receive the second clock signal or the first voltage signal from the second blanking node N, and transmit the received second clock signal or the first voltage signal to the pull-up node Q <n>, so that the pull-up node Q <n>The voltage of the output circuit 3103 is increased, so that the output circuit 3103 is turned on, so that the second output signal terminal Oput2 of the output circuit 3103 <n>A second output signal is output.

[0201] Optional, such as Figure 6 As shown, the transmission circuit 3203 may include: a twenty-fifth transistor M25 and a twenty-sixth transistor M26.

[0202] For example, Figure 6 As shown, the control electrode of the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, the first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and the second electrode of the twenty-fifth transistor M25 is electrically connected to the first electrode of the twenty-sixth transistor M26. The control electrode of the twenty-sixth transistor M26 is electrically connected to the second clock signal terminal CLKA, and the second electrode of the twenty-sixth transistor M26 is electrically connected to the pull-up node Q <n>Electrical connection.

[0203] When the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the twenty-fifth transistor M25 and the second sixteenth transistor M26 can be turned on at the same time under the action of the second clock signal, and the twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the first electrode of the twenty-sixth transistor M26, and the twenty-sixth transistor M26 can receive and transmit the second clock signal or the first voltage signal to the pull-up node Q <n>, pull up node Q <n>The sixth transistor M6 in the output circuit 3103 can pull up the node Q <n>The fourth clock signal is turned on under the control of the voltage of the first output terminal Oput2, and the fourth clock signal is output as the second output signal from the second output signal terminal Oput2 <n>Output.

[0204] The transmission circuit 3203 also has an anti-leakage node OFF <n>In case of electrical connection, Figure 6 As shown, the first electrode of the twenty-sixth transistor M26 can be connected to the anti-leakage node OFF <n>And the second electrode of the twenty-fifth transistor M25 is electrically connected.

[0205] Here, at the pull-up node Q <n>When the potential of the node Q is high and the transmission circuit 3203 is not in operation, the third transistor M3 can pull up the node Q <n>The first voltage signal is transmitted to the anti-leakage node OFF. <n>, making the leakage protection node OFF <n>The voltage of the 26th transistor M26 is increased, so that the voltage difference between the control electrode and the first electrode of the 26th transistor M26 is less than zero, ensuring that the 26th transistor M26 is completely or relatively completely turned off. <n>Leakage occurs through the transmission circuit 3203, causing the pull-up node Q <n>Able to maintain a higher and more stable voltage.

[0206] For example, Figure 6 As shown, when the gate driving circuit 3 further includes a blanking input circuit 32, the shift register 31 may further include: a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A and the second voltage signal terminal VGL1. The sixth reset circuit 3110 is configured to reset the pull-down node QB_A under the common control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H during the blanking period of a frame display stage.

[0207] For example, in the blanking period of a frame display stage, when the level of the second clock signal is high and the voltage of the first blanking node H is high, the sixth reset circuit 3110 can be turned on under the joint control of the second clock signal and the voltage of the first blanking node H, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the pull-down node QB_A, thereby pulling down and resetting the pull-down node QB_A.

[0208] Optional, such as Figure 6 As shown, the sixth reset circuit 3110 may include: a thirty-second transistor M32 and a thirty-third transistor M33.

[0209] For example, Figure 6 As shown, the control electrode of the 32nd transistor M32 is electrically connected to the second clock signal terminal CLKA, the first electrode of the 32nd transistor M32 is electrically connected to the pull-down node QB_A, and the second electrode of the 32nd transistor M32 is electrically connected to the first electrode of the 33rd transistor M33. The control electrode of the 33rd transistor M33 is electrically connected to the first blanking node H, and the second electrode of the 33rd transistor M33 is electrically connected to the second voltage signal terminal VGL1.

[0210] When the level of the second clock signal is high and the voltage of the first blanking node H is high, the thirty-third transistor M33 can be turned on under the control of the voltage of the first blanking node H, and the second voltage signal is transmitted to the first electrode of the thirty-third transistor M33. The thirty-second transistor M32 can be turned on under the control of the second clock signal, and the second voltage signal is transmitted from the first electrode of the thirty-third transistor M33 to the pull-down node QB_A, thereby pulling down and resetting the pull-down node QB_A.

[0211] like Figure 6 As shown, the structure of the gate driving circuit 3 is schematically described by taking the example that two adjacent stages of shift registers 31 share a blanking input circuit 32. In which, further, N represents a positive odd number.

[0212] Here, if Figure 6 As shown, in two adjacent stages of shift registers 31, the output circuit 3103 in the next stage of shift register 31 may not be provided with the fourth transistor M4, and is not electrically connected to the third clock signal terminal CLKD_1.

[0213] Based on this, the shift signal terminal CR in the Nth stage shift register 31 <n>It can be electrically connected to the input signal terminal Iput in the N+2-th and N+3-th shift registers 31, thereby connecting the shift signal terminal CR <n>The output shift signal is used as the input signal of the N+2nd and N+3rd stage shift registers 31. The display reset signal terminal STD of the Nth and N+1st stage shift registers 31 can be connected to the shift signal terminal CR of the N+4th stage shift register 31.<N+4> The shift signal terminal CR of the N+4th stage shift register 31 is electrically connected to<N+4> The output shift signal serves as a display reset signal for the Nth stage and the N+1th stage shift register 31. Of course, the cascade connection of the multiple stages of shift registers 31 is not limited to this.

[0214] For example, the shift signal terminal CR in the first stage shift register 31 <n>The shift signal terminal CR in the fifth stage shift register 31 can be electrically connected to the input signal terminal Iput in the third stage and the fourth stage shift register 31. <n>It can be electrically connected to the display reset signal terminal STD in the first stage and the second stage shift register 31 .

[0215] This helps to simplify the structure of the gate driving circuit 3 and reduce the space occupied by the gate driving circuit 3 in the display panel 100 .

[0216] For example, Figure 6 As shown, in the two adjacent stages of shift registers 31, the first stage (i.e., the Nth stage) shift register 31 can be called the first scanning unit 31a, and the next stage (i.e., the N+1th stage) shift register 31 can be called the second scanning unit 31b. At this time, the pull-up node Q in the first scanning unit 31a can be <n>It is called the first pull-up node Q <n>, pull up the node Q in the second scanning unit 31b <n>The second pull-up node Q<N+1> The pull-down node QB_A in the first scanning unit 31a can be called the first pull-down node QB_A, and the pull-down node QB_A in the second scanning unit 31b can be called the second pull-down node QB_B. The leakage prevention node OFF in the first scanning unit 31a can be called <n>It is called the first leakage protection node OFF <n>, turn off the leakage protection node in the second scanning unit 31b <n>It is called the second leakage protection node OFF<N+1> The first clock signal CLKE_1 in the second scanning unit 31b can be called the fifth clock signal CLKE_2, and the fourth clock signal CLKF_1 in the second scanning unit 31b can be called the sixth clock signal CLKF_2. The first output signal terminal Oput1 in the first scanning unit 31a can be called <n>It is called the first sub-output signal terminal Oput1 <n>, the second output signal terminal Oput2 in the first scanning unit 31a <n>It is called the second sub-output signal terminal Oput2 <n>, the first output signal terminal Oput1 in the second scanning unit 31b <n>It is called the third sub-output signal terminal Oput1<N+1> , the second output signal terminal Oput2 in the second scanning unit 31b <n>It is called the fourth sub-output signal terminal Oput2<N+1> .

[0217] For example, Figure 6 As shown, the control circuit 3104 in the second scanning unit 31b can be electrically connected to the seventh voltage signal terminal VDD_B, and the seventh voltage signal terminal VDD_B is used to replace the sixth voltage signal terminal VDD_A. In the display stage of one frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are inverted signals.

[0218] For example, Figure 6 As shown, the first reset circuit 3105 in the first scanning unit 31a can also be electrically connected to the second pull-down node QB_B. The first reset circuit 3105 is further configured to, under the control of the voltage of the second pull-down node QB_B, reset the first pull-up node Q <n>Perform a reset.

[0219] For example, when the voltage of the second pull-down node QB_B is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the second pull-down node QB_B, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the first pull-up node Q <n>, for the first pull-up node Q <n>Pull-down reset.

[0220] Optional, such as Figure 6 As shown, the first reset circuit 3105 in the first scanning unit 31a may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0221] For example, Figure 6 As shown, in the first scanning unit 31a, the control electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-up node Q <n>The second electrode of the twenty-seventh transistor M27 is electrically connected to the first electrode of the twenty-eighth transistor M28 and the first leakage prevention node OFF. <n>The control electrode of the twenty-eighth transistor M28 is electrically connected to the second pull-down node QB_B, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL1.

[0222] When the voltage of the second pull-down node QB_B is at a high level, the twenty-seventh transistor M27 and the second eighteenth transistor M28 can be turned on at the same time under the action of the voltage of the second pull-down node QB_B, and the twenty-eighth transistor M28 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the first anti-leakage node OFF. <n>The twenty-seventh transistor M27 can turn off the first leakage prevention node <n>The second voltage signal is transmitted to the first pull-up node Q <n>, for the first pull-up node Q <n>Perform a reset.

[0223] For example, Figure 6 As shown, the first reset circuit 3105 in the second scanning unit 31b can also be electrically connected to the first pull-down node QB_A. The first reset circuit 3105 is further configured to, under the control of the voltage of the first pull-down node QB_A, reset the second pull-up node Q<N+1> Perform a reset.

[0224] For example, when the voltage of the first pull-down node QB_A is at a high level, the first reset circuit 3105 can be turned on under the action of the voltage of the first pull-down node QB_A, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the second pull-up node Q<N+1> , for the second pull-up node Q<N+1> Pull-down reset.

[0225] Optional, such as Figure 6 As shown, the first reset circuit 3105 in the second scanning unit 31b may further include: a twenty-seventh transistor M27 and a twenty-eighth transistor M28.

[0226] For example, Figure 6 As shown, in the second scanning unit 31b, the control electrode of the twenty-seventh transistor M27 is electrically connected to the first pull-down node QB_A, and the first electrode of the twenty-seventh transistor M27 is electrically connected to the second pull-up node Q<N+1> The second electrode of the twenty-seventh transistor M27 is electrically connected to the first electrode of the twenty-eighth transistor M28 and the second leakage prevention node OFF.<N+1> The control electrode of the twenty-eighth transistor M28 is electrically connected to the first pull-down node QB_A, and the second electrode of the twenty-eighth transistor M28 is electrically connected to the second voltage signal terminal VGL1.

[0227] When the voltage of the first pull-down node QB_A is at a high level, the twenty-seventh transistor M27 and the second eighteenth transistor M28 can be turned on at the same time under the action of the voltage of the first pull-down node QB_A, and the twenty-eighth transistor M28 can transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the second anti-leakage node OFF.<N+1> The twenty-seventh transistor M27 can turn off the power from the second leakage prevention node<N+1> The second voltage signal is transmitted to the second pull-up node Q<N+1> , for the second pull-up node Q<N+1> Perform a reset.

[0228] For example, Figure 6 As shown, the fourth reset circuit 3108 in the first scanning unit 31a can also be electrically connected to the second pull-down node QB_B. The fourth reset circuit 3108 is further configured to, under the control of the voltage of the second pull-down node QB_B, reset the shift signal terminal CR <n>, the first sub-output signal terminal Oput1 <n>And the second sub-output signal terminal Oput2 <n>Perform a reset.

[0229] For example, when the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the second pull-down node QB_B to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first sub-output signal terminal Oput1 <n>and the second sub-output signal terminal Oput2 <n>, for the first sub-output signal terminal Oput1 <n>and the second sub-output signal terminal Oput2 <n>Pull-down reset.

[0230] Optional, such as Figure 6 As shown, the fourth reset circuit 3108 in the first scanning unit 31a may further include: a twenty-ninth transistor M29, a thirtieth transistor M30 and a thirty-first transistor M31.

[0231] For example, Figure 6 As shown, the control electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-ninth transistor M29 is electrically connected to the shift signal terminal CR <n>The second electrode of the twenty-ninth transistor M29 is electrically connected to the second voltage signal terminal VGL1.

[0232] When the voltage of the second pull-down node QB_B is at a high level, the twenty-ninth transistor M29 can be turned on by the voltage of the second pull-down node QB_B to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR. <n>, for the shift signal terminal CR <n>Pull-down reset.

[0233] For example, Figure 6 As shown, the control electrode of the 30th transistor M30 is electrically connected to the second pull-down node QB_B, and the first electrode of the 30th transistor M30 is electrically connected to the first sub-output signal terminal Oput1 <n>The second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2.

[0234] When the voltage of the second pull-down node QB_B is at a high level, the 30th transistor M30 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmits the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1. <n>, for the first sub-output signal terminal Oput1 <n>Pull-down reset.

[0235] For example, Figure 6 As shown, the control electrode of the thirty-first transistor M31 is electrically connected to the second pull-down node QB_B, and the first electrode of the thirty-first transistor M31 is electrically connected to the second sub-output signal terminal Oput2 <n>The second electrode of the thirty-first transistor M31 is electrically connected to the third voltage signal terminal VGL2.

[0236] When the voltage of the second pull-down node QB_B is at a high level, the thirty-first transistor M31 can be turned on under the action of the voltage of the second pull-down node QB_B to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput2 <n>, for the second sub-output signal terminal Oput2 <n>Pull-down reset.

[0237] For example, Figure 6 As shown, the fourth reset circuit 3108 in the second scanning unit 31b can also be electrically connected to the first pull-down node QB_A. The fourth reset circuit 3108 is also configured to, under the control of the voltage of the first pull-down node QB_A, reset the third sub-output signal terminal Oput1<N+1> And the fourth sub-output signal terminal Oput2<N+1> Perform a reset.

[0238] For example, when the voltage of the first pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the third sub-output signal terminal Oput1.<N+1> , for the third sub-output signal terminal Oput1<N+1> Pull-down reset is performed to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2<N+1> , for the fourth sub-output signal terminal Oput2<N+1> Pull-down reset.

[0239] Optional, such as Figure 6 As shown, the fourth reset circuit 3108 in the second scanning unit 31b may further include: a thirtieth transistor M30 and a thirty-first transistor M31.

[0240] For example, Figure 6 As shown, the control electrode of the thirtieth transistor M30 is electrically connected to the first pull-down node QB_A, and the first electrode of the thirtieth transistor M30 is electrically connected to the third sub-output signal terminal Oput1<N+1> The second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2.

[0241] When the voltage of the first pull-down node QB_A is at a high level, the 30th transistor M30 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmits the third voltage signal transmitted by the third voltage signal terminal VGL2 to the third sub-output signal terminal Oput1.<N+1> , for the third sub-output signal terminal Oput1<N+1> Pull-down reset.

[0242] For example, Figure 6 As shown, the control electrode of the thirty-first transistor M31 is electrically connected to the first pull-down node QB_A, and the first electrode of the thirty-first transistor M31 is electrically connected to the fourth sub-output signal terminal Oput2<N+1> The second electrode of the thirty-first transistor M31 is electrically connected to the third voltage signal terminal VGL2.

[0243] When the voltage of the first pull-down node QB_A is at a high level, the thirty-first transistor M31 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the fourth sub-output signal terminal Oput2<N+1> , for the fourth sub-output signal terminal Oput2<N+1> Pull-down reset.

[0244] In other examples, such as Figure 5 and Figure 8 As shown, the shift register 31 may include: a first input circuit 3101, an anti-leakage circuit 3102, an output circuit 3103, a control circuit 3104, a first reset circuit 3105, a second reset circuit 3106, a third reset circuit 3107, a fourth reset circuit 3108 and a fifth reset circuit 3109.

[0245] Exemplarily, the structure and function of the first input circuit 3101 in this example may be the same as those of the first input circuit 3101 in some of the above examples, the structure and function of the leakage protection circuit 3102 in this example may be the same as those of the leakage protection circuit 3102 in some of the above examples, the structure and function of the control circuit 3104 in this example may be the same as those of the control circuit 3104 in some of the above examples, the structure and function of the first reset circuit 3105 in this example may be the same as those of the first reset circuit 3105 in some of the above examples, the structure and function of the second reset circuit 3106 in this example may be the same as those of the second reset circuit 3106 in some of the above examples, the structure and function of the third reset circuit 3107 in this example may be the same as those of the third reset circuit 3107 in some of the above examples, and the structure and function of the fifth reset circuit 3109 in this example may be the same as those of the fifth reset circuit 3109 in some of the above examples. The structures and functions of the same circuits will not be described in detail here.

[0246] For example, Figure 5 and Figure 8 As shown, the output circuit 3103 and the pull-up node Q <n>, a first clock signal terminal CLKE_1 and a first output signal terminal Oput1 <n>The output circuit 3103 is configured to pull up the node Q during the display period of a frame display stage. <n>Under the control of the voltage of <n>And, during the blanking period in a frame display phase, the pull-up node Q <n>Under the control of the voltage of <n>.

[0247] Of course, if Figure 5 and Figure 8 As shown, the output circuit 3103 can also be connected to the third clock signal terminal CLKD_1 and the shift signal terminal CR <n>The output circuit 3103 is also configured to, during a display period in a frame display phase, pull up the node Q <n>Under the control of the voltage of , the third clock signal received at the third clock signal terminal CLKD_1 is transmitted to the shift signal terminal CR <n>.

[0248] For example, during the display period of a frame display stage, at the pull-up node Q <n>When the voltage of the output circuit 3103 increases, the output circuit 3103 can pull up the node Q <n>The third clock signal received at the third clock signal terminal CLKD_1 is turned on under the control of the voltage of the third clock signal terminal CLKD_1, and the third clock signal received at the third clock signal terminal CLKD_1 is used as the shift signal, and the third clock signal received at the third clock signal terminal CLKD_1 is turned on under the control of the voltage of the third clock signal terminal CLKD_1, and the third clock signal received at the third clock signal terminal CLKD_1 is used as the shift <n>Output; the first clock signal received at the first clock signal terminal CLKE_1 is used as the output signal (ie, the first gate signal received by the pixel driving circuit 21), from the first output signal terminal Oput1 <n>Output. During the blanking period in a frame display phase, the pull-up node Q <n>When the voltage of the output circuit 3103 increases, the output circuit 3103 can pull up the node Q <n>The first clock signal received at the first clock signal terminal CLKE_1 is turned on under the control of the voltage of the first clock signal terminal CLKE_1, and the first clock signal received at the first clock signal terminal CLKE_1 is used as the output signal (that is, the second gate signal received by the pixel driving circuit 21), and the first output signal terminal Oput1 is output. <n>Output.

[0249] In this example, for example, the first output signal terminal Oput1 of the shift register 31 <n>It can be electrically connected to both the first gate line and the second gate line, so that during a display period in a frame display stage, the first output signal terminal Oput1 of the shift register 31 <n>The first gate signal can be transmitted to the pixel driving circuit 21 via the first gate line and the first gate signal terminal G1 in sequence, and during the blanking period in a frame display stage, the first output signal terminal Oput1 of the shift register 31 <n>The second gate signal can be transmitted to the pixel driving circuit 21 via the second gate line and the second gate signal terminal G2 in sequence. <n>The first gate signal terminal G1 and the second gate signal terminal G2 can be electrically connected to each other through a gate line, so that during a display period of a frame display stage, the first output signal terminal Oput1 of the shift register 31 <n>The first gate signal can be transmitted to the pixel driving circuit 21 via the gate line and the first gate signal terminal G1 in sequence, and during the blanking period in a frame display stage, the first output signal terminal Oput1 of the shift register 31 <n>The second gate signal may be transmitted to the pixel driving circuit 21 via the gate line and the second gate signal terminal G2 in sequence.

[0250] Optional, such as Figure 5 and Figure 8 As shown, the output circuit 3103 may include: a fourth transistor M4, a fifth transistor M5 and a first capacitor C1.

[0251] For example, Figure 5 and Figure 8 As shown, the control electrode of the fourth transistor M4 is connected to the pull-up node Q <n>The first electrode of the fourth transistor M4 is electrically connected to the third clock signal terminal CLKD_1, and the second electrode of the fourth transistor M4 is electrically connected to the shift signal terminal CR <n>Electrical connection.

[0252] During the display period of a frame display stage, the first input circuit 3101 is turned on, so that the pull-up node Q <n>When the voltage of the node Q increases, the fourth transistor M4 can pull up the node Q <n>The third clock signal is transmitted to the shift signal terminal CR under the control of the high voltage <n>and uses the third clock signal as a shift signal from the shift signal terminal CR <n>Output.

[0253] For example, Figure 5 and Figure 8 As shown, the control electrode of the fifth transistor M5 is connected to the pull-up node Q <n>The first electrode of the fifth transistor M5 is electrically connected to the first clock signal terminal CLKE_1, and the second electrode of the fifth transistor M5 is electrically connected to the first output signal terminal Oput1 <n>The first end of the first capacitor C1 is electrically connected to the pull-up node Q <n>The second end of the first capacitor C1 is electrically connected to the first output signal end Oput1 <n>Electrical connection.

[0254] During the display period of a frame display stage, when the first input circuit 3101 is turned on, the pull-up node Q <n>When the voltage of the first input circuit 3101 is turned off, the first capacitor C1 can be discharged, so that the pull-up node Q <n>The first clock signal is kept at a high level, so that the fifth transistor M5 can remain in a conducting state, and the first clock signal is transmitted to the first output signal terminal Oput1. <n>and uses the first clock signal as an output signal (that is, the first gate signal received by the pixel driving circuit 21) from the first output signal terminal Oput1 <n>Output.

[0255] During the blanking period of a frame display stage, the pull-up node Q <n>When the voltage of the first capacitor C1 increases, the first capacitor C1 will be charged. In the corresponding stage, the first capacitor C1 can be discharged, so that the pull-up node Q <n>Maintaining a high level, the fifth transistor M6 can remain in a conducting state, transmitting the first clock signal to the first first output signal terminal Oput1 <n>, and the first clock signal is used as an output signal (that is, the second gate signal received by the pixel driving circuit 21) from the first output signal terminal Oput1 <n>Output.

[0256] For example, Figure 5 and Figure 8 As shown, the fourth reset circuit 3108 is connected to the pull-down node QB_A and the shift signal terminal CR <n>, the first output signal terminal Oput1 <n>, the second voltage signal terminal VGL1 and the third voltage signal terminal VGL2 are electrically connected. The fourth reset circuit 3108 is configured to, under the control of the voltage of the pull-down node QB_A, reset the shift signal terminal CR <n>and the first output signal terminal Oput1 <n>Perform a reset.

[0257] For example, when the voltage of the pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed to transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1 <n>, for the first output signal terminal Oput1 <n>Pull-down reset.

[0258] Optional, such as Figure 5 and Figure 8 As shown, the fourth reset circuit 3108 may include: a seventeenth transistor M17 and an eighteenth transistor M18.

[0259] For example, Figure 5 and Figure 8 As shown, the control electrode of the seventeenth transistor M17 is electrically connected to the pull-down node QB_A, and the first electrode of the seventeenth transistor M17 is electrically connected to the shift signal terminal CR <n>The second electrode of the seventeenth transistor M17 is electrically connected to the second voltage signal terminal VGL1.

[0260] When the voltage of the pull-down node QB_A is at a high level, the seventeenth transistor M17 can be turned on by the voltage of the pull-down node QB_A to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset.

[0261] For example, Figure 5 and Figure 8 As shown, the control electrode of the eighteenth transistor M18 is electrically connected to the pull-down node QB_A, and the first electrode of the eighteenth transistor M18 is electrically connected to the first output signal terminal Oput1 <n>The second electrode of the eighteenth transistor M18 is electrically connected to the third voltage signal terminal VGL2.

[0262] When the voltage of the pull-down node QB_A is at a high level, the eighteenth transistor M18 can be turned on under the action of the voltage of the pull-down node QB_A, and transmits the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first output signal terminal Oput1. <n>, for the first output signal terminal Oput1 <n>Pull-down reset.

[0263] It should be noted that if Figure 8 As shown, the gate driving circuit 3 may further include: a plurality of blanking input circuits 32. Among them, one blanking input circuit 32 may be electrically connected to at least two adjacent shift registers 31. That is, at least two shift registers 31 share one blanking input circuit 32. Among them, the blanking input circuit 32 is configured to control the corresponding shift register 31 to input a blanking control signal to the pixel driving circuit 21 of the corresponding row during the blanking period of a frame display stage, so that the pixel driving circuit 21 obtains the sensing signal.

[0264] Here, if Figure 8 As shown, the blanking input circuit 32 may include, for example: a selection control circuit 3201 , a second input circuit 3202 and at least two transmission circuits 3203 .

[0265] Exemplarily, the structure and function of the selection control circuit 3201 in the blanking input circuit 32 in this example may be the same as those of the selection control circuit 3201 in the blanking input circuit 32 in some of the above examples, and the structure and function of the second input circuit 3202 in the blanking input circuit 32 in this example may be the same as those of the second input circuit 3202 in the blanking input circuit 32 in some of the above examples. The structures and functions of the same circuits will not be described in detail here.

[0266] For example, Figure 8 As shown, the at least two transmission circuits 3203 can be electrically connected to at least two shift registers 31 in a one-to-one correspondence. One transmission circuit 3203 is connected to the second blanking node N, the second clock signal terminal CLKA and the pull-up node Q of the first shift register 31. <n>The transmission circuit 3202 is configured to transmit the second clock signal or the first voltage signal received at the second blanking node N to the pull-up node Q under the control of the second clock signal transmitted by the second clock signal terminal CLKA during the blanking period of a frame display stage. <n>.

[0267] For example, during the blanking period of a frame display stage, when the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the transmission circuit 3202 can be turned on under the control of the second clock signal, and receive the second clock signal or the first voltage signal from the second blanking node N, and transmit the received second clock signal or the first voltage signal to the pull-up node Q <n>, so that the pull-up node Q <n>The voltage of the output circuit 3103 is increased, so that the output signal terminal of the output circuit 3103 is output. <n>Output signal.

[0268] Optional, such as Figure 8 As shown, the transmission circuit 3203 may include: a twenty-fifth transistor M25.

[0269] For example, Figure 8 As shown, the control electrode of the twenty-fifth transistor M25 is electrically connected to the second clock signal terminal CLKA, the first electrode of the twenty-fifth transistor M25 is electrically connected to the second blanking node N, and the second electrode of the twenty-fifth transistor M25 is electrically connected to the pull-up node Q <n>Electrical connection.

[0270] During the blanking period of a frame display stage, when the level of the second clock signal transmitted by the second clock signal terminal CLKA is high, the twenty-fifth transistor M25 can be turned on under the action of the second clock signal, and the twenty-fifth transistor M25 can transmit the second clock signal or the first voltage signal from the second blanking node N to the pull-up node Q <n>, pull up node Q <n>The fifth transistor M5 in the output circuit 3103 can pull up the node Q <n>The first clock signal is received and outputted as an output signal from the first output signal terminal Oput1. <n>Output.

[0271] For example, Figure 8 As shown, when the gate driving circuit 3 further includes a blanking input circuit 32, the shift register 31 may further include: a sixth reset circuit 3110. The sixth reset circuit 3110 is electrically connected to the second clock signal terminal CLKA, the first blanking node H, the pull-down node QB_A and the second voltage signal terminal VGL1. The sixth reset circuit 3110 is configured to reset the pull-down node QB_A under the common control of the second clock signal transmitted by the second clock signal terminal CLKA and the voltage of the first blanking node H during the blanking period of a frame display stage.

[0272] For example, in the blanking period of a frame display stage, when the level of the second clock signal is high and the voltage of the first blanking node H is high, the sixth reset circuit 3110 can be turned on under the joint control of the second clock signal and the voltage of the first blanking node H, and the second voltage signal transmitted by the second voltage signal terminal VGL1 is transmitted to the pull-down node QB_A, thereby pulling down and resetting the pull-down node QB_A.

[0273] Optional, such as Figure 8 As shown, the sixth reset circuit 3110 may include: a thirty-second transistor M32 and a thirty-third transistor M33.

[0274] For example, Figure 8 As shown, the control electrode of the 32nd transistor M32 is electrically connected to the first blanking node H, the first electrode of the 32nd transistor M32 is electrically connected to the pull-down node QB_A, and the second electrode of the 32nd transistor M32 is electrically connected to the first electrode of the 33rd transistor M33. The control electrode of the 33rd transistor M33 is electrically connected to the second clock signal terminal CLKA, and the second electrode of the 33rd transistor M33 is electrically connected to the second voltage signal terminal VGL1.

[0275] When the level of the second clock signal is high and the voltage of the first blanking node H is high, the thirty-third transistor M33 can be turned on under the control of the second clock signal, and the second voltage signal is transmitted to the first electrode of the thirty-third transistor M33. The thirty-second transistor M32 can be turned on under the control of the voltage of the first blanking node H, and the second voltage signal is transmitted from the first electrode of the thirty-third transistor M33 to the pull-down node QB_A, thereby pulling down and resetting the pull-down node QB_A.

[0276] like Figure 8 As shown, the structure of the gate driving circuit 3 is schematically described by taking the example that two adjacent stages of shift registers 31 share a blanking input circuit 32. In which, further, N represents a positive odd number.

[0277] Here, if Figure 8 As shown, in two adjacent stages of shift registers 31, the output circuit 3103 in the next stage of shift register 31 may not be provided with the fourth transistor M4, and is not electrically connected to the third clock signal terminal CLKD_1.

[0278] Exemplarily, the cascade relationship of the multi-stage shift registers 31 in this example may be the same as the cascade relationship of the multi-stage shift registers 31 in some of the above examples, which will not be described in detail here.

[0279] For example, in the two adjacent shift registers 31, the first shift register 31 (i.e., the Nth shift register 31) can be called the first scanning unit 31a, and the second shift register 31 (i.e., the N+1th shift register 31) can be called the second scanning unit 31b. <n>It is called the first pull-up node Q <n>, pull up the node Q in the second scanning unit 31b <n>The second pull-up node Q<N+1> The pull-down node QB_A in the first scanning unit 31a can be called the first pull-down node QB_A, and the pull-down node QB_A in the second scanning unit 31b can be called the second pull-down node QB_B. The leakage prevention node OFF in the first scanning unit 31a can be called <n>It is called the first leakage protection node OFF <n>, turn off the leakage protection node in the second scanning unit 31b <n>It is called the second leakage protection node OFF<N+1> The first clock signal CLKE_1 in the second scanning unit 31b can be called the fifth clock signal CLKE_2. The first output signal terminal Oput1 in the first scanning unit 31a can be called <n>It is called the first sub-output signal terminal Oput1 <n>, the first output signal terminal Oput1 in the second scanning unit 31b <n>It is called the second sub-output signal terminal Oput1<N+1> .

[0280] For example, Figure 8 As shown, the control circuit 3104 in the second scanning unit 31b can be electrically connected to the seventh voltage signal terminal VDD_B, and the seventh voltage signal terminal VDD_B is used to replace the sixth voltage signal terminal VDD_A. In the display stage of one frame, the sixth voltage signal transmitted by the sixth voltage signal terminal VDD_A and the seventh voltage signal transmitted by the seventh voltage signal terminal VDD_B are inverted signals.

[0281] Exemplarily, the structure and function of the first reset circuit 3105 in the first scanning unit 31a in this example may be the same as the structure and function of the first reset circuit 3105 in the first scanning unit 31a in some of the above examples, and the structure and function of the first reset circuit 3105 in the second scanning unit 31b in this example may be the same as the structure and function of the first reset circuit 3105 in the second scanning unit 31b in some of the above examples. The structures and functions of the same circuits are not described in detail here.

[0282] For example, Figure 8 As shown, the fourth reset circuit 3108 in the first scanning unit 31a can also be electrically connected to the second pull-down node QB_B. The fourth reset circuit 3108 is further configured to, under the control of the voltage of the second pull-down node QB_B, reset the shift signal terminal CR <n>and the first sub-output signal terminal Oput1 <n>Perform a reset.

[0283] For example, when the voltage of the second pull-down node QB_B is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the second pull-down node QB_B to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR <n>, for the shift signal terminal CR <n>Pull-down reset is performed, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the first sub-output signal terminal Oput1 <n>, for the first sub-output signal terminal Oput1 <n>Pull-down reset.

[0284] Optional, such as Figure 8 As shown, the fourth reset circuit 3108 in the first scanning unit 31a may further include: a twenty-ninth transistor M29 and a thirtieth transistor M30.

[0285] For example, Figure 8 As shown, the control electrode of the twenty-ninth transistor M29 is electrically connected to the second pull-down node QB_B, and the first electrode of the twenty-ninth transistor M29 is electrically connected to the shift signal terminal CR <n>The second electrode of the twenty-ninth transistor M29 is electrically connected to the second voltage signal terminal VGL1.

[0286] When the voltage of the second pull-down node QB_B is at a high level, the twenty-ninth transistor M29 can be turned on by the voltage of the second pull-down node QB_B to transmit the second voltage signal transmitted by the second voltage signal terminal VGL1 to the shift signal terminal CR. <n>, for the shift signal terminal CR <n>Pull-down reset.

[0287] For example, Figure 8 As shown, the control electrode of the 30th transistor M30 is electrically connected to the second pull-down node QB_B, and the first electrode of the 30th transistor M30 is electrically connected to the first sub-output signal terminal Oput1 <n>The second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2.

[0288] When the voltage of the second pull-down node QB_B is at a high level, the 30th transistor M30 can be turned on under the action of the voltage of the second pull-down node QB_B, and transmits the third voltage signal transmitted by the third voltage signal terminal VGL2 to the first sub-output signal terminal Oput1. <n>, for the first sub-output signal terminal Oput1 <n>Pull-down reset.

[0289] For example, Figure 8 As shown, the fourth reset circuit 3108 in the second scanning unit 31b can also be electrically connected to the first pull-down node QB_A. The fourth reset circuit 3108 is also configured to, under the control of the voltage of the first pull-down node QB_A, reset the second sub-output signal terminal Oput1<N+1> Perform a reset.

[0290] For example, when the voltage of the first pull-down node QB_A is at a high level, the fourth reset circuit 3108 can be turned on under the action of the voltage of the first pull-down node QB_A, and the third voltage signal transmitted by the third voltage signal terminal VGL2 is transmitted to the second sub-output signal terminal Oput1.<N+1> , for the second sub-output signal terminal Oput1<N+1> Pull-down reset.

[0291] Optional, such as Figure 8 As shown, the fourth reset circuit 3108 in the second scanning unit 31b may further include: a thirtieth transistor M30.

[0292] For example, Figure 8 As shown, the control electrode of the 30th transistor M30 is electrically connected to the first pull-down node QB_A, and the first electrode of the 30th transistor M30 is electrically connected to the second sub-output signal terminal Oput2<N+1> The second electrode of the thirtieth transistor M30 is electrically connected to the third voltage signal terminal VGL2.

[0293] When the voltage of the first pull-down node QB_A is at a high level, the 30th transistor M30 can be turned on under the action of the voltage of the first pull-down node QB_A, and transmit the third voltage signal transmitted by the third voltage signal terminal VGL2 to the second sub-output signal terminal Oput1.<N+1> , for the second sub-output signal terminal Oput1<N+1> Pull-down reset.

[0294] Next, the structure of the gate driving circuit 3 is further schematically described by taking the structure of the shift register 31 shown in the first example as an example.

[0295] In some examples, such as Figure 7 As shown, the gate driving circuit 3 may further include: a plurality of control signal lines 33 extending along the second direction Y. Among them, the first-stage shift register 31 is electrically connected to at least a portion of the plurality of control signal lines 33. The shift register 31 is configured to provide output signals to a plurality of pixel driving circuits 21 of a corresponding row under the control of at least a portion of the control signal lines 33 electrically connected to the shift register 31.

[0296] Here, at least a portion of the plurality of control signal lines 33 may refer to some control signal lines 33 among the plurality of control signal lines 33 .

[0297] For example, Figure 7 A1, A2, A3...A6 shown in the figure represent the first-stage shift register 31, the second-stage shift register 31, the third-stage shift register 31...the sixth-stage shift register 31, respectively, and are electrically connected to the pixel driving circuit 21 of the first row of sub-pixels 2, the pixel driving circuit 21 of the second row of sub-pixels 2, the pixel driving circuit 21 of the third row of sub-pixels 2...the pixel driving circuit 21 of the sixth row of sub-pixels 2 in the display panel 100, respectively.

[0298] Among them, A1, A3, A5 can be respectively output through the first sub-output signal terminal Oput1 <n>The first gate signal terminal G1 in the corresponding row pixel driving circuit 21 is electrically connected to the second sub-output signal terminal Oput2 <n>A2, A4, A6 can be electrically connected to the second gate signal terminal G2 in the corresponding row pixel driving circuit 21.<N+1> The first gate signal terminal G1 in the corresponding row pixel driving circuit 21 is electrically connected to the fourth sub-output signal terminal Oput2<N+1> Electrically connected to the second gate signal terminal G2 in the pixel driving circuit 21 of the corresponding row.

[0299] Here, A1, A3, and A5 may be respectively referred to as first scanning units 31a, and A2, A4, and A6 may be respectively referred to as second scanning units 31b.

[0300] For example, Figure 7 As shown, the plurality of control signal lines 33 may include: a first clock signal line CLK_1 , a second clock signal line CLK_2 , and a third clock signal line CLK_3 .

[0301] The third clock signal terminal CLKD_1 in the first stage shift register 100 is electrically connected to the first clock signal line CLK_1 to receive the third clock signal. The third clock signal terminal CLKD_1 in the third stage shift register 100 is electrically connected to the second clock signal line CLK_2 to receive the third clock signal. The third clock signal terminal CLKD_1 in the fifth stage shift register 100 is electrically connected to the third clock signal line CLK_3 to receive the third clock signal.

[0302] For example, Figure 7 As shown, the above-mentioned multiple control signal lines 33 may also include: a fourth clock signal line CLK_4, a fifth clock signal line CLK_5, a sixth clock signal line CLK_6, a seventh clock signal line CLK_7, an eighth clock signal line CLK_8, a ninth clock signal line CLK_9, a tenth clock signal line CLK_10, an eleventh clock signal line CLK_11, a twelfth clock signal line CLK_12, a thirteenth clock signal line CLK_13, a fourteenth clock signal line CLK_14 and a fifteenth clock signal line CLK_15.

[0303] The first clock signal terminal CLKE_1 in the first stage shift register 100 is electrically connected to the fourth clock signal line CLK_4 to receive the first clock signal, and the fourth clock signal terminal CLKF_1 is electrically connected to the fifth clock signal line CLK_5 to receive the fourth clock signal.

[0304] The fifth clock signal terminal CLKE_2 in the second stage shift register 100 is electrically connected to the sixth clock signal line CLK_6 to receive the fifth clock signal, and the sixth clock signal terminal CLKE_2 is electrically connected to the seventh clock signal line CLK_7 to receive the sixth clock signal.

[0305] The first clock signal terminal CLKE_1 in the third stage shift register 100 is electrically connected to the eighth clock signal line CLK_8 to receive the first clock signal, and the fourth clock signal terminal CLKF_1 is electrically connected to the ninth clock signal line CLK_9 to receive the fourth clock signal.

[0306] The fifth clock signal terminal CLKE_2 in the fourth stage shift register 100 is electrically connected to the tenth clock signal line CLK_10 to receive the fifth clock signal, and the sixth clock signal terminal CLKE_2 is electrically connected to the eleventh clock signal line CLK_11 to receive the sixth clock signal.

[0307] The first clock signal terminal CLKE_1 in the fifth stage shift register 100 is electrically connected to the twelfth clock signal line CLK_12 to receive the first clock signal, and the fourth clock signal terminal CLKF_1 is electrically connected to the thirteenth clock signal line CLK_13 to receive the fourth clock signal.

[0308] The fifth clock signal terminal CLKE_2 in the sixth stage shift register 100 is electrically connected to the fourteenth clock signal line CLK_14 to receive the fifth clock signal, and the sixth clock signal terminal CLKE_2 is electrically connected to the fifteenth clock signal line CLK_15 to receive the sixth clock signal.

[0309] For example, Figure 7 As shown, the plurality of control signal lines 33 may further include: a sixteenth clock signal line CLK_16.

[0310] The global reset signal terminal TRST in each stage of the shift register 31 is electrically connected to the sixteenth clock signal line CLK_16 to receive the global reset signal.

[0311] For example, Figure 7 As shown, the plurality of control signal lines 33 may further include: a seventeenth clock signal line CLK_17 and an eighteenth clock signal line CLK_18.

[0312] The selection control signal terminal OE of each blanking input circuit 32 is electrically connected to the seventeenth clock signal line CLK_17 to receive the selection control signal.

[0313] The second clock signal terminal CLKA of each blanking input unit 5 is electrically connected to the eighteenth clock signal line CLK_18 to receive the second clock signal.

[0314] For example, Figure 7 As shown, the plurality of control signal lines 33 may further include: a nineteenth clock signal line CLK_19 and a twentieth clock signal line CLK_20.

[0315] The sixth voltage signal terminal VDD_A in the first stage shift register 31 , the sixth voltage signal terminal VDD_A in the third stage shift register 31 and the sixth voltage signal terminal VDD_A in the fifth stage shift register 31 are all electrically connected to the nineteenth clock signal line CLK_19 to receive the sixth voltage signal.

[0316] The seventh voltage signal terminal VDD_B in the second shift register 31, the seventh voltage signal terminal VDD_B in the fourth shift register 31 and the seventh voltage signal terminal VDD_B in the sixth shift register 31 are all electrically connected to the twentieth clock signal line CLK_20 to receive the seventh voltage signal.

[0317] For example, Figure 7 As shown, the plurality of control signal lines 33 may further include: a twenty-first clock signal line CLK_21.

[0318] The input signal terminal Iput in the first-stage shift register 31 and the input signal terminal Iput in the second-stage shift register 31 may both be electrically connected to the twenty-first clock signal line CLK_21 to receive the start signal as an input signal.

[0319] For example, Figure 7 As shown, the plurality of control signal lines 33 may further include: a twenty-second clock signal line CLK_22.

[0320] The display reset signal terminals STD of the last four stages of shift registers 31 in the gate driving circuit 3 may all be electrically connected to the twenty-second clock signal line CLK_22 to receive the display reset signal.

[0321] Exemplarily, in the gate driving circuit 3, in the other stages of the shift registers 31 except the first stage shift register 31 and the second stage shift register 31, the shift signal terminal CR in the Nth stage shift register 31 is <n>It can be electrically connected to the input signal terminal Iput in the N+2-th and N+3-th shift registers 31, thereby connecting the shift signal terminal CR <n>The output shift signal is used as an input signal in the N+2nd and N+3rd shift registers 31. In the shift registers 31 of other stages except the last four stages 31, the display reset signal terminal STD of the Nth and N+1st stage shift registers 31 can be connected to the shift signal terminal CR of the N+4th stage shift register 31.<N+4> The shift signal terminal CR of the N+4th stage shift register 31 is electrically connected to<N+4> The output shift signal serves as a display reset signal for the Nth stage and the N+1th stage shift register 31 .

[0322] In related technologies, such as Figure 1 As shown, the display panel PNL generally has a display area A and a frame area B surrounding the display area A. The sub-pixels P in the display panel PNL are generally arranged in the display area A, and the gate driving circuit 3' electrically connected to the sub-pixels P is generally arranged in the frame area B and located on one side of the extension direction of the gate line GL.

[0323] As the resolution of display panels increases, narrow borders or even borderless display panels have become a current development trend. In the display field, especially in large-size OLED displays, it is difficult to achieve narrow borders or even borderless display panels PNL by setting the gate drive circuit 3' in the border area B of the display panel PNL. Moreover, the shape of the display panel PNL is currently mostly designed as a non-rectangular shape, which makes it more difficult to achieve narrow borders or even borderless display panels PNL using the above-mentioned setting method to set the gate drive circuit 3'.

[0324] Based on this, Figure 3 As shown, the display panel 100 provided by some embodiments of the present disclosure can divide the multiple transistors and capacitors included in each stage of the shift register 31 into multiple device groups 311, and the multiple device groups 311 are respectively arranged in the area (first gap area D) between two adjacent sub-pixels 2 in at least one row of sub-pixels 2.

[0325] For example, Figure 9a to Figure 9h As shown, each device group 311 may include at least one transistor and / or at least one capacitor. Figure 9a to Figure 9h The structure shown is a structure connected sequentially. Since it is difficult to show the structure in one figure, the structure is divided into multiple figures.

[0326] Here, the way of dividing the multiple transistors and capacitors included in the shift register 31 can be selected and set according to actual needs, so that the space occupied by the divided device group 311 is smaller and the complexity of the connection relationship between the device groups 311 is lower.

[0327] For example, Figure 9b As shown, one device group 311 may include a first transistor M1 and a second transistor M2 in a first input circuit 3101 .

[0328] For example, Figure 9a As shown, one device group 311 may include a third transistor M3 in the leakage protection circuit 3102 .

[0329] For example, Figure 9g As shown, one device group 311 may include a first capacitor C1 in the output circuit 3103 .

[0330] For example, Figure 9d As shown, one device group 311 may include a seventh transistor M7 , an eighth transistor M8 , a ninth transistor M9 , and a tenth transistor M10 in the control circuit 3104 .

[0331] For example, Fig.9c As shown, one device group 311 may include the eleventh transistor M11 in the first reset circuit 3105 . Another device group 311 may include the twelfth transistor M12 in the first reset circuit 3105 .

[0332] It should be noted that Figure 9a to Figure 9h The circuit diagram of the shift register 31 shown in FIG. 1 is an equivalent circuit diagram of the shift register 31 in an actual product. In an actual product, some circuits include a plurality of transistors arranged in parallel. Figure 9a to Figure 9h Only one of the shift registers 31 shown in the circuit diagram of FIG.

[0333] For example, the first input circuit 3101 includes a first transistor M1 and a second transistor M2. Figure 9b Only one is shown. In an actual product, the first input circuit 3101 may include a plurality of first transistors M1 and second transistors M2 connected in parallel. Each first transistor M1 and a second transistor M2 may constitute a device group 311, which is disposed in a region between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2.

[0334] For another example, the fifth transistor M5 included in the output circuit 3103 is Figure 9h In the actual product, the output circuit 3103 may include a plurality of fifth transistors M5 connected in parallel, wherein each fifth transistor M5 may constitute a device group 311, which is arranged in the region between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2.

[0335] Exemplarily, one device group 311 is located in the region between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2. That is, at least a portion of the device groups 311 included in the first-stage shift register 31 may be located in the region between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2.

[0336] For example, Figure 9a to Figure 9h As shown, the arrangement of the device group 311 in the region between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2 may be: when the device group 311 is arranged in the region between two adjacent sub-pixels 2 in a row of sub-pixels 2, only one device group 311 is arranged in the region. That is, the regions where the multiple device groups 311 included in the shift register 31 are located are different, and at least one sub-pixel 2 is arranged between two adjacent device groups 311. Among them, "a corresponding row of sub-pixels 2" refers to a row of sub-pixels 2 electrically connected to the primary shift register 31, and the output signal output by the shift register 31 can be transmitted to the row of sub-pixels 2.

[0337] For example, the number of regions between two adjacent sub-pixels 2 in a row of sub-pixels 2 may be greater than the number of device groups 311 included in the primary shift register 31. In this way, the device group 311 included in the primary shift register 31 may be located only in a portion of the regions in a corresponding row of sub-pixels 2, and the device group 311 is not provided in the remaining regions.

[0338] By setting at least a part of the multiple device groups 311 included in the shift register 31 in the area between two adjacent sub-pixels 2 in a corresponding row of sub-pixels 2, the space occupied by the portion of the gate drive circuit 3 located in the border area can be effectively reduced, which is conducive to enabling the display panel 100 to achieve a narrow border design or even a borderless design.

[0339] For example, Figure 9a to Figure 9h As shown, the division method of the multiple device groups 311 included in the shift registers 31 of different stages is the same, and the arrangement order of the multiple device groups 311 included in the shift registers 31 of different stages and the setting positions in the corresponding rows of sub-pixels 2 can be the same. That is, among the multiple device groups 311 included in the shift registers 31 of different stages, the device groups 311 with the same structure can be located in the area between the same two adjacent columns of sub-pixels 2.

[0340] For example, Figure 9a As shown, in the shift registers 31 of different stages, a plurality of device groups 311 including the third transistor M3 can be located in the region between the same two adjacent columns of sub-pixels 2. Fig.9c As shown, in the shift registers 31 of different stages, a plurality of device groups 311 each including the eleventh transistor M11 may be located in a region between two adjacent columns of sub-pixels 2 .

[0341] This helps to reduce the difficulty of layout design of the display panel 100 and improve the regularity of the layout of the display panel 100 .

[0342] Of course, the division method of the multiple device groups 311 included in different levels of shift registers 31 can be different, and the arrangement order of the multiple device groups 311 included in different levels of shift registers 31 and the setting positions in the corresponding row sub-pixels 2 can also be different, which can be selected according to actual needs.

[0343] In some examples, such as Figure 3 , Figure 9f and Fig.10 As shown in FIG. 1 , after the multi-stage shift register 31 is cascaded to form the gate drive circuit 3, the gate drive circuit 3 further includes: a plurality of cascade input signal lines 34 and a plurality of cascade display reset signal lines 35. Each cascade input signal line 34 is configured to connect the shift signal terminal CR of the first-stage shift register 31. <n>and the input signal terminal Iput of another stage of shift register 31. Each cascade display reset signal line 35 is configured to connect the shift signal terminal CR of one stage of shift register 31. <n>And the display reset signal terminal STD of another stage shift register 31.

[0344] For example, Figure 3 , Figure 9f and Fig.10 The cascade relationship of the gate driving circuit 3 shown is taken as an example.

[0345] That is, in the shift registers 31 of the other stages except the first stage shift register 31 and the second stage shift register 31, the shift signal terminal CR in the Nth stage shift register 31 is <n>It can be electrically connected to the input signal terminal Iput in the N+2-th stage shift register 31 through the cascade input signal line 34 , and can be electrically connected to the input signal terminal Iput in the N+3-th stage shift register 31 through the cascade input signal line 34 .

[0346] For example, Fig.10 As shown, the output circuit 3103 in the Nth stage shift register 31 can be electrically connected to the first input circuit 3101 and the fifth reset circuit 3109 in the N+2th stage shift register 31 through the cascade input signal line 34, and can be electrically connected to the first input circuit 3101 and the fifth reset circuit 3109 in the N+3th stage shift register 31 through the cascade input signal line 34.

[0347] In this way, the shift signal terminal CR of the output circuit 3103 in the Nth stage shift register 31 is <n>The output shift signal can be transmitted to the first input circuit 3101 and the fifth reset circuit 3109 in the N+2th stage shift register 31 through the corresponding cascade input signal line 34 as the input signals of the first input circuit 3101 and the fifth reset circuit 3109. At the same time, it can be transmitted to the first input circuit 3101 and the fifth reset circuit 3109 in the N+3th stage shift register 31 through the corresponding cascade input signal line 34 as the input signals of the first input circuit 3101 and the fifth reset circuit 3109.

[0348] In the shift registers 31 of the other stages except the last four stages, the shift signal terminal CR of the N+4th stage shift register 31 is<N+4> The display reset signal line 35 can be electrically connected to the display reset signal terminal STD of the Nth stage shift register 31 through the cascade display reset signal line 35 , and can be electrically connected to the display reset signal terminal STD of the N+1th stage shift register 31 through the cascade display reset signal line 35 .

[0349] For example, Fig.10 As shown, the output circuit 3103 in the N+4th stage shift register 31 can be electrically connected to the second reset circuit 3106 of the Nth stage shift register 31 through the cascade display reset signal line 35, and can be electrically connected to the second reset circuit 3106 of the N+1th stage shift register 31 through the cascade display reset signal line 35.

[0350] Thus, the shift signal terminal CR of the output circuit 3103 in the N+4th stage shift register 31 is<N+4> The output shift signal can be transmitted to the second reset circuit 3106 in the Nth stage shift register 31 through the corresponding cascade display reset signal line 35 as the display reset signal of the second reset circuit 3106. At the same time, it can be transmitted to the second reset circuit 3106 in the N+1th stage shift register 31 through the corresponding cascade display reset signal line 35 as the display reset signal of the second reset circuit 3106.

[0351] In some examples, such as Figure 3 As shown, the display panel 100 includes a display area AA (Active Area, referred to as AA). Figure 9a As shown, the display area AA includes a plurality of pixel areas 20 and a plurality of first gap areas D arranged in an array, each pixel area 20 corresponds to at least one first gap area D, and at least one first gap area D is provided between two adjacent pixel areas 20. At least one sub-pixel 2 is provided in each pixel area 20.

[0352] like Figure 9a As shown, the display panel 100 has a plurality of sub-pixel regions S, and each pixel region 20 includes at least one sub-pixel region S. The plurality of sub-pixel regions S are used to set a plurality of sub-pixels 2 included therein. For example, the plurality of sub-pixel regions S and the plurality of sub-pixels 2 may be set in one-to-one correspondence.

[0353] In some examples, such as Figure 9a As shown, the first gap region D is located between two adjacent columns of sub-pixel regions S. Since the number of sub-pixels 2 included in different columns of sub-pixels 2 in the display panel 100 may be different, the sizes of different first gap regions D in the second direction Y may be different.

[0354] Exemplarily, the above-mentioned “two adjacent columns of sub-pixel areas S” may refer to any two adjacent columns of sub-pixel areas S in the multiple columns of sub-pixel areas S of the display panel 100, or may refer to two adjacent columns of sub-pixel areas S in a part of the multiple columns of sub-pixel areas S of the display panel 100.

[0355] For example, Figure 9a As shown, in this example, the multiple sub-pixels 2 included in the display panel 100 are divided into multiple pixel units 2a, and a pixel unit 2a is arranged in each pixel area 20. Among them, a pixel unit 2a can include at least three sub-pixels 2 arranged in sequence along the first direction X.

[0356] For example, one pixel unit 2a may include three sub-pixels 2 or four sub-pixels 2 arranged in sequence along the first direction X. Where one pixel unit 2a includes three sub-pixels 2 arranged in sequence along the first direction X, the three sub-pixels 2 may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Where one pixel unit 2a includes four sub-pixels 2 arranged in sequence along the first direction X, the four sub-pixels 2 may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0357] For example, Figure 9a As shown, after the plurality of sub-pixels 2 are divided into a plurality of pixel units 2a, the plurality of pixel units 2a may be arranged into a plurality of rows along a first direction X and into a plurality of columns along a second direction Y.

[0358] At this time, the first gap region D may be a region between any two adjacent columns of pixel units 2a. That is, the first gap region D may be a region between two adjacent columns of sub-pixel regions S in a portion of the sub-pixel regions S in the plurality of columns of sub-pixel regions S.

[0359] Based on this, among the multiple device groups 311 included in the same shift register 31 , at least one pixel unit 2 a may be disposed between two adjacent device groups 311 .

[0360] By dividing the multiple sub-pixels 2 into multiple pixel units 2a and setting the area between any two adjacent columns of pixel units 2a as the first gap area D, it is beneficial to reduce the space occupation of the first gap area D and increase the pixel density of the display panel 100.

[0361] In some examples, such as Figure 3 , Figure 9f , Fig.10 and Fig.11 As shown, the cascade display reset signal line 34 and the cascade input signal line 35 are both arranged in the first gap area D, and the two are arranged in different first gap areas D. That is, the first gap area D where the cascade display reset signal line 34 is located is different from the first gap area D where the cascade input signal line 35 is located, and there is no overlap between the two.

[0362] Exemplarily, the device group 311 is not disposed in the first gap region D where the cascade display reset signal line 34 or the cascade input signal line 35 is disposed.

[0363] It should be noted that, in the related art, since the gate driving circuit 3 includes a multi-stage shift register 31, after the multi-stage shift register 31 is cascaded, the number of cascaded display reset signal lines 34 and cascaded input signal lines 35 in the gate driving circuit 3 is large. The cascaded display reset signal line 34 and the cascaded input signal line 35 are arranged in the same first gap area D, which makes the size of the first gap area D in the first direction X larger, reduces the space occupation of the sub-pixel 2, and may lead to a reduction in the PPI of the display panel 100.

[0364] In the above embodiment of the present disclosure, by arranging the cascade display reset signal line 34 and the cascade input signal line 35 in different first gap regions D, the size of each first gap region D in the first direction X can be made smaller, the space share of the first gap region D is reduced, and the space share of the sub-pixel 2 is increased, thereby effectively improving the PPI of the display panel 100. It has been verified that arranging the cascade display reset signal line 34 and the cascade input signal line 35 in different first gap regions D can increase the PPI by about one time compared to arranging the cascade display reset signal line 34 and the cascade input signal line 35 in the same first gap region D.

[0365] Therefore, the display panel 100 provided by some embodiments of the present disclosure can effectively utilize the area between two adjacent sub-pixels 2 by dividing each level of shift register 31 into multiple device groups 311, and setting the multiple device groups 311 in the area between two adjacent sub-pixels 2 in the corresponding row of sub-pixels 2, thereby reducing the space occupied by the gate drive circuit 3 in the border area, so that the display panel 100 can achieve a narrow border design or even a borderless design.

[0366] Furthermore, in the above-mentioned embodiments of the present disclosure, by arranging the cascade display reset signal line 34 and the cascade input signal line 35 in the gate driving circuit 3 in different first gap areas D, it is possible to further reduce the space occupied by the gate driving circuit 3 in the border area while reducing the size of the first gap area D in the first direction X, thereby increasing the space occupied by the sub-pixel 2 and effectively improving the PPI of the display panel 100.

[0367] In some embodiments, Figure 9b , Figure 9d , Fig.9e , Figure 9f , Figure 9h and Fig.10 As shown, at least one control signal line 33 among the plurality of control signal lines 33 included in the gate driving circuit 3 is located in the first gap region D.

[0368] That is, a part of the control signal lines 33 may be located in the first gap region D. Alternatively, all of the control signal lines 33 may be located in the first gap region D.

[0369] In this way, part or even all of the gate driving circuit 3 can be set in the area between the multiple sub-pixels 2 included in the display panel 100, reducing the space occupied by the gate driving circuit 3 in the border area, so that the display panel 100 can achieve a narrow border design or even a borderless design.

[0370] In some examples, such as Figure 9b , Figure 9d , Fig.9e , Figure 9f , Figure 9h and Fig.10 As shown, in the case where a plurality of control signal lines 33 are disposed in the first gap region D, one control signal line 33 may be disposed in one first gap region D, and at least one column of sub-pixels 2 is disposed between two adjacent control signal lines 33 .

[0371] Since the control signal line 33 is relatively large in the first direction X, by providing only one control signal line 33 in one first gap area D, it is possible to avoid increasing the size of the first gap area D in the first direction X, thereby avoiding affecting the PPI of the display panel 100 .

[0372] It should be noted that the device group 311, the cascade input signal line 34 and the cascade display reset signal line 35 are not arranged in the first gap area D provided with the control signal line 33. This can avoid increasing the size of the first gap area D in the first direction X, thereby avoiding affecting the PPI of the display panel 100.

[0373] Here, when the plurality of sub-pixels 2 are divided into a plurality of pixel units 2 a and the first gap region D is a region between any two adjacent columns of pixel units 2 a , at least one column of pixel units 2 a may be disposed between the two control signal lines 33 .

[0374] In some examples, the plurality of control signal lines 33 may be made of the same material and disposed in the same layer as the plurality of data lines DL.

[0375] It should be noted that the "same layer" mentioned herein refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask plate through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. In this way, the above-mentioned multiple control signal lines 33 and multiple data lines DL can be prepared and formed simultaneously in a single patterning process, which is conducive to simplifying the preparation process of the display panel 100.

[0376] Exemplarily, the material of the data line DL may be a metal material, such as molybdenum, titanium, copper, silver or aluminum, etc. The structure of the data line DL may be a single-layer structure or a stacked-layer structure.

[0377] There are many ways to set the cascade input signal line 34 and the cascade display reset signal line 35, and they can be selected according to actual needs.

[0378] In some embodiments, the plurality of cascade input signal lines 34 may be divided into a plurality of groups, wherein each group of cascade input signal lines 34 may include at least one cascade input signal line 34 .

[0379] Exemplarily, each group of cascade input signal lines 34 may include one cascade input signal line 34 , or may include a plurality of cascade input signal lines 34 .

[0380] Here, the manner of grouping the plurality of cascade input signal lines 34 can be selected and set according to actual needs. Exemplarily, for the cascade input signal lines 34 located in the same first gap region D, if they partially overlap in the first direction X, the partially overlapping cascade input signal lines 34 can be grouped together.

[0381] For example, if two cascade input signal lines 34 located in the same first gap region D partially overlap in the first direction X, the two cascade input signal lines 34 may be grouped together.

[0382] For example, Fig.10 As shown, the three cascade input signal lines 34 located in the same first gap area D, along the second direction Y, the first two cascade input signal lines 34 partially overlap in the first direction X, and the last two cascade input signal lines 34 partially overlap in the first direction X, then the three cascade input signal lines 34 can be divided into a group.

[0383] In some examples, at least one group of cascade input signal lines 34 is disposed in at least one first gap region D. That is, the above-mentioned multiple groups of cascade input signal lines 34 can be disposed in multiple first gap regions D, and one group of cascade input signal lines 34 can be disposed in one first gap region D, or two groups of cascade input signal lines 34 can be disposed in one first gap region D. Alternatively, all cascade input signal lines 34 can be disposed in one first gap region D.

[0384] In some examples, at least one column of sub-pixels 2 is disposed between two adjacent groups of cascade input signal lines 34 in different first gap regions D. That is, there may be no first gap region D between two adjacent groups of cascade input signal lines 34, or there may be at least one first gap region D.

[0385] This means that the above-mentioned multiple groups of cascade input signal lines 34 can be arranged in multiple first gap areas D, which is beneficial to further reduce the size of the first gap area D in the first direction X and is beneficial to improve the PPI of the display panel 100.

[0386] Exemplarily, in a plurality of first gap regions D in which cascade input signal lines 34 are provided, in a case in which a plurality of groups of cascade input signal lines 34 are provided in each first gap region D, two adjacent groups of cascade input signal lines 34 may refer to any group of cascade input signal lines 34 in one first gap region D and any group of cascade input signal lines 34 in another first gap region D, and the two first gap regions D where the two groups of cascade input signal lines 34 are located are adjacently arranged, or at least one first gap region D is arranged between the two first gap regions D where the two groups of cascade input signal lines 34 are located, and no cascade input signal line 34 is provided in the at least one first gap region D.

[0387] Illustratively, in the first direction X, the two adjacent groups of cascade input signal lines 34 may be partially overlapped or may not be overlapped.

[0388] Here, when the plurality of sub-pixels 2 are divided into a plurality of pixel units 2 a and the first gap region D is the region between any two adjacent columns of pixel units 2 a , at least one column of pixel units 2 a is disposed between two adjacent groups of cascade input signal lines 34 .

[0389] In some examples, a plurality of groups of cascade input signal lines 34 are disposed in at least one first gap region D, and at least one row of sub-pixels is disposed between two adjacent groups of cascade input signal lines 34 in the same first gap region D.

[0390] For example, one, two, three or even more rows of sub-pixels 2 may be arranged between the two adjacent groups of cascade input signal lines 34. As the number of sub-pixel rows arranged between the two adjacent groups of cascade input signal lines 34 increases, the difference in the number of stages of the shift registers 31 corresponding to the two adjacent groups of cascade input signal lines 34 increases.

[0391] This means that in the first direction X, the remaining groups of cascade input signal lines 34 partially overlapped with the two adjacent groups of cascade input signal lines 34 are located in other first gap regions D. The number of cascade input signal lines 34 located in the same first gap region D and partially overlapped in the first direction X is relatively small. In this way, the size of the first gap region D in the first direction X can be effectively reduced, which is beneficial to improving the PPI of the display panel 100.

[0392] In some embodiments, the plurality of cascade display reset signal lines 35 may be divided into a plurality of groups, wherein each group of cascade display reset signal lines 35 includes at least one cascade display reset signal line 35 .

[0393] Exemplarily, each group of cascade display reset signal lines 35 may include one cascade display reset signal line 35 , or may include a plurality of cascade display reset signal lines 35 .

[0394] In this embodiment, the manner of grouping the plurality of cascade display reset signal lines 35 may refer to the manner of grouping the plurality of cascade input signal lines 34 in some of the above embodiments, which will not be described in detail here.

[0395] In some examples, at least one group of cascade display reset signal lines 35 may be disposed in at least one first gap region D. That is, the above-mentioned multiple groups of cascade display reset signal lines 35 may be disposed in multiple first gap regions D, and one group of cascade display reset signal lines 35 may be disposed in one first gap region D, or two groups of cascade display reset signal lines 35 may be disposed in one first gap region D. Alternatively, all cascade display reset signal lines 35 may be disposed in one first gap region D.

[0396] In some examples, at least one column of sub-pixels 2 is disposed between two adjacent groups of cascade display reset signal lines 35 located in different first gap regions D. That is, there may be no first gap region D between two adjacent groups of cascade display reset signal lines 35, or there may be at least one first gap region D.

[0397] This means that the above-mentioned multiple groups of cascade display reset signal lines 35 can be arranged in multiple first gap areas D, which is beneficial to further reduce the size of the first gap area D in the first direction X and is beneficial to improve the PPI of the display panel 100.

[0398] Exemplarily, in a plurality of first gap regions D provided with cascaded display reset signal lines 35, in a case where a plurality of groups of cascaded display reset signal lines 35 are provided in each first gap region D, two adjacent groups of cascaded display reset signal lines 35 may refer to any group of cascaded display reset signal lines 35 in one first gap region D and any group of cascaded display reset signal lines 35 in another first gap region D, and the two first gap regions D where the two groups of cascaded display reset signal lines 35 are located are adjacently arranged, or at least one first gap region D is arranged between the two first gap regions D where the two groups of cascaded display reset signal lines 35 are located, and the cascaded display reset signal line 35 is not arranged in the at least one first gap region D.

[0399] Exemplarily, in the first direction X, the two adjacent groups of cascade display reset signal lines 35 may be partially overlapped or may not be overlapped.

[0400] Here, when the plurality of sub-pixels 2 are divided into a plurality of pixel units 2 a and the first gap region D is the region between any two adjacent columns of pixel units 2 a , at least one column of pixel units 2 a is disposed between two adjacent groups of cascade display reset signal lines 35 .

[0401] In some examples, a plurality of groups of cascaded display reset signal lines 35 are disposed in at least one first gap region D, and at least one row of sub-pixels 2 is disposed between two adjacent groups of cascaded display reset signal lines 35 in the same first gap region D.

[0402] For example, one, two, three or even more rows of sub-pixels 2 may be arranged between the two adjacent groups of cascade display reset signal lines 35. As the number of sub-pixel rows arranged between the two adjacent groups of cascade display reset signal lines 35 increases, the difference in the number of stages of the shift registers 31 corresponding to the two adjacent groups of cascade display reset signal lines 35 increases.

[0403] This means that in the first direction X, the remaining groups of cascade display reset signal lines 35 partially overlapped with the two adjacent groups of cascade display reset signal lines 35 are located in other first gap regions D. The number of cascade display reset signal lines 35 located in the same first gap region D and partially overlapped in the first direction X is relatively small. In this way, the size of the first gap region D in the first direction X can be effectively reduced, which is beneficial to improving the PPI of the display panel 100.

[0404] In some embodiments, the plurality of cascade input signal lines 34 and the plurality of cascade display reset signal lines 35 may be made of the same material and disposed on the same layer as the plurality of data lines DL.

[0405] In this way, the plurality of cascade input signal lines 34 , the plurality of cascade display reset signal lines 35 , the plurality of control signal lines 33 and the plurality of data lines DL can be simultaneously formed in one patterning process, which is beneficial to simplifying the manufacturing process of the display panel 100 .

[0406] In some embodiments, Figure 9a As shown, each sub-pixel region S may include: a sub-pixel circuit area Sa and a sub-pixel light-emitting area Sb arranged in sequence along the second direction Y. The sub-pixel circuit area Sa is used to set the pixel driving circuit 21 in the corresponding sub-pixel 2, and the sub-pixel light-emitting area Sb is used to set the light-emitting device 22 in the corresponding sub-pixel 2.

[0407] In some examples, such as Figure 9a to Figure 9h As shown, along the second direction Y, any three adjacent rows of sub-pixel regions S can be respectively formed as a first row of sub-pixel regions S1, a second row of sub-pixel regions S2, and a third row of sub-pixel regions S3.

[0408] For example, Figure 9a to Figure 9h As shown, the area between the first row of sub-pixel regions S1 and the second row of sub-pixel regions S2 is the second gap area E, and the area between the second row of sub-pixel regions S2 and the third row of sub-pixel regions S3 is the third gap area F.

[0409] Among them, Figure 9a to Figure 9h As shown, in the first row of sub-pixel regions S1 and the second row of sub-pixel regions S2, the sub-pixel light-emitting regions Sb are closer to the second gap region E than the sub-pixel circuit region Sa. For example, in the first row of sub-pixel regions S1 and the second row of sub-pixel regions S2, each sub-pixel region S is symmetrically arranged relative to the second gap region E, and the sub-pixel light-emitting region Sb in each sub-pixel region S is closer to the second gap region E, and the sub-pixel circuit region Sa in each sub-pixel region S is farther away from the second gap region E.

[0410] like Figure 9a to Figure 9h As shown, in the second row of sub-pixel regions S2 and the third row of sub-pixel regions S3, the sub-pixel circuit area Sa is closer to the third gap area F than the sub-pixel light-emitting area Sb. For example, in the first row of sub-pixel regions S1 and the second row of sub-pixel regions S2, each sub-pixel region S is symmetrically arranged relative to the third gap area F, and the sub-pixel light-emitting area Sb in each sub-pixel region S is relatively far away from the third gap area F, and the sub-pixel circuit area Sa in each sub-pixel region S is relatively close to the third gap area F.

[0411] It should be noted that this example only defines the positions of the sub-pixel circuit area Sa and the sub-pixel light-emitting area Sb in each sub-pixel region S, and does not define whether the structures of the pixel driving circuit 21 provided in the sub-pixel circuit area Sa and the light-emitting device 22 provided in the sub-pixel light-emitting area Sb are symmetrical. Since both the pixel driving circuit 21 and the light-emitting device 22 include multiple film layers, in the process of preparing the multiple film layers, there may be differences in the sizes of the film layers included in different pixel driving circuits 21, or there may be differences in the sizes of the film layers included in different light-emitting devices 22 due to unavoidable reasons such as process errors. In this way, the sub-pixel driving circuit 21 in the first-row sub-pixel region S1 and the sub-pixel driving circuit 21 in the second-row sub-pixel region S2 cannot be arranged strictly symmetrically with respect to the second gap region E, the light-emitting devices 22 in the first-row sub-pixel region S1 and the light-emitting devices 22 in the second-row sub-pixel region S2 cannot be arranged strictly symmetrically with respect to the second gap region E, the sub-pixel driving circuit 21 in the second-row sub-pixel region S2 and the sub-pixel driving circuit 21 in the third-row sub-pixel region S2 cannot be arranged strictly symmetrically with respect to the third gap region F, and the light-emitting devices 22 in the second-row sub-pixel region S2 and the light-emitting devices 22 in the third-row sub-pixel region S2 cannot be arranged strictly symmetrically with respect to the third gap region F.

[0412] In some embodiments, Fig.10 As shown, the display panel 100 further includes a plurality of power supply voltage lines ELVDD extending along the second direction for transmitting power supply voltage signals.

[0413] like Fig.10 As shown, the display panel 100 further includes a plurality of auxiliary power supply voltage lines VDD, the plurality of auxiliary power supply voltage lines VDD extend along a first direction X, and each power supply voltage line ELVDD is electrically connected to the plurality of auxiliary power supply voltage lines VDD.

[0414] Among them, each row of pixel areas 20 corresponds to at least one auxiliary power supply voltage line VDD, and the pixel driving circuits 21 of the multiple sub-pixels 2 in the pixel area 20 corresponding to each auxiliary power supply voltage line VDD are all electrically connected to the auxiliary power supply voltage line VDD, that is, the multiple sub-pixels 2 in the pixel area 20 corresponding to each auxiliary power supply voltage line VDD share an auxiliary power supply voltage line VDD.

[0415] It can be understood that the auxiliary power supply voltage line VDD is electrically connected to the fourth voltage signal terminal Vdd in the pixel driving circuit 21 , that is, the first electrode of the driving transistor T2 is electrically connected to the auxiliary power supply voltage line VDD.

[0416] A power supply voltage signal is transmitted through the power supply voltage line ELVDD to the auxiliary power supply voltage line VDD electrically connected thereto, and then the power supply voltage signal is transmitted through the auxiliary power supply voltage line VDD to the pixel driving circuit 21 of the plurality of sub-pixels 2 in the corresponding pixel area 20, so that the pixel driving circuit 21 drives the light-emitting device 22 to emit light.

[0417] In some embodiments, Fig.10 As shown, each row of pixel areas 20 corresponds to a plurality of auxiliary power supply voltage lines VDD. Along the first direction X, two adjacent auxiliary power supply voltage lines VDD are separated by a first gap region D.

[0418] It should be noted that, in the related art, the power supply voltage line adopts a grid line design, that is, the power supply voltage line includes a horizontal power supply voltage line extending along a first direction X, and a vertical power supply voltage line extending along a second direction Y. A plurality of vertical power supply voltage lines and a plurality of horizontal power supply voltage lines form a grid line electrically connected to each other, which can reduce the voltage drop caused by the power supply voltage line transmitting the power supply voltage signal.

[0419] In the above-mentioned embodiment of the present disclosure, along the first direction X, two adjacent auxiliary power supply voltage lines VDD are separated by the first gap area D, which can avoid the auxiliary power supply voltage line VDD occupying the space of the first gap area D, so that the first gap area D can be used to arrange the signal lines of the gate drive circuit 3 and the device group 311.

[0420] In some embodiments, Fig.10 As shown, each column of pixel regions 20 corresponds to a power supply voltage line ELVDD, and the power supply voltage line ELVDD is located on one side of two opposite sides of the pixel region 20 along the first direction X. Each pixel region 20 corresponds to an auxiliary power supply voltage line VDD, and each auxiliary power supply voltage line VDD is electrically connected to the pixel driving circuit 21 of a plurality of sub-pixels 2 in the corresponding pixel region 20.

[0421] For example, Fig.13b As shown, four sub-pixels 2 are arranged in each pixel area 20 , and each auxiliary power supply voltage line VDD is electrically connected to the pixel driving circuits 21 of the four sub-pixels 2 in the corresponding pixel area 20 .

[0422] In some embodiments, Figure 14a to Figure 14e ,and Fig.15 As shown, from the perspective of film layers, the display panel 100 includes an active layer 104, a gate insulating layer 105, a gate conductive layer 106, an interlayer dielectric layer 107 and a source-drain conductive layer 108 which are sequentially arranged on the substrate 1. The active layer 104 includes a first electrode T21, a channel portion T22 and a second electrode T23 of the driving transistor T2. The source-drain conductive layer 108 includes a plurality of third connection patterns 108C. The auxiliary power supply voltage line VDD is located in the gate conductive layer 106.

[0423] A seventh via hole H7 is formed in the interlayer dielectric layer 107, and an eighth via hole H8 is formed in the interlayer dielectric layer 107 and the gate insulating layer 105. The third connection pattern 108C is electrically connected to the auxiliary power supply voltage line VDD through the seventh via hole H7, and is electrically connected to the first electrode T21 of the driving transistor T2 through the eighth via hole H8, so as to realize the electrical connection between the first electrode T21 of the driving transistor T2 and the auxiliary power supply voltage line VDD.

[0424] It can be understood that the seventh via hole H7 and the eighth via hole H8 may be connected or disconnected.

[0425] In some embodiments, Fig.13b and Fig.14e As shown, the power supply voltage line ELVDD is located in the source-drain conductive layer 108. In the same pixel area 20, the third connection pattern 108C, which is closest to the power supply voltage line ELVDD corresponding to the pixel area 20, among multiple third connection patterns 108C, is electrically connected to the power supply voltage line ELVDD. The electrical connection between the third connection pattern 108C and the power supply voltage line ELVDD is achieved to realize the electrical connection between the power supply voltage line ELVDD and the first electrode T21 of the driving transistor T2 and the auxiliary power supply voltage line VDD.

[0426] Exemplarily, in the same pixel region 20 , the third connection pattern 108C closest to the power supply voltage line ELVDD corresponding to the pixel region 20 among the plurality of third connection patterns 108C is integrally arranged with the power supply voltage line ELVDD.

[0427] In some embodiments, Fig.14d and Fig.14e As shown, the display panel 100 further includes a plurality of power supply voltage connection patterns VDD1, which are located on the gate conductive layer 106. The orthographic projection of the power supply voltage line ELVDD on the substrate 1 overlaps with the orthographic projection of at least one power supply voltage connection pattern VDD1 on the substrate 1.

[0428] A ninth via H9 is also provided in the interlayer dielectric layer 107, and the power voltage line ELVDD is electrically connected to at least one power voltage connection pattern VDD1 through the ninth via H9. By connecting the power voltage connection pattern VDD1 in parallel with the power voltage line ELVDD, the resistance of the power voltage line ELVDD can be reduced, thereby reducing the voltage drop caused by the power voltage line ELVDD transmitting the power voltage signal.

[0429] Based on this, the layout design of the pixel driving circuit 21 is described below.

[0430] In some embodiments, Fig.13a and Fig.15 As shown, the display panel 100 further includes a passivation layer 109, a color filter layer 110, and a flat layer 111, which are sequentially arranged on the substrate 1 and located between the pixel driving circuit 21 of the sub-pixel 2 and the light-emitting device 22. A first via hole H1 penetrating the passivation layer 109 and the flat layer 111 is provided in the passivation layer 109 and the flat layer 111, and the pixel driving circuit 21 is electrically connected to the light-emitting device 22 through the first via hole H1.

[0431] like Fig.13a and Fig.15 As shown, the color filter layer 110 includes a plurality of filter portions 110A, each filter portion 110A is disposed in a sub-pixel light emitting area Sb of a sub-pixel region S. In the same sub-pixel region S, along the second direction Y, the filter portion 110A and the first via hole H1 located in the sub-pixel region S are spaced apart by at least a portion of the pixel driving circuit 21 located in the sub-pixel region S and / or the auxiliary power supply voltage line VDD.

[0432] For example, Fig.13a and Fig.15 As shown, in the same sub-pixel region S, along the second direction Y, between the filter portion 110A and the first via hole H1 located in the sub-pixel region S, at least part of the pixel driving circuit 21 located in the sub-pixel region S and the auxiliary power supply voltage line VDD are spaced.

[0433] In the above-mentioned embodiment of the present disclosure, in the same sub-pixel area S, along the second direction Y, the filter part 110A and the first via hole H1 located in the sub-pixel area S are separated by at least a part of the pixel driving circuit 21 located in the sub-pixel area S and / or the auxiliary power supply voltage line VDD, so that the first via hole H1 is far away from the filter part 110A, so as to avoid the filter part 110A covering the position where the first via hole H1 is etched in the passivation layer 109 and the flat layer 111, thereby avoiding the filter part 110A affecting the etching selectivity of the passivation layer 109 and the flat layer 111 during the process of etching the first via hole H1 in the passivation layer 109 and the flat layer 111, thereby ensuring that the first via hole H1 penetrates the passivation layer 109 and the flat layer 111, and further ensuring that the pixel driving circuit 21 is electrically connected to the light-emitting device 22 through the first via hole H1.

[0434] Furthermore, the above arrangement can provide sufficient space for the filter unit 110A to ensure that the filter unit 110A can cover the sub-pixel light-emitting area Sb, thereby avoiding light leakage due to a large amount of light emitted from the area of ​​the sub-pixel light-emitting area Sb that is not covered by the filter unit 110A.

[0435] In some embodiments, Fig.13b and Fig.14e As shown, the switch transistor T1 and the sensing transistor T3 are farther away from the sub-pixel light-emitting area Sb of the sub-pixel area S where the pixel driving circuit 21 is located than the driving transistor T2, so that the auxiliary power supply voltage line VDD is closer to the sub-pixel light-emitting area Sb, the first via H1 is farther away from the sub-pixel light-emitting area Sb, and the layout of the pixel driving circuit 21 in the sub-pixel circuit area Sa is more compact, which is beneficial to improving the PPI of the display panel 100.

[0436] In some embodiments, Fig.14e As shown, the active layer 104 includes a first electrode T11, a channel portion T12, and a second electrode T13 of the switch transistor T1, a first electrode T21, a channel portion T22, and a second electrode T23 of the drive transistor T2, and a first electrode T31, a channel portion T32, and a second electrode T33 of the sense transistor T3. The gate conductive layer 106 includes a control electrode T14 of the switch transistor T1, a control electrode T24 of the drive transistor T2, and a control electrode T34 of the sense transistor T3. The source-drain conductive layer 108 includes a first connection pattern 108A and a second connection pattern 108B.

[0437] like Fig.14e and Fig.16 As shown, a second via hole H2 penetrating the interlayer dielectric layer 107 and the gate insulating layer 105 is provided in the interlayer dielectric layer 107, and a third via hole H3 is provided in the interlayer dielectric layer 107. The first connection pattern 108A is electrically connected to the second electrode T13 of the switch transistor T1 through the second via hole H2, and is electrically connected to the control electrode T24 of the drive transistor T2 through the third via hole H3, so as to realize the electrical connection between the control electrode T24 of the drive transistor T2 and the second electrode T13 of the switch transistor T1.

[0438] It can be understood that the second via hole H2 and the third via hole H3 may be connected or disconnected.

[0439] like Fig.14e and Fig.15 As shown, a fourth via hole H4 is opened in the interlayer dielectric layer 107 , and the second connection pattern 108B is electrically connected to the second electrode T23 of the driving transistor T2 through the fourth via hole H4 .

[0440] like Fig.14e and Fig.15 As shown, in the same sub-pixel region S, along the second direction Y, the filter portion 110A and the first via hole H1 located in the sub-pixel region S are separated by the control electrode T24, the channel portion T22, the first electrode T21 and the auxiliary power supply voltage line VDD of the driving transistor T2, so that the first via hole H1 is away from the filter portion 110A.

[0441] In some embodiments, Figure 14a to Figure 14e ,and Fig.16 As shown, the display panel 100 further includes a first electrode layer 102 and a buffer layer 103 sequentially disposed on the substrate 1, and the first electrode layer 102 and the buffer layer 103 are located on a side of the active layer 104 close to the substrate 1. The first electrode layer 102 includes a second electrode plate 102A of the storage capacitor Cst, and the active layer 104 further includes a first electrode plate 104A of the storage capacitor Cst.

[0442] Among them, a fifth via hole H5 is provided in the interlayer dielectric layer 107, and the first connection pattern 108A is also electrically connected to the first electrode 104A of the storage capacitor Cst through the fifth via hole H5. A sixth via hole H6 is provided in the interlayer dielectric layer 107 and the buffer layer 103, which penetrates the two, and the second connection pattern 108B is also electrically connected to the second electrode 102A of the storage capacitor Cst through the sixth via hole H6. The fifth via hole H5 and the sixth via hole H6 are both located on the side of the storage capacitor Cst close to the third gap region F.

[0443] It can be understood that the fourth via hole H4 and the sixth via hole H6 may be connected or disconnected.

[0444] Through the above-mentioned setting method, the fifth via H5 and the sixth via H6 are both located on the side of the storage capacitor Cst close to the third gap area F, so that the connection points of the two plates of the storage capacitor Cst are distributed on the same side, which can reduce the layout space occupied by the pixel driving circuit 21 in the sub-pixel circuit area Sa, which is beneficial to improving the PPI of the display panel 100.

[0445] In some embodiments, Fig.13c As shown, each gate line GL is in a zigzag shape and extends substantially along the first direction X. One gate line GL is electrically connected to a plurality of pixel driving circuits 21 in a row of sub-pixels 2 .

[0446] Understandably, Fig.13c and Fig.13b The structures shown are the same, except that the structures marked in the figures are different, so as to focus on describing the corresponding structures.

[0447] As described above, multiple pixel driving circuits 21 in the same row of sub-pixels 2 can be electrically connected to the same gate line GL, and the control electrodes of the switching transistor T1 and the sensing transistor T3 in the same pixel driving circuit 21 can be electrically connected to the same gate line GL. By reducing the number of gate lines GL and adopting a zigzag routing design for the gate lines GL, the layout space of the display panel 100 can be saved, which is beneficial to increasing the PPI of the display panel 100.

[0448] In some embodiments, Fig.13c As shown, the gate line GL includes a plurality of first extension segments GL1, a plurality of second extension segments GL2 and a plurality of connecting segments GL3, each first extension segment GL1 and each second extension segment GL2 extends approximately along the first direction X, the plurality of first extension segments GL1 and the plurality of second extension segments GL2 are alternately arranged, adjacent first extension segments GL1 and second extension segments GL2 are connected by the connecting segments GL3, and along the second direction Y, there is a spacing S1 between the extension lines of adjacent first extension segments GL1 and second extension segments GL2.

[0449] The first extension segment GL1 and the two connecting segments GL3 connected to the first extension segment GL1 form a first recess U1, and the opening of the first recess U1 faces a direction away from the third gap region F. The second extension segment GL2 and the two connecting segments GL3 connected to the second extension segment GL2 form a second recess U2, and the opening of the second recess U2 faces a direction close to the third gap region F. At least part of the pixel driving circuit 21 is located in the first recess U1 and the second recess U2.

[0450] Through the above-mentioned setting method, the gate line GL adopts a zigzag routing design, that is, the gate line GL is bent multiple times and extends approximately along the first direction X, and at least a portion of the pixel driving circuit 21 is located in the first recess U1 and the second recess U2 of the gate line GL, so that the gate line GL is arranged more closely with the pixel driving circuit 21 in the sub-pixel area S, which is beneficial to increase the PPI of the display panel 100.

[0451] For example, Fig.13c As shown, the switch transistor T1 is electrically connected to the data line DL through the tenth via hole H10, and the driving transistor T2 and the sensing transistor T3 are electrically connected to the light emitting device 22 through the first via hole H1. A portion of the first extension segment GL1 serves as a control electrode T34 of the sensing transistor T3, and at least a portion of the orthographic projection of the first via hole H1 on the substrate 1 is located within the orthographic projection of the first recess U1 on the substrate 1. A portion of the second extension segment GL2 serves as a control electrode T14 of the switch transistor T1, and at least a portion of the orthographic projection of the tenth via hole H10 on the substrate 1 is located within the orthographic projection of the second recess U2 on the substrate 1.

[0452] In some embodiments, Figures 9a to 9h and Fig.10 As shown, the pixel driving circuit 21 may further include: a first sensing signal line 211 located in the third gap region F and extending along the first direction X. The first sensing signal line 211 may be electrically connected to the sensing signal terminal Sense in the pixel driving circuit 21, and electrically connected to the sensing transistor T3 in the pixel driving circuit 21 through the sensing signal terminal Sense.

[0453] In some examples, such as Figures 9a to 9h As shown, when the multiple sub-pixels 2 included in the display panel 100 are divided into multiple pixel units 2a, and one pixel unit 2a includes at least three sub-pixels 2 arranged in sequence along the first direction X, among the sub-pixels 2 located in the second row sub-pixel area S2 and the third row sub-pixel area S3, two pixel units 2a opposite to each other along the second direction Y share the first sensing signal line 211.

[0454] Exemplarily, the two pixel units 2 a facing each other along the second direction Y may be electrically connected to the same first sensing signal line 211 .

[0455] For example, Figure 9a As shown, each pixel unit 2 a includes four sub-pixels 2 . The pixel driving circuits 21 of the eight sub-pixels 2 in the two pixel units 2 a adjacent to each first sensing signal line 211 are all electrically connected to the first sensing signal line 211 .

[0456] Since a row of pixel units 2a includes multiple pixel units 2a, the number of two pixel units 2a located in the sub-pixels 2 in the second row sub-pixel area S2 and the third row sub-pixel area S3 and opposite to each other along the second direction Y can be multiple, and thus the number of first sensing signal lines 211 located in the third gap area F can also be multiple.

[0457] The two pixel units 2 a opposite to each other along the second direction Y share the first sensing signal line 211 , that is, the sensing transistors T3 of the pixel driving circuits 21 in at least six sub-pixels 2 included in the two pixel units 2 a can be electrically connected to the same first sensing signal line 211 .

[0458] By setting the first sensing signal line 211 in the third gap area F, the extension direction of the first sensing signal line 211 is the same as the arrangement direction of the multiple sub-pixels 2 included in each pixel unit 2a, so that the pixel driving circuits 21 in the multiple sub-pixels 2 can be electrically connected to the same first sensing signal line 211, thereby reducing the number of first sensing signal lines 211 and simplifying the structure of the pixel driving circuit 21.

[0459] By setting two pixel units 2a opposite to each other along the second direction Y in the sub-pixels 2 located in the second row sub-pixel region S2 and the third row sub-pixel region S3 to share the first sensing signal line 211, not only the spacing between the two pixel units 2a opposite to each other along the second direction Y can be reduced, the size of the third gap region F in the second direction Y can be reduced, and the space occupied by the pixel driving circuit 21 can also be reduced. In this way, the minimum line width spacing of the sub-pixels 2 can be avoided from being compressed, which is conducive to setting more sub-pixels 2 to increase the PPI of the display panel 100, or increasing the area of ​​the sub-pixel light-emitting region Sb to increase the aperture ratio of the display panel 100.

[0460] In some embodiments, Fig.10 As shown, a plurality of first sensing signal lines 211 are arranged between two adjacent rows of pixel units 2a. Along the first direction X, two adjacent first sensing signal lines 211 are separated by a first gap region D.

[0461] It should be noted that, in the related art, the sensing lines adopt a grid line design, that is, the sensing lines include horizontal sensing lines extending along the first direction X, and vertical sensing lines extending along the second direction Y. Multiple vertical sensing lines and multiple horizontal sensing lines form grid lines that are electrically connected to each other, which can reduce the voltage drop generated by the sensing lines transmitting sensing signals.

[0462] In the above-mentioned embodiment of the present disclosure, along the first direction X, two adjacent first sensing signal lines 211 are separated by the first gap area D, which can avoid the first sensing signal line 211 occupying the space of the first gap area D, so that the first gap area D can be used to arrange the signal lines of the gate driving circuit 3 and the device group 311.

[0463] In some embodiments, Figure 14a to Figure 14e ,and Fig.15 As shown, the display panel 100 further includes a light shielding layer 101 disposed on the substrate 1, and the light shielding layer 101 is located on a side of the first electrode layer 102 close to the substrate 1. The first sensing signal line 211 includes at least one sub-first sensing signal line 2110, and at least one sub-first sensing signal line 2110 is located on the light shielding layer 101.

[0464] The source-drain conductive layer 108 further includes a fourth connection pattern 108D. An eleventh via hole H11 penetrating the interlayer dielectric layer 107 and the buffer layer 103 is provided in the interlayer dielectric layer 107, and a twelfth via hole H12 is provided in the interlayer dielectric layer 107. The fourth connection pattern 108D is electrically connected to the first sensing signal line 211 through the eleventh via hole H11, and is electrically connected to the first electrode T31 of the sensing transistor T3 through the twelfth via hole H12, so as to realize the electrical connection between the first electrode T31 of the sensing transistor T3 and the first sensing signal line 211.

[0465] It can be understood that the eleventh via hole H11 and the twelfth via hole H12 may be connected or disconnected.

[0466] The material of the light shielding layer 101 includes a conductive material that is opaque or has low light transmittance.

[0467] For example, Fig.15 As shown, the first sensing signal line 211 includes a first sub-first sensing signal line 2111 and a second sub-first sensing signal line 2112 that are electrically connected, the orthographic projection of the first sub-first sensing signal line 2111 on the substrate 1 overlaps with the orthographic projection of the second sub-first sensing signal line 2112 on the substrate 1, the first sub-first sensing signal line 2111 is located in the light shielding layer 101, and the second sub-first sensing signal line 2112 is located in the first electrode layer 102. By arranging the first sub-first sensing signal line 2111 and the second sub-first sensing signal line 2112 in parallel, the resistance of the first sensing signal line 211 can be reduced, thereby reducing the voltage drop generated by the first sensing signal line 211 transmitting the sensing signal.

[0468] In some examples, such as Figures 9a to 9h and Fig.10 As shown, the pixel driving circuit 21 may further include: a second sensing signal line 212 extending along the second direction Y. The second sensing signal line 212 is located in the region between two adjacent columns of sub-pixels 2 in the two pixel units 2a opposite to each other along the second direction Y.

[0469] For example, Figures 9a to 9h and Fig.10 As shown, taking the pixel unit 2a including four sub-pixels 2 as an example, the four sub-pixels 2 arranged in sequence along the first direction X can be called the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel. Among them, the data line DL electrically connected to the pixel driving circuit 21 in the first sub-pixel and the data line DL electrically connected to the pixel driving circuit 21 in the second sub-pixel can be arranged in the area between the first sub-pixel and the second sub-pixel. The data line DL electrically connected to the pixel driving circuit 21 in the third sub-pixel and the data line DL electrically connected to the pixel driving circuit 21 in the fourth sub-pixel can be arranged in the area between the third sub-pixel and the fourth sub-pixel. The second sensing signal line 212 electrically connected to the first sensing signal line 211 can be arranged in the area between the second sub-pixel and the third sub-pixel. The data line DL and the second sensing signal line 212 are arranged in the above manner, which is conducive to the rational use of the space of the display panel 100 and reduces the complexity of the circuit.

[0470] For example, Fig.13b As shown, the first sensing signal line 211 is electrically connected to the second sensing signal line 212 through the via G. The second sensing signal line 212 is also electrically connected to an external sensing circuit, for example.

[0471] That is, the first sensing signal line 211 and the second sensing signal line 212 are connected in alternate layers to realize the electrical connection between the pixel driving circuit 21 and the external sensing circuit. This is conducive to simplifying the layout design of the display panel 100 and reducing the space occupied by the pixel driving circuit 21.

[0472] For example, a second sensing signal line 212 may be located in a column of pixel units 2a, in a region between adjacent yield sub-pixels 2. A column of pixel units 2a includes a plurality of two pixel units 2a opposite to each other along the second direction Y, so that a second sensing signal line 212 may be electrically connected to a plurality of first sensing signal lines 211.

[0473] For example, during the operation of the pixel driving circuit 21, in the reset stage in the display period, the reset signal can be transmitted to the sensing transistor T3 via the second sensing signal line 212, the first sensing signal line 211 and the sensing signal terminal Sense in sequence; in the first stage in the blanking period, the reset signal can be transmitted to the sensing transistor T3 via the second sensing signal line 212, the first sensing signal line 211 and the sensing signal terminal Sense in sequence; in the second stage in the blanking period, while the driving transistor T2 is charging the second node S, the driving transistor T2 can also charge the first sensing signal line 211 and the second sensing signal line 212 via the sensing transistor T3 and the sensing signal terminal Sense in sequence, and when performing voltage sampling, the voltage of the second sensing signal line 212 can be sampled, and the voltage sampling result can be transmitted to the external sensing circuit.

[0474] In some examples, such as Fig.13b As shown, the second sensing signal line 212 is made of the same material and disposed in the same layer as the plurality of data lines GL, that is, the second sensing signal line 212 is located in the source-drain conductive layer 108 .

[0475] In this way, the second sensing signal line 212 and the plurality of data lines DL can be simultaneously formed in one patterning process, which is beneficial to simplifying the manufacturing process of the display panel 100 .

[0476] In the same pixel area 20, among the multiple fourth connection patterns 108D located on the opposite sides of the second sensing signal line 212 along the first direction X, the two fourth connection patterns 108D closest to the second sensing signal line 212 are electrically connected to the second sensing signal line 212, and the electrical connection between the second sensing signal line 212 and the first electrode T31 of the sensing transistor T3 and the first sensing signal line 211 is achieved through the electrical connection between the fourth connection patterns 108D and the second sensing signal line 212.

[0477] Exemplarily, in the same pixel area 20 , among the plurality of fourth connection patterns 108D located on opposite sides of the second sensing signal line 212 along the first direction X, two fourth connection patterns 108D closest to the second sensing signal line 212 are integrally arranged with the second sensing signal line 212 .

[0478] In some embodiments, Fig.13b As shown, the display panel 100 further includes a plurality of sensing connection patterns 212A, and the sensing connection patterns 212A are located on the gate conductive layer 106. The orthographic projection of the second sensing signal line 212 on the substrate 1 overlaps with the orthographic projection of at least one sensing connection pattern 212A on the substrate 1.

[0479] A thirteenth via hole H13 is also provided in the interlayer dielectric layer 107, and the second sensing signal line 212 is electrically connected to at least one sensing connection pattern 212A through the thirteenth via hole H13. By connecting the sensing connection pattern 212A in parallel with the second sensing signal line 212, the resistance of the second sensing signal line 212 can be reduced, thereby reducing the voltage drop generated by the second sensing signal line 212 transmitting the sensing signal.

[0480] In some embodiments, Figure 9a to Figure 9h As shown, the gate driving circuit 3 may further include: a plurality of transmission signal lines 36 located in the second gap region E and extending along the first direction X.

[0481] In some examples, such as Figure 9a to Figure 9h As shown, the two-stage shift register 31 electrically connected to the sub-pixels 2 located in the first row of sub-pixel region S1 and the sub-pixels 2 located in the second row of sub-pixel region S2 shares at least one transmission signal line 36 among the plurality of transmission signal lines 36 .

[0482] Exemplarily, the two-stage shift register 31 may share one transmission signal line 36 , or two transmission signal lines 36 , or three transmission signal lines 36 , or even a plurality of transmission signal lines 36 .

[0483] By arranging the sub-pixel circuit area Sa and the sub-pixel light-emitting area Sb in the first row of sub-pixel areas S1, the second row of sub-pixel areas S2 and the third row of sub-pixel areas S3 in the above manner, the sub-pixel circuit area Sa in the second row of sub-pixel areas S2 and the sub-pixel circuit area Sa in the third row of sub-pixel areas S3 can be made to be closer together (that is, the size of the third gap area F in the second direction Y is smaller), so that the size of the second gap area E between the sub-pixel light-emitting area Sb in the first row of sub-pixel areas S1 and the sub-pixel light-emitting area Sb in the second row of sub-pixel areas S2 in the second direction Y is larger (the size of the second gap area E in the second direction Y is larger than the size of the third gap area F in the second direction Y), and thus the spacing between the sub-pixel light-emitting areas Sb in each row of sub-pixel areas S can be equal or approximately equal, thereby ensuring the uniformity of light emission of the display panel 100.

[0484] On this basis, the required wiring inside each level of the shift register 31 and the required wiring between the shift register 31 and the control signal line 33 can be arranged in the second gap area E adjacent to the shift register 31. The plurality of transmission signal lines 36 can include, for example, the required wiring inside the two-stage shift register 31 and the required wiring between the two-stage shift register 31 and the control signal line 33, which are electrically connected to the sub-pixels 2 in the first row of the sub-pixel area S1 and the sub-pixels 2 in the second row of the sub-pixel area S2.

[0485] The present disclosure can reduce the number of transmission signal lines 36 arranged in the second gap area E and reduce the space occupied by the transmission signal lines 36 in the second gap area E by using the two-stage shift register 31 to share at least one transmission signal line 36 among the plurality of transmission signal lines 36. In this way, more sub-pixels 2 can be arranged to increase the PPI of the display panel 100, or the area of ​​the sub-pixel light-emitting area Sb can be increased to increase the aperture ratio of the display panel 100 by reducing the size of the second gap area E in the second direction Y.

[0486] In some embodiments, the plurality of transmission signal lines 36 and the plurality of gate lines GL may be made of the same material and disposed in the same layer.

[0487] In this way, the plurality of transmission signal lines 36 and the plurality of gate lines GL can be simultaneously prepared and formed in one patterning process, which is conducive to simplifying the manufacturing process of the display panel 100. Moreover, since the transmission signal lines 36 extend along the first direction X, by arranging the transmission signal lines 36 and the gate lines GL in the same layer, it is possible to avoid short circuits between the transmission signal lines 36 and the control signal lines 33, the cascade input signal lines 34, and the cascade display reset signal lines 35 extending along the second direction Y, and it is also possible to avoid the increase in the thickness of the display panel 100 and the increase in the manufacturing process of the display panel 100 caused by the separate preparation of the transmission signal lines 36.

[0488] Here, the types of the plurality of transmission signal lines 36 include various types, and can be selected and set according to actual needs.

[0489] In some examples, such as Figure 9a to Figure 9g As shown, the gate driving circuit 3 may further include: a first voltage signal line 36a, a second voltage signal line 36b and a third voltage signal line 36c.

[0490] For example, Figure 9a As shown, the first voltage signal line 36 a may be electrically connected to the first voltage signal terminal VDD of the two-stage shift register 31 .

[0491] Since the leakage protection circuits 3102 in the two-stage shift register 31 are electrically connected to the first voltage signal terminal VDD, the first voltage signal line 36a can be electrically connected to the leakage protection circuits 3102 in the two-stage shift register 31. When each leakage protection circuit 3102 is working, the first voltage signal can be transmitted to the corresponding leakage protection circuit 3102 through the first voltage signal line 36a.

[0492] For example, Figure 9a to Figure 9f and Fig.12 As shown, the second voltage signal line 36 b may be electrically connected to the second voltage signal terminal VGL1 of the two-stage shift register 31 .

[0493] Since the control circuit 3104, the first reset circuit 3105, the second reset circuit 3106, the third reset circuit 3107, the fourth reset circuit 3108 and the fifth reset circuit 3109 in the two-stage shift register 31 are all electrically connected to the second voltage signal line 36b, the second voltage signal line 36b can be electrically connected to the control circuit 3104 and each reset circuit in the two-stage shift register 31. In this way, when each control circuit 3104 and each reset circuit are working, the second voltage signal can be transmitted to the corresponding control circuit 3104 or reset circuit through the second voltage signal line 36b.

[0494] For example, Figure 9g As shown, the third voltage signal line 36 c may be electrically connected to the third voltage signal terminal VGL2 of the two-stage shift register 31 .

[0495] Since the fourth reset circuits 3108 in the two-stage shift register 31 are electrically connected to the third voltage signal terminal VGL2, the third voltage signal line 36c can be electrically connected to the fourth reset circuits 3108 in the two-stage shift register 31. When each fourth reset circuit 3108 is working, the third voltage signal can be transmitted to the corresponding fourth reset circuit 3108 through the third voltage signal line 36c.

[0496] Based on this, the two-stage shift register 31 can share at least one of the first voltage signal line 36a, the second voltage signal line 36b and the third voltage signal line 36c. The transmission signal line 36 can be the first voltage signal line 36a, the second voltage signal line 36b or the third voltage signal line 36c.

[0497] In addition, the gate drive circuit 3 adopts Figure 9a to Figure 9h and Fig.10 In the case of the structure shown, the input signal terminal Iput in the first-stage shift register 31 and the input signal terminal Iput in the second-stage shift register 31 can be electrically connected to the twenty-first clock signal line CLK_21 in the control signal line 33. At this time, the first-stage shift register 31 and the second-stage shift register 31 can share a transmission signal line 36, connecting the input signal terminal Iput in the two-stage shift register 31 and the twenty-first clock signal line CLK_21, so that the twenty-first clock signal line CLK_21 can transmit a start signal (i.e., an input signal) to the first input circuit 3101 or the fifth reset circuit 3109 in the corresponding shift register 31 through a transmission signal line 36.

[0498] The gate drive circuit 3 adopts Figure 9a to Figure 9h and Fig.10 In the case of the structure shown, the display reset signal terminal SDT in the last four-stage shift register 31 can be connected to the 22nd clock signal line CLK_22. At this time, in the last four-stage shift register 31, the shift register 31 corresponding to the first row of sub-pixel area S1 and the shift register 31 corresponding to the second row of sub-pixels S2 can share a transmission signal line 36, and the display reset signal terminal SDT in the two-stage shift register 31 and the 22nd clock signal line CLK_22 are connected so that the 22nd clock signal line CLK_22 can transmit the display reset signal to the second reset circuit 3106 in the corresponding shift register 31 through a transmission signal line 36.

[0499] In other examples, such as Figure 9a to Figure 9g As shown, the gate driving circuit may further include: a plurality of node voltage transmission lines 36d located in the second gap region E. The transmission signal lines 36 may be node voltage transmission lines 36d.

[0500] Here, the node voltage transmission line 36 d may be used to connect the device groups 311 in the same stage of the shift register 31 , and may also be used to connect the device groups 311 in different stages of the shift register 31 .

[0501] For example, Figure 9a to Figure 9g As shown, in the same stage of the shift register 31, at least two device groups 311 are electrically connected to the same node via a node voltage transmission line 36d.

[0502] The first input circuit 3101 , the output circuit 3103 and the leakage protection circuit 3102 in the same stage of the shift register 31 each include at least one device group 311 .

[0503] Take the example that the first input circuit 3101 includes six device groups 311, the anti-leakage circuit 3102 includes one device group 311, and the output circuit 3103 includes thirteen device groups 311. Among them, the six device groups 311 included in the first input circuit 3101 are arranged in parallel, and each device group 311 includes a first transistor M1 and a second transistor M2. One device group 311 included in the anti-leakage circuit 3102 includes a third transistor M3. Among the thirteen device groups 311 included in the output circuit 3103, one device group 311 includes a fourth transistor M4, each of the two parallel device groups 311 includes a first capacitor C1, and each of the ten parallel device groups 311 includes a fifth transistor M5.

[0504] Since the first input circuit 3101 and the output circuit 3103 are both connected to the pull-up node Q <n>The first input circuit 3101 is electrically connected to the pull-up node Q <n>The device group 311 is electrically connected, and the output circuit 3103 is used to pull up the node Q <n>The electrically connected device group 311 can be connected to the pull-up node Q through the same node voltage transmission line 36d. <n>Electrical connection.

[0505] For example, the second electrode of the second transistor M2 in the six device groups 311 included in the first input circuit 3101, the control electrode of the third transistor M3 in the one device group 311 included in the leakage protection circuit 3102, and the control electrode of the fourth transistor M4, the control electrode of the fifth transistor M5, and the first end of the first capacitor C1 in the thirteen device groups 311 included in the output circuit 3103 can be connected to the pull-up node Q through the same node voltage transmission line 36d. <n>Electrical connection.

[0506] Of course, in the same stage shift register 31, the control circuit 3104 is used to pull up the node Q <n>The electrically connected device group 311 and the first reset circuit 3105 are used to pull up the node Q <n>The electrically connected device group 311 and the second reset circuit 3106 are used to pull up the node Q <n>The electrically connected device group 311 and the third reset circuit 3107 are used to pull up the node Q <n>The electrically connected device group 311 can also be connected to the pull-up node Q through the same voltage transmission line 36d. <n>Electrical connection.

[0507] Since the first input circuit 3101 and the leakage protection circuit 3102 are both connected to the leakage protection node OFF <n>Therefore, the first input circuit 3101 is used to connect to the leakage prevention node OFF <n>The device group 311 is electrically connected, and the leakage prevention circuit 3102 is used to connect to the leakage prevention node OFF <n>The electrically connected device group 311 can be connected to the leakage prevention node OFF through the same node voltage transmission line 36d. <n>Electrical connection.

[0508] For example, the first electrode of the second transistor M2 in the six device groups 311 included in the first input circuit 3101 and the second electrode of the third transistor M3 in the one device group 311 included in the leakage prevention circuit 3102 can be connected to the leakage prevention node OFF through the same node voltage transmission line 36d. <n>Electrical connection.

[0509] Of course, in the same level shift register 31, the first reset circuit 3105 is used to connect to the leakage prevention node OFF <n>The device group 311 electrically connected to the second reset circuit 3106 is used to connect to the leakage prevention node OFF <n>The device group 311 and the third reset circuit 3107 are electrically connected to the leakage prevention node OFF. <n>The electrically connected device group 311 can also be connected to the leakage prevention node OFF through the same voltage transmission line 36d. <n>Electrical connection.

[0510] For example, Figure 9a As shown, in the two-stage shift register 31 electrically connected to the sub-pixels 2 in the first row sub-pixel region S1 and the sub-pixels 2 in the second row sub-pixel region S2, at least two device groups 311 are electrically connected to the same node through a node voltage transmission line 36d.

[0511] The gate drive circuit 3 adopts Figure 9a to Figure 9h The structure shown in the figure is taken as an example, in which a blanking input circuit 32 is electrically connected to the above-mentioned two-stage shift register 31.

[0512] The selection control circuit 3201, the second input circuit 3202 and the two transmission circuits 3203 in the blanking input circuit 32 each include at least one device group 311. Each device group 311 is located in a row of sub-pixels 2 where the corresponding shift register 31 is located, and in the area between two adjacent sub-pixels 2.

[0513] For example, Figure 9a As shown, the selection control circuit 3201 may include two device groups 311, wherein one device group 311 includes a twenty-first transistor M21, a twenty-second transistor M22, and a twenty-third transistor M23, and is located in a region between two adjacent sub-pixels 2 in a first row of sub-pixels in the sub-pixel region S1, and the other device group 311 includes a third capacitor C3, and is located in a region between two adjacent sub-pixels 2 in a second row of sub-pixels in the sub-pixel region S1.

[0514] For example, Figure 9a As shown, the second input circuit 3202 may include a device group 311, which includes a twenty-fourth transistor M4 and is located in a region between two adjacent sub-pixels 2 in the first row of sub-pixels region S1.

[0515] For example, Figure 9a As shown, each of the two transmission circuits 3203 includes a device group 311, and the device group 311 includes a twenty-fifth transistor M25 and a twenty-sixth transistor M26. The device group 311 included in one of the transmission circuits 3203 is located in the region between two adjacent sub-pixels 2 in the first row of sub-pixels region S1, and the device group 311 included in the other transmission circuit 3203 is located in the region between two adjacent sub-pixels 2 in the second row of sub-pixels region S1.

[0516] Since the second input circuit 3202 and the above-mentioned two transmission circuits 3203 are both electrically connected to the second blanking node N, the device group 311 in the second input circuit 3202 used to be electrically connected to the second blanking node N and the device group 311 in the two transmission circuits 3203 used to be electrically connected to the second blanking node N can be electrically connected to the second blanking node N through the same node voltage transmission line 36d.

[0517] For example, the second electrode of the twenty-fourth transistor M24 in the device group 311 included in the second input circuit 3202 and the first electrode of the twenty-fifth transistor M25 in the device group included in the two transmission circuits 3203 can be electrically connected to the second blanking node N through the same node voltage transmission line 36d.

[0518] In some other examples, such as Fig.10 As shown, at least one cascade input signal line 34 includes a first sub-input signal line 341 and a second sub-input signal line 342 located in different first gap regions D. The gate drive circuit 3 may further include: an input signal connection line 36e located in the second gap region E and electrically connected to the first sub-input signal line 341 and the second sub-input signal line 342. The transmission signal line 36 may be the input signal connection line 36e.

[0519] For example, Fig.10 As shown, in the shift registers 31 of different stages, the device groups 311 with the same structure can be located in the same first gap region D, so as to reduce the difficulty of the layout design of the display panel 100 .

[0520] For example, Fig.10 As shown, in the shift registers 31 of different stages, the device group 311 including the first input circuit 3101 (including the first transistor M1) is located in the same first gap region D. For another example, in the shift registers 31 of different stages, the device group 311 including the output circuit 3103 (including the fourth transistor M4) is located in the same first gap region D. Among them, in the shift registers 31 of different stages, the first gap region D where the first input circuit 3101 is located and the first gap region D where the output circuit 3103 is located are not the same.

[0521] Based on this, for example, Fig.10 As shown, in a cascade input signal line 34, the first sub-input signal line 341 can be connected to the shift signal terminal CR of the output circuit 3103 in the first-stage shift register 31. <n>The second sub-input signal line 342 can be electrically connected to the input signal terminal Iput of the first input circuit 3101 in another stage of the shift register 31, and can be located in the same first gap region D as or different from the output circuit 3103. The second sub-input signal line 342 can be electrically connected to the input signal terminal Iput of the first input circuit 3101 in another stage of the shift register 31, and can be located in the same first gap region D as the first input circuit 3101. The first gap region D where the first input circuit 3101 is located and the first sub-input signal line 341 are located are not the same, therefore, an input signal connection line 36e can be set to connect the first sub-input signal line 341 and the second sub-input signal line 342 located in different first gap regions D.

[0522] Here, since the shift signal terminal CR in the Nth stage shift register 31 <n>, and is electrically connected to the input signal terminal Iput in the N+2-stage shift register 31 (e.g., corresponding to the first row of sub-pixel regions S1) and the N+3-stage shift register 31 (e.g., corresponding to the second row of sub-pixel regions S2), so the input signal connection line 36e can be set in the second gap region E, and the two-stage shift register 31 shares one input signal connection line 36e, thereby realizing electrical connection with the N-stage shift register 31. The two-stage shift register 31 can also share one second sub-input signal line 342.

[0523] For example, Fig.10 As shown, for the output circuit 3103 in the first stage shift register 31, the first input circuit 3101 in the third stage shift register 31, and the first input circuit 3101 in the fourth stage shift register 31, the first sub-input signal line 341 can be connected to the shift signal terminal CR of the output circuit 3103. <1> The second sub-input signal line 342 can be located in the same first gap region D as the two first input circuits 3101, and is electrically connected to the input signal terminals Iput of the two first input circuits 3101. The input signal connection line 36e can be located in the second gap region E between the third-stage shift register 31 and the fourth-stage shift register 31, and is electrically connected to the first sub-input signal line 341 and the second sub-input signal line 342. In this way, the two-stage shift register 31 shares the same input signal connection line 36e.

[0524] In some other examples, such as Fig.10 As shown, at least one cascaded display reset signal line 35 includes a first sub-display reset signal line 351 and a second sub-display reset signal line 352 located in different first gap regions D. The gate drive circuit 3 may further include: a display reset connection line 36f located in the second gap region E and electrically connected to the first sub-display reset signal line 351 and the second sub-display reset signal line 352. The transmission signal line 36 may be a display reset connection line 36f.

[0525] Exemplarily, in the shift registers 31 of different stages, the device groups 311 with the same structure may be located in the same first gap region D, so as to reduce the difficulty of the layout design of the display panel 100 .

[0526] For example, in the shift registers 31 of different stages, the device group 311 including the first input circuit 3101 (including the first transistor M1) is located in the same first gap region D. For another example, in the shift registers 31 of different stages, the device group 311 of the second reset circuit 3106 (including the thirteenth transistor M13 and the fourteenth transistor M14) is located in the same first gap region D. Among them, in the shift registers 31 of different stages, the first gap region D where the output circuit 3103 is located and the first gap region D where the second reset circuit 3106 is located are not the same.

[0527] Based on this, for example, Fig.10 As shown, in a cascade display reset signal line 35, the first sub-display reset signal line 351 can be connected to the shift signal terminal CR of the output circuit 3103 in the first-stage shift register 31. <n>The second sub-display reset signal line 352 can be electrically connected to the display reset signal terminal STD of the second reset circuit 3106 in another stage of the shift register 31, and can be located in the same first gap area D as the output circuit 3103. The second sub-display reset signal line 352 can be electrically connected to the display reset signal terminal STD of the second reset circuit 3106 in another stage of the shift register 31, and can be located in the same first gap area D as the second reset circuit 3106. The first gap area D where the output circuit 3103 is located and the first sub-display reset signal line 351 are located are not the same, therefore, a display reset connection line 36f can be set to connect the first sub-display reset signal line 351 and the second sub-display reset signal line 352 located in different first gap areas D.

[0528] Here, since the shift signal terminal CR in the N+4th stage shift register 31 <n>, and is electrically connected to the display reset signal end STD in the Nth stage shift register 31 (e.g., corresponding to the first row sub-pixel region S1) and the N+1th stage shift register 31 (e.g., corresponding to the second row sub-pixel region S2), so the display reset connection line 36f can be set in the second gap region E, and the two stages of shift registers 31 share one display reset connection line 36f to achieve electrical connection with the N+4th stage shift register 31. The two stages of shift registers 31 can also share one second sub-display reset signal line 352.

[0529] For example, Fig.10 As shown, for the output circuit 3103 in the fifth stage shift register 31, the second reset circuit 3106 in the first stage shift register 31, and the second reset circuit 3106 in the second stage shift register 31, the first sub-display reset signal line 351 can be located in the same first gap area D as the output circuit 3103 and connected to the shift signal terminal CR of the output circuit 3103. <n>The second sub-display reset signal line 352 can be located in the same first gap area D with the two second reset circuits 3106, and is electrically connected to the display reset signal terminals STD of the two second reset circuits 3106. The display reset connection line 36f can be located in the second gap area E between the first-stage shift register 31 and the second-stage shift register 31, and is electrically connected to the first sub-display reset signal line 351 and the second sub-display reset signal line 352. In this way, the two-stage shift registers 31 share the same display reset connection line 36f.

[0530] In some embodiments, Figure 14a to Figure 14e ,and Fig.15 As shown, the display panel 100 further includes a light shielding pattern 101A located on the light shielding layer 101, and the orthographic projections of the channel portions of the switch transistor T1 and the drive transistor T2 on the substrate 1 are located within the orthographic projection range of the light shielding pattern 101A on the substrate. In this way, the light shielding pattern 101A can be used to shield the light incident from the substrate 1 to the channel portions of the switch transistor T1 and the drive transistor T2, thereby avoiding affecting the performance of the switch transistor T1 and the drive transistor T2.

[0531] Fig.15 The light shielding pattern 101A in the embodiment is made of metal material. The light shielding pattern 101A can be electrically connected to the source-drain conductive layer 108 in the switch transistor T1, the drive transistor T2 and the sensing transistor T3 to form a structure similar to an upper and lower double channel in the switch transistor T1, the drive transistor T2 and the sensing transistor T3 to improve the electrical performance of the transistor. The source-drain conductive layer 108 includes the first electrode and the second electrode of each transistor, as well as a plurality of data lines DL, etc.

[0532] The structure of the light shielding pattern 101A may be a single-layer structure or a multi-layer structure formed by sequentially stacking multiple thin films.

[0533] The light emitting device 22 comprises an anode 221, a light emitting layer 222 and a cathode layer 223 which are stacked in sequence. The anode 221 is electrically connected to the second electrode of the driving transistor T2.

[0534] Exemplarily, at least one of the anode 221 and the cathode 223 is a light-transmitting layer. That is, at least one of the anode 221 and the cathode 223 can be made of a conductive material with high light transmittance.

[0535] For example, the conductive material with high light transmittance may be indium tin oxide (ITO for short).

[0536] When the anode 221 is a light-transmitting layer, the light emitted by the light-emitting device 22 can be emitted in a direction pointing to the substrate 1, and in this case, the display panel 100 can be a bottom-emitting display panel. When the cathode 223 is a light-transmitting layer, the light emitted by the light-emitting device 22 can be emitted in a direction away from the substrate 1, and in this case, the display panel 100 can be a top-emitting display panel. When both the anode 221 and the cathode 223 are light-transmitting layers, the display panel 100 can emit light from both sides.

[0537] The display panel 100 provided in the present disclosure realizes a layout design with a high aperture ratio. The average aperture ratio of each area of ​​the display area AA of the display panel 100 can reach 32% to 38.5%. For example, the average aperture ratio can reach 32%, 34%, 35.25%, 36% or 38.5%.

[0538] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A display panel, comprising: substrate; A plurality of sub-pixels are arranged on one side of the substrate; the plurality of sub-pixels are arranged in a plurality of rows along a first direction and in a plurality of columns along a second direction; the sub-pixels include a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit; and, A gate driving circuit is located on the same side of the substrate as the plurality of sub-pixels; the gate driving circuit comprises a multi-stage cascaded shift register, wherein a stage of the shift register is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels; the shift register comprises a plurality of device groups, wherein one device group is located in a region between two adjacent sub-pixels in a corresponding row of sub-pixels; the device group comprises at least one transistor and / or at least one capacitor; Wherein, the gate drive circuit further includes: a plurality of cascade input signal lines and a plurality of cascade display reset signal lines; the cascade input signal lines are configured to connect the shift signal end of a shift register at one stage and the input signal end of another shift register; the cascade display reset signal lines are configured to connect the shift signal end of a shift register at one stage and the display reset signal end of another shift register; The display panel has a plurality of sub-pixel regions for arranging the plurality of sub-pixels, and a first gap region located between two adjacent columns of sub-pixel regions; the cascade display reset signal line and the cascade input signal line are both arranged in the first gap region, and the two are arranged in different first gap regions; Each sub-pixel region includes: a sub-pixel circuit region arranged along the second direction and used to set a corresponding pixel driving circuit and a sub-pixel light-emitting region used to set a corresponding light-emitting device; Along the second direction, any three adjacent rows of sub-pixel regions are respectively a first row of sub-pixel regions, a second row of sub-pixel regions, and a third row of sub-pixel regions; The area between the first row of sub-pixel areas and the second row of sub-pixel areas is a second gap area, and the area between the second row of sub-pixel areas and the third row of sub-pixel areas is a third gap area; Wherein, in the first row of sub-pixel regions and the second row of sub-pixel regions, the sub-pixel light-emitting regions are closer to the second gap region than the sub-pixel circuit region; In the second row of sub-pixel regions and the third row of sub-pixel regions, the sub-pixel circuit regions are closer to the third gap region than the sub-pixel light emitting regions.

2. The display panel according to claim 1, wherein: The plurality of cascade input signal lines are divided into a plurality of groups, each group of cascade input signal lines includes at least one cascade input signal line, and at least one group of cascade input signal lines is arranged in one of the first gap regions; The plurality of cascade display reset signal lines are divided into a plurality of groups, each group of cascade display reset signal lines includes at least one cascade display reset signal line, and at least one group of cascade display reset signal lines is arranged in one of the first gap regions.

3. The display panel according to claim 2, wherein: At least one column of sub-pixels is arranged between two adjacent groups of cascade input signal lines located in different first gap regions; At least one column of sub-pixels is arranged between two adjacent groups of cascade display reset signal lines that are located in different first gap regions.

4. The display panel according to claim 2, wherein: A plurality of groups of cascade input signal lines are arranged in one of the first gap regions, and at least one row of sub-pixels is arranged between two adjacent groups of cascade input signal lines in the same first gap region; A plurality of groups of cascade display reset signal lines are arranged in one of the first gap regions, and at least one row of sub-pixels is arranged between two adjacent groups of cascade display reset signal lines in the same first gap region.

5. The display panel according to claim 1, further comprising: A plurality of data lines extending along the second direction; one data line is electrically connected to a plurality of pixel driving circuits in a column of sub-pixels; The plurality of cascade input signal lines, the plurality of cascade display reset signal lines and the plurality of data lines are made of the same material and are arranged in the same layer.

6. The display panel according to claim 1, wherein: The plurality of sub-pixels are divided into a plurality of pixel units; one pixel unit comprises at least three sub-pixels arranged in sequence along the first direction; the plurality of pixel units are arranged into a plurality of rows along the first direction and into a plurality of columns along the second direction; The area between any two adjacent columns of pixel units is the first gap area.

7. The display panel according to claim 1, further comprising: a plurality of power supply voltage lines extending along the second direction; a plurality of auxiliary power supply voltage lines extending along the first direction, each power supply voltage line being electrically connected to a plurality of auxiliary power supply voltage lines; Wherein, each row of pixel areas corresponds to at least one auxiliary power supply voltage line; The pixel driving circuits of the plurality of sub-pixels in the pixel area corresponding to each auxiliary power voltage line are electrically connected to the auxiliary power voltage line.

8. The display panel according to claim 7, further comprising: A passivation layer, a color filter layer and a flat layer are sequentially arranged on the substrate and located between the pixel driving circuit of the sub-pixel and the light-emitting device; The passivation layer and the planar layer are provided with a first via hole penetrating the two; the pixel driving circuit is electrically connected to the light emitting device through the first via hole; The color filter layer includes a plurality of filter parts, each of which is arranged in a sub-pixel light-emitting area of ​​a sub-pixel area; in the same sub-pixel area, along the second direction, the filter part is separated from the first via hole located in the sub-pixel area by at least part of the pixel driving circuit located in the sub-pixel area and / or the auxiliary power supply voltage line.

9. The display panel according to claim 8, further comprising: A gate line for transmitting a gate signal, a data line for transmitting a data signal, and a first sensing signal line for transmitting a sensing signal; The pixel driving circuit comprises: a switch transistor, wherein a control electrode of the switch transistor is electrically connected to the gate line, and a first electrode of the switch transistor is electrically connected to the data line; A storage capacitor, wherein a first electrode of the storage capacitor is electrically connected to a second electrode of the switching transistor, and a second electrode of the storage capacitor is electrically connected to the light emitting device; a driving transistor, wherein a control electrode of the driving transistor is electrically connected to a second electrode of the switching transistor and a first electrode plate of the storage capacitor, a first electrode of the driving transistor is electrically connected to the auxiliary power supply voltage line, and a second electrode of the driving transistor is electrically connected to the light emitting device and a second electrode plate of the storage capacitor; a sensing transistor, wherein a control electrode of the sensing transistor is electrically connected to the gate line, a first electrode of the sensing transistor is electrically connected to the first sensing signal line, and a second electrode of the sensing transistor is electrically connected to the light emitting device, a second electrode plate of the storage capacitor, and a second electrode of the driving transistor; The switch transistor and the sensing transistor are located farther away from the sub-pixel light emitting area of ​​the sub-pixel region where the pixel driving circuit is located than the driving transistor.

10. The display panel according to claim 9, further comprising: An active layer, a gate insulating layer, a gate conductive layer, an interlayer dielectric layer and a source-drain conductive layer are sequentially arranged on the substrate; The active layer includes a first electrode, a channel portion, and a second electrode of the switch transistor, the drive transistor, and the sense transistor; the gate conductive layer includes a control electrode of the switch transistor, the drive transistor, and the sense transistor; and the source-drain conductive layer includes a first connection pattern and a second connection pattern. A second via hole penetrating the interlayer dielectric layer and the gate insulating layer is provided in the interlayer dielectric layer, and a third via hole is provided in the interlayer dielectric layer; the first connection pattern is electrically connected to the second electrode of the switch transistor through the second via hole, and is electrically connected to the control electrode of the drive transistor through the third via hole; A fourth via hole is provided in the interlayer dielectric layer, and the second connection pattern is electrically connected to the second electrode of the driving transistor through the fourth via hole; In the same sub-pixel region, along the second direction, the filter portion and the first via hole located in the sub-pixel region are separated by the control electrode, the channel portion and the first electrode of the driving transistor and the auxiliary power supply voltage line.

11. The display panel according to claim 10, further comprising: A first electrode layer and a buffer layer are sequentially arranged on the substrate, wherein the first electrode layer and the buffer layer are located on a side of the active layer close to the substrate; The first electrode layer includes the second electrode plate of the storage capacitor, and the active layer also includes the first electrode plate of the storage capacitor; A fifth via hole is provided in the interlayer dielectric layer, and the first connection pattern is also electrically connected to the first electrode plate of the storage capacitor through the fifth via hole; a sixth via hole is provided in the interlayer dielectric layer and the buffer layer and passes through the two, and the second connection pattern is also electrically connected to the second electrode plate of the storage capacitor through the sixth via hole; The fifth via hole and the sixth via hole are both located on a side of the storage capacitor close to the third gap region.

12. The display panel according to claim 7, wherein: Each row of pixel areas corresponds to a plurality of auxiliary power supply voltage lines; Along the first direction, two adjacent auxiliary power supply voltage lines are separated by the first gap area.

13. The display panel according to claim 7, wherein: Each column of pixel areas corresponds to a power supply voltage line, and the power supply voltage line is located on one of two opposite sides of the pixel area along the first direction; Each pixel region corresponds to an auxiliary power supply voltage line, and each of the auxiliary power supply voltage lines is electrically connected to a pixel driving circuit of a plurality of sub-pixels in the corresponding pixel region.

14. The display panel according to claim 7, further comprising: An active layer, a gate insulating layer, a gate conductive layer, an interlayer dielectric layer and a source-drain conductive layer are sequentially arranged on the substrate; Wherein, the pixel driving circuit includes a driving transistor, the active layer includes a first electrode, a channel portion and a second electrode of the driving transistor; the source-drain conductive layer includes a plurality of third connection patterns; the auxiliary power supply voltage line is located in the gate conductive layer; A seventh via hole is provided in the interlayer dielectric layer, and an eighth via hole is provided in the interlayer dielectric layer and the gate insulating layer; the third connection pattern is electrically connected to the auxiliary power supply voltage line through the seventh via hole, and is electrically connected to the first electrode of the driving transistor through the eighth via hole; The power supply voltage line is located in the source-drain conductive layer; in the same pixel area, a third connection pattern closest to the power supply voltage line corresponding to the pixel area among a plurality of third connection patterns is electrically connected to the power supply voltage line.

15. The display panel according to claim 7, further comprising: A plurality of grid lines, each grid line is in a zigzag shape and extends substantially along the first direction; A gate line is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels; The grid line includes a plurality of first extension segments, a plurality of second extension segments and a plurality of connecting segments, each of the first extension segments and each of the second extension segments extends substantially along the first direction, the plurality of first extension segments and the plurality of second extension segments are alternately arranged, adjacent first extension segments and second extension segments are connected by connecting segments, and along the second direction, there is a spacing between the extension lines of adjacent first extension segments and second extension segments; The first extension segment and two connecting segments connected to the first extension segment form a first recess, and the opening of the first recess faces a direction away from the third gap region; The second extension segment and the two connecting segments connected to the second extension segment form a second recess, and the opening of the second recess faces a direction close to the third gap area; At least part of the pixel driving circuit is located in the first recess and the second recess.

16. The display panel according to claim 7, wherein: The pixel driving circuit includes: a first sensing signal line located in the third gap area and extending along the first direction; In the case where the plurality of sub-pixels are divided into a plurality of pixel units, and one pixel unit includes at least three sub-pixels sequentially arranged along the first direction, In the sub-pixels located in the second row of sub-pixel regions and the third row of sub-pixel regions, two pixel units facing each other along the second direction share the first sensing signal line.

17. The display panel according to claim 16, wherein: The sub-pixel further includes: a light shielding layer disposed on a side of the pixel driving circuit close to the substrate; The first sensing signal line and the light shielding layer are made of the same material and are disposed in the same layer.

18. The display panel according to claim 16, wherein: The pixel driving circuit further includes: a second sensing signal line extending along the second direction; The second sensing signal line is located in a region between two adjacent columns of sub-pixels in two pixel units that are opposite to each other along the second direction; The first sensing signal line is electrically connected to the second sensing signal line through a via hole.

19. The display panel according to claim 18, wherein: In the case where the display panel further includes a plurality of data lines, The second sensing signal line is made of the same material and disposed in the same layer as the plurality of data lines.

20. The display panel according to claim 7, wherein: The gate driving circuit further includes: a plurality of transmission signal lines located in the second gap region and extending along the first direction; The two-stage shift register electrically connected to the sub-pixels located in the first row of sub-pixel regions and the sub-pixels located in the second row of sub-pixel regions shares at least one transmission signal line among the plurality of transmission signal lines.

21. The display panel according to claim 20, wherein: The gate drive circuit further includes: A first voltage signal line, electrically connected to a first voltage signal terminal of the two-stage shift register; a second voltage signal line electrically connected to the second voltage signal terminal of the two-stage shift register; and a third voltage signal line electrically connected to the third voltage signal terminal of the two-stage shift register; The transmission signal line is the first voltage signal line, the second voltage signal line or the third voltage signal line.

22. The display panel according to claim 20, wherein: At least one cascade input signal line includes a first sub-input signal line and a second sub-input signal line located in different first gap regions; The gate driving circuit further includes: an input signal connection line located in the second gap region and electrically connected to the first sub-input signal line and the second sub-input signal line; The transmission signal line is the input signal connection line; and / or, at least one cascade display reset signal line includes a first sub-display reset signal line and a second sub-display reset signal line located in different first gap regions; The gate driving circuit further includes: a display reset connection line located in the second gap region and electrically connected to the first sub-display reset signal line and the second sub-display reset signal line; The transmission signal line is the display reset connection line.

23. The display panel according to claim 20, wherein: The gate drive circuit further includes: a plurality of node voltage transmission lines located in the second gap region; In the same level of shift register, at least two device groups are electrically connected to the same node through a node voltage transmission line; In the two-stage shift register, at least two device groups are electrically connected to the same node via a node voltage transmission line; The transmission signal line is the node voltage transmission line.

24. The display panel according to claim 23, wherein: The shift register comprises: A first input circuit is electrically connected to the input signal terminal, the pull-up node and the leakage prevention node; the first input circuit is configured to transmit the input signal to the pull-up node in response to an input signal received at the input signal terminal during a display period of a frame display stage; an output circuit electrically connected to the pull-up node, the first clock signal terminal and the first output signal terminal; the output circuit is configured to transmit the first clock signal received at the first clock signal terminal to the first output signal terminal under the control of the voltage of the pull-up node during a display period of a frame display stage; and an anti-leakage circuit electrically connected to the pull-up node, the first voltage signal terminal and the anti-leakage node; the anti-leakage circuit is configured to, under the control of the voltage of the pull-up node, transmit the first voltage signal received at the first voltage signal terminal to the anti-leakage node to prevent leakage of the pull-up node; The first input circuit, the output circuit and the leakage protection circuit each include at least one device group; The device group in the first input circuit for being electrically connected to the pull-up node, and the device group in the output circuit for being electrically connected to the pull-up node, are electrically connected to the pull-up node via a node voltage transmission line; The device group in the first input circuit for electrically connecting to the anti-leakage node and the device group in the anti-leakage circuit for electrically connecting to the anti-leakage node are electrically connected to the anti-leakage node via a node voltage transmission line.

25. The display panel according to claim 24, wherein: The gate drive circuit further includes: a plurality of blanking input circuits; one blanking input circuit is electrically connected to at least two adjacent shift registers; The blanking input circuit is configured to control the corresponding shift register to input a blanking control signal to the pixel driving circuit of the corresponding row during the blanking period of a frame display stage, so that the pixel driving circuit obtains the sensing signal; The blanking input circuit comprises: A selection control circuit is electrically connected to the selection control signal terminal, the shift signal terminal, the second voltage signal terminal and the first blanking node; the selection control circuit is configured to transmit the shift signal received at the shift signal terminal to the first blanking node under the control of the selection control signal transmitted by the selection control signal terminal; a second input circuit electrically connected to the first blanking node, the second blanking node and the second clock signal terminal or the first voltage signal terminal; the second input circuit is configured to, under the control of the voltage of the first blanking node, transmit the second clock signal received at the second clock signal terminal or the first voltage signal received at the first voltage signal terminal to the second blanking node; and at least two transmission circuits, one transmission circuit being electrically connected to the pull-up node of the first-stage shift register; the transmission circuit being also electrically connected to the second blanking node and the second clock signal terminal; the transmission circuit being configured to, under the control of the second clock signal transmitted by the second clock signal terminal, transmit the second clock signal or the first voltage signal received at the second blanking node to the pull-up node; The second input circuit and the transmission circuit each include at least one device group; each device group included in the second input circuit and the transmission circuit is respectively located in a row of sub-pixels where the corresponding shift register is located, and in an area between two adjacent sub-pixels; The device group in the second input circuit for being electrically connected to the second blanking node and the device group in the at least two transmission circuits for being electrically connected to the second blanking node are electrically connected to the second blanking node via a node voltage transmission line.

26. The display panel according to any one of claims 20 to 25, further comprising: A plurality of gate lines extending along the first direction; one gate line is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels; The plurality of transmission signal lines and the plurality of gate lines are made of the same material and are arranged in the same layer.

27. The display panel according to any one of claims 1 to 26, wherein: The gate driving circuit further includes: a plurality of control signal lines extending along the second direction; A first-stage shift register is electrically connected to at least a portion of the plurality of control signal lines; the shift register is configured to provide output signals to a plurality of pixel driving circuits of a corresponding row under the control of at least a portion of the control signal lines electrically connected to the shift register.

28. The display panel according to claim 27, wherein: At least one control signal line among the plurality of control signal lines is located in the first gap region.

29. A display device comprising: The display panel according to any one of claims 1 to 28.

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