High Dynamic Range (HDR) video rotation animation

Abstract

In some aspects, the present disclosure provides a method for high dynamic range (HDR) video rotation. The method includes receiving, by a display processor, an indication that a frame rotation animation process has been initiated for video playback, the display processor comprising a display processor pipeline. The method also includes determining whether the video playback is in HDR format or another format. In response to the determination and receiving the indication: if the video playback is in HDR format: bypassing loading the frame rotation animation into a first portion of the display processor pipeline, and loading the frame rotation animation into a second portion of the display processor pipeline.

Description

Technical Field

[0001] Generally speaking, the teachings of this disclosure relate to graphics and display operations, and more specifically, the teachings of this disclosure relate to techniques for improving rotation animation performance. Background Art

[0002] The video playback can be displayed by the electronic device using any suitable display and / or user interface. In some cases, the size of the video playback can change as the user moves the electronic device. For example, the device can be rotated so that the display of the video playback switches between portrait mode and landscape mode. In some cases, the device can provide a graphical transition between portrait mode and landscape mode, such as using a graphics engine to render a rotation animation.

[0003] However, such animations can require significant processing power, which may be limited in portable electronic devices. In addition, such animations can suffer from flickering issues caused by different display parameters used between the graphics processor and the display processor. Therefore, implementing rotational animations in electronic devices can be challenging. Summary of the Invention

[0004] A brief overview of one or more aspects of the present disclosure is provided below to provide a basic understanding of such aspects. This overview is not an extensive overview of all anticipated features of the present disclosure and is neither intended to identify key or important elements of all aspects of the present disclosure nor to delineate the scope of any or all aspects of the present disclosure. Its sole purpose is to provide some concepts of one or more aspects of the present disclosure in a simplified form as a prelude to a more detailed description that will be provided later.

[0005] Certain aspects relate to a method for high dynamic range (HDR) video rotation. The method includes receiving an indication by a display processor that a frame rotation animation process has been initiated for video playback, the display processor including a display processor pipeline. The method also includes determining whether the video playback is in HDR format or another format. The method also includes, in response to the determination and receiving the indication: if the video playback is in HDR format: bypassing loading the frame rotation animation into a first portion of the display processor pipeline, and loading the frame rotation animation into a second portion of the display processor pipeline. The method also includes: if the video playback is in the other format, loading the frame rotation animation into the first portion of the display processor pipeline, wherein the second portion is further in a processing step of the display processor pipeline than the first portion.

[0006] Certain aspects relate to an apparatus comprising: a memory; and a processor coupled to the memory. In some examples, the processor and the memory are configured to: receive an indication that a frame rotation animation process has been initiated for video playback, the processor comprising a display processor pipeline; determine whether the video playback is in HDR format or another format; and in response to the determination and the received indication: if the video playback is in HDR format: bypass loading the frame rotation animation into a first portion of the display processor pipeline and load the frame rotation animation into a second portion of the display processor pipeline; and if the video playback is in the other format, load the frame rotation animation into the first portion of the display processor pipeline, wherein the second portion is further in the processing steps of the display processor pipeline than the first portion.

[0007] Certain aspects relate to an apparatus comprising: a unit for receiving an indication that a frame rotation animation process has been initiated for video playback, the unit for receiving comprising a processor pipeline; a unit for determining whether the video playback is in HDR format or another format; in response to determining the format of the video playback and receiving the indication: if the video playback has an HDR format: a unit for bypassing loading the frame rotation animation into a first portion of the display processor pipeline, and a unit for loading the frame rotation animation into a second portion of the display processor pipeline; and if the video playback has the another format, a unit for loading the frame rotation animation into the first portion of the display processor pipeline, wherein the second portion is further in a processing step of the display processor pipeline than the first portion.

[0008] Certain aspects relate to a non-transitory computer-readable storage medium storing instructions that, when executed by a processor of a device, cause the device to perform a method for high dynamic range (HDR) video rotation, the method comprising: receiving an indication by a display processor that a frame rotation animation process has been initiated for video playback, the display processor comprising a display processor pipeline; determining whether the video playback is in HDR format or another format; in response to the determination and receiving the indication: if the video playback has an HDR format: bypassing loading the frame rotation animation into a first portion of the display processor pipeline, and loading the frame rotation animation into a second portion of the display processor pipeline; and if the video playback has the other format, loading the frame rotation animation into the first portion of the display processor pipeline, wherein the second portion is further in a processing step of the display processor pipeline than the first portion.

[0009] Aspects of the present disclosure provide apparatuses, processors, computer-readable media, and units for performing techniques and methods for high dynamic range (HDR) video rotation animation.

[0010] To accomplish the foregoing and related ends, one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and accompanying drawings set forth in detail certain illustrative features of one or more aspects. However, these features are indicative of only a few of the various ways in which the principles of the various aspects may be employed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the above-mentioned features of the present disclosure may be understood in detail, a more detailed description of the content briefly summarized above may be obtained by reference to various aspects, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only certain typical aspects of the present disclosure and are therefore not to be considered limiting of its scope, as the description may admit to other equally effective aspects.

[0012] Figure 1 is a block diagram illustrating an exemplary system-on-a-chip (SoC) integrated circuit according to certain aspects of the present disclosure.

[0013] Figure 2 is a block diagram illustrating an exemplary computing device according to certain aspects of the present disclosure.

[0014] Figure 3 is a schematic diagram of an electronic device rotated from a portrait orientation to a landscape orientation according to certain aspects of the present disclosure.

[0015] Figure 4 is a flow chart illustrating example operations for improving HDR video rotation animation, in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION

[0016] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be implemented. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be implemented without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0017] Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts. Reference to specific examples and implementations is for illustrative purposes and is not intended to limit the scope of the invention or the claims.

[0018] Although features of the present invention may be discussed below with respect to certain embodiments and figures, all embodiments of the present invention may include one or more of the advantageous features discussed herein. In other words, although one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with various other embodiments discussed herein.

[0019] The term "system on a chip" (SOC) is used herein to refer to a single integrated circuit (IC) chip that includes multiple resources and / or processors integrated on a single substrate. A single SOC may include circuits for digital, analog, mixed-signal, and radio frequency functions. A single SOC may also include any number of general-purpose and / or special-purpose processors (digital signal processors, modem processors, video processors, etc.), memory blocks (e.g., ROM, RAM, flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.

[0020] A variety of different types of memory and memory technologies are available or envisioned in the future, all of which are suitable for use with various aspects of the present disclosure. Such memory technologies / types may include phase change memory (PRAM), dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM), flash memory (e.g., embedded multimedia card (eMMC) flash memory, flash erasable programmable read-only memory (FEPROM)), pseudo-static random access memory (PSRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), and other random access memory (RAM) and read-only memory (ROM) technologies known in the art. DDRSDRAM memory may be DDR type 1 SDRAM memory, DDR type 2 SDRAM memory, DDR type 3 SDRAM memory, or DDR type 4 SDRAM memory.

[0021] Each of the above-mentioned memory technologies includes, for example, elements suitable for storing instructions, programs, control signals and / or data for use in or by a computer or other digital electronic device. Any reference to terms and / or technical details related to separate types of memory, interfaces, standards or memory technologies is for illustrative purposes only and is not intended to limit the scope of the claims to a particular memory system or technology unless specifically recited in the claim language. Mobile computing device architectures have increased in complexity and now typically include multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, global positioning system (GPS) processors, display processors, etc.), complex memory systems, intricate electrical interconnections (e.g., buses and / or structures), and many other resources to execute complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0022] Figure 1 1 is a block diagram illustrating an exemplary system on a chip (SoC) 100 suitable for implementing various aspects of the present disclosure. SoC 100 includes a processing system 120 that includes multiple heterogeneous processors, such as a central processing unit (CPU) 102, a display processing unit 104, a graphics processing unit 106, and a processor memory 108. It should be noted that processing system 120 may include additional processing units, such as a digital signal processor (DSP), an application processor, etc. As used herein, a processing unit may include one or more processors and any suitable supporting hardware and / or software (e.g., registers, combinational logic, controllers, etc.). Processing system 120 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. Processing units 102, 104, and 106 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.) so that they can operate at much higher frequencies / clock rates (compared to frequencies / clock rates that would be possible if signals were to travel off-chip). The proximity of the cores may also allow for sharing of on-chip memory and resources (eg, voltage rails), as well as allowing for more coordinated cooperation between the cores.

[0023] The processing system 120 is interconnected with one or more controller modules 112, input / output (I / O) modules 114, memory modules 116, and system components and resource modules 118 via a bus module 110, which may include a reconfigurable logic gate array and / or implement a bus architecture (e.g., CoreConnect, Advanced Microcontroller Bus Architecture (AMBA), etc.). Bus module 110 communication may be provided by an advanced interconnect such as a high-performance network on chip (NoC). The interconnect / bus module 110 may include or provide a bus master system that is configured to grant SoC components (e.g., processors, peripherals, etc.) exclusive control of the bus for a set duration, for multiple operations, multiple bytes, etc. (e.g., transferring data in burst mode, block transfer mode, etc.). In some cases, the bus module 110 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus simultaneously.

[0024] The controller module 112 can be a dedicated hardware module that is configured to manage data flow to and from the memory module 116, the processor memory 108, or a memory device located off-chip (e.g., a flash memory device). In some examples, the memory module may include a UFS host device that is configured to receive various memory commands from multiple master devices and address and transmit the memory commands to the memory device. The multiple master devices may include processing units 102, 104, and 106 and / or multiple applications running on one or more of the processing units 102, 104, and 106. The controller module 112 may include one or more processors configured to perform the operations disclosed herein. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gating logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure.

[0025] I / O modules 114 are configured to communicate with resources external to the SoC. For example, I / O modules 114 include input / output interfaces (e.g., bus architectures or interconnects) or hardware designs for performing specific functions (e.g., memory, wireless devices, and digital signal processors). In some examples, I / O modules include circuits for interfacing with peripheral devices (such as memory or digital storage devices located off-chip).

[0026] Memory module 116 is a computer-readable storage medium implemented in SoC 100. Memory module 116 may provide non-volatile storage, such as flash memory, for one or more of processing system 120, controller module 112, I / O module 114, and / or system components and resource module 118. Memory module 116 may include cache memory to provide temporary storage of information to enhance processing speed of SoC 100.

[0027] SoC 100 may include system components and resource modules 118 for managing sensor data, analog-to-digital conversion, wireless data transmission, and for performing other specialized operations (e.g., supporting interoperability between different devices). System components and resource modules 118 may also include components such as voltage regulators, oscillators, phase-locked loops, peripheral bridges, data controllers, system controllers, access ports, timers, and other similar components for supporting processors and software clients running on the computing device. System components and resources 118 may also include circuits for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0028] Figure 2 is a block diagram illustrating an exemplary computing device 200 according to certain aspects of the present disclosure. In some embodiments, the computing device 200 may be Figure 1 As further discussed herein, the computing device 200 provides an improved user experience and reduced power consumption by eliminating display flickering of the rotation animation and by bypassing one or more display processing elements.

[0029] The computing device 200 includes Figure 1104 , and a CPU 102 , a DPU 104 , and a GPU 106 . In some aspects, one or more applications 202 a - 202 n (collectively, “applications 202 ”) may execute on the CPU 102 and may communicate with a window manager service (WMS) 204 . The WMS 204 communicates with the DPU 104 and the GPU 106 . In this example, the GPU 106 includes an animation transformation module 206 . The DPU 104 includes a display processor pipeline having multiple components configured to prepare data for display. In this example, the display processor pipeline includes a compositor 208 , a source surface processor pipeline (SSPP) 214 , a mixer 216 , a display surface processor pipeline (DSPP) 218 ​​, and one or more buffers (e.g., an HDR buffer 220 and a non-HDR buffer 222 ). The compositor 208 includes a display hardware abstraction layer (HAL) 210 and a video identification (ID) module 212 . Compositor 208 may communicate with SSPP 214, and SSPP 214 may communicate with mixer 216. Mixer 216 may communicate with DSPP 218, which may output processed display data to HDR buffer 220 and non-HDR buffer 222, from which display device 224 may draw the processed display data for display.

[0030] exist Figure 2 The components shown in FIG may be implemented by hardware, software in combination with hardware, firmware, or a combination thereof. And although not required, one or more of the components (e.g., display HAL 210 and video ID module 212) may be implemented by additions and modifications to existing computing devices that would be apparent to one of ordinary skill in the art (in light of this disclosure). For example, in FIG Figure 2 The embodiments depicted in can be implemented by modifying user-level and kernel-level components of an ANDROID-based computing device.

[0031] The WMS 204 is typically used to manage the z-order list of visible windows and how the windows are laid out on the display device 224. Among other things, it automatically performs window transitions and animations when applications are opened or closed or the screen is rotated. The z-order is the ordering of overlapping two-dimensional objects (such as a background and an image or video frame). For example, if the display is in portrait mode, the z-order can include a black background and overlapping frames for video playback.

[0032] In general, the GPU 106 can perform various functions on image and video data for presentation on the display device 224. For example, the GPU 106 can perform functions such as shading, blending, lighting, and other functions to generate pixel values ​​for the data to be displayed. In this example, the GPU 106 includes an animation transformation module 206 that is configured to generate a screen rotation animation using one or more images and / or video frames. For example, if a user rotates the computing device 200 during video playback, the WMS 204 can request the GPU 106 to use the animation transformation module 206 to generate a screen rotation animation using one or more images and / or video frames, which will be presented to the user via the display device 224 during the transition between landscape and portrait modes.

[0033] Typically, the DPU 104 is configured to receive data from an application 202a running on the CPU 102, a memory or a digital storage device (e.g., Figure 1 The DPU 104 receives and retrieves image and / or video frames from the processor memory 108 or memory module 116 of the display device 204 or the WMS 204. The DPU 104 may perform one or more image processing operations on the frames and output the processed frames to the display device 224 for display. Such image processing operations may include format conversion, scaling, rotation, blending and compositing, layering of images with additional graphics, etc. In other words, the DPU 104 obtains video and / or image data and outputs values ​​that cause the pixels of the display device 224 to illuminate and display the video or image.

[0034] The compositor 208 typically manages video and / or image data from one or more applications 202. Although not required, the compositor 208 can be implemented by the SurfaceFlinger module of the ANDROID framework (or a derivative of the SurfaceFlinger module). In some examples, the CPU 102 can execute multiple applications 202 with independent video and / or image data to be displayed on the display device 224. The compositor 208 determines what will be displayed on the display device 224 and provides overlay synthesis as needed. In some aspects, the compositor 208 is configured to receive / retrieve video and / or image data from one or more buffers used by the application 202 and synthesize the data for later display.

[0035] The compositor 208 includes a display hardware abstraction layer (HAL) 210, which is used by the compositor 208 to perform compositing using hardware resources of the DPU 104, GPU 106, processor memory 108, and / or any other suitable hardware. The compositor 208 also includes a video ID module 212, which is configured to determine the display format of the video and / or image data. For example, the video ID module 212 can determine whether the video and / or image data received from one or more buffers is in a high dynamic range (HDR) format, a standard dynamic range (SDR) format, or some other format.

[0036] SSPP 214 may receive video and / or image data from compositor 208 or retrieve video and / or image data from a buffer used by application 202. SSPP 214 may perform format conversion and quality improvement on the video and images. For example, SSPP 214 may process the image data by performing color space conversion, content-adaptive contrast enhancement, etc. on the received image data, and may output the processed image to mixer 216.

[0037] The mixer 216 can receive image data processed by the SSPP 214 and can perform blending and mixing of the image with one or more other surfaces. For example, the mixer 216 can perform alpha blending, color generation, setting of transparency color keys, blending of surfaces in arbitrary order, and blending in linear space. The mixer 216 can then output the blended / mixed image data to the DSPP 218.

[0038] The DSPP 218 may perform conversions, corrections, and adjustments to the image received from the mixer 216 based on the specific characteristics of the display device 224. For example, the DSPP 218 may perform operations for sunlight visibility improvement, content-adaptive backlight scaling, panel color correction, gamma correction, dithering, picture adjustments, etc. Once the DSPP 218 has completed its operations on the image data, the DSPP 218 may output the processed image data to one of the HDR buffer 220 or the non-HDR buffer 222 so that the processed image data is queued for display on the display device 224.

[0039] Example technique for improved HDR video rotation animation

[0040] When a user rotates an electronic device or apparatus, the orientation of a display or user interface may change in many different types of applications. For example, the orientation of a display may change in an application that provides textual information, graphical information, or a combination of these. For illustrative purposes, the following discussion will describe changing the orientation of a display in the context of an application that provides HDR video playback. However, it will be understood that the present disclosure may be applicable to any other suitable application provided by an electronic device.

[0041] Figure 3 3 is a schematic diagram of an electronic device 300 being rotated from a portrait orientation to a landscape orientation, and in response to the electronic device being rotated, the display transitions from a portrait mode display to a landscape mode display. In this example, the electronic device 300 displays an HDR video playback that was initially positioned in portrait mode. The portrait mode display includes a background layer 302 and a video playback layer 304.

[0042] As the electronic device 300 is rotated, the rotation animation presented on the display shows that the video playback layer 304 and the background layer 302 are rotated to be displayed in landscape mode. In the example shown, the background layer 302 is gradually eliminated during the transition from portrait mode to landscape mode, and the video playback layer 304 is gradually resized to fit the entire display. Similarly, in response to the rotation of the electronic device 300 from landscape orientation to portrait orientation, the background layer 302 can be gradually introduced into the display during the transition from landscape mode to portrait mode, and the video playback layer 304 is gradually resized to fit the reduced area of ​​the display. Therefore, the rotation animation is configured to present to the user an animation of adjusting the size of the video playback layer 304 to adapt to the orientation of the electronic device and the gradual introduction or elimination of the background layer 302.

[0043] As previously described, GPU 106 can be configured to generate a rotation animation based on one or more frames of video playback. However, when the rotation animation is processed by the display processor pipeline, one or more components may degrade the quality of the rotation animation. For example, GPU 106 and DPU 104 may operate using different mapping parameters such as hue, color, and contrast. Using these components may also unnecessarily use power for unneeded image processing.

[0044] For example, in a conventional system, and in response to determining that the electronic device is being rotated, the WMS may request the GPU to generate a screen rotation animation and request a screen capture buffer from the DPU. That is, the GPU will use frames from the video playback to generate the screen rotation animation, and send the generated screen rotation animation to the screen capture buffer requested by the WMS. However, in a conventional system, the DPU will not determine whether the video playback is in HDR format before receiving and displaying the rotation animation. Therefore, in response to a request for the screen capture buffer, the DPU will provide a non-HDR buffer. Therefore, the DPU processing pipeline will process the rotation animation as if it were non-HDR (e.g., SDR). Since the DPU and GPU may have differences in their tones and color mapping parameters, the additional processing performed by the DPU may reduce the quality of the rotation animation.

[0045] Now refer to Figure 2 , a technique for improved HDR video rotation animation will be described. Initially, and in response to determining that the electronic device is being rotated, the WMS 204 may initiate a screen rotation process by requesting the GPU 106 to generate a screen rotation animation using the animation transformation module 206 and requesting screen capture buffers (e.g., HDR buffer 220 and non-HDR buffer 222) from the compositor 208 of the DPU 104. That is, the DPU 104 receives an indication that a frame rotation animation process for video playback has been initiated.

[0046] In response to the request for the screen capture buffer, the compositor 208 can utilize the video ID module 212 to determine whether the video playback is in an HDR format or another format. If the video ID module 212 determines that the video playback is in a non-HDR format, the compositor 208 can return the address or identification of the non-HDR buffer 222 to the WMS 204. The WMS 204 can then receive the rotation animation from the GPU 106 and pass the rotation animation for processing by the remaining components of the processor pipeline: the SSPP 214, the mixer 216, and the DSPP 218. The DSPP 218 can then store the processed rotation animation in the non-HDR buffer 222 for later display on the display device 224.

[0047] If the video ID module 212 determines that the video playback is in HDR format, then in response to this determination and the WMS indication, the display HAL 210 can initiate a concurrent write-back (CWB) function, which is configured to allow the compositor 208 to do two things: (i) return the address or identification of the HDR buffer 220 as a screen capture buffer to the WMS 204, and (ii) bypass loading the rotation animation into one or more components of the display processor pipeline. For example, the CWB function can provide the compositor 208 and / or WMS 204 with the ability to write rotation animation data and / or background frame data directly to the HDR buffer 220 without passing the rotation animation data through one or more of the SSPP 214, the mixer 216, or the DSPP 218. In some examples, the HDR buffer 220 is configured to store HDR format display data, while the non-HDR buffer 222 can be configured to store non-HDR format display data, such as SDR format data. In some examples, the HDR buffer 220 may include an RGBA 1010102 buffer and range from 10 to 24 bits. In contrast, the non-HDR buffer 222 may range from 8 to 16 bits.

[0048] In some examples, compositor 208 is configured to shut down (e.g., power off, put to sleep, bypass, etc.) DSPP 218 in response to determining that the video playback is in HDR format. Thus, by shutting down DSPP 218, compositor 208 and / or WMS 204 can bypass loading the rotation animation into DSPP 218 before loading the rotation animation into HDR buffer 220. Compositor 208 can then receive an indication from WMS 204 that the frame rotation animation process has ended. In response, compositor 208 can turn on DSPP 218 and end the bypass.

[0049] In this example, the frames used by GPU 106 to generate the spinning animation are HDR-formatted frames. Therefore, the spinning animation data is in HDR format. Consequently, by shutting down one or more components of DPU 104, less power is consumed for image / video processing. Furthermore, because the spinning animation is already in HDR format, by bypassing components of the display processing pipeline, the spinning animation does not experience degradation due to mismatches in mapping data between DPU 104 and GPU 106.

[0050] Figure 4 is a flow chart illustrating example operations 400 for improving HDR video rotation animation. Operations 400 may be performed, for example, by a SoC (e.g., Figure 1 SoC 100) and / or electronic devices (e.g., Figure 2 Operation 400 may be implemented as a process performed on one or more processors (e.g., Figure 1 In some aspects, the sending and / or receiving of data by various hardware components can be via a bus interface (e.g., Figure 1 This is achieved by the bus module 110).

[0051] In this example, operation 400 begins at a first step 402 where a display processor, including a display processor pipeline, receives an indication that a frame rotation animation process has been initiated for video playback. Operation 400 then proceeds to step 404 by determining whether the video playback is in HDR format or another format.

[0052] Operation 400 then proceeds to step 406 where, in response to determining and receiving the indication, if the video playback is in HDR format: bypassing loading the frame rotation animation into the first portion of the display processor pipeline and loading the frame rotation animation into the second portion of the display processor pipeline.

[0053] If the video playback is in another format, operation 400 then proceeds to step 408 by loading the frame rotation animation into a first portion of the display processor pipeline, wherein the second portion is further in the display processor pipeline processing steps than the first portion.

[0054] In certain aspects, loading the frame rotation animation into the first portion includes loading the frame rotation animation into a first buffer, and loading the frame rotation animation into the second portion includes loading the frame rotation animation into a second buffer.

[0055] In certain aspects, the second buffer is configured to store HDR format data and the first buffer is configured to store non-HDR format data.

[0056] In certain aspects, the operation 400 further includes performing a concurrent write-back function to enable loading of the frame rotation animation into the second portion if the video playback is in an HDR format.

[0057] In certain aspects, the display processor pipeline includes a source surface processor pipeline (SSPP), a display surface processor pipeline (DSPP), and a mixer.

[0058] In certain aspects, bypassing loading the frame rotation animation into the first portion of the display processor pipeline further includes shutting down, by the display processor, the DSPP in response to determining that the video playback is in an HDR format.

[0059] In certain aspects, the operation 400 further includes: receiving, by the display processor, an indication that the frame rotation animation process has ended; and turning on, by the display processor, the DSPP in response to the indication that the frame rotation animation process has ended.

[0060] In certain aspects, determining whether video playback is in HDR format or another format is performed by a display processor.

[0061] Additional considerations

[0062] In some configurations, the terms "communicate," "communicating," and / or "communication" may refer to "receive," "receiving," "reception," and / or other related or appropriate aspects without necessarily departing from the scope of the present disclosure. In some configurations, the terms "communicate," "communicating," and "communication" may refer to "transmit," "transmitting," "transmission," and / or other related or appropriate aspects without necessarily departing from the scope of the present disclosure.

[0063] Within this disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspect" does not require that all aspects of the disclosure include the feature, advantage, or mode of operation discussed. The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other even if they are not physically in direct contact with each other. For example, a first object can be coupled to a second object even if the first object has never been in direct physical contact with the second object. The terms "circuit" and "circuitry" are used broadly and are intended to include hardware implementations of electronic devices and conductors that, when connected and configured, enable the functions described in this disclosure to be performed, without limitation as to the type of electronic circuitry.

[0064] One or more of the components, steps, features and / or functions shown herein can be rearranged and / or combined into a single component, step, feature or function, or embedded in several components, steps or functions. Additional elements, components, steps and / or functions can also be added without departing from the novel features disclosed herein. The apparatus, equipment and / or components shown herein can be configured to perform one or more of the methods, features or steps described herein. The novel algorithms described herein can also be effectively implemented in software and / or embedded in hardware.

[0065] It should be understood that the specific order or hierarchy of steps in the disclosed methods is an illustration of exemplary processes. It should be understood that the specific order or hierarchy of steps in these methods may be rearranged based on design preferences. The accompanying method claims present elements of the various steps in a sample order and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.

[0066] The foregoing description is provided to enable any person skilled in the art to implement the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Accordingly, the claims are not intended to be limited to the aspects shown herein, but rather to be given the full scope consistent with the language of the claims, wherein, unless expressly stated otherwise, reference to an element in the singular is not intended to mean "one and only one," but rather "one or more." Unless otherwise expressly stated, the term "some" refers to one or more. A phrase referring to "at least one of" a list of items refers to any combination of those items, including a single member. For example, "at least one of a, b, or c" is intended to encompass: a; b; c; a and b; a and c; b and c; and a, b, and c. All structural and functional equivalents of the elements of the various aspects described throughout this disclosure are expressly incorporated herein by reference and are intended to be encompassed by the claims, where such structural and functional equivalents are known or will later become known to those skilled in the art. In addition, no disclosure herein is intended to be dedicated to the public, regardless of whether such disclosure is expressly recited in the claims. No claim element is to be construed under 35 U.S.C. §112(f) unless the element is expressly recited using the phrase "means for..." or, in the case of a method claim, the element is recited using the phrase "step for..." or simply as a "block" as shown in a figure.

[0067] These devices and methods will be described in the following detailed description and illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using hardware, software, or a combination thereof. Whether such elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0068] For example, an element, or any part of an element, or any combination of elements can be implemented using a "processing system" comprising one or more processors. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functions described throughout this disclosure. One or more processors in a processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language, or other names, software should be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc. Software can be stored on a non-transitory computer-readable medium included in a processing system.

[0069] Accordingly, in one or more exemplary embodiments, the described functions can be implemented using hardware, software, or a combination thereof. If implemented using software, the functions can be stored on a computer-readable medium or encoded as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media. The storage medium can be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, PCM (phase change memory), flash memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage objects, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disks and optical disks include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs use lasers to reproduce data optically. Combinations of the above are also included within the scope of computer-readable media.

Claims

1. A method for high dynamic range (HDR) video rotation, comprising: receiving, by a display processor, an indication that a frame rotation animation process for video playback has been initiated, the display processor comprising a display processor pipeline; determining whether the video playback is in HDR format or another format; In response to the determining and receiving the indication: If the video playback is in HDR format: bypassing loading the frame rotation animation into the first portion of the display processor pipeline, and loading the frame rotation animation into a second portion of the display processor pipeline; as well as If the video playback is in the other format, loading the frame rotation animation into the first portion of the display processor pipeline, wherein the second portion is further in a processing step of the display processor pipeline in addition to the first portion, The display processor pipeline includes a source surface processor pipeline SSPP, a display surface processor pipeline DSPP and a mixer. Wherein, bypassing loading the frame rotation animation into the first part of the display processor pipeline further includes: in response to determining that the video playback is in HDR format, turning off the DSPP by the display processor.

2. The method according to claim 1, wherein Loading the frame rotation animation into the first portion includes loading the frame rotation animation into a first buffer, and loading the frame rotation animation into the second portion includes loading the frame rotation animation into a second buffer.

3. The method according to claim 2, wherein: The second buffer is configured to store HDR format data, and the first buffer is configured to store non-HDR format data.

4. The method according to claim 1, further comprising: If the video playback is in HDR format, a concurrent write-back function is performed to enable the frame rotation animation to be loaded into the second part.

5. The method according to claim 1, further comprising: receiving, by the display processor, an indication that the frame rotation animation process has ended; as well as The DSPP is turned on by the display processor in response to the indication that the frame rotation animation process has ended.

6. The method according to claim 1, wherein Determining whether the video playback is in HDR format or another format is performed by the display processor.

7. A device for display, comprising: Memory; as well as a processor coupled to the memory, the processor and the memory being configured to: receiving an indication that a frame rotation animation process has been initiated for video playback, the processor comprising a display processor pipeline; determining whether the video playback is in HDR format or another format; In response to the determining and the received indication: If the video playback is in HDR format: bypassing loading the frame rotation animation into the first portion of the display processor pipeline, and loading the frame rotation animation into a second portion of the display processor pipeline; as well as If the video playback is in the other format, loading the frame rotation animation into the first portion of the display processor pipeline, wherein the second portion is further in a processing step of the display processor pipeline in addition to the first portion, The display processor pipeline includes a source surface processor pipeline SSPP, a display surface processor pipeline DSPP and a mixer. The processor and the memory configured to bypass loading the frame rotation animation into the first portion of the display processor pipeline are further configured to: shut down the DSPP in response to determining that the video playback is in HDR format.

8. The device according to claim 7, wherein The processor and the memory configured to load the frame rotation animation into the first part are also configured to load the frame rotation animation into a first buffer, and wherein the processor and the memory configured to load the frame rotation animation into the second part are also configured to load the frame rotation animation into a second buffer.

9. The device according to claim 8, wherein The second buffer is configured to store HDR format data, and the first buffer is configured to store non-HDR format data.

10. The device according to claim 7, wherein The processor and the memory are further configured to perform a concurrent write-back function to enable the frame rotation animation to be loaded into the second portion if the video playback is in HDR format.

11. The device according to claim 7, wherein The processor and the memory are further configured to: receiving an indication that the frame rotation animation process has ended; and The DSPP is opened in response to the indication that the frame rotation animation process has ended.

12. A device for display, comprising: means for receiving an indication that a frame rotation animation process for video playback has been initiated, the means for receiving comprising a processor pipeline; means for determining whether the video playback is in HDR format or another format; In response to determining the format of the video playback and receiving the indication: If the video playback is in HDR format: for bypassing the unit for loading the frame rotation animation into the first portion of the display processor pipeline, and means for loading said frame rotation animation into a second portion of said display processor pipeline; as well as means for loading the frame rotation animation into the first portion of the processor pipeline if the video playback is in the other format, wherein the second portion is further in a processing step of the display processor pipeline in addition to the first portion, The processor pipeline includes a source surface processor pipeline SSPP, a display surface processor pipeline DSPP and a mixer. The unit for bypassing loading the frame rotation animation into the first portion of the processor pipeline further comprises: a unit for shutting down the DSPP in response to determining that the video playback is in HDR format.

13. The device according to claim 12, wherein The unit for loading the frame rotation animation into the first portion includes a unit for loading the frame rotation animation into a first buffer, and the unit for loading the frame rotation animation into the second portion includes a unit for loading the frame rotation animation into a second buffer.

14. The device according to claim 13, wherein The second buffer is configured to store HDR format data, and the first buffer is configured to store non-HDR format data.

15. The apparatus according to claim 12, further comprising: and means for performing a concurrent write-back function to enable loading of the frame rotation animation into the second portion if the video playback is in HDR format.

16. The apparatus according to claim 12, further comprising: means for receiving an indication that the frame rotation animation process has ended; as well as means for opening the DSPP in response to the indication that the frame rotation animation process has ended.

17. The apparatus of claim 12, wherein: The means for receiving includes a display processor; and The means for determining includes the display processor.

18. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor of a device, cause the device to perform a method for high dynamic range (HDR) video rotation, the method comprising: receiving, by a display processor, an indication that a frame rotation animation process for video playback has been initiated, the display processor comprising a display processor pipeline; determining whether the video playback is in HDR format or another format; In response to the determining and receiving the indication: If the video playback is in HDR format: bypassing loading the frame rotation animation into the first portion of the display processor pipeline, and loading the frame rotation animation into a second portion of the display processor pipeline; as well as If the video playback is in the other format, loading the frame rotation animation into the first portion of the display processor pipeline, wherein the second portion is further in a processing step of the display processor pipeline in addition to the first portion, The display processor pipeline includes a source surface processor pipeline SSPP, a display surface processor pipeline DSPP and a mixer. Wherein, bypassing loading the frame rotation animation into the first part of the display processor pipeline further includes: in response to determining that the video playback is in HDR format, turning off the DSPP by the display processor.

19. The non-transitory computer-readable storage medium of claim 18, wherein: Loading the frame rotation animation into the first portion includes loading the frame rotation animation into a first buffer, and loading the frame rotation animation into the second portion includes loading the frame rotation animation into a second buffer.

20. The non-transitory computer-readable storage medium of claim 19, wherein: The second buffer is configured to store HDR format data, and the first buffer is configured to store non-HDR format data.

21. The non-transitory computer-readable storage medium of claim 18, further comprising: If the video playback is in HDR format, a concurrent write-back function is performed to enable the frame rotation animation to be loaded into the second part.

22. The non-transitory computer-readable storage medium of claim 18, wherein: The method further comprises: receiving, by the display processor, an indication that the frame rotation animation process has ended; and The DSPP is turned on by the display processor in response to the indication that the frame rotation animation process has ended.

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