An active on-chip sum-differential device and sum-differential beam network

Abstract

The present invention provides an active on-chip sum-differential and sum-differential beam network, including: a signal input conversion unit, used to convert input radio frequency signals A and B into differential signals A+, A-, B+, B-; an active sum-differential operation unit, connected to the signal input conversion unit, used to convert the voltage signals A+, A-, B+, B- output by the signal input conversion unit into current signals, and perform current power division, difference calculation, and sum calculation; a signal output conversion unit, connected to the active sum-differential operation unit, used to convert the current signal into a voltage signal, and convert (A+B), -(A+B), (B-A), -(B-A) into single-ended signals A+B, B-A; the signal input conversion unit and the signal output conversion unit are also used to provide a DC bias point for the active sum-differential operation unit. In principle and physical structure, it is ensured that it has very ideal amplitude and phase consistency; the sum-differential does not introduce insertion loss; the sum-differential has a relatively wide bandwidth; and the area overhead on the layout is very small.

Description

Technical Field

[0001] The present invention relates to the technical field of microwave radio frequency integrated circuits, and more particularly, to an active on-chip sum-difference device and a sum-difference beam network. Background Art

[0002] In radar and electronic warfare systems, sum-difference beams are often used for monopulse angle measurement. As the core device of the sum-difference beam network, the performance of the sum-difference device directly affects the angle measurement accuracy of the system. The performance indicators of the sum-difference device usually include sum-difference amplitude consistency, sum-difference phase consistency, insertion loss, and operating bandwidth. In many cases, the volume and weight of the sum-difference device also limit its application platform.

[0003] Traditional three-dimensional structure-based sum-difference devices usually use magic Ts, ferrite, or other three-dimensional microwave structures. These three-dimensional structure-based sum-difference devices are large in volume, and each port is not in the same direction or plane, making it difficult to integrate with planar circuits and restricting the miniaturization of upper-level components. With the development of planar process technology, many planar structure-based sum-difference devices have emerged, such as rat-race, tapered matching lines, and coupled lines. Their implementation methods usually use passive circuits, so it is inevitable to introduce additional insertion loss. In addition, since the sum signal and the difference signal usually pass through different RF paths, there are often different degrees of mismatch in amplitude and phase. This mismatch becomes more serious as the RF bandwidth increases. If precise angle measurement is required, digital means are needed to assist in calibrating the mismatch.

[0004] With the development of integrated circuits, it has become possible to implement a miniaturized sum-difference device by combining active and passive circuits on a single chip. Summary of the Invention

[0005] The present invention aims to at least solve one of the technical problems existing in the prior art, such as the small operating bandwidth of the on-chip sum-difference device, the easy mismatch of amplitude and phase between the sum port and the difference port, the insufficient degree of miniaturization, and the difficulty in providing gain.

[0006] To this end, in the first aspect of the present invention, an active on-chip sum-difference device is provided.

[0007] In the second aspect of the present invention, a sum-difference beam network is provided.

[0008] The present invention provides an active on-chip sum-difference device, including:

[0009] A signal input conversion unit for converting the input RF signals A and B into differential signals A+, A-, B+, and B-.

[0010] An active sum-difference operation unit, connected to the signal input conversion unit, is configured to convert the voltage signals A+, A-, B+, and B- output by the signal input conversion unit into current signals, and perform current power division, difference calculation, and sum calculation;

[0011] A signal output conversion unit, connected to the active sum-difference operation unit, is configured to convert the current signal into a voltage signal, and convert (A + B), -(A + B), (B - A), and -(B - A) into single-ended signals A + B and B - A;

[0012] The signal input conversion unit and the signal output conversion unit are further configured to provide a DC bias point for the active sum-difference operation unit.

[0013] An active on-chip sum-difference device according to the above technical solution of the present invention may further have the following additional technical features:

[0014] In the above technical solution, the signal input conversion unit includes a first balun, a second balun, a first on-chip capacitor, and a second on-chip capacitor;

[0015] One port of the primary coil of the first balun serves as the input terminal for the input radio frequency signal A, and the other port is grounded after being connected in series with the first on-chip capacitor; the center tap of the secondary coil of the first balun is grounded and connected to the input terminal of the active sum-difference operation unit;

[0016] One port of the primary coil of the second balun serves as the input terminal for the input radio frequency signal B, and the other port is grounded after being connected in series with the second on-chip capacitor; the center tap of the secondary coil of the second balun is grounded and connected to the input terminal of the active sum-difference operation unit.

[0017] In the above technical solution, the signal output conversion unit includes a third balun, a fourth balun, a third on-chip capacitor, and a fourth on-chip capacitor;

[0018] The port of the primary coil of the third balun is connected to the output terminal of the active sum-difference operation unit, and the center tap of the primary coil of the third balun is connected to the power supply voltage;

[0019] The port of the primary coil of the fourth balun is connected to the other output terminal of the active sum-difference operation unit, and the center tap of the primary coil of the fourth balun is connected to the power supply voltage;

[0020] One port of the secondary coil of the third balun is the differential signal output terminal, and the other port is grounded after being connected in series with the third on-chip capacitor; one port of the secondary coil of the fourth balun is the sum signal output terminal, and the other port is grounded after being connected in series with the fourth on-chip capacitor.

[0021] In the above technical solution, the active sum-difference operation unit includes the first to twelfth transistors and the first to second on-chip resistors;

[0022] One port of the secondary coil of the first balun is connected to the gate of the first transistor, and the other port is connected to the gate of the second transistor; one port of the secondary coil of the second balun is connected to the gate of the third transistor, and the other port is connected to the gate of the fourth transistor;

[0023] One end of the first on-chip resistor is respectively connected to the sources of the first transistor and the second transistor, and the other end is connected to the ground; one end of the second on-chip resistor is respectively connected to the sources of the third transistor and the fourth transistor, and the other end is connected to the ground;

[0024] The first transistor, the second transistor, the third transistor, and the fourth transistor are connected in common source for amplifying the input signal;

[0025] The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor form an open-drain common-gate connection for generating a current sum-difference signal and inputting the current sum-difference signal into the third balun and the fourth balun respectively.

[0026] In the above technical solution, the sources of the fifth transistor and the seventh transistor are connected to the drain of the second transistor; the sources of the sixth transistor and the eighth transistor are connected to the drain of the first transistor; the sources of the ninth transistor and the twelfth transistor are connected to the drain of the fourth transistor; the sources of the tenth transistor and the eleventh transistor are connected to the drain of the third transistor;

[0027] The drains of the fifth transistor and the ninth transistor are connected to one port of the primary coil of the third balun; the drains of the sixth transistor and the tenth transistor are connected to the other port of the primary coil of the third balun;

[0028] The drains of the seventh transistor and the eleventh transistor are connected to one port of the primary coil of the fourth balun; the drains of the eighth transistor and the twelfth transistor are connected to the other port of the primary coil of the fourth balun;

[0029] The gates of the fifth to twelfth transistors are connected to a bias voltage.

[0030] In the above technical solution, a bias voltage generating unit is further included, and the bias voltage generating unit is connected to the active sum-difference operation unit for providing a DC bias voltage for the active sum-difference operation unit.

[0031] In the above technical solution, the bias voltage generating unit includes the third to twelfth on-chip resistors. One end of the third on-chip resistor is connected to the power supply voltage, and the other end is connected in series with the fourth on-chip resistor and then grounded;

[0032] One end of the fifth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the fifth transistor;

[0033] One end of the sixth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the sixth transistor;

[0034] One end of the seventh on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the seventh transistor;

[0035] One end of the eighth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the eighth transistor;

[0036] One end of the ninth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the ninth transistor;

[0037] One end of the tenth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the tenth transistor;

[0038] One end of the eleventh on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the eleventh transistor;

[0039] One end of the twelfth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the twelfth transistor.

[0040] In the above technical solution, the first balun, the second balun, the third balun and the fourth balun all include a primary coil and a secondary coil. The primary coil and the secondary coil adopt the same metal layer, and the coupling coefficient of the balun is adjusted by adjusting the distance between the primary coil and the secondary coil.

[0041] The present invention also provides a sum-difference beam network, including an active on-chip sum-difference device as described in any one of the above technical solutions.

[0042] In summary, due to the adoption of the above technical features, the beneficial effects of the present invention are as follows:

[0043] 1. Since the sum signal and the difference signal pass through exactly the same and layout-symmetrical paths, it is ensured that they have very ideal amplitude and phase consistency in principle and physical structure;

[0044] 2. Since an active amplification circuit is adopted, the present sum-difference device does not introduce insertion loss;

[0045] 3. Since broadband matching technology is adopted, the sum-difference device has a relatively wide bandwidth;

[0046] 4. Since the operations of signal power splitting, summation, and subtraction are all implemented using active circuits, the area overhead on the layout is very small.

[0047] The additional aspects and advantages of the present invention will become apparent in the following description section or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the description of the embodiments in conjunction with the following drawings, where:

[0049] Figure 1 is a schematic diagram of a 19 - 23 GHz active on - chip sum - difference circuit designed using the GaAs P25ED process in an embodiment of the present invention;

[0050] Figure 2 is a schematic diagram of the reflection coefficient curves of the input and output ports of an active on - chip sum - difference circuit in an embodiment of the present invention;

[0051] Figure 3 is a schematic diagram of the gain curve of an active on - chip sum - difference circuit in an embodiment of the present invention;

[0052] Figure 4 is a schematic diagram of the phase curve of an active on - chip sum - difference circuit in an embodiment of the present invention;

[0053] Figure 5 is a schematic diagram of the curve of the power of the sum port and the difference port varying with the signal phase difference in the case of two 20 GHz equal - amplitude input signals for an active on - chip sum - difference circuit in an embodiment of the present invention.

[0054] Wherein, Figures 1 to 5 the corresponding relationship between the reference numerals in the drawings and the component names is as follows:

[0055] 1. Signal input conversion unit; 2. Active sum - difference operation unit; 3. Signal output conversion unit; 4. Bias voltage generation unit;

[0056] 11. First balun; 12. Second balun; 13. Third balun; 14. Fourth balun;

[0057] M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; M9. Ninth transistor; M10. Tenth transistor; M11. Eleventh transistor; M12. Twelfth transistor;

[0058] R1, the first on-chip resistor; R2, the second on-chip resistor; R3, the third on-chip resistor; R4, the fourth on-chip resistor; R5, the fifth on-chip resistor; R6, the sixth on-chip resistor; R7, the seventh on-chip resistor; R8, the eighth on-chip resistor; R9, the ninth on-chip resistor; R10, the tenth on-chip resistor; R11, the eleventh on-chip resistor; R12, the twelfth on-chip resistor;

[0059] C1, the first on-chip capacitor; C2, the second on-chip capacitor; C3, the third on-chip capacitor; C4, the fourth on-chip capacitor. Detailed implementation manners

[0060] In order to more clearly understand the above objects, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.

[0061] In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

[0062] The following refers to Figures 1 to 5 to describe an active on-chip sum-difference device and a sum-difference beam network according to some embodiments of the present invention.

[0063] Some embodiments of the present application provide an active on-chip sum-difference device.

[0064] As Figures 1 to 5 shown, the first embodiment of the present invention proposes an active on-chip sum-difference device, including: a signal input conversion unit 1, an active sum-difference operation unit 2, a signal output conversion unit 3, and a bias voltage generation unit 4;

[0065] The signal input conversion unit 1 is configured to convert the input radio frequency signals A and B into differential signals A+, A-, B+, B-;

[0066] The active sum-difference operation unit 2 is connected to the signal input conversion unit 1, and is configured to convert the voltage signals A+, A-, B+, B- output by the signal input conversion unit 1 into current signals, and perform current power splitting, difference calculation, and sum calculation;

[0067] The signal output conversion unit 3 is connected to the active sum-difference operation unit 2, and is configured to convert the current signals into voltage signals, and convert (A + B), -(A + B), (B - A), -(B - A) into single-ended signals A + B, B - A.

[0068] The signal input conversion unit 1 includes a first balun 11, a second balun 12, a first on-chip capacitor C1, and a second on-chip capacitor C2;

[0069] The primary coil of the first balun 11 is provided with two ports. One port of the primary coil of the first balun 11 serves as the input terminal for the input radio frequency signal A, and the other port is grounded after being connected in series with the first on-chip capacitor C1; the center tap of the secondary coil of the first balun 11 is grounded and connected to the input terminal of the active sum-difference operation unit 2. The secondary coil of the first balun 11 is also provided with two ports, and both ports are connected to the input terminal of the active sum-difference operation unit 2;

[0070] The primary coil of the second balun 12 is provided with two ports. One port of the primary coil of the second balun 12 serves as the input terminal for the input radio frequency signal B, and the other port is grounded after being connected in series with the second on-chip capacitor C2; the center tap of the secondary coil of the second balun 12 is grounded and connected to the input terminal of the active sum-difference operation unit 2. The secondary coil of the second balun 12 is also provided with two ports, and both ports are connected to the input terminal of the active sum-difference operation unit 2.

[0071] The first balun 11, the first on-chip capacitor C1, the gate parasitic capacitance of the first transistor M1, and the gate parasitic capacitance of the second transistor M2 together form a high-order resonance network to complete broadband matching at the input terminal of the input radio frequency signal A; the second balun 12, the second on-chip capacitor C2, the gate parasitic capacitance of the third transistor M3, and the gate parasitic capacitance of the fourth transistor M4 together form a high-order resonance network to complete broadband matching at the input terminal of the input radio frequency signal B; the signal input conversion unit 1 realizes the conversion of the input radio frequency signal A and the input radio frequency signal B from single-ended to differential, and provides a DC bias point for the gates of the first to fourth transistors M1 - M4 in the active sum-difference operation unit 2.

[0072] The signal output conversion unit 3 includes a third balun 13, a fourth balun 14, a third on-chip capacitor C3, and a fourth on-chip capacitor C4;

[0073] The primary coil of the third balun 13 is provided with two ports. The ports of the primary coil of the third balun 13 are connected to the output terminal of the active sum-difference operation unit 2, and the center tap of the primary coil of the third balun 13 is connected to the power supply voltage;

[0074] The primary coil of the fourth balun 14 is provided with two ports. The ports of the primary coil of the fourth balun 14 are connected to the other output terminal of the active sum-difference operation unit 2, and the center tap of the primary coil of the fourth balun 14 is connected to the power supply voltage;

[0075] Both the secondary coils of the third balun 13 and the fourth balun 14 are provided with two ports. One port of the secondary coil of the third balun 13 is a differential signal output terminal, and the other port is grounded after being connected in series with the third on-chip capacitor C3; one port of the secondary coil of the fourth balun 14 is a sum signal output terminal, and the other port is grounded after being connected in series with the fourth on-chip capacitor C4.

[0076] The third balun 13, the third on-chip capacitor C3, the drain parasitic capacitances of the fifth transistor M5, the sixth transistor M6, the ninth transistor M9, and the tenth transistor together form a high-order resonance network to complete the broadband matching of the differential signal output terminal; the fourth balun 14, the fourth capacitor, the drain parasitic capacitances of the seventh transistor M7, the eighth transistor M8, the eleventh transistor M11, and the twelfth transistor M12 together form a high-order resonance network to complete the broadband matching of the sum signal output terminal; the transistor can adopt a high electron mobility transistor. The signal output conversion unit 3 realizes the conversion of the current signal to the voltage signal, realizes the conversion of the differential signal B - A and the sum signal B + A from differential to single-ended, and provides a DC bias point for the drains of the fifth to twelfth transistors M5 - M12 in the active sum-difference operation unit 2.

[0077] The active sum-difference operation unit 2 includes the first to twelfth transistors M1 - M12, and the first to second on-chip resistors R1 - R2;

[0078] One port of the secondary coil of the first balun 11 is connected to the gate of the first transistor M1, and the other port is connected to the gate of the second transistor M2; one port of the secondary coil of the second balun 12 is connected to the gate of the third transistor M3, and the other port is connected to the gate of the fourth transistor M4;

[0079] One end of the first on-chip resistor R1 is respectively connected to the sources of the first transistor M1 and the second transistor M2, and the other end is connected to the ground; one end of the second on-chip resistor R2 is respectively connected to the sources of the third transistor M3 and the fourth transistor M4, and the other end is connected to the ground; through the above settings, a self-bias voltage is provided for the first to fourth transistors M1 - M4.

[0080] The first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are connected in common source and are used for amplifying the input signal;

[0081] The fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are connected in open-drain common-gate and are used for generating a current sum-difference signal and inputting the current sum-difference signal to the third balun 13 and the fourth balun 14 respectively.

[0082] The sources of the fifth transistor M5 and the seventh transistor M7 are connected to the drain of the second transistor M2; the sources of the sixth transistor M6 and the eighth transistor M8 are connected to the drain of the first transistor M1; the sources of the ninth transistor M9 and the twelfth transistor M12 are connected to the drain of the fourth transistor M4; the sources of the tenth transistor M10 and the eleventh transistor M11 are connected to the drain of the third transistor M3;

[0083] The drains of the fifth transistor M5 and the ninth transistor M9 are connected to one port of the primary coil of the third balun 13; the drains of the sixth transistor M6 and the tenth transistor M10 are connected to the other port of the primary coil of the third balun 13;

[0084] The drains of the seventh transistor M7 and the eleventh transistor M11 are connected to one port of the primary coil of the fourth balun 14; the drains of the eighth transistor M8 and the twelfth transistor M12 are connected to the other port of the primary coil of the third balun 13;

[0085] The gates of the fifth to twelfth transistors M5 - M12 are connected to a bias voltage.

[0086] The active sum - difference operation unit 2 is used to perform the sum and difference operations of currents, converting the voltage - domain operation into a current - domain operation. As Figure 1 shown, the currents at points C, D, E, and F are I B -I A , -(I B -I A ), -(I B +I A ), I B +I A . The components of each branch are exactly the same and the layout is completely symmetrical, thus ensuring very ideal amplitude and phase consistency.

[0087] The bias voltage generation unit 4 is connected to the active sum - difference operation unit 2 and is used to provide a DC bias voltage for the active sum - difference operation unit 2.

[0088] In the above - mentioned technical solution, the bias voltage generation unit 4 includes the third to twelfth on - chip resistors R3 - R12. One end of the third on - chip resistor R3 is connected to the power supply voltage, and the other end is connected in series with the fourth on - chip resistor R4 and then grounded; the third on - chip resistor R3 and the fourth on - chip resistor R4 form a voltage - dividing network to generate the DC voltage required for the gates of the fifth to twelfth transistors M5 - M12;

[0089] One end of the fifth on-chip resistor R5 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the fifth transistor M5; one end of the sixth on-chip resistor R6 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the sixth transistor M6; one end of the seventh on-chip resistor R7 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the seventh transistor M7; one end of the eighth on-chip resistor R8 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the eighth transistor M8; one end of the ninth on-chip resistor R9 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the ninth transistor M9; one end of the tenth on-chip resistor R10 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the tenth transistor M10; one end of the eleventh on-chip resistor R11 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the eleventh transistor M11; one end of the twelfth on-chip resistor R12 is connected between the third on-chip resistor R3 and the fourth on-chip resistor R4, and the other end is connected to the gate of the twelfth transistor M12. The fifth to twelfth on-chip resistors R5 - R12 are used to provide high impedance for the gates of the fifth to twelfth transistors M5 - M12, ensuring the stability of the active sum-difference operation unit 2.

[0090] The first balun 11, the second balun 12, the third balun 13 and the fourth balun 14 each include a primary coil and a secondary coil. The primary coil and the secondary coil are made of the same metal layer, and the coupling coefficient of the balun is adjusted by adjusting the spacing between the primary coil and the secondary coil.

[0091] Figure 2 It is the reflection coefficient curve of the input port and the output port of the active on-chip sum-difference device. It can be seen that due to the adoption of the coupled resonance matching network, this embodiment can obtain excellent reflection coefficient performance within a relatively wide frequency band. Figure 3 It is the gain curve of the active on-chip sum-difference device, showing positive gain, thus avoiding the insertion loss introduced by using a traditional passive sum-difference device, and the amplitude consistency is relatively good within the entire working frequency band. Its mismatch is mainly due to the fact that the gallium arsenide process only provides two metal layers, and there are inevitable small asymmetries on the wiring. Figure 4 The phase curve of the active on-chip sum-difference device is given, and its phase curve has very good consistency within the entire frequency band. Figure 5 It gives the variation of the power of the sum port and the difference port with the signal phase difference under the condition of two 20GHz equal-amplitude input signals. It can be seen that the zero value depth near 0 degrees is very deep, and there is still a zero value depth of about 20dB within ±15°, showing excellent sum-difference performance, and Figures 3 to 4The frequency response shows that at other frequencies within the 19 - 23 GHz band, this active on - chip sum - difference divider also has sum - difference performance comparable to that at 20 GHz. This active sum - difference divider uses a 5V power supply voltage, consumes approximately 40 mA of current, and the entire chip size is only 1 mm × 1 mm.

[0092] From the above principles and simulation analysis, it can be seen that in theory, the paths from each input port to the output port of this active on - chip sum - difference divider are exactly the same, unlike passive sum - difference dividers where the paths of signals to the sum port and difference port are different in theory. Therefore, in theory, this active on - chip sum - difference divider can achieve very ideal amplitude and phase consistency.

[0093] Some embodiments of this application provide a sum - difference beam network.

[0094] The second embodiment of the present invention proposes a sum - difference beam network, and on the basis of any of the above - mentioned embodiments, as Figures 1 to 5 shown, it includes an active on - chip sum - difference divider proposed in the above - mentioned embodiment. The sum - difference beam network is used for monopulse angle measurement in radar or electronic warfare systems.

[0095] In this specification, the schematic representations of the above - mentioned terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0096] Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. An active on-chip sum-differential device, characterized in that: include: A signal input conversion unit, used for converting input radio frequency signals A and B into differential signals A+, A-, B+, B-; the signal input conversion unit comprises a first balun, a second balun, a first on-chip capacitor and a second on-chip capacitor; An active sum-difference operation unit is connected to the signal input conversion unit and is used to convert the voltage signals A+, A-, B+, B- output by the signal input conversion unit into current signals, and perform current power division, difference calculation, and summation; the active sum-difference operation unit includes first to twelfth transistors and first to second on-chip resistors; A signal output conversion unit is connected to the active and differential operation unit, and is used to convert the current signal into a voltage signal, and convert (A+B), -(A+B), (BA), -(BA) into single-ended signals A+B, BA; the signal output conversion unit includes a third balun, a fourth balun, a third on-chip capacitor and a fourth on-chip capacitor; The signal input conversion unit and the signal output conversion unit are also used to provide a DC bias point for the active sum-difference operation unit; One port of the secondary coil of the first balun is connected to the gate of the first transistor, and the other port is connected to the gate of the second transistor; one port of the secondary coil of the second balun is connected to the gate of the third transistor, and the other port is connected to the gate of the fourth transistor; One end of the first on-chip resistor is connected to the source of the first transistor and the source of the second transistor respectively, and the other end is connected to the ground; One end of the second on-chip resistor is connected to the source of the third transistor and the source of the fourth transistor respectively, and the other end is connected to the ground; The first transistor, the second transistor, the third transistor and the fourth transistor are connected to a common source and are used to amplify an input signal; The fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor form an open-drain common-gate connection for generating a current and a difference signal, and inputting the current and the difference signal to the third balun and the fourth balun respectively; The sources of the fifth transistor and the seventh transistor are connected to the drain of the second transistor; the sources of the sixth transistor and the eighth transistor are connected to the drain of the first transistor; the sources of the ninth transistor and the twelfth transistor are connected to the drain of the fourth transistor; the sources of the tenth transistor and the eleventh transistor are connected to the drain of the third transistor; The drains of the fifth transistor and the ninth transistor are connected to one port of the primary coil of the third balun; the drains of the sixth transistor and the tenth transistor are connected to the other port of the primary coil of the third balun; The drains of the seventh transistor and the eleventh transistor are connected to one port of the primary coil of the fourth balun; the drains of the eighth transistor and the twelfth transistor are connected to the other port of the primary coil of the third balun; The gates of the fifth to twelfth transistors are connected to a bias voltage.

2. The active on-chip summator according to claim 1, characterized in that: One port of the primary coil of the first balun is used as the input end of the input radio frequency signal A, and the other port is connected in series with the first on-chip capacitor and then grounded; the center tap of the secondary coil of the first balun is grounded and connected to the input end of the active sum-difference operation unit; One port of the primary coil of the second balun is used as the input end of the input RF signal B, and the other port is connected in series with the second on-chip capacitor and then grounded; the center tap of the secondary coil of the second balun is grounded and connected to the input end of the active sum-difference operation unit.

3. The active on-chip summator according to claim 2, characterized in that: A port of the primary coil of the third balun is connected to an output end of the active sum-difference operation unit, and a center tap of the primary coil of the third balun is connected to a power supply voltage; A port of the primary coil of the fourth balun is connected to another output end of the active sum-difference operation unit, and a center tap of the primary coil of the fourth balun is connected to a power supply voltage; One port of the secondary coil of the third balun is a difference signal output terminal, and the other port is connected in series with the third on-chip capacitor and then grounded; one port of the secondary coil of the fourth balun is a sum signal output terminal, and the other port is connected in series with the fourth on-chip capacitor and then grounded.

4. The active on-chip summator according to claim 3, characterized in that: It also includes a bias voltage generating unit, which is connected to the active and differential operation unit and is used to provide a DC bias voltage for the active and differential operation unit.

5. The active on-chip summator according to claim 4, characterized in that: The bias voltage generating unit includes third to twelfth on-chip resistors, one end of the third on-chip resistor is connected to the power supply voltage, and the other end is connected in series with the fourth on-chip resistor and then grounded; One end of the fifth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the fifth transistor; One end of the sixth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the sixth transistor; One end of the seventh on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the seventh transistor; One end of the eighth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the eighth transistor; One end of the ninth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the ninth transistor; One end of the tenth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the tenth transistor; One end of the eleventh on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the eleventh transistor; One end of the twelfth on-chip resistor is connected between the third on-chip resistor and the fourth on-chip resistor, and the other end is connected to the gate of the twelfth transistor.

6. The active on-chip summator according to claim 5, characterized in that: The first balun, the second balun, the third balun and the fourth balun all include a primary coil and a secondary coil. The primary coil and the secondary coil use the same metal layer, and the coupling coefficient of the balun is adjusted by adjusting the distance between the primary coil and the secondary coil.

7. A sum and difference beam network, characterized in that: An active on-chip summator as claimed in any one of claims 1 to 6.

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